WO2020259450A1 - 防闪屏电路及方法、用于显示面板的驱动电路、显示装置 - Google Patents

防闪屏电路及方法、用于显示面板的驱动电路、显示装置 Download PDF

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Publication number
WO2020259450A1
WO2020259450A1 PCT/CN2020/097522 CN2020097522W WO2020259450A1 WO 2020259450 A1 WO2020259450 A1 WO 2020259450A1 CN 2020097522 W CN2020097522 W CN 2020097522W WO 2020259450 A1 WO2020259450 A1 WO 2020259450A1
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Prior art keywords
noise reduction
voltage signal
circuit
reduction voltage
output
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PCT/CN2020/097522
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English (en)
French (fr)
Inventor
杨秀琴
刘荣铖
赵鹏
王会明
马京
鲁思颖
孔超
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/259,218 priority Critical patent/US11605360B2/en
Publication of WO2020259450A1 publication Critical patent/WO2020259450A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers

Definitions

  • the present disclosure relates to the field of display technology, in particular to an anti-flash screen circuit and method, a driving circuit for a display panel, and a display device.
  • the embodiments of the present disclosure provide an anti-flash screen circuit and method, a driving circuit for a display panel, and a display device.
  • embodiments of the present disclosure provide an anti-flash screen circuit, which is applied to a drive circuit of a display panel, the drive circuit includes a gate drive circuit, and the anti-flash screen circuit includes:
  • the control sub-circuit is configured to control the gate drive circuit to output a gate cut-off level during the power-on period of the display panel.
  • the gate drive circuit includes a noise reduction module, and the noise reduction module is configured to pull the output level of the gate drive circuit to a level when the received noise reduction voltage signal is at a turn-on level.
  • the control sub-circuit is configured to control the noise reduction voltage signal output to the noise reduction module to the conduction level during the power-on time period.
  • control sub-circuit is configured to use an external input voltage signal of the drive circuit as the noise reduction voltage signal during the power-on period to output to the noise reduction module.
  • the gate drive circuit includes a first noise reduction module and a second noise reduction module, the drive circuit further includes a level conversion circuit, and the level conversion circuit is configured to provide the first noise reduction module Providing a first noise reduction voltage signal to provide a second noise reduction voltage signal for the second noise reduction module;
  • the anti-flash screen circuit further includes: a determining sub-circuit configured to determine whether it is in the power-on time period according to the first noise reduction voltage signal and the second noise reduction voltage signal.
  • the determining sub-circuit is configured to determine whether the voltages of the first noise reduction voltage signal and the second noise reduction voltage signal are equal, and the first noise reduction voltage signal and the second noise reduction voltage signal The voltage of the signal is equal, indicating that it is in the power-on time period;
  • the control sub-circuit is configured to control the gate driving circuit to output a gate cut-off level when the voltages of the first noise reduction voltage signal and the second noise reduction voltage signal are equal.
  • the determining sub-circuit includes:
  • the first comparator and the second comparator, the first comparator and the second comparator each include: a non-inverting input terminal, an inverting input terminal and an output terminal; the non-inverting input terminal of the first comparator and the first comparator Both the inverting input terminals of the two comparators are electrically connected to the first noise reduction voltage signal output terminal of the level conversion circuit; the inverting input terminal of the first comparator and the non-inverting input terminal of the second comparator Are electrically connected to the second noise reduction voltage signal output terminal of the level conversion circuit;
  • the two input terminals of the OR gate are respectively electrically connected to the output terminal of the first comparator and the output terminal of the second comparator, and the output terminal of the OR gate is connected to the control terminal of the control sub-circuit Electrical connection
  • the first noise reduction signal output terminal is used to output the first noise reduction voltage signal
  • the second noise reduction signal output terminal is used to output the second noise reduction voltage signal
  • control sub-circuit includes:
  • a first selector the two input terminals of the first selector are respectively connected to the first noise reduction voltage signal output terminal of the level conversion circuit and the external input voltage signal input terminal of the power management integrated circuit of the display panel Electrically connected; the control terminal of the first selector is electrically connected with the output terminal of the determining sub-circuit; the first selector is configured to pass the first selector under the control of the output signal of the determining sub-circuit The output terminal of a selector outputs one of the first noise reduction voltage signal and the external input voltage signal;
  • a second selector two input terminals of the second selector are respectively electrically connected to a second noise reduction voltage signal output terminal of the level conversion circuit and an external input voltage signal input terminal of the power management integrated circuit;
  • the control terminal of the second selector is electrically connected to the output terminal of the determining sub-circuit;
  • the second selector is configured to pass the second selector under the control of the output signal of the determining sub-circuit The output terminal of which outputs one of the second noise reduction voltage signal and the external input voltage signal;
  • the external input voltage signal input terminal is used to receive an external input voltage signal provided to the driving circuit of the display panel.
  • an embodiment of the present disclosure provides a driving circuit for a display panel, and the driving circuit includes the anti-flash screen circuit as described in any one of the preceding items.
  • an embodiment of the present disclosure provides a display device including the driving circuit as described above.
  • an embodiment of the present disclosure provides an anti-flash screen method, which is applied to a driving circuit of a display panel, the driving circuit includes a gate driving circuit, and the method includes:
  • the gate driving circuit is controlled to output a gate cut-off level during the power-on period of the display panel.
  • the gate drive circuit includes a noise reduction module, and the noise reduction module is configured to pull the output level of the gate drive circuit to a level when the received noise reduction voltage signal is at a turn-on level.
  • the controlling the gate drive circuit to output the gate cut-off level during the power-on period of the display panel includes:
  • the noise reduction voltage signal output to the noise reduction module is controlled to be at a conduction level.
  • controlling the noise reduction voltage signal output to the noise reduction module to be at a conduction level during the power-on time period includes:
  • the external input voltage signal of the driving circuit is used as the noise reduction voltage signal during the power-on time period and is output to the noise reduction module.
  • the gate drive circuit includes a first noise reduction module and a second noise reduction module, the drive circuit further includes a level conversion circuit, and the level conversion circuit is configured to provide the first noise reduction module Providing a first noise reduction voltage signal to provide a second noise reduction voltage signal for the second noise reduction module;
  • the method also includes:
  • the determining whether it is in the power-on period according to the first noise reduction voltage signal and the second noise reduction voltage signal includes:
  • the controlling the gate drive circuit to output the gate cut-off level during the power-on period of the display panel includes:
  • the gate driving circuit is controlled to output a gate cut-off level.
  • FIG. 1 is a schematic diagram of a partial structure of a driving circuit of a display panel
  • FIG. 2 is a signal timing diagram of the driving circuit shown in FIG. 1;
  • 3 to 10 are schematic diagrams of the timing of each signal shown in FIG. 2;
  • FIG. 11 is a structural block diagram of an anti-flash screen circuit provided by an embodiment of the present disclosure.
  • FIG. 12 is a structural block diagram of an anti-flash screen circuit provided by an embodiment of the present disclosure.
  • FIG. 13 is a detailed structural diagram of an anti-flash screen circuit provided by an embodiment of the present disclosure.
  • FIG. 16 is a flowchart of a method for preventing flicker screen provided by an embodiment of the present disclosure.
  • the display includes a display panel and a drive circuit of the display panel.
  • the function of the display panel is to emit light to display images
  • the driving circuit is used to provide signals required for the display of the display panel, and the operation of the display panel is controlled by these signals.
  • the structure of the display panel is also different.
  • the display panel of the liquid crystal display includes an array substrate, a color filter substrate arranged in a box with the array substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate.
  • the array substrate includes gate lines and data lines. The gate lines and the data lines intersect to form a plurality of sub-pixel regions.
  • the sub-pixel regions are provided with pixel driving circuits, and the pixel driving circuits are used to control the corresponding pixel units to emit light.
  • the pixel drive circuit includes a thin film transistor (Thin Film Transistor, TFT).
  • the gate of the TFT is connected to a gate line, the source of the TFT is connected to the data line, and the drain of the TFT is connected to the pixel electrode. Control the on and off of the TFT, thereby controlling whether to write the signal of the data line to the pixel electrode.
  • the display may also be other types of displays such as organic light emitting diode displays.
  • the function of the driving circuit is to provide signals for the gate line and the data line to control the operation of the display panel.
  • the driving circuit usually includes a counter control register (Timer Control Register, TCON) circuit, a gate driving circuit, and a source driving circuit.
  • TCON Timer Control Register
  • the TCON circuit is used to provide a variety of voltage signals that support the operation of the gate drive circuit and the source drive circuit, such as the start signal (STV), the clock signal (CLK), the low level signal (VSS), and the noise reduction voltage signal (VDDO/VDDE), etc.
  • the gate drive circuit and source drive circuit use these signals output by the TCON circuit to generate gate drive signals and source drive signals, respectively.
  • the TCON circuit, the source drive circuit, and the gate drive circuit can be implemented using integrated circuit boards, respectively.
  • the gate drive circuit can adopt a shift register, that is, a gate on array (Gate On Array, GOA) manner to be set in the display panel, that is, a shift register unit (GOA unit) in the display panel is used as the gate. Pole drive circuit.
  • FIG. 1 is a schematic diagram of a part of the structure of a driving circuit.
  • the schematic diagram mainly shows the part of the TCON circuit related to gate driving, and does not show the part of the TCON circuit related to source driving (such as a gamma Gamma circuit).
  • the driving circuit includes a power management integrated circuit (Power Management IC, PMIC) 10, a level shift (L/S) circuit 30 and a TCON IC 30 (hereinafter referred to as TCON), and the L/S circuit 20 is respectively Electrically connected with PMIC 10 and TCON 30.
  • Power Management IC Power Management IC
  • L/S level shift
  • TCON TCON
  • PMIC 10 is used to output digital power signal (DVDD), analog power signal (AVDD), semi-analog power signal (HAVDD), gate high level signal (VGH), gate low level signal ( VGL) and other signals.
  • TCON 30 integrates a crystal oscillator, which can generate a clock signal CLKT (the low level of the clock signal is 0V, and the high level is 3.3V).
  • CLKT the low level of the clock signal is 0V, and the high level is 3.3V.
  • the L/S circuit 20 is used to generate STV, CLK, and CLK according to the signals output by the PMIC and TCON.
  • VSS, VDDO, VDDE, VGL, VGH and other signals are provided to the gate driving circuit 40.
  • the gate driving circuit 40 outputs a signal (Gout signal) to the gate line under the control of the signal output by the L/S circuit 20, and the Gout signal is VGL or VGH during the working period.
  • the VGL and VGH output by the L/S circuit 20 to the gate drive circuit 40 are the VGL and VGH output by the PMIC 10 to the L/S circuit 20.
  • the gate drive circuit 40 determines the display direction according to the level of the CLK signal. Which gate line of the panel outputs VGH and which gate line outputs VGL. It should be noted that, in addition to performing the gate driving function described above, TCON also needs to perform a source driving function, for example, demodulating the received data information and transmitting it to the source driving circuit.
  • the gate driving circuit 40 includes a plurality of cascaded GOA units.
  • the GOA unit usually consists of a plurality of switches (such as thin film transistors (TFT)) and capacitors (C), for example, 10 TFTs and A 10T2C circuit composed of 2 capacitors, or a circuit composed of more TFTs and capacitors.
  • a GOA unit usually includes an input module, a reset module, a noise reduction module, and an output module.
  • the input module outputs electrical signals to the output module according to the received output signal of the L/S circuit 20, and the output module outputs electrical signals according to the electrical output of the input module.
  • the signal outputs the gate conduction level or gate cut-off level to the display panel.
  • the noise reduction module is connected between the input module and the output module.
  • the gate drive circuit 40 may also include pull-up modules, pull-down modules, etc.
  • the noise reduction module plays the same role as the aforementioned GOA unit. Has the same effect.
  • the noise reduction module is controlled by the noise reduction voltage signal and works when the noise reduction voltage signal is at the on-level, so that the corresponding GOA unit outputs the gate cut-off level (VGL or VGH) to the gate line of the display panel, and the gate line connects the gate
  • VGL or VGH gate cut-off level
  • the extreme cut-off level is output to the connected TFT, which controls the TFT to be in the cut-off state.
  • the two noise reduction modules can work alternately, and the two noise reduction modules are controlled by VDDO and VDDE respectively, for example, two noise reduction modules.
  • the noise module is turned on when VDDO/VDDE is at a high level, pulling down the output of the gate drive circuit 40 to VGL, and at the same time achieving noise reduction. That is, the gate driving circuit 40 includes a first noise reduction module and a second noise reduction module, the first noise reduction module is controlled by the first noise reduction voltage signal, and the second noise reduction module is controlled by the second noise reduction voltage signal.
  • the noise reduction module works when the noise reduction voltage signal is high, and pulls the output of the gate drive circuit down to VGL, thereby controlling the TFT of the display panel to turn off, that is, controlling the display
  • the pixel drive circuit of the panel does not work.
  • the noise reduction voltage signal is at a low level, so the noise reduction module cannot be controlled to pull down the output of the gate drive circuit.
  • the gate drive circuit will have a leakage phenomenon (the output of the gate drive circuit has leakage current), and the leakage current will accumulate in the gate of the TFT in the display panel, causing the TFT in the display panel to turn on and the pixels of the display panel to emit light. , Causing a splash screen at startup.
  • Fig. 2 is a signal timing diagram of the driving circuit shown in Fig. 1, and Figs. 3-10 are timing diagrams of various signals shown in Fig. 2 respectively.
  • the PMIC 10 of the drive circuit first loads the Vin signal. After Vin is input, the PMIC 10 generates the DVDD signal.
  • the DVDD signal is used as the PMIC 10, the L/S circuit 20, and the TCON 30.
  • Working voltage, PMIC 10 and L/S circuit 20 generate other signals according to the working voltage.
  • the output Gout signal (close to 0V) of the gate drive circuit is higher than the VGL signal (that is, the gate cut-off signal).
  • VGL signal that is, the gate cut-off signal.
  • FIG. 11 is a structural block diagram of an anti-flash screen circuit provided by an embodiment of the present disclosure.
  • the anti-flash screen circuit 50 is applied to a driving circuit of a display panel, and the anti-flash screen circuit 50 includes:
  • the control sub-circuit 51 is configured to control the gate driving circuit 40 to output the gate-off level during the power-on period of the display panel.
  • the power-on time period refers to the period in which the driving circuit of the display panel is turned on and generates various driving signals under the action of the power supply.
  • the gate cut-off level refers to the level signal that controls the TFT in the display panel to be in the cut-off state, that is, the gate cut-off level is the electrical power that controls the pixel drive circuit in the display panel to not work, so that the corresponding pixel unit does not emit light. Flat signal.
  • the gate drive circuit of the display panel is controlled to output the gate cut-off level during the power-on period, and the gate cut-off level is provided to the TFT in the display panel, so that the TFT in the display panel is on the upper side.
  • the power period is in the cut-off state.
  • the pixel unit of the display panel will not emit light, which eliminates the phenomenon of booting flicker.
  • the gate drive circuit 40 includes a noise reduction module, and the noise reduction module is used to pull the output level of the gate drive circuit 40 to when the received noise reduction voltage signal is at the on level Gate cut-off level.
  • the control sub-circuit 51 is configured to control the noise reduction voltage signal output to the noise reduction module to a conduction level during the power-on period.
  • the conduction level can control the operation of the noise reduction module, and the output of the gate drive circuit 40 can be noise-reduced during the power-on period.
  • the module is pulled to the gate cut-off level.
  • the aforementioned noise reduction module includes a switch.
  • the switch is controlled by the noise reduction voltage signal.
  • the switch in the noise reduction module is driven to be turned on.
  • the switch of the noise reduction module in the gate drive circuit 40 When turned on, the gate driving circuit 40 outputs a gate off level to the TFT of the display panel.
  • the noise reduction module includes multiple TFTs, and the multiple TFTs play different roles.
  • the multiple TFTs at least one TFT functions as the aforementioned switch, that is, it is turned on or turned on under the control of the noise reduction voltage signal. disconnect.
  • the gate cut-off level may be the aforementioned VGL or VGH.
  • the gate cut-off level here is also different depending on the type of thin film transistor. For example, when the thin film transistor is an NMOS thin film transistor, the gate cut-off level is VGL, When the thin film transistor is a PMOS thin film transistor, the gate cut-off level is VGH.
  • control sub-circuit 51 is configured to use the external input voltage signal of the driving circuit (for example, Vin in FIG. 1) as the noise reduction voltage signal (VDDO/VDDE) during the power-on period. ), output to the noise reduction module.
  • VDDO/VDDE noise reduction voltage signal
  • the external input voltage signal Vin of the drive circuit is replaced by the noise reduction voltage signal of the noise reduction module and is output to the gate drive circuit during the power-on period, so that the control switch of the noise reduction module is It can be turned on and the noise reduction module works.
  • the external input voltage signal Vin provided to the driving circuit of the display panel is the first signal, it can be provided to the noise reduction module of the gate driving circuit during the power-on period.
  • the noise reduction voltage signal (VDDO/VDDE) is used to input the switch in the noise reduction module of the gate drive circuit 40 during the working period of the display panel. Reduce the operating voltage of the switch to achieve the purpose of noise reduction.
  • the noise reduction voltage signal (VDDO/VDDE) follows the low level of VGL, so it cannot turn on the noise reduction module in the gate drive circuit 40
  • the switch is turned on, and at the same time, the gate driving circuit 40 will have a leakage phenomenon, and the leakage will accumulate in the gate of the TFT in the display panel, and finally the TFT in the display panel can be turned on, resulting in a boot flash screen.
  • this application uses an input voltage signal (Vin) to replace the noise reduction voltage signal (VDDO/VDDE) during the power-on period.
  • the input voltage signal (Vin) is at a high level and can turn on the aforementioned noise reduction Switch in the module.
  • the switch of the gate drive circuit 40 can be turned on during the power-on period. , Output the VGL signal to the TFT in the display panel, keep the TFT in the display panel disconnected, and then there will be no flickering phenomenon.
  • the input voltage signal here can also be replaced by other signals other than Vin, as long as it is a high-level signal and exists before the power-on period, which is not limited in this application.
  • control sub-circuit 51 is configured to control the noise reduction voltage signal (VDDO/VDDE) to output to the noise reduction module, so that the gate driving circuit 40 can work normally during the working period.
  • VDDO/VDDE noise reduction voltage signal
  • the gate drive circuit 40 has two noise reduction modules, namely the first noise reduction module and the second noise reduction module.
  • the first noise reduction module is used to receive the level conversion circuit 20 during the working period of the display panel.
  • the output first noise reduction voltage signal the second noise reduction module is used to receive the second noise reduction voltage signal output by the level conversion circuit 20 during the working period of the display panel, that is, the level conversion circuit 20 is used for
  • the first noise reduction module provides a first noise reduction voltage signal
  • the second noise reduction module provides a second noise reduction voltage signal.
  • the working time period refers to the stage in which the display panel is working normally and displaying pictures. When the aforementioned power-on time period ends, the display panel enters the working time period.
  • FIG. 12 is a schematic structural diagram of an anti-flash screen circuit shown in an embodiment of the present disclosure.
  • the anti-flash screen circuit may further include: a determining sub-circuit 52 configured to determine whether it is in the power-on period according to the first noise reduction voltage signal and the second noise reduction voltage signal.
  • the gate drive circuit there are two types of noise reduction modules.
  • the noise reduction module which are the aforementioned VDDO and VDDE.
  • the two noise reduction voltages The voltages of the signals are equal during the power-on time period t1, but are not equal during the working time period t2. Therefore, it can be determined whether it is in the power-on time period by judging whether the voltages of the two noise reduction voltage signals are equal. If it is judged that it is in the power-on time period, the aforementioned solution is adopted to eliminate the flicker screen to ensure normal operation of the display panel.
  • the determining sub-circuit 52 is configured to determine whether the voltages of the first noise reduction voltage signal and the second noise reduction voltage signal are equal. As described above, it can be determined whether the voltages of the two noise reduction voltage signals are equal. It indicates whether it is in the power-on time period, and the voltages of the first noise reduction voltage signal and the second noise-reduction voltage signal are equal, indicating that they are in the power-on time period.
  • the control sub-circuit 51 is configured to control the gate driving circuit 40 to output the gate cut-off level when the voltages of the first noise reduction voltage signal and the second noise reduction voltage signal are equal.
  • the input terminal of the determining sub-circuit 52 is electrically connected to the output terminal of the L/S circuit 20 to obtain two noise reduction voltage signals (VDDO/VDDE) output by the L/S circuit 20.
  • the input terminal of the control sub-circuit 51 is electrically connected to the output terminal of the L/S circuit 20 to obtain two noise reduction voltage signals (such as VDDO/VDDE) output by the L/S circuit 20; at the same time, the input terminal of the control sub-circuit 51 It is also electrically connected to the input terminal of the PMIC 10 to obtain an external input voltage signal (for example, Vin).
  • VDDO/VDDE noise reduction voltage signals
  • the judgment result of the determining sub-circuit 52 can be represented by high and low levels. For example, if the determining sub-circuit 52 outputs a low level, it means that the voltage of the two noise reduction voltage signals is equal, and the determining sub-circuit 52 outputs a high level. The judgment result is that the two noise reduction voltage signals are not equal.
  • FIG. 13 is a detailed structural diagram of an anti-flash screen circuit provided by an embodiment of the present disclosure.
  • the determining sub-circuit 52 may include: a first comparator 521, a second comparator 522, and an OR gate 523.
  • the first comparator 521 and the second comparator 522 both include: a non-inverting input terminal (shown by "+” in the figure), an inverting input terminal (shown by "-” in the figure) and an output terminal; Both the non-inverting input terminal and the inverting input terminal of the second comparator 522 are electrically connected to the first noise reduction voltage signal output terminal of the L/S circuit 20, and receive the first noise reduction voltage signal output by the L/S circuit 20; The inverting input terminal of the comparator 521 and the non-inverting input terminal of the second comparator 522 are both electrically connected to the second noise reduction voltage signal output terminal of the L/S circuit 20, and receive the second noise reduction voltage output by the L/S circuit 20 signal.
  • the two input terminals of the OR gate 523 are electrically connected to the output terminals of the first comparator 521 and the second comparator 522 respectively, and the output terminal of the OR gate 523 is electrically connected to the control terminal of the control sub-circuit 51.
  • the voltages of the two input signals of the comparator are VIN+ (the voltage of the non-inverting input terminal signal) and VIN- (the voltage of the inverting input terminal signal), when VIN+>VIN-, output "1" (low level) , When VIN+ ⁇ VIN-, output "0" (high level). Therefore, when the voltages of the 2 noise reduction voltage signals are equal, the two comparators both output 0, and the OR gate output is 0; when the voltages of the 2 noise reduction voltage signals are not equal, the outputs of the two comparators are 0 respectively. And 1, the output of the OR gate is 1. The output of the OR gate indicates whether the voltages of the two noise reduction voltage signals are equal, so as to determine whether it is in the power-on period.
  • first comparator 521 and the second comparator 522 may be the same comparator.
  • the first comparator 521 and the second comparator 522 may be implemented by using differential amplifiers.
  • control sub-circuit 51 may include: a first selector 511 and a second selector 512.
  • the first selector 511 includes a control terminal, two input terminals and an output terminal.
  • the two input terminals of the first selector 511 are respectively electrically connected to the first noise reduction voltage signal output terminal of the L/S circuit 20 and the external input voltage signal input terminal of the PMIC 10 of the display panel.
  • the control terminal of the first selector 511 is electrically connected to the output terminal of the determining sub-circuit 52.
  • the first selector 511 is configured to output one of the first noise reduction voltage signal and the external input voltage signal through the output terminal of the first selector 511 under the control of the output signal of the determining sub-circuit 52.
  • the second selector 512 includes a control terminal, two input terminals and an output terminal.
  • the two input terminals of the second selector 512 are electrically connected to the second noise reduction voltage signal output terminal of the L/S circuit 20 and the external input voltage signal input terminal of the PMIC 10, respectively.
  • the control terminal of the second selector 512 is electrically connected to the output terminal of the determining sub-circuit 52; the second selector 512 is configured to output the second selector 512 through the output terminal of the second selector 512 under the control of the output signal of the determining sub-circuit 52 2.
  • the first noise reduction signal output terminal is used to output a first noise reduction voltage signal
  • the second noise reduction signal output terminal is used to output a second noise reduction voltage signal.
  • the first noise reduction voltage signal output terminal may be a VDDO noise reduction voltage signal output terminal
  • the second noise reduction voltage signal output terminal may be a VDDE noise reduction voltage signal output terminal.
  • the external input voltage signal input terminal is used to receive the external input voltage signal of the display panel.
  • two selectors are used to control the output of the two noise reduction voltage signals; when it is determined that the output of the sub-circuit indicates that the voltages of the two noise reduction voltage signals are equal, the selector selects the external input voltage signal of the drive circuit.
  • the output that is, the power-on time period, adopts Vin to control the operation of the noise reduction module; when it is determined that the output of the sub-circuit indicates that the two noise reduction voltage signals are not equal, the selector selects one of the two noise reduction voltage signals for output, that is VDDO and VDDE are respectively used to control the operation of the first noise reduction module and the second noise reduction module.
  • VDDO and VDDE is always high, and one of the noise reduction modules is kept working.
  • the first selector 511 and the second selector 512 may be the same selector. Since the first selector 511 and the second selector 512 are controlled by the output signal of the determining sub-circuit 52, they are triggered at a low level, that is, valid when the input "0" (low level) is input, and Vin is used as the output (that is, with high voltage). When inputting "1" (high level), it is invalid. VDDO/VDDE is used as output (that is, low level is used as output), so it can also be called a high and low level converter.
  • the Gout signal is the VGL signal, and the TFT in the display panel will be in an off state under the action of the Gout signal, and the display panel will not have flicker.
  • the Gout signal can be VGL or VGH, which is just an example here.
  • the embodiment of the present disclosure also provides a driving circuit for a display panel, the driving circuit includes a gate driving circuit and an anti-flash screen circuit as shown in any one of FIGS. 11 to 13.
  • the gate drive circuit of the display panel is controlled to output the gate cut-off level during the power-on period, and the gate cut-off level is provided to the gate line of the display panel so that the gate line in the display panel is connected
  • the pixel unit of the display panel will not emit light when the TFT in the display panel is in the off state, which eliminates the phenomenon of booting flicker.
  • the anti-flash screen circuit may be integrated on the logic board of the display, and the gate driving circuit may be a GOA unit on the display panel, or the gate driving circuit may be a separate integrated circuit.
  • the embodiments of the present disclosure also provide a display device, which includes the driving circuit as described above.
  • the display device provided by the embodiments of the present disclosure may be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the gate drive circuit of the display panel is controlled to output the gate cut-off level during the power-on period, and the gate cut-off level is provided to the TFT in the display panel, so that the TFT in the display panel is on the upper side.
  • the power period is in the cut-off state.
  • the pixel unit of the display panel will not emit light, which eliminates the phenomenon of booting flicker.
  • FIG. 16 is a flowchart of an anti-flash screen method provided by an embodiment of the present disclosure. The method is implemented by using the anti-flash screen circuit shown in any one of FIGS. 11 to 13 and is applied to a drive circuit of a display panel.
  • the circuit includes a gate drive circuit. See Figure 16.
  • the method includes:
  • Step 301 Control the gate driving circuit to output the gate cut-off level during the power-on period of the display panel.
  • the gate drive circuit of the display panel is controlled to output the gate cut-off level during the power-on period, and the gate cut-off level is provided to the TFT in the display panel, so that the TFT in the display panel is on the upper side.
  • the power period is in the cut-off state.
  • the pixel unit of the display panel will not emit light, which eliminates the phenomenon of booting flicker.
  • the gate drive circuit includes a noise reduction module, and the noise reduction module is used to be controlled by a noise reduction voltage signal.
  • the gate drive circuit When the noise reduction voltage signal is at a conduction level, the gate drive circuit The output level is pulled to the gate cut-off level.
  • controlling the gate drive circuit of the display panel to output the gate cut-off level during the power-on period of the display panel includes: controlling the noise reduction voltage signal output to the noise reduction module to the on-level during the power-up period .
  • controlling the noise reduction voltage signal output to the noise reduction module to the on-level during the power-on period includes: inputting an external voltage signal of the driving circuit during the power-on period As a noise reduction voltage signal, it is output to the noise reduction module.
  • the gate drive circuit includes a first noise reduction module and a second noise reduction module
  • the drive circuit further includes a level conversion circuit
  • the level conversion circuit is The first noise reduction module provides a first noise reduction voltage signal, and provides a second noise reduction voltage signal for the second noise reduction module. Accordingly, the first noise reduction module is used for receiving the first noise reduction voltage signal during the working period.
  • determining whether it is in the power-on period according to the first noise reduction voltage signal and the second noise reduction voltage signal includes: determining the first noise reduction voltage signal and the second noise reduction voltage signal Whether the voltages are equal, the voltages of the first noise reduction voltage signal and the second noise reduction voltage signal are equal, indicating that they are in the power-on period.
  • controlling the gate drive circuit of the display panel to output the gate cut-off level during the power-on period includes: controlling the gate drive circuit to output when the voltages of the first noise reduction voltage signal and the second noise reduction voltage signal are equal Gate cut-off level.
  • the method may further include: controlling the noise reduction voltage signal (VDDO/VDDE) to be output to the noise reduction module during the working period of the display panel, so that the gate driving circuit can be Normal work during working hours.
  • VDDO/VDDE noise reduction voltage signal

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Abstract

一种防闪屏电路及方法、用于显示面板的驱动电路、显示装置，属于显示技术领域。防闪屏电路包括：控制子电路(51)，被配置为在显示面板的上电时间段控制显示面板的栅极驱动电路(40)输出栅极截止电平。通过在上电时间段(t1)内控制显示面板的栅极驱动电路(40)输出栅极截止电平，栅极截止电平被提供给显示面板的栅线，使得栅线所连接的TFT在上电时间段(t1)处于截止状态，在显示面板中栅线所连接的TFT处于截止状态时，显示面板的像素单元不会发光，消除了开机闪屏现象。

Description

防闪屏电路及方法、用于显示面板的驱动电路、显示装置
本申请要求于2019年6月26日提交的申请号为201910561102.3、发明名称为“防闪屏电路及方法、驱动电路、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种防闪屏电路及方法、用于显示面板的驱动电路、显示装置。
背景技术
随着显示技术的发展和人民物质水平的提高，对显示器各方面的要求也越来越高。消除各种显示不良是提高显示器的产品质量的重要途径。显示不良包括液晶显示器的开机闪屏(也称闪白)现象。
发明内容
本公开实施例提供了一种防闪屏电路及方法、用于显示面板的驱动电路、显示装置。
一方面，本公开实施例提供了一种防闪屏电路，应用于显示面板的驱动电路，所述驱动电路包括栅极驱动电路，所述防闪屏电路包括：
控制子电路，被配置为在所述显示面板的上电时间段控制所述栅极驱动电路输出栅极截止电平。
可选地，所述栅极驱动电路包括降噪模块，所述降噪模块用于在接收到的降噪电压信号为导通电平时，将所述栅极驱动电路的输出电平拉至所述栅极截止电平；
所述控制子电路，被配置为在所述上电时间段控制输出到所述降噪模块的所述降噪电压信号为所述导通电平。
可选地，所述控制子电路，被配置为在所述上电时间段将所述驱动电路的外部输入电压信号作为所述降噪电压信号，输出到所述降噪模块。
可选地，所述栅极驱动电路包括第一降噪模块和第二降噪模块，所述驱动 电路还包括电平转换电路，所述电平转换电路用于为所述第一降噪模块提供第一降噪电压信号，为所述第二降噪模块提供第二降噪电压信号；
所述防闪屏电路还包括：确定子电路，被配置为根据所述第一降噪电压信号和所述第二降噪电压信号确定是否处于所述上电时间段。
可选地，所述确定子电路，被配置为判断所述第一降噪电压信号和所述第二降噪电压信号的电压是否相等，所述第一降噪电压信号和第二降噪电压信号的电压相等，表示处于上电时间段；
所述控制子电路，被配置为在所述第一降噪电压信号和所述第二降噪电压信号的电压相等时，控制所述栅极驱动电路输出栅极截止电平。
可选地，所述确定子电路包括：
第一比较器和第二比较器，所述第一比较器和第二比较器均包括：同相输入端、反相输入端和输出端；所述第一比较器的同相输入端和所述第二比较器的反相输入端均与所述电平转换电路的第一降噪电压信号输出端电连接；所述第一比较器的反相输入端和所述第二比较器的同相输入端均与所述电平转换电路的第二降噪电压信号输出端电连接；
或门，所述或门的两个输入端分别与所述第一比较器的输出端和第二比较器的输出端电连接，所述或门的输出端与所述控制子电路的控制端电连接；
其中，所述第一降噪信号输出端用于输出所述第一降噪电压信号，所述第二降噪信号输出端用于输出所述第二降噪电压信号。
可选地，所述控制子电路包括：
第一选择器，所述第一选择器的两个输入端分别与所述电平转换电路的第一降噪电压信号输出端和所述显示面板的电源管理集成电路的外部输入电压信号输入端电连接；所述第一选择器的控制端与所述确定子电路的输出端电连接；所述第一选择器被配置为在所述确定子电路的输出信号的控制下，通过所述第一选择器的输出端输出所述第一降噪电压信号和所述外部输入电压信号中的一个；
第二选择器，所述第二选择器的两个输入端分别与所述电平转换电路的第二降噪电压信号输出端和所述电源管理集成电路的外部输入电压信号输入端电连接；所述第二选择器的控制端与所述确定子电路的输出端电连接；所述第二选择器被配置为在所述确定子电路的输出信号的控制下，通过所述第二选择器的输出端输出所述第二降噪电压信号和所述外部输入电压信号中的一个；
其中，所述外部输入电压信号输入端用于接收提供给所述显示面板的驱动电路的外部输入电压信号。
另一方面，本公开实施例提供了一种用于显示面板的驱动电路，所述驱动电路包括如前任一项所述的防闪屏电路。
另一方面，本公开实施例提供了一种显示装置，所述显示装置包括如前所述的驱动电路。
另一方面，本公开实施例提供了一种防闪屏方法，应用于显示面板的驱动电路，所述驱动电路包括栅极驱动电路，所述方法包括：
在所述显示面板的上电时间段控制所述栅极驱动电路输出栅极截止电平。
可选地，所述栅极驱动电路包括降噪模块，所述降噪模块用于在接收到的降噪电压信号为导通电平时，将所述栅极驱动电路的输出电平拉至所述栅极截止电平；
所述在所述显示面板的上电时间段控制所述栅极驱动电路输出栅极截止电平，包括：
在所述上电时间段控制输出到所述降噪模块的所述降噪电压信号为导通电平。
可选地，所述在所述上电时间段控制输出到所述降噪模块的所述降噪电压信号为导通电平，包括：
在所述上电时间段将所述驱动电路的外部输入电压信号作为所述降噪电压信号，输出到所述降噪模块。
可选地，所述栅极驱动电路包括第一降噪模块和第二降噪模块，所述驱动电路还包括电平转换电路，所述电平转换电路用于为所述第一降噪模块提供第一降噪电压信号，为所述第二降噪模块提供第二降噪电压信号；
所述方法还包括：
根据所述第一降噪电压信号和所述第二降噪电压信号确定是否处于所述上电时间段。
可选地，所述根据所述第一降噪电压信号和所述第二降噪电压信号确定是否处于所述上电时间段，包括：
判断所述第一降噪电压信号和所述第二降噪电压信号的电压是否相等，所述第一降噪电压信号和第二降噪电压信号的电压相等，表示处于上电时间段；
所述在所述显示面板的上电时间段控制所述栅极驱动电路输出栅极截止电平，包括：
在所述第一降噪电压信号和所述第二降噪电压信号的电压相等时，控制所述栅极驱动电路输出栅极截止电平。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是一种显示面板的驱动电路的部分结构示意图；
图2是图1所示驱动电路的信号时序图；
图3～图10分别是图2所示各路信号的时序示意图；
图11是本公开实施例提供的一种防闪屏电路的结构框图；
图12是本公开实施例提供的一种防闪屏电路的结构框图；
图13是本公开实施例提供的一种防闪屏电路的详细结构示意图；
图14～图15是采用本申请提供的防闪屏电路后的驱动电路的信号时序图；
图16是本公开实施例提供的一种防闪屏方法的流程图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
为了便于理解对本申请提供的方案，下面先对显示器进行简单说明：
显示器包括显示面板和该显示面板的驱动电路。其中，显示面板的作用是发光显示图像，驱动电路用于提供显示面板显示所需的信号，通过这些信号控制显示面板的工作。
对于不同类型的显示器，显示面板的结构也有所不同。以液晶显示器为例，液晶显示器的显示面板包括阵列基板、与阵列基板对盒设置的彩膜基板以及夹设在阵列基板和彩膜基板之间的液晶层。阵列基板包括栅线和数据线，栅线与 数据线交叉构成多个子像素区域，子像素区域中设置有像素驱动电路，像素驱动电路用于控制对应的像素单元发光。示例性地，像素驱动电路包括一个薄膜晶体管(Thin Film Transistor，TFT)，该TFT的栅极连接栅线，该TFT的源极连接数据线，该TFT的漏极连接像素电极，通过栅线能够控制该TFT的通断，从而控制是否将数据线的信号写入像素电极。这里，显示器除了液晶显示器外，还可以是有机发光二极管显示器等其他类型显示器。
驱动电路的作用是为栅线和数据线提供信号，从而控制显示面板工作。驱动电路通常包括计数器控制寄存器(Timer Control Register，TCON)电路、栅极驱动电路和源极驱动电路。其中，TCON电路用于提供支持栅极驱动电路和源极驱动电路工作的多种电压信号，如起始信号(STV)、时钟信号(CLK)、低电平信号(VSS)、降噪电压信号(VDDO/VDDE)等，栅极驱动电路和源极驱动电路采用TCON电路输出的这些信号，分别生成栅极驱动信号和源极驱动信号。
可选地，TCON电路、源极驱动电路和栅极驱动电路可以分别采用集成电路板实现。此外，栅极驱动电路可以采用移位寄存器，也即阵列上栅极(Gate On Array，GOA)的方式设置在显示面板中，也即采用显示面板中的移位寄存器单元(GOA单元)作为栅极驱动电路。
图1是一种驱动电路的部分结构示意图，该示意图主要示出了与栅极驱动相关的TCON电路部分，未示出与源极驱动相关的TCON电路部分(如伽马Gamma电路)。参见图1，该驱动电路包括电源管理集成电路(Power Management IC，PMIC)10、电平转换(Level Shift，L/S)电路30和TCON IC 30(以下简称TCON)，L/S电路20分别与PMIC 10和TCON 30电连接。
其中，PMIC 10用于根据输入信号Vin输出数字电源信号(DVDD)、模拟电源信号(AVDD)、半模拟电源信号(HAVDD)、栅极高电平信号(VGH)、栅极低电平信号(VGL)等信号。TCON 30内部集成了晶振，能够产生时钟信号CLKT(该时钟信号的低电平为0V、高电平为3.3V)，L/S电路20用于根据PMIC和TCON输出的信号生成STV、CLK、VSS、VDDO、VDDE、VGL、VGH等信号并提供给栅极驱动电路40。栅极驱动电路40在L/S电路20输出的信号控制下输出信号(Gout信号)给栅线，该Gout信号在工作时间段为VGL或VGH。这里，L/S电路20输出给栅极驱动电路40的VGL和VGH就是PMIC 10输出给L/S电路20的VGL和VGH，栅极驱动电路40根据CLK信号的电平高低， 来确定向显示面板的哪根栅线输出VGH，哪根栅线输出VGL。需要说明的是，TCON除了执行上述栅极驱动的功能外，还需要执行源极驱动功能，例如将接收到的数据信息解调出来传输给源极驱动电路。
示例性地，栅极驱动电路40包括多个级联的GOA单元，GOA单元通常由多个开关(如薄膜晶体管(Thin Film Transistor，TFT))和电容(C)组成，例如采用10个TFT和2个电容组成的10T2C电路，或者更多TFT和电容组成的电路。一个GOA单元通常包括输入模块、复位模块、降噪模块和输出模块等，其中，输入模块根据接收到的L/S电路20的输出信号向输出模块输出电信号，输出模块根据输入模块输出的电信号向显示面板输出栅极导通电平或栅极截止电平，降噪模块连接在输入模块和输出模块之间，在降噪模块工作时可以保持输出模块输入端的电压，使输出模块输出栅极截止电平。栅极驱动电路40除了包括上述模块外，还可以包括上拉模块、下拉模块等，在包括上拉模块和下拉模块的GOA单元中，降噪模块所起的作用与在前述GOA单元中所起的作用相同。
降噪模块通过降噪电压信号控制，在降噪电压信号为导通电平时工作，使得对应的GOA单元输出栅极截止电平(VGL或VGH)给显示面板的栅线，栅线将该栅极截止电平输出给所连接的TFT，控制该TFT处于截止状态。
值得说明的是，在栅极驱动电路40的一个GOA单元中，降噪模块通常有2个，2个降噪模块可以交替工作，2个降噪模块分别通过VDDO和VDDE控制，例如2个降噪模块在VDDO/VDDE高电平时导通，拉低栅极驱动电路40的输出到VGL，同时实现降噪。也即是，栅极驱动电路40包括第一降噪模块和第二降噪模块，第一降噪模块通过第一降噪电压信号控制，第二降噪模块通过第二降噪电压信号控制。
以高电平为导通电平为例，降噪模块在降噪电压信号为高电平时工作，将栅极驱动电路的输出拉低至VGL，从而控制显示面板的TFT断开，即控制显示面板的像素驱动电路不工作。相关技术中，在显示面板的上电时间段，降噪电压信号为低电平，所以无法控制降噪模块拉低栅极驱动电路的输出。而同时，栅极驱动电路会存在漏电现象(栅极驱动电路的输出存在漏电流)，漏电流在显示面板内的TFT的栅极累积，导致显示面板内的TFT导通，显示面板的像素发光，造成开机闪屏。
图2是图1所示驱动电路的信号时序图，图3～图10分别是图2所示各路信 号的时序示意图。参见图2～图10，在上电时间段t1内，驱动电路的PMIC 10首先加载Vin信号，Vin输入后PMIC 10产生DVDD信号，DVDD信号作为PMIC 10、L/S电路20和TCON 30等的工作电压，PMIC 10和L/S电路20根据该工作电压生成其他信号。
如图2～图10所示，在上电时间段t1，栅极驱动电路的输出Gout信号(接近0V)高于VGL信号(即栅极截止信号)，显示面板内的TFT在Gout信号的作用下会处于一定的导通状态，在后续像素电极有电荷后会导致像素发光，出现闪屏现象。
图11是本公开实施例提供的一种防闪屏电路的结构框图。参见图11，该防闪屏电路50应用于显示面板的驱动电路，该防闪屏电路50包括：
控制子电路51，被配置为在显示面板的上电时间段控制栅极驱动电路40输出栅极截止电平。
在本公开实施例中，上电时间段是指显示面板的驱动电路接通电源，并在电源作用下产生各种驱动信号的阶段。栅极截止电平是指控制显示面板内TFT处于截止状态的电平信号，也即是，栅极截止电平是控制显示面板内的像素驱动电路不工作，使得对应的像素单元不发光的电平信号。
在该方案中，通过在上电时间段内控制显示面板的栅极驱动电路输出栅极截止电平，该栅极截止电平被提供给显示面板内的TFT，使得显示面板内的TFT在上电时间段处于截止状态，在显示面板中的TFT处于截止状态时，显示面板的像素单元不会发光，消除了开机闪屏现象。
在一种可能的实施方式中，栅极驱动电路40包括降噪模块，降噪模块用于在接收到的降噪电压信号为导通电平时，将栅极驱动电路40的输出电平拉至栅极截止电平。控制子电路51，被配置为在上电时间段控制输出到降噪模块的降噪电压信号为导通电平。
通过在上电时间段内向栅极驱动电路40的降噪模块提供导通电平，该导通电平可以控制降噪模块工作，栅极驱动电路40的输出可以在上电时间段被降噪模块拉至栅极截止电平。
前述降噪模块中包括开关，该开关受到降噪电压信号控制，当降噪电压信号为导通电平时，驱动降噪模块中的开关导通，在栅极驱动电路40中降噪模块的开关导通时，栅极驱动电路40向显示面板的TFT输出栅极截止电平。例如， 降噪模块包括多个TFT，这多个TFT所起的作用不同，在这多个TFT中，至少一个TFT的作用是作为前述开关，也即在降噪电压信号的控制下导通或断开。
这里，栅极截止电平可以为前述VGL或者VGH，根据薄膜晶体管的类型不同，这里的栅极截止电平也不同，例如当薄膜晶体管为NMOS薄膜晶体管时，该栅极截止电平为VGL，当薄膜晶体管为PMOS薄膜晶体管时，该栅极截止电平为VGH。
在本公开实施例的一种实现方式中，控制子电路51，被配置为在上电时间段将驱动电路的外部输入电压信号(例如图1中的Vin)作为降噪电压信号(VDDO/VDDE)，输出到降噪模块。
在该实现方式中，通过在上电时间段将驱动电路的外部输入电压信号Vin代替降噪模块的降噪电压信号输出给栅极驱动电路，使得在上电时间段，降噪模块的控制开关能够导通，降噪模块工作。这里，由于提供给显示面板的驱动电路的外部输入电压信号Vin是最先存在的信号，所以可以在上电时间段提供给栅极驱动电路的降噪模块。
以显示面板的栅线所连接的开关采用NMOS薄膜晶体管为例，降噪电压信号(VDDO/VDDE)用于在显示面板工作时间段输入给栅极驱动电路40的降噪模块中的开关，以降低开关的工作电压，从而达到降噪的目的。但根据图2所示的时序图可知，在上电时间段，该降噪电压信号(VDDO/VDDE)是跟随VGL的低电平，所以无法导通栅极驱动电路40内降噪模块中的开关导通，同时，栅极驱动电路40会存在漏电现象，漏电在显示面板内的TFT的栅极累积，最终能够导通显示面板内的TFT，造成开机闪屏。为了避免出现闪屏，本申请在上电时间段通过采用输入电压信号(Vin)替代降噪电压信号(VDDO/VDDE)，该输入电压信号(Vin)为高电平，能够导通前述降噪模块中的开关。而通过在上电时间段将显示面板的外部输入电压信号代替栅极驱动电路的降噪电压信号输出给栅极驱动电路40，使得在上电时间段，栅极驱动电路40的开关能够导通，输出VGL信号给显示面板内的TFT，保持显示面板内的TFT断开，进而不会出现闪屏现象。
当然，这里的输入电压信号也可以采用Vin外的其他信号替代，只要是高电平信号且在上电时间段之前存在即可，本申请对此不做限制。
而在显示面板工作时间段，该控制子电路51，被配置为控制降噪电压信号(VDDO/VDDE)输出到降噪模块，从而使得栅极驱动电路40能够在工作时间 段正常工作。
如前所述，栅极驱动电路40具有两种降噪模块，即第一降噪模块和第二降噪模块，第一降噪模块用于在显示面板的工作时间段接收电平转换电路20输出的第一降噪电压信号，第二降噪模块用于在显示面板的工作时间段接收电平转换电路20输出的第二降噪电压信号，也即是，电平转换电路20用于为第一降噪模块提供第一降噪电压信号，为第二降噪模块提供第二降噪电压信号。这里，工作时间段是指显示面板正常工作，显示画面的阶段，当前述上电时间段结束时，显示面板即进入工作时间段。
图12是本公开实施例示出的一种防闪屏电路的结构示意图。参见图12，该防闪屏电路还可以包括：确定子电路52，被配置为根据第一降噪电压信号和第二降噪电压信号确定是否处于上电时间段。
在栅极驱动电路中，降噪模块有2种，相应地，提供给降噪模块的降噪电压信号有两路，分别为前述VDDO和VDDE，根据图2的时序可知，两路降噪电压信号的电压在上电时间段t1相等，而在工作时间段t2不等，因此，通过判断两路降噪电压信号的电压是否相等即可确定是否处于上电时间段。如果判断处于上电时间段，则采用前述方案消除闪屏，保证显示面板的正常工作。
示例性地，确定子电路52，被配置为判断第一降噪电压信号和第二降噪电压信号的电压是否相等，如前所述，根据两路降噪电压信号的电压是否相等，可以确定出是否处于上电时间段，第一降噪电压信号和第二降噪电压信号的电压相等，表示处于上电时间段。相应地，控制子电路51，被配置为在第一降噪电压信号和第二降噪电压信号的电压相等时，控制栅极驱动电路40输出栅极截止电平。
这里，确定子电路52的输入端与L/S电路20的输出端电连接，以获取L/S电路20输出的两路降噪电压信号(VDDO/VDDE)。
而控制子电路51的输入端与L/S电路20的输出端电连接，以获取L/S电路20输出的两路降噪电压信号(例如VDDO/VDDE)；同时控制子电路51的输入端还与PMIC 10的输入端电连接，以获取外部输入电压信号(例如Vin)。
这里，确定子电路52的判断结果可以采用高低电平表示，例如确定子电路52输出低电平则表示判断结果为两路降噪电压信号的电压相等，确定子电路52输出高电平则表示判断结果为两路降噪电压信号不等。
图13是本公开实施例提供的一种防闪屏电路的详细结构示意图，参见图13， 确定子电路52可以包括：第一比较器521、第二比较器522和或门523。
第一比较器521和第二比较器522均包括：同相输入端(图中“+”所示)、反相输入端(图中“-”所示)和输出端；第一比较器521的同相输入端和第二比较器522的反相输入端均与L/S电路20的第一降噪电压信号输出端电连接，接收L/S电路20输出的第一降噪电压信号；第一比较器521的反相输入端和第二比较器522的同相输入端均与L/S电路20的第二降噪电压信号输出端电连接，接收L/S电路20输出的第二降噪电压信号。
或门523的两个输入端分别与第一比较器521和第二比较器522的输出端电连接，或门523的输出端与控制子电路51的控制端电连接。
假设比较器的两个输入信号的电压分别为VIN+(同相输入端信号的电压)和VIN-(反相输入端信号的电压)，当VIN+＞VIN-时，输出“1”(低电平)，当VIN+≤VIN-时，输出“0”(高电平)。所以，当2路降噪电压信号的电压相等时，两个比较器均输出0，或门输出为0；当2路降噪电压信号的电压不相等时，两个比较器的输出分别为0和1，或门输出为1。通过或门的输出来表示两路降噪电压信号的电压是否相等，从而确定出是否处于上电时间段。
其中，第一比较器521和第二比较器522可以为相同的比较器。第一比较器521和第二比较器522可以采用差分放大器实现。
再次参见图13，控制子电路51可以包括：第一选择器511和第二选择器512。
第一选择器511包括：控制端、两个输入端和输出端。第一选择器511的两个输入端分别与L/S电路20的第一降噪电压信号输出端和显示面板的PMIC10的外部输入电压信号输入端电连接。第一选择器511的控制端与确定子电路52的输出端电连接。第一选择器511被配置为在确定子电路52的输出信号的控制下，通过第一选择器511的输出端输出第一降噪电压信号和外部输入电压信号中的一个。
第二选择器512包括：控制端、两个输入端和输出端。第二选择器512的两个输入端分别与L/S电路20的第二降噪电压信号输出端和PMIC 10的外部输入电压信号输入端电连接。第二选择器512的控制端与确定子电路52的输出端电连接；第二选择器512被配置为在确定子电路52的输出信号的控制下，通过第二选择器512的输出端输出第二降噪电压信号和外部输入电压信号中的一个。
其中，第一降噪信号输出端用于输出第一降噪电压信号，第二降噪信号输 出端用于输出第二降噪电压信号。例如，第一降噪电压信号输出端可以为VDDO降噪电压信号输出端，第二降噪电压信号输出端可以为VDDE降噪电压信号输出端。外部输入电压信号输入端用于接收显示面板的外部输入电压信号。
在该实现方式中，通过2个选择器来控制两路降噪电压信号的输出；在确定子电路输出表示两路降噪电压信号的电压相等时，选择器选择驱动电路的外部输入电压信号进行输出，也即上电时间段，采用Vin控制降噪模块工作；在确定子电路输出表示两路降噪电压信号不等时，选择器选择两路降噪电压信号中的一路进行输出，也即分别采用VDDO和VDDE控制第一降噪模块和第二降噪模块工作，VDDO和VDDE中始终有1个为高电平，保持其中一个降噪模块工作。上述方案实现了在开机时消除闪屏，在工作时保证显示面板正常工作。
其中，第一选择器511和第二选择器512可以为相同的选择器。由于第一选择器511和第二选择器512是受确定子电路52的输出信号控制，低电平触发，即输入“0”(低电平)时有效，采用Vin作为输出(即以高电平作为输出)，输入“1”(高电平)时无效，采用VDDO/VDDE作为输出(即以低电平作为输出)，所以也可以被称为高低电平转换器。
结合图13所示的详细结构可知，本申请在消除开机闪屏时，仅在原有电路的基础上，增加比较器、门电路和选择器，电路设计简单，成本低。同时，该方案通用性好，可以用于现有的各种显示器的驱动电路中。
图14和图15是采用本申请提供的防闪屏电路后驱动电路的信号时序图。参见图14和图15，在采用防闪屏电路后，在上电时间段t1，Gout信号为VGL信号，显示面板内的TFT在Gout信号的作用下会处于截止状态，显示面板不发生闪屏。在上电时间段t1，Gout信号可以为VGL，也可以为VGH，这里仅仅是一种示例。
本公开实施例还提供了一种用于显示面板的驱动电路，所述驱动电路包括栅极驱动电路和如图11～图13任一所示的防闪屏电路。
在该方案中，通过在上电时间段内控制显示面板的栅极驱动电路输出栅极截止电平，该栅极截止电平被提供给显示面板的栅线，使得显示面板内栅线所连接的TFT在上电时间段处于截止状态，在显示面板中的TFT处于截止状态时，显示面板的像素单元不会发光，消除了开机闪屏现象。
可选地，防闪屏电路可以集成在显示器的逻辑板上，栅极驱动电路可以为 显示面板上的GOA单元，或者，栅极驱动电路可以为单独的集成电路。
本公开实施例还提供了一种显示装置，所述显示装置包括如前所述的驱动电路。
在本公开实施例中，本公开实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在该方案中，通过在上电时间段内控制显示面板的栅极驱动电路输出栅极截止电平，该栅极截止电平被提供给显示面板内的TFT，使得显示面板内的TFT在上电时间段处于截止状态，在显示面板中的TFT处于截止状态时，显示面板的像素单元不会发光，消除了开机闪屏现象。
图16是本公开实施例提供的一种防闪屏方法的流程图，该方法采用前述图11～图13任一项所示的防闪屏电路实现，应用于显示面板的驱动电路，该驱动电路包括栅极驱动电路，参见图16，该方法包括：
步骤301：在显示面板的上电时间段控制栅极驱动电路输出栅极截止电平。
在该方案中，通过在上电时间段内控制显示面板的栅极驱动电路输出栅极截止电平，该栅极截止电平被提供给显示面板内的TFT，使得显示面板内的TFT在上电时间段处于截止状态，在显示面板中的TFT处于截止状态时，显示面板的像素单元不会发光，消除了开机闪屏现象。
在本公开实施例的一种实现方式中，栅极驱动电路包括降噪模块，降噪模块用于受降噪电压信号的控制，在降噪电压信号为导通电平时，将栅极驱动电路的输出电平拉至栅极截止电平。相应地，在显示面板的上电时间段控制显示面板的栅极驱动电路输出栅极截止电平，包括：在该上电时间段控制输出到降噪模块的降噪电压信号为导通电平。
在本公开实施例的一种实现方式中，在该上电时间段控制输出到降噪模块的降噪电压信号为导通电平，包括：在上电时间段将驱动电路的外部输入电压信号作为降噪电压信号，输出到降噪模块。
在本公开实施例的一种实现方式中，栅极驱动电路包括第一降噪模块和第二降噪模块，所述驱动电路还包括电平转换电路，所述电平转换电路用于为所述第一降噪模块提供第一降噪电压信号，并为所述第二降噪模块提供第二降噪 电压信号，相应地，第一降噪模块用于在工作时间段受第一降噪电压信号的控制，第二降噪模块在工作时间段受第二降噪电压信号的控制。该方法还包括：根据第一降噪电压信号和第二降噪电压信号确定是否处于上电时间段。
在本公开实施例的一种实现方式中，根据第一降噪电压信号和第二降噪电压信号确定是否处于上电时间段，包括：判断第一降噪电压信号和第二降噪电压信号的电压是否相等，第一降噪电压信号和第二降噪电压信号的电压相等，表示处于上电时间段。相应地，在上电时间段控制显示面板的栅极驱动电路输出栅极截止电平，包括：在第一降噪电压信号和第二降噪电压信号的电压相等时，控制栅极驱动电路输出栅极截止电平。
在本公开实施例的一种实现方式中，该方法还可以包括：在显示面板的工作时间段，控制降噪电压信号(VDDO/VDDE)输出到降噪模块，从而使得栅极驱动电路能够在工作时间段正常工作。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种防闪屏电路，应用于显示面板的驱动电路，所述驱动电路包括栅极驱动电路，所述防闪屏电路包括：
    控制子电路(51)，被配置为在所述显示面板的上电时间段控制所述栅极驱动电路(40)输出栅极截止电平。
  2. 根据权利要求1所述的防闪屏电路，其中，所述栅极驱动电路(40)包括降噪模块，所述降噪模块用于在接收到的降噪电压信号为导通电平时，将所述栅极驱动电路(40)的输出电平拉至所述栅极截止电平；
    所述控制子电路(51)，被配置为在所述上电时间段控制输出到所述降噪模块的所述降噪电压信号为所述导通电平。
  3. 根据权利要求2所述的防闪屏电路，其中，所述控制子电路(51)，被配置为在所述上电时间段将所述驱动电路的外部输入电压信号作为所述降噪电压信号，输出到所述降噪模块。
  4. 根据权利要求1至3任一项所述的防闪屏电路，其中，所述栅极驱动电路(40)包括第一降噪模块和第二降噪模块，所述驱动电路还包括电平转换电路(20)，所述电平转换电路(20)用于为所述第一降噪模块提供第一降噪电压信号，为所述第二降噪模块提供第二降噪电压信号；
    所述防闪屏电路还包括：确定子电路(52)，被配置为根据所述第一降噪电压信号和所述第二降噪电压信号确定是否处于所述上电时间段。
  5. 根据权利要求4所述的防闪屏电路，其中，所述确定子电路(52)，被配置为判断所述第一降噪电压信号和所述第二降噪电压信号的电压是否相等，所述第一降噪电压信号和第二降噪电压信号的电压相等，表示处于所述上电时间段；
    所述控制子电路(51)，被配置为在所述第一降噪电压信号和所述第二降噪电压信号的电压相等时，控制所述栅极驱动电路(40)输出所述栅极截止电平。
  6. 根据权利要求5所述的防闪屏电路，其中，所述确定子电路(52)包括：
    第一比较器(521)和第二比较器(522)，所述第一比较器(521)和第二比较器(522)均包括：同相输入端、反相输入端和输出端；所述第一比较器(521)的同相输入端和所述第二比较器(522)的反相输入端均与所述电平转换电路(20)的第一降噪电压信号输出端电连接；所述第一比较器(521)的反相输入 端和所述第二比较器(522)的同相输入端均与所述电平转换电路(20)的第二降噪电压信号输出端电连接；
    或门(523)，所述或门(523)的两个输入端分别与所述第一比较器(521)的输出端和第二比较器(522)的输出端电连接，所述或门(523)的输出端与所述控制子电路(51)的控制端电连接；
    其中，所述第一降噪信号输出端用于输出所述第一降噪电压信号，所述第二降噪信号输出端用于输出所述第二降噪电压信号。
  7. 根据权利要求4至6任一项所述的防闪屏电路，其中，所述控制子电路(51)包括：
    第一选择器(511)，所述第一选择器(511)的两个输入端分别与所述电平转换电路(20)的第一降噪电压信号输出端和所述显示面板的电源管理集成电路(10)的外部输入电压信号输入端电连接；所述第一选择器(511)的控制端与所述确定子电路(52)的输出端电连接；所述第一选择器(511)被配置为在所述确定子电路(52)的输出信号的控制下，通过所述第一选择器(511)的输出端输出所述第一降噪电压信号和所述外部输入电压信号中的一个；
    第二选择器(512)，所述第二选择器(512)的两个输入端分别与所述电平转换电路(20)的第二降噪电压信号输出端和所述电源管理集成电路(10)的外部输入电压信号输入端电连接；所述第二选择器(512)的控制端与所述确定子电路(52)的输出端电连接；所述第二选择器(512)被配置为在所述确定子电路(52)的输出信号的控制下，通过所述第二选择器(512)的输出端输出所述第二降噪电压信号和所述外部输入电压信号中的一个；
    其中，所述外部输入电压信号输入端用于接收提供给所述显示面板的驱动电路的外部输入电压信号。
  8. 一种用于显示面板的驱动电路，包括栅极驱动电路和防闪屏电路，其中，所述防闪屏电路包括：
    控制子电路(51)，被配置为在所述显示面板的上电时间段控制所述栅极驱动电路(40)输出栅极截止电平。
  9. 根据权利要求8所述的驱动电路，其中，所述栅极驱动电路(40)包括降噪模块，所述降噪模块用于在接收到的降噪电压信号为导通电平时，将所述 栅极驱动电路(40)的输出电平拉至所述栅极截止电平；
    所述控制子电路(51)，被配置为在所述上电时间段控制输出到所述降噪模块的所述降噪电压信号为所述导通电平。
  10. 根据权利要求9所述的驱动电路，其中，所述控制子电路(51)，被配置为在所述上电时间段将所述驱动电路的外部输入电压信号作为所述降噪电压信号，输出到所述降噪模块。
  11. 根据权利要求8至10任一项所述的驱动电路，其中，所述栅极驱动电路(40)包括第一降噪模块和第二降噪模块，所述驱动电路还包括电平转换电路(20)，所述电平转换电路(20)用于为所述第一降噪模块提供第一降噪电压信号，为所述第二降噪模块提供第二降噪电压信号；
    所述防闪屏电路还包括：确定子电路(52)，被配置为根据所述电平转换电路(20)提供的所述第一降噪电压信号和所述第二降噪电压信号确定是否处于所述上电时间段。
  12. 根据权利要求11所述的驱动电路，其中，所述确定子电路(52)，被配置为判断所述第一降噪电压信号和所述第二降噪电压信号的电压是否相等，所述第一降噪电压信号和第二降噪电压信号的电压相等，表示处于所述上电时间段；
    所述控制子电路(51)，被配置为在所述第一降噪电压信号和所述第二降噪电压信号的电压相等时，控制所述栅极驱动电路(40)输出所述栅极截止电平。
  13. 根据权利要求12所述的驱动电路，其中，所述确定子电路(52)包括：
    第一比较器(521)和第二比较器(522)，所述第一比较器(521)和第二比较器(522)均包括：同相输入端、反相输入端和输出端；所述第一比较器(521)的同相输入端和所述第二比较器(522)的反相输入端均与所述电平转换电路(20)的第一降噪电压信号输出端电连接；所述第一比较器(521)的反相输入端和所述第二比较器(522)的同相输入端均与所述电平转换电路(20)的第二降噪电压信号输出端电连接；
    或门(523)，所述或门(523)的两个输入端分别与所述第一比较器(521)的输出端和第二比较器(522)的输出端电连接，所述或门(523)的输出端与所述控制子电路(51)的控制端电连接；
    其中，所述第一降噪信号输出端用于输出所述第一降噪电压信号，所述第 二降噪信号输出端用于输出所述第二降噪电压信号。
  14. 根据权利要求13所述的驱动电路，其中，所述控制子电路(51)包括：
    第一选择器(511)，所述第一选择器(511)的两个输入端分别与所述电平转换电路(20)的第一降噪电压信号输出端和所述显示面板的电源管理集成电路(10)的外部输入电压信号输入端电连接；所述第一选择器(511)的控制端与所述确定子电路(52)的输出端电连接；所述第一选择器(511)被配置为在所述确定子电路(52)的输出信号的控制下，通过所述第一选择器(511)的输出端输出所述第一降噪电压信号和所述外部输入电压信号中的一个；
    第二选择器(512)，所述第二选择器(512)的两个输入端分别与所述电平转换电路(20)的第二降噪电压信号输出端和所述电源管理集成电路(10)的外部输入电压信号输入端电连接；所述第二选择器(512)的控制端与所述确定子电路(52)的输出端电连接；所述第二选择器(512)被配置为在所述确定子电路(52)的输出信号的控制下，通过所述第二选择器(512)的输出端输出所述第二降噪电压信号和所述外部输入电压信号中的一个；
    其中，所述外部输入电压信号输入端用于接收提供给所述显示面板的驱动电路的外部输入电压信号。
  15. 一种显示装置，包括如权利要求8至14任一项所述的驱动电路。
  16. 一种防闪屏方法，应用于显示面板的驱动电路，所述驱动电路包括栅极驱动电路，包括：
    在所述显示面板的上电时间段控制所述栅极驱动电路输出栅极截止电平。
  17. 根据权利要求16所述的方法，其中，所述栅极驱动电路包括降噪模块，所述降噪模块用于在接收到的降噪电压信号为导通电平时，将所述栅极驱动电路的输出电平拉至所述栅极截止电平；
    所述在所述显示面板的上电时间段控制所述栅极驱动电路输出栅极截止电平，包括：
    在所述上电时间段控制输出到所述降噪模块的所述降噪电压信号为所述导通电平。
  18. 根据权利要求17所述的方法，其中，所述在所述上电时间段控制输出 到所述降噪模块的所述降噪电压信号为导通电平，包括：
    在所述上电时间段将所述驱动电路的外部输入电压信号作为所述降噪电压信号，输出到所述降噪模块。
  19. 根据权利要求16至18任一项所述的方法，其中，所述栅极驱动电路包括第一降噪模块和第二降噪模块，所述驱动电路还包括电平转换电路，所述电平转换电路用于为所述第一降噪模块提供第一降噪电压信号，并为所述第二降噪模块提供第二降噪电压信号；
    所述方法还包括：
    根据所述第一降噪电压信号和所述第二降噪电压信号确定是否处于所述上电时间段。
  20. 根据权利要求19所述的方法，其中，所述根据所述第一降噪电压信号和所述第二降噪电压信号确定是否处于所述上电时间段，包括：
    判断所述第一降噪电压信号和所述第二降噪电压信号的电压是否相等，所述第一降噪电压信号和所述第二降噪电压信号的电压相等，表示处于上电时间段；
    所述在所述显示面板的上电时间段控制所述栅极驱动电路输出栅极截止电平，包括：
    在所述第一降噪电压信号和所述第二降噪电压信号的电压相等时，控制所述栅极驱动电路输出栅极截止电平。
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