WO2020254910A1 - 金属酸化物、金属酸化物の形成方法、半導体装置、および半導体装置の作製方法 - Google Patents

金属酸化物、金属酸化物の形成方法、半導体装置、および半導体装置の作製方法 Download PDF

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WO2020254910A1
WO2020254910A1 PCT/IB2020/055353 IB2020055353W WO2020254910A1 WO 2020254910 A1 WO2020254910 A1 WO 2020254910A1 IB 2020055353 W IB2020055353 W IB 2020055353W WO 2020254910 A1 WO2020254910 A1 WO 2020254910A1
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Prior art keywords
insulator
oxide
conductor
metal oxide
transistor
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
小松良寛
澤井寛美
渡邊了介
川口忍
伊藤俊一
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2021528028A priority Critical patent/JP7637619B2/ja
Priority to US17/615,859 priority patent/US20220320339A1/en
Publication of WO2020254910A1 publication Critical patent/WO2020254910A1/ja
Anticipated expiration legal-status Critical
Priority to JP2025023722A priority patent/JP2025071143A/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C30B23/08—Epitaxial-layer growth by condensing ionised vapours
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/16—Oxides
    • C30B29/22—Complex oxides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/08—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • One aspect of the present invention relates to a metal oxide and a method for forming the metal oxide. Further, one aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Further, one aspect of the present invention relates to semiconductor wafers, modules, and electronic devices.
  • the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics.
  • a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic unit, and a storage device are one aspect of a semiconductor device. It may be said that a display device (liquid crystal display device, light emission display device, etc.), projection device, lighting device, electro-optical device, power storage device, storage device, semiconductor circuit, image pickup device, electronic device, and the like have a semiconductor device.
  • One aspect of the present invention is not limited to the above technical fields.
  • One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method.
  • one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter).
  • transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices).
  • ICs integrated circuits
  • image display devices also simply referred to as display devices.
  • Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
  • Non-Patent Document 1 In oxide semiconductors, CAAC (c-axis aligned crystalline) structures and nc (nanocrystalline) structures that are neither single crystal nor amorphous have been found (see Non-Patent Document 1 and Non-Patent Document 2).
  • Non-Patent Document 1 and Non-Patent Document 2 disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure.
  • One aspect of the present invention is a metal oxide containing crystals oriented in the c-axis.
  • the metal oxide has indium, the element M (where M is gallium, aluminum, yttrium, or tin) and zinc.
  • the diffusion length of hydrogen in the metal oxide is 200 nm or less.
  • the absorption due to the localized level calculated by CPM is 1 ⁇ 10 -2 cm -1 or less.
  • the diffusion length of hydrogen is preferably calculated assuming that the temperature is 400 ° C. for 1 hour.
  • Another aspect of the present invention is a transistor having the metal oxide described above in the channel forming region.
  • Another aspect of the present invention is a metal oxide, a first conductor in contact with the metal oxide, a second conductor, a third conductor overlapping the metal oxide, and the metal oxide. It is a semiconductor device having an insulator located between the third conductor and the third conductor.
  • the metal oxide has indium, the element M (where M is gallium, aluminum, yttrium, or tin) and zinc.
  • Metal oxides include crystals oriented in the c-axis.
  • the diffusion length of hydrogen in the metal oxide is 200 nm or less. In metal oxides, the absorption due to the localized level calculated by CPM is 1 ⁇ 10 -2 cm -1 or less.
  • another aspect of the present invention is between the metal oxide, the first conductor and the second conductor on the metal oxide, and the first conductor and the second conductor.
  • It is a semiconductor device having an insulator arranged and arranged on a metal oxide, and a third conductor on the insulator.
  • the metal oxide has indium, the element M (where M is gallium, aluminum, yttrium, or tin) and zinc.
  • Metal oxides include crystals oriented in the c-axis.
  • the diffusion length of hydrogen in the metal oxide is 200 nm or less. In metal oxides, the absorption due to the localized level calculated by CPM is 1 ⁇ 10 -2 cm -1 or less.
  • the diffusion length of hydrogen is preferably calculated with a temperature of 400 ° C. for 1 hour.
  • Another aspect of the present invention includes a step of forming a metal oxide film on a substrate, a step of forming a metal oxide film, and then performing a heat treatment at a temperature of 500 ° C. or higher and 600 ° C. or lower. It is a method for forming a metal oxide having an island-like step of forming the metal oxide by processing the metal oxide film by using a lithography method.
  • the metal oxide film is formed by a sputtering method using an In—M—Zn oxide target (M is gallium, aluminum, yttrium, or tin) at a substrate temperature of 200 ° C. or higher and 400 ° C. or lower. ..
  • the heat treatment is performed by performing the first heat treatment in an atmosphere of nitrogen gas and then performing the second heat treatment in an atmosphere of oxygen gas.
  • Another aspect of the present invention includes a step of forming a metal oxide film on a substrate, a step of forming a metal oxide film, and then performing a heat treatment at a temperature of 500 ° C. or higher and 600 ° C. or lower.
  • This is a method for producing a semiconductor device having.
  • the metal oxide film is formed by a sputtering method using an In—M—Zn oxide target (M is gallium, aluminum, yttrium, or tin) at a substrate temperature of 200 ° C. or higher and 400 ° C. or lower. ..
  • the heat treatment is performed in the atmosphere of nitrogen gas after the first heat treatment, and then in the atmosphere of oxygen gas.
  • a novel metal oxide and a method for forming the same can be provided. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device having good reliability and a method for manufacturing the same. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device having good electrical characteristics and a method for manufacturing the same. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device having little variation in transistor characteristics and a method for manufacturing the same. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration, and a method for manufacturing the same.
  • a semiconductor device having a large on-current and a method for manufacturing the same it is possible to provide a semiconductor device having high frequency characteristics and a method for manufacturing the same. Further, according to one aspect of the present invention, a semiconductor device having low power consumption and a method for manufacturing the same can be provided.
  • FIG. 1A is a top view of the semiconductor device.
  • 1B to 1D are cross-sectional views of a semiconductor device.
  • FIG. 2 is a cross-sectional view of the semiconductor device.
  • FIG. 3A is a diagram illustrating classification of the crystal structure of IGZO.
  • FIG. 3B is a diagram illustrating an XRD spectrum of the CAAC-IGZO film.
  • FIG. 3C is a diagram for explaining the microelectron diffraction pattern of the CAAC-IGZO film.
  • FIG. 4A is a top view of the semiconductor device. 4B to 4D are cross-sectional views of the semiconductor device.
  • FIG. 5A is a top view showing a method for manufacturing a semiconductor device.
  • FIG. 5B to 5D are cross-sectional views showing a method of manufacturing a semiconductor device.
  • FIG. 6A is a top view showing a method for manufacturing a semiconductor device.
  • 6B to 6D are cross-sectional views showing a method of manufacturing a semiconductor device.
  • FIG. 7A is a top view showing a method for manufacturing a semiconductor device.
  • 7B to 7D are cross-sectional views showing a method of manufacturing a semiconductor device.
  • FIG. 8A is a top view showing a method for manufacturing a semiconductor device.
  • 8B to 8D are cross-sectional views showing a method of manufacturing a semiconductor device.
  • FIG. 9A is a top view showing a method for manufacturing a semiconductor device.
  • 9B to 9D are cross-sectional views showing a method of manufacturing a semiconductor device.
  • 10A is a top view showing a method for manufacturing a semiconductor device.
  • 10B to 10D are cross-sectional views showing a method of manufacturing a semiconductor device.
  • FIG. 11A is a top view showing a method for manufacturing a semiconductor device.
  • 11B to 11D are cross-sectional views showing a method of manufacturing a semiconductor device.
  • FIG. 12A is a top view showing a method for manufacturing a semiconductor device.
  • 12B to 12D are cross-sectional views showing a method of manufacturing a semiconductor device.
  • FIG. 13A is a top view showing a method for manufacturing a semiconductor device.
  • 13B to 13D are cross-sectional views showing a method of manufacturing a semiconductor device.
  • FIG. 14A is a top view showing a method for manufacturing a semiconductor device.
  • FIG. 14B to 14D are cross-sectional views showing a method of manufacturing a semiconductor device.
  • FIG. 15A is a top view showing a method for manufacturing a semiconductor device.
  • 15B to 15D are cross-sectional views showing a method of manufacturing a semiconductor device.
  • FIG. 16A is a top view showing a method for manufacturing a semiconductor device.
  • 16B to 16D are cross-sectional views showing a method of manufacturing a semiconductor device.
  • FIG. 17A is a top view showing a method for manufacturing a semiconductor device.
  • 17B to 17D are cross-sectional views showing a method of manufacturing a semiconductor device.
  • FIG. 18A is a top view of the semiconductor device.
  • 18B to 18D are cross-sectional views of the semiconductor device.
  • FIG. 19A and 19B are cross-sectional views of the semiconductor device.
  • FIG. 20 is a cross-sectional view showing the configuration of the storage device.
  • FIG. 21 is a cross-sectional view showing the configuration of the storage device.
  • FIG. 22 is a cross-sectional view of the semiconductor device.
  • FIG. 23 is a cross-sectional view of the semiconductor device.
  • FIG. 24A is a top view of the semiconductor device.
  • FIG. 24B is a cross-sectional view of the semiconductor device.
  • FIG. 25 is a cross-sectional view of the semiconductor device.
  • FIG. 26A is a block diagram showing a configuration example of the storage device.
  • FIG. 26B is a schematic view showing a configuration example of the storage device.
  • 27A to 27H are circuit diagrams showing a configuration example of the storage device.
  • FIG. 20 is a cross-sectional view showing the configuration of the storage device.
  • FIG. 21 is a cross-sectional view showing the configuration of the storage device.
  • FIG. 28 is a diagram showing various storage devices for each layer.
  • FIG. 29A is a block diagram of the semiconductor device.
  • FIG. 29B is a schematic view of the semiconductor device.
  • 30A and 30B are diagrams illustrating an example of an electronic component.
  • 31A to 31E are schematic views of a storage device.
  • 32A to 32H are diagrams showing electronic devices.
  • FIG. 33 is a schematic view showing the structure of the sample.
  • FIG. 34 is a diagram showing the measurement result of the CPM measurement of the sample.
  • FIG. 35 is a schematic view showing the structure of the sample.
  • 36A and 36B are diagrams showing the measurement results of SIMS measurement of the sample.
  • 37A and 37B are diagrams showing the measurement results of SIMS measurement of the sample.
  • FIG. 38 is a diagram showing a measurement result of SIMS measurement of a sample.
  • FIG. 39 is a diagram illustrating the diffusion length of deuterium in the sample.
  • FIG. 40 is a schematic view showing the structure of the sample.
  • 41A and 41B are diagrams showing the measurement results of SIMS measurement of the sample.
  • 42A and 42B are diagrams showing the measurement results of SIMS measurement of the sample.
  • FIG. 43 is a diagram showing the measurement result of SIMS measurement of the sample.
  • the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.
  • the drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but they may not be reflected in the figure for the sake of easy understanding. Further, in the drawings, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted. Further, when referring to the same function, the hatch pattern may be the same and no particular sign may be added.
  • a top view also referred to as a "plan view”
  • a perspective view the description of some components may be omitted.
  • some hidden lines may be omitted.
  • the ordinal numbers attached as the first, second, etc. are used for convenience, and do not indicate the process order or the stacking order. Therefore, for example, the "first” can be appropriately replaced with the “second” or “third” for explanation.
  • the ordinal numbers described in the present specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.
  • X and Y are connected, the case where X and Y are electrically connected and the case where X and Y function. It is assumed that the case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification and the like. Therefore, it is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text, and other than the connection relationship shown in the figure or text, it is assumed that the connection relationship is disclosed in the figure or text.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • a transistor is an element having at least three terminals including a gate, a drain, and a source. It also has a region (hereinafter, also referred to as a channel forming region) in which a channel is formed between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode). A current can flow between the source and the drain through the channel formation region.
  • the channel formation region means a region in which a current mainly flows.
  • source and drain functions may be interchanged when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in the present specification and the like, the terms source and drain may be used interchangeably.
  • the channel length is, for example, the source in the top view of the transistor, the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other, or the channel formation region.
  • the channel length does not always take the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in the present specification, the channel length is set to any one value, the maximum value, the minimum value, or the average value in the channel formation region.
  • the channel width is, for example, the channel length direction in the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other in the top view of the transistor, or the channel formation region. Refers to the length of the channel formation region in the vertical direction with reference to. In one transistor, the channel width does not always take the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in the present specification, the channel width is set to any one value, the maximum value, the minimum value, or the average value in the channel formation region.
  • the channel width in the region where the channel is actually formed (hereinafter, also referred to as “effective channel width”) and the channel width shown in the top view of the transistor. (Hereinafter, also referred to as “apparent channel width”) and may be different.
  • the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible.
  • the proportion of the channel forming region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.
  • channel width may refer to the apparent channel width.
  • channel width may refer to an effective channel width.
  • the channel length, channel width, effective channel width, apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
  • the semiconductor impurity means, for example, a component other than the main components constituting the semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be said to be an impurity. Due to the inclusion of impurities, for example, the defect level density of the semiconductor may increase or the crystallinity may decrease.
  • the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxide semiconductors.
  • transition metals other than the main component such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water may also function as an impurity. Further, for example, by mixing of impurities, it may (may be referred to as V O.) Oxygen vacancies in the oxide semiconductor is formed.
  • silicon oxide nitriding has a higher oxygen content than nitrogen as its composition. Further, silicon nitride has a higher nitrogen content than oxygen in its composition.
  • the term “insulator” can be paraphrased as an insulating film or an insulating layer.
  • the term “conductor” can be rephrased as a conductive film or a conductive layer.
  • semiconductor can be paraphrased as a semiconductor film or a semiconductor layer.
  • parallel means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included.
  • approximately parallel means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • vertical means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.
  • approximately vertical means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used in the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when it is described as an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
  • normally off means that when a potential is not applied to the gate or a ground potential is applied to the gate, the drain current per 1 ⁇ m of the channel width flowing through the transistor is 1 ⁇ 10 ⁇ at room temperature. It means that it is 20 A or less, 1 ⁇ 10 -18 A or less at 85 ° C, or 1 ⁇ 10 -16 A or less at 125 ° C.
  • Metal oxide and its formation method This section describes metal oxides applicable to the semiconductor layer of transistors and methods for forming them.
  • a metal oxide hereinafter, also referred to as an oxide semiconductor that functions as a semiconductor in the semiconductor layer including the channel forming region.
  • the metal oxide that functions as a semiconductor preferably has a band gap of 2 eV or more, and more preferably 2.5 eV or more. As described above, by using a metal oxide having a large bandgap, the off-current of the transistor can be reduced.
  • a transistor using an oxide semiconductor in the channel formation region has an extremely small leakage current (off current) in a non-conducting state, so that a semiconductor device with low power consumption can be provided. Further, since the oxide semiconductor can be formed into a film by using a sputtering method or the like, it can be used for a transistor constituting a highly integrated semiconductor device.
  • oxide semiconductors for example, In-M-Zn oxide having indium, element M and zinc (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium). , Zinc, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. (one or more) and other metal oxides may be used. Further, as the oxide semiconductor, In—Ga oxide, In—Zn oxide, or indium oxide may be used.
  • the oxide semiconductor is an In-M-Zn oxide having indium (In), element M, and zinc (Zn).
  • the element M includes aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like.
  • the element M a plurality of the above-mentioned elements may be combined in some cases.
  • impurities and oxygen deficiency are present in the channel formation region of the oxide semiconductor, the transistor using the oxide semiconductor is liable to fluctuate in electrical characteristics and may have poor reliability.
  • impurities in oxide semiconductors include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the hydrogen contained in the oxide semiconductor is reacted with oxygen bonded to a metal atom, it may form a H 2 O, and oxygen deficiency.
  • the hydrogen of oxygen vacancies near defects containing the hydrogen to the oxygen deficiency (hereinafter, may be referred to as V O H.) To form, which may produce electrons as carriers.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normal-on characteristic (a characteristic in which a channel exists even if a voltage is not applied to the gate electrode and a current flows through the transistor).
  • Defects containing hydrogen to an oxygen vacancy can function as a donor of the metal oxide.
  • the carrier concentration may be evaluated instead of the donor concentration. Therefore, in the present specification and the like, as a parameter of the metal oxide, a carrier concentration assuming a state in which an electric field is not applied may be used instead of the donor concentration. That is, the "carrier concentration” described in the present specification and the like may be paraphrased as the "donor concentration”. In addition, the "carrier concentration” described in the present specification and the like can be rephrased as "carrier density”.
  • the hydrogen concentration obtained by secondary ion mass spectrometry is less than 1 ⁇ 10 20 atoms / cm 3 , preferably 1 ⁇ . It should be less than 10 19 atoms / cm 3 , more preferably less than 5 ⁇ 10 18 atoms / cm 3 , and even more preferably less than 1 ⁇ 10 18 atoms / cm 3 . Further, it is preferable that the channel forming region in the oxide semiconductor has a reduced carrier concentration and is i-shaped (intrinsicized) or substantially i-shaped.
  • the metal oxide used in the channel forming region of the transistor suppresses the diffusion of hydrogen.
  • a metal oxide in which hydrogen diffusion is suppressed can be rephrased as a metal oxide having a small hydrogen diffusion length.
  • the diffusion of hydrogen is suppressed because the oxygen deficiency of the metal oxide is reduced and the diffusion frequency of hydrogen through the oxygen deficiency is reduced.
  • suppressing the diffusion of hydrogen is also referred to as freezing hydrogen.
  • the diffusion coefficient is estimated from the results obtained by SIMS, an Arrhenius plot of the diffusion coefficient and temperature is created, and the frequency factor and activity calculated from the Arrhenius plot. It can be calculated using the chemical energy.
  • the method for calculating the diffusion length of hydrogen in a metal oxide will be described in detail in Examples described later.
  • the diffusion length of hydrogen in the metal oxide is 200 nm or less, preferably 100 nm or less, and more preferably 60 nm or less.
  • the diffusion length of the hydrogen is calculated assuming that the temperature is 400 ° C. for 1 hour.
  • the amount of oxygen deficiency contained in the metal oxide is reduced.
  • the carrier concentration in the channel formation region is reduced, and the channel formation region is made i-shaped (intrinsic) or substantially i-shaped. can do. Therefore, a semiconductor device including a transistor having good electrical characteristics can be manufactured.
  • the amount of oxygen deficiency contained in the metal oxide may be evaluated by using, for example, a constant photocurrent method (CPM: Constant Photocurent Method).
  • CPM Constant Photocurent Method
  • the deep defect level caused by oxygen deficiency is, for example, from a position 0.5 eV away from the upper end of the valence band of the metal oxide to the conduction band side to the lower end of the conduction band of the metal oxide to the valence band side.
  • the localization level formed in the range of 0.5 eV away Specifically, in metal oxides, the absorption due to the localized level calculated by CPM is less than 2 ⁇ 10 ⁇ 2 cm -1 , preferably less than 1 ⁇ 10 ⁇ 2 cm -1 .
  • the metal oxide preferably contains crystals oriented in the c-axis.
  • the metal oxide containing crystals with c-axis orientation is, for example, CAAC-OS (c-axis aligned crystal line oxide semiconductor) described later.
  • a semiconductor device including a transistor having good electrical characteristics can be manufactured.
  • a semiconductor device having a transistor with good reliability can be manufactured.
  • a metal oxide containing crystals oriented on the c-axis is formed.
  • the metal oxide is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an atomic layer. It can be carried out by using a layer deposition (ALD: Atomic Layer Deposition) method or the like. In particular, it is preferable to use a sputtering method.
  • the In-M-Zn oxide target or the like is used. Further, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the crystallinity of the metal oxide can be improved.
  • the proportion of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less.
  • the crystallinity of the metal oxide can be improved by forming the film while heating the substrate.
  • the substrate is heated so that the temperature of the substrate is 100 ° C. or higher and lower than 500 ° C., preferably 200 ° C. or higher and 400 ° C. or lower.
  • the metal oxide is heat-treated at a temperature at which the metal oxide does not crystallize.
  • the temperature at which the metal oxide does not crystallize is 250 ° C. or higher and 650 ° C. or lower, preferably 450 ° C. or higher and 600 ° C. or lower, and more preferably 500 ° C. or higher and lower than 600 ° C.
  • the metal oxide does not polycrystallize, but the crystals in the metal oxide are compared with the case where the heat treatment is performed at a temperature lower than 600 ° C. There is a high probability that the sex will change and the reduction in the amount of oxygen deficiency will be suppressed, or that oxygen deficiency will form. Further, when the heat treatment is performed at a temperature of 700 ° C. or higher, the metal oxide tends to be polycrystalline. The polycrystal has grain boundaries, and the grain boundaries serve as recombination centers and carriers are captured.
  • the heat treatment is performed at a temperature lower than 250 ° C., the hydrogen concentration in the metal oxide may not be sufficiently reduced.
  • the heat treatment is preferably performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the oxygen gas may be set to about 20%.
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then the heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement the desorbed oxygen. You may.
  • the heat treatment it is preferable to perform the treatment in a nitrogen atmosphere for 1 hour and then continuously perform the treatment in an oxygen atmosphere for 1 hour.
  • the gas used in the above heat treatment is highly purified.
  • the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • the crystallinity of the metal oxide can be further enhanced. Therefore, it is possible to form a metal oxide that is dense, has high crystallinity, reduces the amount of oxygen deficiency, and suppresses the diffusion of hydrogen.
  • CAAC-OS is an oxide semiconductor having a plurality of crystal regions, the plurality of crystal regions having the c-axis oriented in a specific direction.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film.
  • the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region in which the lattice arrangement is aligned. Further, the CAAC-OS has a region in which a plurality of crystal regions are connected in the ab plane direction, and the region may have distortion.
  • the strain refers to a region in which a plurality of crystal regions are connected, in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another grid arrangement is aligned. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and not clearly oriented in the ab plane direction.
  • Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the size of the crystal region may be about several tens of nm.
  • CAAC-OS has indium (In) and oxygen. It tends to have a layered crystal structure (also referred to as a layered structure) in which a layer (hereinafter, In layer) and a layer having elements M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are laminated. There is. Indium and element M can be replaced with each other. Therefore, the (M, Zn) layer may contain indium. In addition, the In layer may contain the element M. In addition, Zn may be contained in the In layer.
  • the layered structure is observed as a lattice image in, for example, a high-resolution TEM image.
  • the position of the peak indicating the c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.
  • a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that a certain spot and another spot are observed at point-symmetrical positions with the spot of the incident electron beam passing through the sample (also referred to as a direct spot) as the center of symmetry.
  • the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit lattice is not limited to a regular hexagon and may be a non-regular hexagon. Further, in the above strain, it may have a lattice arrangement such as a pentagon or a heptagon.
  • a clear grain boundary cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal atoms. It is thought that this is the reason.
  • CAAC-OS for which no clear crystal grain boundary is confirmed, is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor.
  • a configuration having Zn is preferable.
  • In-Zn oxide and In-Ga-Zn oxide are more suitable than indium oxide because they can suppress the generation of grain boundaries.
  • CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries. Further, since the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures in the manufacturing process (so-called thermal budget). Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
  • FIGS. 1A to 1D are a top view and a cross-sectional view of a semiconductor device including the transistor 200.
  • FIG. 1A is a top view of the semiconductor device.
  • 1B to 1D are cross-sectional views of the semiconductor device.
  • FIG. 1B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • FIG. 1B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • FIG. 1B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • FIG. 1C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction.
  • FIG. 1D is a cross-sectional view of the portion shown by the alternate long and short dash line in FIG. 1A. In the top view of FIG. 1A, some elements are omitted for the purpose of clarifying the figure.
  • the semiconductor device includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, an insulator 216 on the insulator 214, an insulator 214, and an insulator.
  • Insulator 284 and.
  • the insulator 212, the insulator 214, the insulator 216, the insulator 254, the insulator 280, the insulator 282, the insulator 283, and the insulator 284 function as an interlayer film.
  • the insulator 241a is provided in contact with the side surface of the conductor 240a, and the insulator 241b is provided in contact with the side surface of the conductor 240b. Further, on the insulator 284, the conductor 240a, and the conductor 240b, the conductor 240a is electrically connected to the conductor 240a, and the conductor 246a and the conductor 240b are electrically connected to the conductor 240b as wiring. A functional conductor 246b is provided. Further, an insulator 286 is provided on the conductor 246a, the conductor 246b, and the insulator 284.
  • the insulator 241a is provided in contact with the side wall of the opening of the insulator 254, the insulator 280, the insulator 282, the insulator 283, and the insulator 284, and the first conductivity of the conductor 240a is in contact with the side surface of the insulator 241a.
  • a body is provided, and a second conductor of the conductor 240a is further provided inside.
  • the insulator 241b is provided in contact with the side wall of the opening of the insulator 254, the insulator 280, the insulator 282, the insulator 283, and the insulator 284, and the first of the conductor 240b is in contact with the side surface of the insulator 241b.
  • the conductor 240a and the conductor 240b may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be given in the order of formation to distinguish them.
  • the transistor 200 is arranged on the insulator 214 and / or the insulator 216 so as to be embedded in the insulator 205 (conductor 205a and the conductor 205b) and the insulator 216. , And the insulator 222 on the conductor 205, the insulator 224 on the insulator 222, the oxide 230a on the insulator 224, the oxide 230b on the oxide 230a, and the oxide on the oxide 230b.
  • oxide 243a, oxide 243b, and oxide 230c conductor 242a on oxide 243a, conductor 242b on oxide 243b, oxide 230d on oxide 230c, and insulator 250 on oxide 230d.
  • a conductor 260 (conductor 260a and conductor 260b) located on the insulator 250 and overlapping a part of the oxide 230c.
  • the oxide 230c is in contact with the side surface of the oxide 243a, the side surface of the oxide 243b, the side surface of the conductor 242a, and the side surface of the conductor 242b.
  • the insulator 282 is in contact with the upper surfaces of the conductor 260, the insulator 250, the oxide 230d, the oxide 230c, and the insulator 280, respectively.
  • the insulator 280 and the insulator 254 are provided with an opening reaching the oxide 230b.
  • Oxide 230c, oxide 230d, insulator 250, and conductor 260 are arranged in the opening. Further, in the channel length direction of the transistor 200, the conductor 260, the insulator 250, the oxide 230d, and the oxide 230c are placed between the conductor 242a and the oxide 243a and the conductor 242b and the oxide 243b. It is provided.
  • the insulator 250 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260.
  • the oxide 230c has a region in contact with the oxide 230b, a region overlapping the side surface of the conductor 260 via the oxide 230d and the insulator 250, and the conductor 260 via the oxide 230d and the insulator 250. It has an area that overlaps with the bottom surface of the.
  • the oxide 230 is arranged on the oxide 230a arranged on the insulator 224, the oxide 230b arranged on the oxide 230a, and the oxide 230b, and at least a part of the oxide 230 is formed on the oxide 230b. It is preferable to have an oxide 230c in contact with the oxide 230c and an oxide 230d arranged on the oxide 230c.
  • the transistor 200 shows a configuration in which the oxide 230 is laminated with four layers of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d, but the present embodiment is limited to this. is not.
  • a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230d, or a laminated structure of five or more layers may be provided, or the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d may be provided. Each may have a laminated structure.
  • the conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode.
  • the insulator 250, the insulator 224, and the insulator 222 function as a gate insulator.
  • the conductor 242a functions as one of the source electrode and the drain electrode, and the conductor 242b functions as the other of the source electrode and the drain electrode.
  • the oxide 230 functions as a channel forming region.
  • the oxide 230 has a region 234 that functions as a channel forming region of the transistor 200, and regions 236a and 236b that are provided so as to sandwich the region 234 and function as a source region or a drain region. Has. At least part of the region 234 overlaps with the conductor 260.
  • a conductor 242a and a conductor 242b are provided on the oxide 230b, and a lower resistance region is formed in the vicinity of the conductor 242a in the region 236a and in the vicinity of the conductor 242b in the region 236b.
  • the region 236a and the region 236b that function as the source region or the drain region are regions in which the carrier concentration is increased due to a low oxygen concentration, impurities such as hydrogen, nitrogen, and metal elements are contained, and the resistance is lowered. That is, the regions 236a and 236b are regions having a high carrier concentration and low resistance as compared with the region 234. Further, the region 234 functioning as a channel forming region is a region having a low carrier concentration and a high resistance due to a higher oxygen concentration, a lower impurity concentration, and the like than the regions 236a and 236b.
  • the oxygen concentration between the region 234 and the region 236a (region 236b) is equal to or higher than the oxygen concentration of the region 236a (region 236b), and is equal to or lower than the oxygen concentration of the region 234.
  • Regions may be formed.
  • the width of the region 234 in the channel length direction coincides with the width of the conductor 260, but the present embodiment is not limited to this.
  • the width of the region 234 may be narrower than the width of the conductor 260, or the width of the region 234 may be wider than the width of the conductor 260.
  • the concentration of impurities such as hydrogen, nitrogen, and metal elements detected in each region is not limited to a gradual change in each region, and may be continuously changed in each region. That is, it suffices that the concentration of impurities such as hydrogen, nitrogen, and metal elements decreases as the region is closer to the channel formation region.
  • an insulator containing oxygen desorbed by heating (hereinafter, may be referred to as excess oxygen) is provided in the vicinity of the oxide semiconductor, and heat treatment is performed. Then, oxygen may be supplied from the insulator to the oxide semiconductor. Thereby, the oxygen deficiency contained in the channel forming region in the oxide semiconductor can be repaired by the supplied oxygen. Further, by reacting with hydrogen supplied oxygen remained in the oxide semiconductor, removing the hydrogen as H 2 O (to dehydration) can. Thus, it is possible to prevent the V O H is formed in an oxide semiconductor.
  • the carrier concentration in the source region or the drain region may decrease, which may cause a decrease in the on-current of the transistor 200, a decrease in the field effect mobility, and the like. is there. Further, the amount of oxygen supplied to the source region or the drain region becomes non-uniform in the substrate surface, which causes variations in the characteristics of the semiconductor device having the transistor.
  • the region 234 that functions as a channel forming region preferably has a reduced carrier concentration and is i-shaped or substantially i-shaped, but functions as a source region or a drain region.
  • the regions 236a and 236b preferably have a high carrier concentration and are n-shaped.
  • the transistor 200 it is preferable to use the above-mentioned metal oxide for the oxide 230 (oxide 230a, oxide 230b, oxide 230c, and oxide 230d) containing the channel forming region. In particular, it is preferable to use the above-mentioned metal oxide for the oxide 230b.
  • the diffusion of hydrogen in the channel formation region can be suppressed, and the diffusion of hydrogen from the source region to the drain region or from the drain region to the source region can be suppressed. Therefore, in the oxide semiconductor, an i-typed or substantially i-shaped region and an n-typed region can be retained. Therefore, it is possible to manufacture a semiconductor device having a transistor having good reliability. In addition, a semiconductor device with little variation in transistor characteristics can be manufactured.
  • the above-mentioned metal oxide for a transistor having a finer channel length.
  • the metal oxide described above it is possible to prevent hydrogen from diffusing from the source region to the drain region or from the drain region to the source region even in a transistor having a fine channel length. Therefore, it is possible to retain an i-typed or substantially i-shaped region and an n-typed region in the oxide semiconductor.
  • the channel length can be set to 500 nm or less, preferably 300 nm or less, and more preferably 150 nm or less.
  • the above-mentioned metal oxide may be used for a transistor having a channel length larger than 500 nm.
  • the above-mentioned metal oxide has a highly crystalline and dense structure, so that the diffusion of oxygen in the metal oxide can be suppressed.
  • the diffusion of oxygen in the oxide 230b is suppressed. Therefore, it is possible to prevent the oxygen supplied to the region 234 via the oxide 230c from diffusing into the regions 236a and 236b that function as the source region or the drain region. As a result, it is possible to suppress the formation of an offset region between the region 234 and the region 236a or the region 236b, and to manufacture a transistor having a large on-current.
  • the oxide 230b by suppressing the diffusion of oxygen in the oxide 230b, it is possible to suppress the diffusion of oxygen to the conductor 242a (conductor 242b) in contact with the oxide 230b via the oxide 243a (oxide 243b). can do. Therefore, it is possible to suppress the oxidation of the conductor 242a and the conductor 242b and suppress the increase in the contact resistance between the transistor and the wiring. Therefore, good electrical characteristics and reliability can be given to the transistor.
  • the above-mentioned metal oxide may be used for the oxide 230a.
  • the above-mentioned metal oxide for the oxide 230a it is possible to suppress the diffusion of hydrogen from the structure formed below the oxide 230a to the oxide 230b.
  • the above-mentioned metal oxide may be used for the oxide 230c.
  • the above-mentioned metal oxide for the oxide 230c, it is possible to suppress the diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b.
  • the oxide 230 preferably has a laminated structure of a plurality of oxide layers having different chemical compositions. Further, the oxide 230 preferably has a laminated structure of a plurality of oxide layers having a common element (main component) other than oxygen.
  • the ratio of the number of elements M to In in the metal oxide used for the oxide 230a or 230d is the number of atoms of the element M to In in the metal oxide used for the oxide 230b or 230c. It is preferably larger than the ratio.
  • the larger the atomic number ratio of the element M to In the easier it is to suppress the diffusion of impurities or oxygen. Therefore, by having the oxide 230a under the oxide 230b, it is possible to suppress the diffusion of impurities into the oxide 230b from the structure formed below the oxide 230a. Further, by having the oxide 230d on the oxide 230c, it is possible to suppress the diffusion of impurities into the oxide 230c from the structure formed above the oxide 230d.
  • the atomic number ratio of In to the element M in the metal oxide used for the oxide 230b or 230c is the atomic number ratio of In to the element M in the metal oxide used for the oxide 230a or the oxide 230d. It is preferably larger.
  • the on-current of the transistor can be increased.
  • the main path of the carrier is the interface between the oxide 230b, the oxide 230c or its vicinity, for example, the oxide 230b and the oxide 230c.
  • the oxide 230b and the oxide 230c have a common element (main component) other than oxygen, the defect level density at the interface between the oxide 230b and the oxide 230c can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is small, and a high on-current can be obtained.
  • the lower end of the conduction band of the oxide 230b and the oxide 230c is oxidized. It is preferable that the object 230a and the oxide 230d are separated from the vacuum level from the lower end of the conduction band.
  • the electron affinity of the oxide 230b and the oxide 230c is preferably larger than the electron affinity of the oxide 230a and the oxide 230d.
  • the oxide 230b and the oxide 230c are preferably crystalline. In particular, it is preferable to use the above-mentioned CAAC-OS as the oxide 230b and the oxide 230c. Further, the oxide 230d may have a crystalline structure.
  • CAAC-OS for oxide 230b or oxide 230c
  • impurities and oxygen deficiency can be reduced in the region where channels are formed in the oxide semiconductor.
  • CAAC-OS has the property of easily moving oxygen in the direction perpendicular to the c-axis of the crystal of the metal oxide. Therefore, the oxygen contained in the oxide 230c can be efficiently supplied to the oxide 230b.
  • CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (oxygen deficiency, etc.).
  • the CAAC-OS is subjected to heat treatment at a temperature at which the metal oxide does not undergo polycrystallization (for example, 400 ° C. or higher and 600 ° C. or lower), whereby CAAC-OS has a more crystalline and dense structure. Can be.
  • a temperature at which the metal oxide does not undergo polycrystallization for example, 400 ° C. or higher and 600 ° C. or lower
  • the oxide 230b it is possible to reduce the diffusion of impurities and oxygen in the oxide 230b. Therefore, it is possible to reduce the diffusion of oxygen supplied to the region 234 of the oxide 230b into the regions 236a and 236b of the oxide 230b.
  • oxygen is selectively supplied to the region 234 that functions as the channel formation region to form the region 234 i-type or substantially i-type, and the region functions as the source region or the drain region.
  • Oxygen diffusing into the regions 236a and 236b can be suppressed and the n-type of the regions 236a and 236b can be maintained.
  • fluctuations in the electrical characteristics of the transistor 200 can be suppressed, and fluctuations in the electrical characteristics of the transistor 200 can be suppressed within the substrate surface.
  • the oxide 230d preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230c, and more preferably contains all the metal elements.
  • the oxide 230c In-M-Zn oxide, In-Zn oxide, or indium oxide is used as the oxide 230c, and In-M-Zn oxide, M-Zn oxide, or element M is used as the oxide 230d.
  • Oxides may be used. As a result, the defect level density at the interface between the oxide 230c and the oxide 230d can be lowered.
  • the oxide 230d is more preferably a metal oxide that suppresses the diffusion or permeation of oxygen than the oxide 230c.
  • the oxide 230d is more preferably a metal oxide that suppresses the diffusion or permeation of oxygen than the oxide 230c.
  • the atomic number ratio of In to the metal element as the main component is smaller than the atomic number ratio of In to the metal element as the main component in the metal oxide used for the oxide 230c.
  • the insulator 250 functions as a gate insulator, if In is mixed in the insulator 250 or the like, the characteristics of the transistor become poor. Therefore, by providing the oxide 230d between the oxide 230c and the insulator 250, it is possible to provide a highly reliable semiconductor device.
  • the lower end of the conduction band changes gently.
  • the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d is continuously changed or continuously bonded.
  • the defect quasi of the mixed layer formed at the interface between the oxide 230a and the oxide 230b, the interface between the oxide 230b and the oxide 230c, and the interface between the oxide 230c and the oxide 230d It is advisable to lower the position density.
  • oxide 230a and oxide 230b, oxide 230b and oxide 230c, and oxide 230c and oxide 230d have a common element other than oxygen as a main component, so that a mixed layer having a low defect level density can be obtained.
  • the oxide 230b is an In-M-Zn oxide
  • the oxides 230a, 230c, and 230d are In-M-Zn oxide, M-Zn oxide, and element M oxide. In-Zn oxide, indium oxide and the like may be used.
  • M: Zn 1: 3: 4 [atomic number ratio] or a composition in the vicinity thereof
  • M: Zn 2: 1 [atomic number ratio] or a composition in the vicinity thereof
  • the composition in the vicinity includes a range of ⁇ 30% of the desired atomic number ratio.
  • gallium it is preferable to use gallium as the element M.
  • the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d As described above, the interface between the oxide 230a and the oxide 230b, the interface between the oxide 230b and the oxide 230c, and the oxide The defect level density at the interface between the 230c and the oxide 230d can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.
  • the oxide 230c is arranged so as to cover the inner wall (side wall and bottom surface) of the groove.
  • the depth of the groove portion of the oxide 230b is substantially the same as the film thickness of the oxide 230c.
  • the upper surface of the oxide 230c in the region overlapping the oxide 230b is arranged so as to be substantially aligned with the interface between the oxide 230b and the oxide 243a or the oxide 243b.
  • the difference between the height of the interface between the oxide 230b and the oxide 243a or the oxide 243b and the height of the interface between the oxide 230c and the oxide 230d is the difference between the oxide 230c. It is preferably less than or equal to the film thickness, and more preferably less than or equal to half the film thickness of the oxide 230c.
  • the transistor to reduce the influence of defects and impurities, such as V O H, it is possible to form a channel in the oxide 230c. As a result, good electrical characteristics can be imparted to the transistor. Further, it is possible to provide a semiconductor device having less variation in transistor characteristics and good reliability.
  • impurities at the interface between the oxide 230b and the oxide 230c and in the vicinity thereof are reduced or removed.
  • impurities such as aluminum and silicon are preferably reduced or removed because they hinder the improvement of the crystallinity or c-axis orientation of the oxide 230c and the oxide 230b.
  • the concentration of aluminum atoms at the interface between the oxide 230b and the oxide 230c and its vicinity is preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, and further preferably 1.0 atomic% or less. preferable.
  • a-like OS amorphous-like oxide semiconductor
  • V O H in the non CAAC region is heavily formed, there is a high probability that the transistor is likely to normally on of. From the above, it is preferable that the non-CAAC region is reduced or removed.
  • the oxide 230b and the oxide 230c having a CAAC structure since a dense crystal structure is formed, V O H is less likely to exist stably. Further, the oxygen supplying treatment to be described later, by supplying an excess of oxygen in the oxide 230b and the oxide 230c, it is possible to reduce the V O H, and V O in the oxide 230b and oxides 230c. As described above, when the oxide 230b and the oxide 230c have a CAAC structure, normalization of the transistor can be suppressed.
  • FIG. 2 shows a configuration in which the side surface of the opening into which the conductor 260 or the like is embedded is substantially perpendicular to the surface to be formed of the oxide 230b, including the groove portion of the oxide 230b, the present embodiment is shown. Is not limited to this.
  • the bottom of the opening may have a U-shape having a gently curved surface.
  • the c-axis of the CAAC structure faces a direction substantially perpendicular to the surface to be formed or the upper surface of the oxide 230c. Therefore, it has a region in which the crystal layer is extended so as to be substantially parallel to the bottom surface and the side surface of the opening. It is more preferable that the oxide 230d also has the same crystal structure as the oxide 230c.
  • the angle formed by the ab surface of the CAAC structure of the oxide 230c and the ab surface of the CAAC structure of the oxide 230b in the groove is preferably 60 degrees or less, and preferably 45 degrees or less. Is more preferable, and 30 degrees or less is further preferable. In this way, by reducing the angle formed by the ab surface of the CAAC structure of the oxide 230c and the ab surface of the CAAC structure of the oxide 230b in the groove, the crystal of the oxide 230c is formed in the groove. It can be made more sexual.
  • the oxide composed of the non-CAAC region is not limited to the case where it is formed so as to be surrounded by the oxide 230b, the oxide 243a, the oxide 230c, and the oxide 230d, and is sandwiched between the oxide 230b and the oxide 230c. It may be formed as follows.
  • a curved surface may be provided between the side surface of the oxide 230b and the upper surface of the oxide 230b in a cross-sectional view of the transistor 200 in the channel width direction. That is, the end of the side surface and the end of the upper surface may be curved (hereinafter, also referred to as a round shape).
  • the radius of curvature on the curved surface is larger than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping the conductor 242a or the conductor 242b, or the region on the upper surface of the oxide 230b that does not have the curved surface. It is preferably smaller than half the length of. Specifically, the radius of curvature on the curved surface is larger than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less. With such a shape, the coverage of the insulator 250 and the conductor 260, which will be formed in a later step, on the groove can be improved.
  • the oxide 230c may be provided for each transistor 200. That is, the oxide 230c of the transistor 200 and the oxide 230c of the transistor 200 adjacent to the transistor 200 do not have to be in contact with each other. Further, the oxide 230c of the transistor 200 and the oxide 230c of the transistor 200 adjacent to the transistor 200 may be separated from each other. In other words, the oxide 230c may not be arranged between the transistor 200 and the transistor 200 adjacent to the transistor 200.
  • the oxide 230c is independently provided on the transistors 200 by the above configuration. Therefore, it is possible to suppress the occurrence of a parasitic transistor between the transistor 200 and the transistor 200 adjacent to the transistor 200, and to suppress the occurrence of a leak path along the conductor 260. Therefore, it is possible to provide a semiconductor device having good electrical characteristics and capable of miniaturization or high integration.
  • L 1 is made larger than 0 nm.
  • the value of the ratio of L 1 (L 1 / L 2) for L 2 is preferably greater than 0 less than 1, more preferably 0.1 to 0.9, more preferably 0.2 to 0.8 Is.
  • L 2 may be the distance between the side ends of the oxide 230b of the transistor 200 facing each other and the side ends of the oxide 230b of the transistor 200 adjacent to the transistor 200.
  • oxides 230c is a transistor 200, the positional deviation of the arrangement that are not regions between the transistors 200 adjacent to the transistor 200 Even if it occurs, the oxide 230c of the transistor 200 and the oxide 230c of the transistor 200 adjacent to the transistor 200 can be separated from each other.
  • the transistor 200 by increasing the ratio of L 1 to the above L 2 (L 1 / L 2 ), the transistor 200, even by narrowing the interval between the transistor 200 adjacent to the transistor 200, the width of the minimum feature size It can be secured, and the semiconductor device can be further miniaturized or highly integrated.
  • each of the conductor 260 and the insulator 250 may be commonly used between adjacent transistors 200. That is, the conductor 260 of the transistor 200 has a region continuously provided with the conductor 260 of the transistor 200 adjacent to the transistor 200. Further, the insulator 250 of the transistor 200 has a region continuously provided with the insulator 250 of the transistor 200 adjacent to the transistor 200.
  • the oxide 230d has a region in contact with the insulator 224 between the transistor 200 and the transistor 200 adjacent to the transistor 200.
  • the oxide 230d of the transistor 200 may be configured to be separated from the oxide 230d of the transistor 200 adjacent to the transistor 200.
  • the insulator 250 has a region in contact with the insulator 224 between the transistor 200 and the transistor 200 adjacent to the transistor 200.
  • Insulator 212, insulator 214, insulator 254, insulator 282, insulator 283, insulator 284, and insulator 286 are transistors in which impurities such as water and hydrogen are removed from the substrate side or from above the transistor 200. It preferably functions as a barrier insulating film that suppresses diffusion to 200. Therefore, the insulator 212, the insulator 214, the insulator 254, the insulator 282, the insulator 283, the insulator 284, and the insulator 286 are hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules.
  • an insulating material N 2 O, NO, NO 2, etc.
  • an insulating material having a function of suppressing the diffusion of oxygen for example, at least one oxygen atom, oxygen molecule, etc.
  • the barrier insulating film refers to an insulating film having a barrier property.
  • the barrier property is defined as a function of suppressing the diffusion of the corresponding substance (also referred to as low permeability).
  • the corresponding substance has a function of capturing and fixing (also called gettering).
  • the insulator 212 it is preferable to use silicon nitride or the like as the insulator 212, the insulator 283, and the insulator 284, and to use aluminum oxide or the like as the insulator 214, the insulator 254, and the insulator 282.
  • impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 side via the insulator 212 and the insulator 214.
  • oxygen contained in the insulator 224 and the like from diffusing toward the substrate side via the insulator 212 and the insulator 214.
  • the transistor 200 is made of the insulator 212, the insulator 214, the insulator 254, the insulator 282, the insulator 283, and the insulator 284 having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen. It is preferable to have a structure that surrounds it.
  • the resistivity of the insulator 212, the insulator 284, and the insulator 286 may be preferable to reduce the resistivity of the insulator 212, the insulator 284, and the insulator 286.
  • the insulator 286 can alleviate the charge-up of the conductor 205, the conductor 242a, the conductor 242b, the conductor 260, the conductor 246a, or the conductor 246b.
  • the resistivity of the insulator 212, the insulator 284, and the insulator 286 is preferably 1 ⁇ 10 10 ⁇ cm or more and 1 ⁇ 10 15 ⁇ cm or less.
  • the insulator 283 or the insulator 284 does not necessarily have to be provided.
  • the insulator 216 and the insulator 280 have a lower dielectric constant than the insulator 214.
  • a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.
  • silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, empty. Silicon oxide having pores or the like may be appropriately used.
  • silicon oxide and silicon oxide nitride are preferable because they are thermally stable.
  • materials such as silicon oxide, silicon oxide nitride, and silicon oxide having pores are preferable because a region containing oxygen desorbed by heating can be easily formed.
  • the conductor 205 may function as a second gate electrode.
  • the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without interlocking with it.
  • Vth threshold voltage
  • the conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260.
  • the conductor 205 may be provided larger than the size of the region that does not overlap with the conductor 242a and the conductor 242b of the oxide 230.
  • the conductor 205 is also stretched in a region outside the end portion of the oxide 230a and the oxide 230b intersecting the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 are superposed on each other via an insulator on the outside of the side surface of the oxide 230 in the channel width direction.
  • the channel forming region of the oxide 230 is electrically surrounded by the electric field of the conductor 260 that functions as the first gate electrode and the electric field of the conductor 205 that functions as the second gate electrode. Can be done.
  • the structure of the transistor that electrically surrounds the channel forming region by the electric fields of the first gate electrode and the second gate electrode is referred to as a slurried channel (S-channel) structure.
  • the transistor having the S-channel structure represents the structure of the transistor that electrically surrounds the channel formation region by the electric fields of one and the other of the pair of gate electrodes.
  • the S-channel structure disclosed in the present specification and the like is different from the Fin type structure and the planar type structure.
  • the conductor 205 is stretched to function as wiring.
  • the present invention is not limited to this, and a conductor that functions as wiring may be provided under the conductor 205. Further, it is not always necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by a plurality of transistors.
  • the conductor 205a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O, NO, etc. NO 2), the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a conductive material having. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.).
  • the conductor 205a By using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 205a, it is possible to prevent the conductor 205b from being oxidized and the conductivity from being lowered.
  • the conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used. Therefore, the conductor 205a may be a single layer or a laminated material of the conductive material.
  • the conductor 205a may be a laminate of tantalum, tantalum nitride, ruthenium, or ruthenium oxide and titanium or titanium nitride.
  • the conductor 205b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 205b is shown as a single layer, it may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.
  • the conductor 205 shows a configuration in which the conductor 205a and the conductor 205b are laminated, but the present embodiment is not limited to this.
  • the conductor 205 may be provided as a single layer or a laminated structure having three or more layers. When the structure has a laminated structure, an ordinal number may be given in the order of formation to distinguish them.
  • the insulator 222 has a function of suppressing the diffusion of hydrogen (for example, at least one hydrogen atom, hydrogen molecule, etc.). Further, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.
  • the insulator 222 it is preferable to use an insulator containing oxides of one or both of aluminum and hafnium, which are insulating materials. Insulators containing oxides of one or both of aluminum and hafnium have barrier properties against oxygen, hydrogen, and water. As the insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like. When the insulator 222 is formed by using such a material, the insulator 222 releases oxygen from the oxide 230 to the substrate side and diffuses impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Functions as a layer that suppresses.
  • the insulator 222 it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and suppress the generation of oxygen deficiency in the oxide 230. Further, it is possible to suppress the conductor 205 from reacting with the oxygen contained in the insulator 224 and the oxide 230.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to the insulator.
  • these insulators may be nitrided.
  • the insulator 222 may be used by laminating silicon oxide, silicon oxide or silicon nitride on these insulators.
  • the insulator 222 includes, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTIO 3 ), (Ba, Sr) TiO 3 (BST) and the like. Insulators containing so-called high-k materials may be used in single layers or in layers. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for an insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • the insulator 224 in contact with the oxide 230 desorbs oxygen by heating.
  • the insulator 224 silicon oxide, silicon oxide nitride, or the like may be appropriately used.
  • an excess oxygen region a region in which oxygen is excessively present
  • an oxide film containing an excess oxygen region or an excess oxygen is a film in which the amount of desorbed oxygen molecules is 1.0 ⁇ 10 18 molecules / cm 3 or more, preferably 1.0 ⁇ 10 19 in TDS (Thermal Desolation Spectroscopy) analysis.
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
  • the insulator having the excess oxygen region and the oxide 230 may be brought into contact with each other to perform one or more of heat treatment, microwave treatment, or RF treatment. By performing this treatment, water or hydrogen in the oxide 230 can be removed. A part of hydrogen may be diffused or captured (also referred to as gettering) in the conductor 242a and the conductor 242b.
  • the microwave processing for example, it is preferable to use an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side.
  • an apparatus having a power source for generating high-density plasma for example, by using a gas containing oxygen and using a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be generated.
  • the pressure may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more.
  • oxygen and argon are used as the gas to be introduced into the apparatus for performing microwave treatment, and the oxygen flow rate ratio (O 2 / (O 2 + Ar)) is 50% or less, preferably 10% or more and 30%.
  • Microwave processing may be performed below.
  • the heat treatment may be performed, for example, at 100 ° C. or higher and 450 ° C. or lower, more preferably 350 ° C. or higher and 400 ° C. or lower.
  • the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment is preferably performed in an oxygen atmosphere. As a result, oxygen can be supplied to the oxide 230 to reduce oxygen deficiency. Further, the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or an inert gas.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of the oxidizing gas, and then the heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.
  • the reaction of repairing the oxygen deficiency in the oxide 230 with the supplied oxygen can be promoted. Further, since the oxygen supplied to the hydrogen remaining in the oxide 230 is reacted to remove the hydrogen as H 2 O (to dehydration) can. Thus, the hydrogen remained in the oxide 230 can be prevented from recombine V O H is formed by oxygen vacancies.
  • each of the insulator 222 and the insulator 224 may have a laminated structure of two or more layers.
  • the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • Oxide 243a and oxide 243b may be provided on the oxide 230b.
  • Oxide 243a and oxide 243b preferably have a function of suppressing oxygen permeation.
  • an oxide 243a (oxide 243b) having a function of suppressing oxygen permeation between a conductor 242a (conductor 242b) that functions as a source electrode or a drain electrode and an oxide 230b the conductor 242a It is preferable because the electric resistance between (conductor 242b) and oxide 230b is reduced. With such a configuration, the electrical characteristics of the transistor 200 and the reliability of the transistor 200 can be improved. If the electrical resistance between the conductor 242a (conductor 242b) and the oxide 230b can be sufficiently reduced, the oxide 243a (oxide 243b) may not be provided.
  • a metal oxide having an element M may be used as the oxide 243a and the oxide 243b.
  • the element M aluminum, gallium, yttrium, or tin may be used.
  • Oxide 243a and oxide 243b preferably have a higher concentration of element M than oxide 230b.
  • gallium oxide may be used as the oxide 243a and the oxide 243b.
  • a metal oxide such as In—M—Zn oxide may be used.
  • the atomic number ratio of the element M to In is larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 230b.
  • the film thickness of the oxide 243a and the oxide 243b is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and further preferably 1 nm or more and 2 nm or less. Further, the oxides 243a and 243b are preferably crystalline. When the oxides 243a and 243b are crystalline, the release of oxygen in the oxide 230 can be suitably suppressed. For example, if the oxides 243a and 243b have a crystal structure such as hexagonal crystals, the release of oxygen in the oxide 230 may be suppressed.
  • the conductor 242a is provided on the oxide 243a, and the conductor 242b is provided on the oxide 243b.
  • the conductors 242a and 242b include, for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum. It is preferable to use. In this embodiment, a nitride containing tantalum is particularly preferable. Further, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxygen is absorbed.
  • a curved surface may be provided between the side surface of the conductor 242a (conductor 242b) and the upper surface of the conductor 242a (conductor 242b). That is, the side edge and the top edge may be curved.
  • the curved surface has, for example, a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less at each end of the conductor 242a and the conductor 242b.
  • the conductor 242a (conductor 242b) is in contact with the oxide 230b or the oxide 230c, so that the oxygen in the oxide 230b or the oxide 230c becomes conductive. It may diffuse to the body 242a (conductor 242b) and oxidize the conductor 242a (conductor 242b). It is highly probable that the conductivity of the conductor 242a and the conductor 242b will decrease due to the oxidation of the conductor 242a and the conductor 242b.
  • the diffusion of oxygen in the oxide 230b or the oxide 230c to the conductor 242a and the conductor 242b is paraphrased as the conductor 242a and the conductor 242b absorbing the oxygen in the oxide 230b or the oxide 230c. be able to.
  • oxygen in the oxide 230b or the oxide 230c diffuses into the conductor 242a and the conductor 242b, so that between the conductor 242a and the oxide 230b and between the conductor 242b and the oxide 230b, Alternatively, a layer may be formed between the conductor 242a and the oxide 230c, and between the conductor 242b and the oxide 230c. Since the layer contains more oxygen than the conductor 242a or the conductor 242b, it is presumed that the layer has insulating properties.
  • the three-layer structure of the conductor 242a or the conductor 242b, the layer, and the oxide 230b or the oxide 230c can be regarded as a three-layer structure composed of a metal, an insulator, and a semiconductor, and is MIS (Metal). It can be regarded as a -Insulator-Semiconductor) structure or a diode junction structure mainly composed of a MIS structure.
  • hydrogen contained in the oxide 230b, the oxide 230c, etc. may diffuse into the conductor 242a or the conductor 242b.
  • the hydrogen contained in the oxide 230b, the oxide 230c, etc. is easily diffused into the conductor 242a or the conductor 242b, and the diffused hydrogen. May combine with the nitrogen contained in the conductor 242a or the conductor 242b. That is, hydrogen contained in the oxide 230b, the oxide 230c, and the like may be absorbed by the conductor 242a or the conductor 242b.
  • the insulator 254 includes a side surface of the oxide 230a, a side surface of the oxide 230b, a side surface of the oxide 243a, a side surface of the oxide 243b, a side surface of the conductor 242a, an upper surface of the conductor 242a, a side surface of the conductor 242b, and a conductor. It is provided so as to cover the upper surface of 242b.
  • the insulator 254 preferably has a function of suppressing the diffusion of oxygen.
  • the insulator 254 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280.
  • an insulator containing an oxide of one or both of aluminum and hafnium may be formed.
  • the insulator 254 is formed with aluminum oxide or hafnium oxide in an atmosphere containing oxygen by a bias sputtering method.
  • the bias sputtering method is a method of sputtering while applying RF power to a substrate.
  • the potential of the substrate becomes a negative potential (referred to as a bias potential) with respect to the plasma potential, and + ions in the plasma are accelerated by this bias potential and injected into the substrate.
  • the bias potential can be controlled by the magnitude of the RF power applied to the substrate. Therefore, oxygen can be injected into the insulator 224 by forming aluminum oxide or hafnium oxide in an atmosphere containing oxygen by the bias sputtering method.
  • the amount of oxygen injected into the insulator 224 can be controlled by the magnitude of the RF power applied to the substrate.
  • the RF power power density 0.31 W / cm 2 or more, preferably 0.62 W / cm 2 or more, more preferably may be applied to 1.86W / cm 2 or more bias to the substrate. That is, the amount of oxygen suitable for the characteristics of the transistor can be changed and injected by the RF power when the insulator 254 is formed. In addition, an amount of oxygen suitable for improving the reliability of the transistor can be injected.
  • the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz.
  • the amount of oxygen injected into the insulator 224 can be controlled by adjusting the RF power applied to the substrate, so that the amount of oxygen injected into the insulator 224 can be optimized.
  • the bias applied to the substrate is not limited to RF power, but may be DC voltage.
  • the insulator 254 has a function of injecting oxygen into the underlying film, but the insulator 254 itself has a function of suppressing the permeation of oxygen. Therefore, when the insulator 280 is formed on the insulator 254 in a later step and oxygen is diffused from the insulator 280, the oxide 230a, the oxide 230b, the oxide 243a and the oxide 243b are formed from the insulator 280. It is possible to prevent oxygen from directly diffusing into the oxide layer and the conductive layer as the conductor 242a and the conductor 242b.
  • the oxide 230a, the oxide 230b, the oxide 243a, the oxide 243b, the conductor 242a, and the conductor 242b can be separated from the insulator 280. Therefore, it is possible to suppress the direct diffusion of oxygen from the insulator 280 into the oxide 230a, the oxide 230b, the oxide 243a, the oxide 243b, the conductor 242a, and the conductor 242b. This can prevent excess oxygen from being supplied to the source and drain regions of the oxide 230 and reducing the carrier concentration in the source and drain regions. Further, it is possible to prevent the conductors 242a and 242b from being excessively oxidized to increase the resistivity and reduce the on-current.
  • the insulator 250 is preferably arranged in contact with at least a part of the oxide 230d.
  • silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having pores, etc. are used.
  • silicon oxide and silicon oxide nitride are preferable because they are stable against heat.
  • the insulator 250 is preferably formed by using an insulator that releases oxygen by heating.
  • an insulator that releases oxygen by heating As an insulator 250 in contact with at least a part of the oxide 230d, oxygen is effectively supplied to the channel forming region of the oxide 230, and the oxide 230 is provided. Oxygen deficiency in the channel formation region can be reduced. Therefore, it is possible to provide a transistor in which fluctuations in electrical characteristics are suppressed, stable electrical characteristics are realized, and reliability is improved. Further, similarly to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced.
  • the film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.
  • the insulator 250 is shown as a single layer in FIGS. 1B and 1C, it may have a laminated structure of two or more layers. A description of the insulator 250 having a laminated structure will be described later.
  • a metal oxide may be provided between the insulator 250 and the conductor 260.
  • the metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260.
  • the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230.
  • the oxidation of the conductor 260 by oxygen of the insulator 250 can be suppressed.
  • the metal oxide has a function as a part of the first gate electrode.
  • the metal oxide it is possible to improve the on-current of the transistor 200 without weakening the influence of the electric field from the conductor 260.
  • a metal oxide that can be used as the oxide 230 can be used as the metal oxide.
  • the conductor 260a into a film by a sputtering method, the electric resistance value of the metal oxide can be lowered to form a conductor. This can be called an OC (Oxide Conductor) electrode.
  • the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a.
  • the conductor 260a is preferably arranged so as to wrap the bottom surface and the side surface of the conductor 260b.
  • the upper surface of the conductor 260 is arranged substantially in agreement with the upper surface of the insulator 250, the upper surface of the oxide 230d, and the upper surface of the oxide 230c.
  • the conductor 260 is shown as a two-layer structure of the conductor 260a and the conductor 260b in FIGS. 1B and 1C, it may be a single-layer structure or a laminated structure of three or more layers.
  • the conductor 260a it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule and copper atom.
  • impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule and copper atom.
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one oxygen atom, oxygen molecule, etc.
  • the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 260b from being oxidized by the oxygen contained in the insulator 250 to reduce the conductivity.
  • the conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • the conductor 260 also functions as wiring, it is preferable to use a conductor having high conductivity.
  • a conductor having high conductivity for example, as the conductor 260b, a conductive material containing tungsten, copper, or aluminum as a main component can be used.
  • the conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the conductive material.
  • the conductor 260 is self-aligned so as to fill the opening formed in the insulator 280 or the like.
  • the conductor 260 can be reliably arranged in the region between the conductor 242a and the conductor 242b without aligning the conductor 260.
  • the bottom surface of the region of the conductor 260 in which the conductor 260 and the oxide 230b do not overlap is lower than the bottom surface of the oxide 230b in the channel width direction of the transistor 200.
  • the conductor 260 which functions as a gate electrode, covers the side surface and the upper surface of the channel forming region of the oxide 230b via an insulator 250 or the like, so that the electric field of the conductor 260 is covered with the channel forming region of the oxide 230b. It becomes easier to act on the whole. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.
  • the insulator 280 is provided on the insulator 254. Further, the upper surface of the insulator 280 may be flattened.
  • the concentration of impurities such as water and hydrogen in the insulator 280 is reduced.
  • the insulator 280 preferably has a low hydrogen concentration and an excess oxygen region or excess oxygen, and may be provided by using the same material as the insulator 216, for example.
  • the insulator 280 may have a structure in which the above materials are laminated.
  • the insulator 280 may have a laminated structure of silicon oxide formed by a sputtering method and silicon oxide formed on the silicon oxide by a CVD method. .. Further, silicon nitride may be further laminated on the silicon nitride.
  • a conductive material containing tungsten, copper, or aluminum is preferable to use as a main component.
  • each of the conductor 240a and the conductor 240b may have a laminated structure.
  • the conductor in contact with the insulator 284, the insulator 283, the insulator 282, the insulator 280, and the insulator 254 contains impurities such as water and hydrogen.
  • a conductive material having a function of suppressing permeation For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated state.
  • impurities such as water and hydrogen contained in the layer above the insulator 284 can be suppressed from being mixed into the oxide 230 through the conductor 240a and the conductor 240b.
  • an insulator such as silicon nitride, aluminum oxide, or silicon nitride may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 254, impurities such as water and hydrogen contained in the insulator 280 and the like are prevented from being mixed into the oxide 230 through the conductor 240a and the conductor 240b. It can be suppressed.
  • silicon nitride is suitable because it has a high blocking property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240a and the conductor 240b.
  • the conductor 246a which is in contact with the upper surface of the conductor 240a and functions as wiring, and the conductor 246b which is in contact with the upper surface of the conductor 240b and functions as wiring may be arranged.
  • the conductor 246a and the conductor 246b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor may have a laminated structure, for example, titanium or titanium nitride may be laminated with the above-mentioned conductive material.
  • the conductor may be formed so as to be embedded in an opening provided in the insulator.
  • the insulator 286 is provided on the conductor 246a, the conductor 246b, and the insulator 284.
  • the upper surface of the conductor 246a, the side surface of the conductor 246a, the upper surface of the conductor 246b, and the side surface of the conductor 246b are in contact with the insulator 286, and the lower surface of the conductor 246a and the lower surface of the conductor 246b are insulated. It touches the body 284. That is, each of the conductor 246a and the conductor 246b can be wrapped with the insulator 284 and the insulator 286, respectively.
  • the substrate on which the transistor 200 is formed for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria-stabilized zirconia substrate, etc.), a resin substrate, and the like.
  • the semiconductor substrate include a semiconductor substrate made of silicon and germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide.
  • the conductor substrate includes a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate having a metal nitride a substrate having a metal oxide, and the like.
  • a substrate in which a conductor or a semiconductor is provided in an insulator substrate a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like.
  • those substrates provided with elements may be used.
  • Elements provided on the substrate include capacitive elements, resistance elements, switch elements, light emitting elements, storage elements, and the like.
  • Examples of the insulator include oxides, nitrides, oxide nitrides, nitride oxides, metal oxides, metal oxide nitrides, and metal nitride oxides having insulating properties.
  • the material may be selected according to the function of the insulator.
  • Examples of the insulator having a high specific dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, nitrides having aluminum and hafnium, oxides having silicon and hafnium, silicon and hafnium. There are nitrides having oxides, or nitrides having silicon and hafnium.
  • Examples of insulators having a low relative permittivity include silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, and empty. There are silicon oxide having holes, resin, and the like.
  • the electric characteristics of the transistor can be stabilized by surrounding the transistor using the metal oxide with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen.
  • the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators containing, lanthanum, neodymium, hafnium, or tantalum may be used in single layers or in layers.
  • an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen
  • Metal oxides such as tantalum oxide and metal nitrides such as aluminum nitride, silicon nitride and silicon nitride can be used.
  • the insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating.
  • the oxygen deficiency of the oxide 230 can be compensated.
  • Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like.
  • tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. are used. Is preferable.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a plurality of conductive layers formed of the above materials may be laminated and used.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
  • the conductor functioning as the gate electrode shall have a laminated structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. Is preferable.
  • a conductive material containing oxygen may be provided on the channel forming region side.
  • a conductor that functions as a gate electrode it is preferable to use a conductive material containing a metal element and oxygen contained in a metal oxide in which a channel is formed.
  • the above-mentioned conductive material containing a metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • Metal oxide As the oxide 230, it is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor.
  • a metal oxide oxide semiconductor
  • the metal oxide applicable to the oxide 230 according to the present invention will be described.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, it is preferable that aluminum, gallium, yttrium, tin and the like are contained. Further, one or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like may be contained.
  • a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.
  • FIG. 3A is a diagram illustrating the classification of crystal structures of oxide semiconductors, typically IGZO (metal oxides containing In, Ga, and Zn).
  • IGZO metal oxides containing In, Ga, and Zn.
  • oxide semiconductors are roughly classified into “Amorphous (amorphous)”, “Crystalline (crystallinity)", and “Crystal (crystal)”.
  • Amorphous includes “completable amorphous”.
  • Crystalline includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite).
  • single crystal, poly crystal, and single crystal amorphous are excluded from the classification of "Crystalline”.
  • “Crystal” includes single crystal and poly crystal.
  • the structure in the thick frame shown in FIG. 3A is an intermediate state between "Amorphous” and “Crystal", and belongs to a new boundary region (New crystal line phase). .. That is, the structure can be rephrased as a structure completely different from the energetically unstable "Amorphous” and "Crystal".
  • the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Evaluation) spectrum.
  • XRD X-ray diffraction
  • FIG. 3B the XRD spectrum obtained by GIXD (Glazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline" is shown in FIG. 3B.
  • the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
  • the XRD spectrum obtained by the GIXD measurement shown in FIG. 3B will be simply referred to as an XRD spectrum.
  • the thickness of the CAAC-IGZO film shown in FIG. 3B is 500 nm.
  • the horizontal axis is 2 ⁇ [deg. ], And the vertical axis is the intensity [a. u. ].
  • a peak showing clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film.
  • the crystal structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a microelectron diffraction pattern) observed by a micro electron diffraction method (NBED: Nano Beam Electron Diffraction).
  • the diffraction pattern of the CAAC-IGZO film is shown in FIG. 3C.
  • FIG. 3C is a diffraction pattern observed by the NBED in which the electron beam is incident parallel to the substrate.
  • electron beam diffraction is performed with the probe diameter set to 1 nm.
  • oxide semiconductors may be classified differently from FIG. 3A.
  • oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS.
  • the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, an a-like OS, an amorphous oxide semiconductor, and the like.
  • nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • nc-OS has tiny crystals. Since the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also referred to as a nanocrystal.
  • nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
  • the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method.
  • a peak indicating crystallinity is not detected in the Out-of-plane XRD measurement using a ⁇ / 2 ⁇ scan.
  • electron beam diffraction also referred to as limited field electron diffraction
  • a diffraction pattern such as a halo pattern is performed. Is observed.
  • electron diffraction also referred to as nanobeam electron diffraction
  • an electron beam having a probe diameter for example, 1 nm or more and 30 nm or less
  • An electron diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be acquired.
  • the a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or low density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.
  • a-like OS has a higher hydrogen concentration in the membrane than nc-OS and CAAC-OS.
  • CAC-OS relates to the material composition.
  • CAC-OS is, for example, a composition of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
  • the mixed state is also called a mosaic shape or a patch shape.
  • CAC-OS has a structure in which the material is separated into a first region and a second region to form a mosaic shape, and the first region is distributed in the membrane (hereinafter, also referred to as a cloud shape). It says.). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
  • the atomic number ratios of In, Ga, and Zn to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively.
  • the first region is a region in which [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region in which [Ga] is larger than [Ga] in the composition of the CAC-OS film.
  • the first region is a region in which [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
  • the first region is a region in which indium oxide, indium zinc oxide, or the like is the main component.
  • the second region is a region in which gallium oxide, gallium zinc oxide, or the like is the main component. That is, the first region can be rephrased as a region containing In as a main component. Further, the second region can be rephrased as a region containing Ga as a main component.
  • a region containing In as a main component (No. 1) by EDX mapping acquired by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region (1 region) and the region containing Ga as a main component (second region) have a structure in which they are unevenly distributed and mixed.
  • EDX Energy Dispersive X-ray spectroscopy
  • CAC-OS When CAC-OS is used for a transistor, the conductivity caused by the first region and the insulating property caused by the second region act in a complementary manner to switch the switching function (On / Off function). Can be added to CAC-OS. That is, the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS as a transistor, high on-current ( Ion ), high field effect mobility ( ⁇ ), and good switching operation can be realized.
  • Ion on-current
  • ⁇ high field effect mobility
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of the present embodiment has two or more kinds of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS. May be good.
  • the oxide semiconductor as a transistor, a transistor with high field effect mobility can be realized. Moreover, a highly reliable transistor can be realized.
  • the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm -3 or less, preferably 1 ⁇ 10 15 cm -3 or less, more preferably 1 ⁇ 10 13 cm -3 or less, and more preferably 1 ⁇ 10 11 cm ⁇ . It is 3 or less, more preferably less than 1 ⁇ 10 10 cm -3 , and more than 1 ⁇ 10 -9 cm -3 .
  • the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • the case where the carrier concentration of the metal oxide in the channel forming region is 1 ⁇ 10 16 cm -3 or less is defined as substantially high purity authenticity.
  • the trap level density may also be low.
  • the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel forming region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.
  • the resistance of the oxide semiconductor may be lowered.
  • the electrical characteristics are liable to fluctuate, and reliability may deteriorate.
  • a leakage current (parasitic channel) between the source electrode and the drain electrode of the transistor is generated in the low resistance region.
  • parasitic channel tends to cause poor transistor characteristics such as normalization of the transistor, increase in leakage current, and fluctuation (shift) of the threshold voltage due to stress application.
  • the parasitic channel varies from transistor to transistor, resulting in variation in transistor characteristics.
  • the impurity concentration in the oxide semiconductor in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the adjacent film.
  • Impurities mixed in oxide semiconductors may cause defect levels or oxygen deficiencies. Therefore, when impurities are mixed in the channel forming region of the oxide semiconductor, the electrical characteristics of the transistor using the oxide semiconductor are likely to fluctuate, and the reliability may be deteriorated. Further, when the channel formation region contains oxygen deficiency, the transistor tends to have a normal-on characteristic (a characteristic that a channel exists even if a voltage is not applied to the gate electrode and a current flows through the transistor).
  • Transistors using metal oxides tend to have normal-on characteristics because their electrical characteristics fluctuate due to impurities and oxygen deficiency in the metal oxides. Further, when the transistor is driven in a state where the metal oxide contains excess oxygen exceeding an appropriate amount value, the valence of the excess oxygen atom changes and the electrical characteristics of the transistor fluctuate. , May be unreliable.
  • the crystallinity of the channel forming region may be lowered, or the crystallinity of the oxide provided in contact with the channel forming region may be lowered. Poor crystallinity in the channel formation region tends to reduce the stability or reliability of the transistor. Further, if the crystallinity of the oxide provided in contact with the channel forming region is low, an interface state may be formed and the stability or reliability of the transistor may be deteriorated.
  • Impurities in metal oxides include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon near the interface with the oxide semiconductor are 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ . 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, and more preferably 1 ⁇ 10 18 atoms / cm 3 or less. , More preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • FIG. 4A shows a top view of the semiconductor device.
  • FIG. 4B is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line of A1-A2 in FIG. 4A.
  • FIG. 4C is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line of A3-A4 in FIG. 4A.
  • FIG. 4D is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line in FIG. 4A.
  • some elements are omitted for the sake of clarity.
  • the same reference numerals are added to the structures having the same functions as the structures constituting the semiconductor devices shown in ⁇ Semiconductor device configuration example>.
  • the constituent material of the semiconductor device the material described in detail in ⁇ Semiconductor device configuration example> can be used.
  • the semiconductor device shown in FIGS. 4A to 4D is a modification of the semiconductor device shown in FIGS. 1A to 1D.
  • the semiconductor device shown in FIGS. 4A to 4D has a different shape of the insulator 283 from the semiconductor device shown in FIGS. 1A to 1D. It is also different from having an insulator 287 and an insulator 274. Another difference is that it does not have an insulator 284.
  • the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 254, the insulator 280, and the insulator 282 are patterned. Further, the insulator 287 and the insulator 283 have a structure that covers the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 254, the insulator 280, and the insulator 282.
  • the insulator 287 includes the upper surface of the insulator 212, the side surface of the insulator 214, the side surface of the insulator 216, the side surface of the insulator 222, the side surface of the insulator 224, the side surface of the insulator 254, the side surface of the insulator 280, and the insulator. It is in contact with the side surface of the body 282 and the upper surface of the insulator 282, and the insulator 283 is in contact with the upper surface and the side surface of the insulator 287.
  • the oxide 230, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 254, the insulator 280, and the insulator 282 become the insulator 287, the insulator 283, and the insulator 212. Is isolated from the outside. In other words, the transistor 200 is arranged in the region sealed by the insulator 287 and the insulator 283 and the insulator 212.
  • insulator 214, insulator 282, and insulator 287 are formed using a material having a function of capturing hydrogen and fixing hydrogen, and insulator 212 and insulator 283 suppress diffusion to hydrogen and oxygen. It is preferable to form it using a material having a function of forming.
  • aluminum oxide can be used as the insulator 214, the insulator 282, and the insulator 287.
  • silicon nitride can be used as the insulator 212 and the insulator 283.
  • the configuration in which the insulator 212, the insulator 287, and the insulator 283 are provided as a single layer is shown, but the present embodiment is not limited to this. ..
  • the insulator 212, the insulator 287, and the insulator 283 may each be provided as a laminated structure of two or more layers.
  • the insulator 287 does not have to be provided.
  • the transistor 200 is arranged in the region sealed by the insulator 212 and the insulator 283.
  • the insulator 274 functions as an interlayer film.
  • the insulator 274 preferably has a lower dielectric constant than the insulator 214.
  • the insulator 274 can be provided, for example, by using the same material as the insulator 280.
  • 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A show top views.
  • 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, and 17B are FIGS. 5A, 6A, and 17B, respectively.
  • 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A are cross-sectional views corresponding to the parts indicated by the alternate long and short dash lines of A1-A2. It is also a cross-sectional view of the transistor 200 in the channel length direction.
  • FIGS. 5A, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C, 16C, and 17C are FIGS. 5A, 6A, and 17C, respectively.
  • 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A are cross-sectional views corresponding to the parts indicated by the alternate long and short dash lines of A3-A4. It is also a cross-sectional view of the transistor 200 in the channel width direction.
  • 5D, 6D, 7D, 8D, 9D, 10D, 11D, 12D, 13D, 14D, 15D, 16D, and 17D are FIGS. 5A, 6A, and 17D, respectively.
  • 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A are cross-sectional views corresponding to the parts indicated by the alternate long and short dash lines of A5-A6. .. Clarification of the figures in the top views of FIGS. 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A. Some elements are omitted for the sake of.
  • a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate.
  • the film formation of the insulator 212 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, an optical CVD (Photo CVD) method using light, and the like. .. Further, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organometallic CVD (MOCVD: Metal organic CVD) method depending on the raw material gas used.
  • PECVD Plasma Enhanced CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal organic CVD
  • the plasma CVD method can obtain a high quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film forming method capable of reducing plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) and the like included in a semiconductor device may be charged up by receiving electric charges from plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased. Further, in the thermal CVD method, plasma damage does not occur during film formation, so that a film having few defects can be obtained.
  • a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactor is performed only by thermal energy, a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactor, or the like can be used.
  • the ALD method utilizes the self-regulating properties of atoms and allows atoms to be deposited layer by layer, so ultra-thin film formation is possible, and film formation into structures with a high aspect ratio is possible. It has the effects of being able to form a film with few defects such as holes, being able to form a film with excellent coverage, and being able to form a film at a low temperature.
  • PEALD Pulsma Enhanced ALD
  • Some precursors used in the ALD method contain impurities such as carbon.
  • the film provided by the ALD method may contain a large amount of impurities such as carbon as compared with the film provided by other film forming methods.
  • the quantification of impurities can be performed by using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).
  • the CVD method and the ALD method are different from the film forming method in which particles emitted from a target or the like are deposited, and are film forming methods in which a film is formed by a reaction on the surface of an object to be treated. Therefore, it is a film forming method that is not easily affected by the shape of the object to be treated and has good step coverage.
  • the ALD method has excellent step covering property and excellent thickness uniformity, and is therefore suitable for covering the surface of an opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method having a high film formation rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the raw material gas.
  • a film having an arbitrary composition can be formed depending on the flow rate ratio of the raw material gas.
  • a film having a continuously changed composition can be formed by changing the flow rate ratio of the raw material gas while forming the film.
  • silicon nitride is formed as the insulator 212 by a sputtering method.
  • an insulator such as silicon nitride that does not easily allow copper to permeate as the insulator 212, even if a metal such as copper that easily diffuses is used for the conductor in the lower layer (not shown) of the insulator 212. , It is possible to prevent the metal from diffusing upward through the insulator 212.
  • an insulator such as silicon nitride which is difficult for impurities such as water and hydrogen to permeate, diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed.
  • the insulator 214 is formed on the insulator 212.
  • the film formation of the insulator 214 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • aluminum oxide is used as the insulator 214.
  • the hydrogen concentration of the insulator 214 is preferably lower than the hydrogen concentration of the insulator 212.
  • silicon nitride as the insulator 212 by a sputtering method, silicon nitride having a low hydrogen concentration can be formed. Further, by using aluminum oxide for the insulator 214, the hydrogen concentration can be made lower than that of the insulator 212.
  • the transistor 200 is formed on the insulator 214 in the subsequent step.
  • the film close to the transistor 200 preferably has a relatively low hydrogen concentration, and the film having a relatively high hydrogen concentration is remote from the transistor 200. It is preferable to arrange them.
  • the insulator 216 is formed on the insulator 214.
  • the film formation of the insulator 216 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide or silicon oxide nitride is used as the insulator 216.
  • the insulator 216 is formed by a film forming method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulator 216 can be reduced.
  • an opening is formed in the insulator 216 to reach the insulator 214.
  • the opening also includes, for example, a groove or a slit. Further, the region where the opening is formed may be referred to as an opening. Wet etching may be used to form the openings, but dry etching is preferable for microfabrication.
  • the insulator 214 it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove. For example, when silicon oxide or silicon oxide nitride is used for the insulator 216 forming the groove, silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214.
  • a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate type electrodes can be used.
  • the capacitively coupled plasma etching apparatus having the parallel plate type electrodes may be configured to apply a high frequency voltage to one of the parallel plate type electrodes.
  • a plurality of different high frequency voltages may be applied to one of the parallel plate type electrodes.
  • a high frequency voltage having the same frequency may be applied to each of the parallel plate type electrodes.
  • a high frequency voltage having a different frequency may be applied to each of the parallel plate type electrodes.
  • a dry etching apparatus having a high-density plasma source can be used.
  • an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching apparatus or the like can be used.
  • a conductive film to be the conductor 205a is formed. It is desirable that the conductive film contains a conductor having a function of suppressing the permeation of oxygen.
  • a conductor having a function of suppressing the permeation of oxygen For example, tantalum nitride, tungsten nitride, titanium nitride and the like can be used. Alternatively, it can be a laminated film of a conductor having a function of suppressing oxygen permeation and a tantalum, tungsten, titanium, molybdenum, aluminum, copper or molybdenum tungsten alloy.
  • the film formation of the conductive film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 205a has a multilayer structure.
  • tantalum nitride is formed into a film by a sputtering method, and titanium nitride is laminated on the tantalum nitride.
  • a metal nitride in the lower layer of the conductor 205b, even if a easily diffusible metal such as copper is used as the conductive film to be the conductor 205b described later, the metal diffuses out from the conductor 205a. Can be prevented.
  • a conductive film to be the conductor 205b is formed.
  • the film formation of the conductive film can be performed by using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a low resistance conductive material such as copper is formed as the conductive film.
  • a part of the conductive film to be the conductor 205a and a part of the conductive film to be the conductor 205b is removed, and the insulator 216 is exposed.
  • the conductor 205a and the conductor 205b remain only in the opening.
  • the conductor 205 having a flat upper surface can be formed (see FIGS. 5A to 5D).
  • a part of the insulator 216 may be removed by the CMP treatment.
  • the conductor 205 is formed so as to be embedded in the opening of the insulator 216, but one aspect of the present invention is not limited to this.
  • a conductor 205 is formed on the insulator 214, an insulator 216 is formed on the insulator 205, and the insulator 216 is subjected to CMP treatment to remove a part of the insulator 216 and to remove the conductor.
  • the surface of 205 may be exposed.
  • the insulator 222 is formed on the insulator 216 and the conductor 205.
  • an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Insulators containing oxides of one or both of aluminum and hafnium have barrier properties against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in the structure provided around the transistor 200 are suppressed from diffusing into the inside of the transistor 200 through the insulator 222. , The formation of oxygen deficiency in the oxide 230 can be suppressed.
  • the film formation of the insulator 222 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the heat treatment may be carried out at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, and more preferably 320 ° C. or higher and 450 ° C. or lower.
  • the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the oxygen gas may be set to about 20%.
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then the heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement the desorbed oxygen. You may.
  • the gas used in the above heat treatment is highly purified.
  • the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • the treatment is performed at a temperature of 400 ° C. for 1 hour with the flow rate of nitrogen gas as 4 slm and the flow rate of oxygen gas as 1 slm.
  • impurities such as water and hydrogen contained in the insulator 222 can be removed.
  • the heat treatment can be performed at a timing such as after the film formation of the insulator 224 is performed.
  • the insulator 224 is formed on the insulator 222.
  • the film formation of the insulator 224 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide or silicon oxide film is formed as the insulator 224 by the CVD method.
  • the insulator 224 is preferably formed by a film forming method using a gas in which hydrogen atoms have been reduced or removed. Thereby, the hydrogen concentration of the insulator 224 can be reduced. Since the insulator 224 becomes an insulator 224 that comes into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this way.
  • plasma treatment containing oxygen may be performed in a reduced pressure state.
  • the plasma treatment containing oxygen for example, it is preferable to use an apparatus having a power source for generating high-density plasma using microwaves.
  • the substrate side may have a power supply for applying RF (Radio Frequency).
  • RF Radio Frequency
  • high-density plasma high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224. it can.
  • plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, the heat treatment does not have to be performed.
  • CMP treatment may be performed until the insulator 224 is reached.
  • the surface of the insulator 224 can be flattened and smoothed.
  • a part of the insulator 224 may be polished by the CMP treatment to reduce the film thickness of the insulator 224, but the film thickness may be adjusted when the insulator 224 is formed.
  • oxygen can be added to the insulator 224 by forming aluminum oxide on the insulator 224 by a sputtering method.
  • the oxide film 230A and the oxide film 230B are formed on the insulator 224 in this order (see FIGS. 5A to 5D). It is preferable that the oxide film 230A and the oxide film 230B are continuously formed without being exposed to the atmospheric environment. By forming the film without opening it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B. Can be kept clean.
  • the oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230A and the oxide film 230B are formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas.
  • excess oxygen in the oxide film formed can be increased.
  • the above oxide film is formed by a sputtering method
  • the above In—M—Zn oxide target or the like can be used.
  • the proportion of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.
  • the oxide film 230B is formed by a sputtering method, if the ratio of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, the oxygen excess type oxidation is performed. A physical semiconductor is formed. Transistors using oxygen-rich oxide semiconductors in the channel formation region can obtain relatively high reliability. However, one aspect of the present invention is not limited to this.
  • the oxide film 230B is formed by a sputtering method and the ratio of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. To. A transistor using an oxygen-deficient oxide semiconductor in the channel formation region can obtain a relatively high field-effect mobility. Further, the crystallinity of the oxide film can be improved by forming a film while heating the substrate.
  • an oxide film 243A is formed on the oxide film 230B (see FIGS. 5A to 5D).
  • the oxide film 243A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the atomic number ratio of Ga to In is preferably larger than the atomic number ratio of Ga to In in the oxide film 230B.
  • the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A without exposing them to the atmosphere.
  • a multi-chamber type film forming apparatus may be used.
  • the heat treatment conditions described in ⁇ Metal oxide and its formation method> can be used.
  • the treatment after performing the treatment at a temperature of 550 ° C. for 1 hour in a nitrogen atmosphere, the treatment is continuously performed at a temperature of 550 ° C. for 1 hour in an oxygen atmosphere.
  • impurities such as water and hydrogen in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be removed.
  • the heat treatment can improve the crystallinity of the oxide film 230B to obtain a denser and more dense structure. As a result, the diffusion of oxygen or impurities in the oxide film 230B can be suppressed.
  • a conductive film 242A is formed on the oxide film 243A (see FIGS. 5A to 5D).
  • the film formation of the conductive film 242A can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the heat treatment may be performed before the film formation of the conductive film 242A.
  • the heat treatment may be carried out under reduced pressure to continuously form a conductive film 242A without exposing it to the atmosphere. By performing such a treatment, water and hydrogen adsorbed on the surface of the oxide film 243A and the like are removed, and the water concentration and the hydrogen concentration in the oxide film 230A, the oxide film 230B, and the oxide film 243A are further increased. It can be reduced.
  • the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower. In the present embodiment, the temperature of the heat treatment is set to 200 ° C.
  • the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are processed into an island shape by using a lithography method to form an oxide 230a, an oxide 230b, an oxide layer 243B, and a conductive layer 242B.
  • a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for microfabrication.
  • the processing of the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A may be performed under different conditions. In this step, the film thickness of the region that does not overlap with the oxide 230a of the insulator 224 may be reduced (see FIGS. 6A to 6D).
  • the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are formed so that at least a part thereof overlaps with the conductor 205. Further, it is preferable that the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are substantially perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are substantially perpendicular to the upper surface of the insulator 222, the area is reduced and the height is increased when a plurality of transistors 200 are provided. It is possible to increase the density.
  • the angle formed by the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B and the upper surface of the insulator 222 may be low.
  • the covering property of the insulator 254 and the like can be improved and defects such as voids can be reduced in the subsequent steps.
  • the curved surface has, for example, a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less at the end of the conductive layer 242B.
  • the insulator 254 is formed on the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B (see FIGS. 7B to 7D).
  • the film formation of the insulator 254 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • aluminum oxide is formed as the insulator 254 by a sputtering method.
  • an insulating film to be the insulator 280 is formed on the insulator 254.
  • the film formation of the insulating film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide film may be formed by using a sputtering method, and a silicon oxide film may be formed on the silicon oxide film by using a PEALD method or a thermal ALD method.
  • the insulating film is formed by a film forming method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulator 280 can be reduced.
  • heat treatment may be performed before the film formation of the insulating film.
  • the heat treatment may be performed under reduced pressure to continuously form the insulating film without exposing it to the atmosphere.
  • water and hydrogen adsorbed on the surface of the insulator 254 and the like are removed, and further, in the oxide 230a, in the oxide 230b, in the oxide layer 243B, and in the insulator 224.
  • the water concentration and hydrogen concentration can be reduced.
  • the above-mentioned heat treatment conditions can be used for the heat treatment.
  • the insulating film is subjected to CMP treatment to form an insulator 280 having a flat upper surface (see FIGS. 7B to 7D).
  • CMP treatment Similar to the insulator 224, aluminum oxide may be formed on the insulator 280 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 280.
  • microwave processing may be performed.
  • the microwave treatment is preferably performed in an atmosphere containing oxygen and under reduced pressure.
  • the hydrogen concentration in the oxide 230b and the oxide 230a can be reduced.
  • a part of hydrogen may be gettered to the conductor 242a and the conductor 242b via the insulator 254.
  • the heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment.
  • hydrogen in the insulator 280, the oxide 230b, and the oxide 230a can be efficiently removed.
  • the heat treatment temperature is preferably 300 ° C. or higher and 500 ° C. or lower.
  • the film quality of the insulator 280 by modifying the film quality of the insulator 280 by performing microwave treatment, it is possible to suppress the diffusion of hydrogen, water, impurities and the like. Therefore, it is possible to prevent hydrogen, water, impurities, etc. from diffusing into the oxide 230 through the insulator 280 by a post-process after forming the insulator 280, heat treatment, or the like.
  • a part of the insulator 280, a part of the insulator 254, a part of the conductive layer 242B, and a part of the oxide layer 243B are processed to form an opening reaching the oxide 230b.
  • the opening is preferably formed so as to overlap the conductor 205.
  • a conductor 242a, a conductor 242b, an oxide 243a, and an oxide 243b are formed (see FIGS. 8A to 8D).
  • the upper part of the oxide 230b is removed.
  • a groove is formed in the oxide 230b.
  • the groove may be formed in the opening forming step, or may be formed in a step different from the opening forming step.
  • the processing of a part of the insulator 280, a part of the insulator 254, a part of the conductive layer 242B, a part of the oxide layer 243B, and a part of the oxide 230b is performed by a dry etching method or a wet etching method. Can be used. Processing by the dry etching method is suitable for microfabrication. Further, the processing may be performed under different conditions. For example, a part of the insulator 280 is processed by a dry etching method, a part of the insulator 254 is processed by a wet etching method, and a part of the oxide layer 243B, a part of the conductive layer 242B, and the oxide 230b are processed. A part may be processed by a dry etching method. Further, the processing of a part of the oxide layer 243B and a part of the conductive layer 242B and the processing of a part of the oxide 230b may be performed under different conditions.
  • the power density of the bias power is preferably to 0.03 W / cm 2 or more, more preferably between 0.06 W / cm 2 or more.
  • the dry etching processing time may be appropriately set according to the depth of the groove portion.
  • impurities adhering to or diffused inside the surface such as oxide 230a and oxide 230b.
  • the impurities include a component contained in the insulator 280, the insulator 254, and the conductive layer 242B, a component contained in a member used in the apparatus used for forming the opening, and a gas or liquid used for etching. Examples include those caused by the components contained in.
  • the impurities include aluminum, silicon, tantalum, fluorine, chlorine and the like.
  • the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleanings may be appropriately combined.
  • the cleaning treatment may deepen the groove.
  • the cleaning treatment may be performed using an aqueous solution obtained by diluting ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid or the like with carbonated water or pure water, pure water, carbonated water or the like.
  • ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water.
  • these washings may be appropriately combined.
  • a commercially available aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid
  • a commercially available aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water.
  • concentration, temperature, etc. of the aqueous solution may be appropriately adjusted depending on the impurities to be removed, the configuration of the semiconductor device to be washed, and the like.
  • the ammonia concentration of the diluted ammonia water may be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less.
  • the hydrogen fluoride concentration of the diluted hydrofluoric acid may be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.
  • a frequency of 200 kHz or higher, preferably 900 kHz or higher for ultrasonic cleaning it is preferable to use a frequency of 200 kHz or higher, preferably 900 kHz or higher for ultrasonic cleaning. By using this frequency, damage to the oxide 230b and the like can be reduced.
  • the above cleaning treatment may be performed a plurality of times, and the cleaning liquid may be changed for each cleaning treatment.
  • a treatment using diluted hydrofluoric acid or diluted aqueous ammonia may be performed as the first cleaning treatment
  • a treatment using pure water or carbonated water may be performed as the second cleaning treatment.
  • wet cleaning is performed using diluted hydrofluoric acid, and then wet cleaning is performed using pure water or carbonated water.
  • impurities adhering to or diffused inside the surface such as oxide 230a and oxide 230b can be removed. Further, the crystallinity of the oxide 230c formed on the oxide 230b can be enhanced.
  • the heat treatment may be performed after the etching or the cleaning.
  • the heat treatment may be performed at 100 ° C. or higher and 450 ° C. or lower, preferably 350 ° C. or higher and 400 ° C. or lower.
  • the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen can be supplied to the oxide 230a and the oxide 230b to reduce the oxygen deficiency.
  • the crystallinity of the oxide 230b can be improved, and the crystallinity of the oxide 230c formed in the groove portion of the oxide 230b can also be improved.
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be continuously performed in a nitrogen atmosphere without being exposed to the atmosphere.
  • the oxide film 230C is formed.
  • the heat treatment may be performed before the oxide film 230C is formed, and it is preferable that the heat treatment is performed under reduced pressure to continuously form the oxide film 230C without exposing to the atmosphere. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, it is possible to remove the water and hydrogen adsorbed on the surface of the oxide 230b and the like, and further reduce the water concentration and the hydrogen concentration in the oxide 230a and the oxide 230b.
  • the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower. In the present embodiment, the temperature of the heat treatment is set to 200 ° C.
  • the oxide film 230C is at least the inner wall of the groove formed in the oxide 230b, a part of the side surface of the oxide 243a, a part of the side surface of the oxide 243b, a part of the side surface of the conductor 242a, and the conductor 242b. It is preferably provided so as to be in contact with a part of the side surface of the insulator 254, a part of the side surface of the insulator 254, and a part of the side surface of the insulator 280.
  • the conductor 242a (conductor 242b) is surrounded by the oxide 343a (oxide 243b), the insulator 254, and the oxide film 230C, so that the conductivity due to the oxidation of the conductor 242a (conductor 242b) in the subsequent steps Can be suppressed.
  • the film formation of the oxide film 230C can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230C may be formed by using the same film forming method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230C.
  • a part of oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b.
  • a part of oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%. Further, by forming the oxide film 230C in such an atmosphere containing a large amount of oxygen, the oxide film 230C can be easily converted into CAAC-OS.
  • the oxide film 230C is formed while heating the substrate. At this time, by setting the substrate temperature to 200 ° C. or higher, oxygen deficiency in the oxide film 230C and the oxide 230b can be reduced. By forming a film while heating the substrate, the crystallinity of the oxide film 230C and the oxide 230b can be improved.
  • a part of the oxide film 230C is selectively removed by a lithography method (see FIGS. 9A, 9C and 9D).
  • a part of the oxide film 230C may be removed by a wet etching method or the like.
  • a part of the oxide film 230C located between the transistors 200 adjacent to each other in the channel width direction can be removed.
  • the surface of the insulator 224 and the surface of the insulator 280 are exposed in the region where a part of the oxide film 230C is removed by the above step. At this time, the film thickness of the insulator 224 and the film thickness of the insulator 280 in the region may be reduced. In addition, the insulator 224 in the region may be removed to expose the surface of the insulator 222.
  • an oxide film 230D is formed (see FIGS. 10A to 10D).
  • the oxide film 230D can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230D may be formed by using the same film forming method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230D.
  • the proportion of oxygen contained in the sputtering gas of the oxide film 230D may be 70% or more, preferably 80% or more, and more preferably 100%.
  • an insulating film 250A is formed (see FIGS. 10A to 10D).
  • the heat treatment may be performed before the film formation of the insulating film 250A, and the heat treatment may be performed under reduced pressure to continuously form the insulating film 250A without exposure to the atmosphere. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, water and hydrogen adsorbed on the surface of the oxide film 230D and the like are removed, and further, water content in the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D is removed. The concentration and hydrogen concentration can be reduced.
  • the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower.
  • the insulating film 250A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the insulating film 250A is preferably formed by a film forming method using a gas in which hydrogen atoms have been reduced or removed. Thereby, the hydrogen concentration of the insulating film 250A can be reduced. Since the insulating film 250A becomes an insulator 250 in contact with the oxide 230d in a later step, it is preferable that the hydrogen concentration is reduced in this way.
  • microwave treatment may be performed in an atmosphere containing oxygen and under reduced pressure.
  • the hydrogen concentration in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be reduced.
  • a part of hydrogen may be gettered on the conductor 242a and the conductor 242b.
  • the oxide 230a, in the oxide 230b, the oxide film 230C, and the V O in the oxide film 230D can repair or compensate.
  • the heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment.
  • hydrogen in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be efficiently removed.
  • a part of hydrogen may be gettered on the conductor 242a and the conductor 242b.
  • the step of performing the heat treatment may be repeated a plurality of times while maintaining the reduced pressure state after the microwave treatment. By repeating the heat treatment, hydrogen in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be removed more efficiently.
  • the heat treatment temperature is preferably 300 ° C. or higher and 500 ° C. or lower.
  • the film quality of the insulating film 250A by modifying the film quality of the insulating film 250A by performing microwave treatment, it is possible to suppress the diffusion of hydrogen, water, impurities and the like. Therefore, hydrogen, water, impurities, etc. are diffused to the oxide 230b, the oxide 230a, etc. through the insulator 250 by a post-process such as film formation of a conductive film to be a conductor 260 or a post-treatment such as heat treatment. It can be suppressed.
  • a post-process such as film formation of a conductive film to be a conductor 260 or a post-treatment such as heat treatment. It can be suppressed.
  • the conductive film 260A and the conductive film 260B are formed in this order (see FIGS. 11A to 11D).
  • the film formation of the conductive film 260A and the conductive film 260B can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film 260A is formed by using the ALD method
  • the conductive film 260B is formed by using the CVD method.
  • the oxide film 230C, the oxide film 230D, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished until the insulator 280 is exposed, so that the oxide 230c, the oxide 230d, and the insulator are exposed.
  • 250 and conductor 260 are formed (see FIGS. 12A-12D).
  • the oxide 230c is arranged so as to cover a part of the inner wall (side wall and bottom surface) of the opening reaching the oxide 230b and the groove portion of the oxide 230b.
  • the oxide 230d is arranged so as to cover the opening and the inner wall of the groove via the oxide 230c.
  • the insulator 250 is arranged so as to cover the inner wall of the opening and the groove portion via the oxide 230c and the oxide 230d.
  • the conductor 260 is arranged so as to embed the opening and the groove through the oxide 230c, the oxide 230d, and the insulator 250.
  • heat treatment may be performed.
  • the treatment is carried out in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour.
  • the heat treatment the water concentration and the hydrogen concentration in the insulator 250 and the insulator 280 can be reduced.
  • the insulator 282 may be continuously formed without being exposed to the atmosphere.
  • the insulator 282 is formed on the oxide 230c, the oxide 230d, the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 13B to 13D).
  • the film formation of the insulator 282 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • oxygen can be added to the insulator 280 while forming the film.
  • the insulator 282 it is preferable to form the insulator 282 while heating the substrate. Further, by forming the insulator 282 in contact with the upper surface of the conductor 260, it is possible to suppress the oxygen contained in the insulator 280 from being absorbed by the conductor 260 in the subsequent heat treatment, which is preferable. ..
  • a portion is processed to form an opening that reaches the insulator 212 (see FIGS. 14A-14D).
  • the opening may be formed so as to surround the transistor 200.
  • the opening may be formed so as to surround a plurality of transistors 200.
  • a dry etching method or a wet etching method can be used for processing. Processing by the dry etching method is suitable for microfabrication. Further, the processing may be performed under different conditions. In this step, the film thickness of the region overlapping the opening of the insulator 212 may be reduced.
  • the insulator 282, the insulator 280, the insulator 254, the insulator 224, the insulator 222, the insulator 216, and the insulator 214 are covered to form the insulator 287 (see FIGS. 15B to 15D). ..
  • the film formation of the insulator 287 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 287 may have multiple layers. For example, aluminum oxide may be formed on the aluminum oxide by a sputtering method, and silicon nitride may be formed on the aluminum oxide by a sputtering method. As shown in FIGS.
  • the insulator 287 is in contact with the insulator 212 at the bottom surface of the opening. That is, the upper surface and the side surface of the transistor 200 are wrapped in the insulator 287, and the lower surface is wrapped in the insulator 212.
  • the transistor 200 By wrapping the transistor 200 with the insulator 287 and the insulator 212 having high barrier properties in this way, it is possible to prevent water and hydrogen from entering from the outside.
  • the insulator 283 may be formed on the insulator 287 (see FIGS. 15B to 15D).
  • the insulator 283 is preferably formed by a film forming method having a high film property.
  • the film formation of the insulator 283 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, it is preferable to use the same material as the insulator 212 for the insulator 283.
  • the insulator 283 may be formed by a CVD method using a compound gas that does not contain hydrogen atoms or has a low content of hydrogen atoms.
  • an insulating film to be the insulator 274 is formed on the insulator 283.
  • the film formation of the insulating film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a sputtering method e.g., a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film is formed by the above-mentioned film forming method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulating film can be reduced.
  • the insulating film to be the insulator 274 is subjected to CMP treatment to form the insulator 274 having a flat upper surface (see FIGS. 15B to 15D).
  • heat treatment may be performed.
  • the treatment is carried out in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour.
  • oxygen added by the film formation of the insulator 282 can be diffused to the insulator 280, and further supplied to the oxide 230a and the oxide 230b via the oxide 230c.
  • the heat treatment is not limited to after the formation of the insulator 274, but may be performed after the film formation of the insulator 282, the film formation of the insulator 283, and the like.
  • the insulator 254, the insulator 280, the insulator 282, the insulator 287, and the insulator 283 are formed with an opening reaching the conductor 242a and an opening reaching the conductor 242b (see FIGS. 16A and 16B).
  • the opening may be formed by using a lithography method.
  • the shape of the opening is circular in the top view, but the shape is not limited to this.
  • the opening may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a polygonal shape such as a quadrangle with rounded corners when viewed from above.
  • an insulating film to be the insulator 241a and the insulator 241b is formed, and the insulating film is anisotropically etched to form the insulator 241a and the insulator 241b.
  • the film formation of the insulating film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film it is preferable to use an insulating film having a function of suppressing the permeation of oxygen.
  • the anisotropic etching of the insulating film to be the insulator 241a and the insulator 241b for example, a dry etching method or the like may be used.
  • a dry etching method or the like By providing the insulator 241a and the insulator 241b on the side wall portion of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent the oxidation of the conductor 240a and the conductor 240b to be formed next. Further, it is possible to prevent impurities such as water and hydrogen from diffusing from the conductor 240a and the conductor 240b to the outside.
  • a conductive film to be a conductor 240a and a conductor 240b is formed. It is desirable that the conductive film has a laminated structure containing a conductor having a function of suppressing the permeation of impurities such as water and hydrogen.
  • impurities such as water and hydrogen.
  • tantalum nitride, titanium nitride and the like can be laminated with tungsten, molybdenum, copper and the like.
  • the film formation of the conductive film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a part of the conductive film to be the conductor 240a and the conductor 240b is removed, and the upper surfaces of the insulator 283 and the insulator 274 are exposed.
  • the conductor 240a and the conductor 240b having a flat upper surface can be formed by leaving the conductive film only in the opening (see FIGS. 16A and 16B).
  • a part of the upper surface of the insulator 283 and a part of the upper surface of the insulator 274 may be removed by the CMP treatment.
  • a conductive film to be a conductor 246a and a conductor 246b is formed.
  • the film formation of the conductive film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 246a and the conductor 246b is processed by a lithography method to form the conductor 246a in contact with the upper surface of the conductor 240a and the conductor 246b in contact with the upper surface of the conductor 240b.
  • a part of the insulator 283 in the region where the conductor 246a and the conductor 246b and the insulator 283 do not overlap may be removed (see FIGS. 17A and 17B).
  • the insulator 286 is formed on the conductor 246a, the conductor 246b, and the insulator 283 (see FIGS. 4A to 4D).
  • the film formation of the insulator 286 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 286 may have multiple layers. For example, silicon nitride may be formed into a film by using a sputtering method, and silicon nitride may be formed on the silicon nitride by a CVD method.
  • the semiconductor device having the transistor 200 shown in FIGS. 4A to 4D can be manufactured.
  • the transistor 200 can be manufactured by using the method for manufacturing the semiconductor device shown in the present embodiment.
  • FIG. 18A shows a top view of a semiconductor device having a transistor 200A.
  • FIG. 18B is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line of A1-A2 in FIG. 18A.
  • FIG. 18C is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line in FIG. 18A.
  • FIG. 18D is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line in FIG. 18A.
  • some elements are omitted for the sake of clarity.
  • the same reference numerals are given to the structures having the same functions as the structures constituting the semiconductor devices shown in ⁇ Semiconductor device configuration example> and ⁇ Semiconductor device modification 1>. I will add it. In this item as well, the materials described in detail in ⁇ Semiconductor device configuration example> and ⁇ Semiconductor device modification 1> can be used as the constituent materials of the semiconductor device.
  • the semiconductor device shown in FIGS. 18A to 18D is a modification of the semiconductor device shown in FIGS. 4A to 4D.
  • the semiconductor device shown in FIGS. 18A to 18D is different from the semiconductor device shown in FIGS. 4A to 4D in that it has an insulator 271a and an insulator 271b. It is also different that it does not have oxide 230c and oxide 230d.
  • the insulator 250 is different in that it has a two-layer structure of the insulator 250a and the insulator 250b.
  • an insulator 271a is provided between the conductor 242a and the insulator 254, and an insulator 271b is provided between the conductor 242b and the insulator 254.
  • the insulator 271a and the insulator 271b have a function of suppressing the diffusion of oxygen. This makes it possible to suppress the absorption of excess oxygen contained in the insulator 280 by the conductors 242a and 242b that function as source electrodes or drain electrodes. Further, by suppressing the oxidation of the conductor 242a and the conductor 242b, it is possible to suppress an increase in the contact resistance between the transistor and the wiring. Therefore, good electrical characteristics and reliability can be given to the transistor 200A.
  • the insulator 271a and the insulator 271b can be provided, for example, by using the same material as the insulator 254.
  • the insulating layer to be the insulator 271a and the insulator 271b and the conductive layer provided on the insulating film are made to function as a mask of the conductive film 242A.
  • Each of the conductor 242a and the conductor 242b has a square end where the side surface and the upper surface intersect.
  • the cross-sectional area of the conductor 242a and the conductor 242b becomes larger than that when the end has a curved surface. ..
  • the resistance of the conductor 242a and the conductor 242b is reduced, so that the on-current of the transistor 200A can be increased.
  • the oxide 230c and the oxide 230d are not provided, it is possible to suppress the generation of a parasitic transistor between the transistor 200A and the transistor 200A adjacent to the transistor 200A, and along the conductor 260. It is possible to suppress the occurrence of leak paths. Therefore, it is possible to provide a semiconductor device having good electrical characteristics and capable of miniaturization or high integration.
  • the insulator 250 may have a laminated structure of the insulator 250a and the insulator 250b.
  • the insulator 250a is formed by using an insulator that releases oxygen by heating, and the insulator 250b has a function of suppressing the diffusion of oxygen. It is preferable to form using an insulator having. With such a configuration, oxygen contained in the insulator 250a can be suppressed from diffusing into the conductor 260. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. In addition, oxidation of the conductor 260 by oxygen contained in the insulator 250a can be suppressed.
  • the insulator 250a can be provided using a material that can be used for the insulator 250 described above, and the insulator 250b can be provided using the same material as the insulator 222.
  • an insulating material which is a high-k material having a high relative permittivity may be used for the insulator 250b.
  • the gate insulator By forming the gate insulator into a laminated structure of the insulator 250a and the insulator 250b, it is possible to obtain a laminated structure that is stable against heat and has a high relative permittivity. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator.
  • the equivalent oxide film thickness (EOT) of an insulator that functions as a gate insulator can be thinned.
  • a metal oxide that can be used as the oxide 230 can be used.
  • the insulator 250 By forming the insulator 250 into a laminated structure of the insulator 250a and the insulator 250b, the distance between the conductor 260 and the oxide 230 is maintained due to the physical thickness of the insulator 250, and the conductor 260 and the conductor 260 Leakage current with the oxide 230 can be suppressed. Further, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily and appropriately adjusted.
  • FIGS. 19A and 19B a transistor 200 according to an aspect of the present invention, which is different from that shown in the above ⁇ Semiconductor device configuration example> and the above ⁇ Semiconductor device modification 1>.
  • An example of the semiconductor device having will be described.
  • the structures having the same functions as the structures constituting the semiconductor devices (see FIGS. 4A to 4D) shown in ⁇ Modification example 1 of the semiconductor device> have the same reference numerals. Is added.
  • the constituent material of the transistor 200 the materials described in detail in ⁇ Semiconductor device configuration example> and ⁇ Semiconductor device modification 1> can be used.
  • FIGS. 19A and 19B show a configuration in which a plurality of transistors (transistors 200_1 to 200_n) are comprehensively sealed with an insulator 287, an insulator 283, and an insulator 212.
  • the plurality of transistors appear to be arranged in the channel length direction, but the number of transistors is not limited to this.
  • the plurality of transistors may be arranged in the channel width direction or may be arranged in a matrix. Further, depending on the design, they may be arranged without regularity.
  • a portion where the insulator 287 and the insulator 283 and the insulator 212 are in contact with each other on the outside of the plurality of transistors (transistors 200_1 to 200_n) (hereinafter, may be referred to as a sealing portion 265). Is formed.
  • the sealing portion 265 is formed so as to surround a plurality of transistors (also referred to as transistor groups). With such a structure, a plurality of transistors can be wrapped by the insulator 287, the insulator 283, and the insulator 212. Therefore, a plurality of transistor groups surrounded by the sealing portion 265 are provided on the substrate.
  • a dicing line (sometimes referred to as a scribe line, a dividing line, or a cutting line) may be provided on the sealing portion 265. Since the substrate is divided at the dicing line, the transistor group surrounded by the sealing portion 265 is taken out as one chip.
  • FIG. 19A an example in which a plurality of transistors (transistors 200_1 to 200_n) are surrounded by one sealing portion 265 is shown, but the present invention is not limited to this.
  • a plurality of transistors may be surrounded by a plurality of sealing portions.
  • a plurality of transistors are surrounded by a sealing portion 265a, and further surrounded by an outer sealing portion 265b.
  • a dicing line may be provided on the sealing portion 265a or the sealing portion 265b, or a dicing line may be provided between the sealing portion 265a and the sealing portion 265b.
  • the present invention it is possible to provide a semiconductor device having little variation in transistor characteristics. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device having good reliability. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device having good electrical characteristics. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device having a large on-current. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration.
  • FIG. 20 shows an example of a semiconductor device (storage device) according to one aspect of the present invention.
  • the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300 and the transistor 200.
  • the transistor 200 the transistor 200 described in the previous embodiment can be used.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200 has a small off-current, it is possible to retain the stored contents for a long period of time by using the transistor 200 as a storage device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitive element 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitive element 100. ..
  • the storage devices shown in FIG. 20 can form a memory cell array by arranging them in a matrix.
  • the transistor 300 is provided on the substrate 311 and functions as a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311 and a low that functions as a source region or a drain region. It has a resistance region 314a and a low resistance region 314b.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • the semiconductor region 313 (a part of the substrate 311) on which the channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered with the conductor 316 via the insulator 315.
  • the conductor 316 may be made of a material that adjusts the work function. Since such a transistor 300 utilizes the convex portion of the semiconductor substrate, it is also called a FIN type transistor. It should be noted that an insulator that is in contact with the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Further, although the case where a part of the semiconductor substrate is processed to form a convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.
  • transistor 300 shown in FIG. 20 is an example, and the transistor 300 is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration and the driving method.
  • the capacitive element 100 is provided above the transistor 200.
  • the capacitive element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric.
  • the insulator 130 it is preferable to use an insulator that can be used as the insulator 286 shown in the above embodiment.
  • the conductor 112 provided on the conductor 240 and the conductor 110 can be formed at the same time.
  • the conductor 112 has a function as a plug or wiring that electrically connects to the capacitance element 100, the transistor 200, or the transistor 300.
  • the conductor 112 and the conductor 110 are shown in a single-layer structure, but the structure is not limited to this, and a laminated structure of two or more layers may be used.
  • a conductor having a barrier property and a conductor having a high adhesion to a conductor having a high conductivity may be formed between a conductor having a barrier property and a conductor having a high conductivity.
  • the insulator 130 includes, for example, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium oxide, and nitride. Hafnium or the like may be used, and it can be provided in a laminated or single layer.
  • the capacitive element 100 can secure a sufficient capacitance by having an insulator having a high dielectric constant (high-k), and by having an insulator having a large dielectric strength, the dielectric strength is improved and the capacitance is improved. Electrostatic destruction of the element 100 can be suppressed.
  • high-k materials materials having a high specific dielectric constant
  • examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, nitride nitrides having aluminum and hafnium, silicon, and the like. There are oxides with hafnium, nitrides with silicon and hafnium, or nitrides with silicon and hafnium.
  • silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon and nitrogen are used as materials with high dielectric strength (materials with low relative permittivity).
  • silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon and nitrogen are used as materials with high dielectric strength (materials with low relative permittivity).
  • silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon and nitrogen are used as materials with high dielectric strength (materials with low relative permittivity).
  • silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon and nitrogen are used as materials with high dielectric strength (materials with low relative permittivity).
  • a wiring layer provided with an interlayer film, wiring, a plug, etc. may be provided between the structures. Further, a plurality of wiring layers can be provided according to the design.
  • the conductor having a function as a plug or wiring may collectively give a plurality of structures the same reference numerals. Further, in the present specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order on the transistor 300 as an interlayer film. Further, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitance element 100, a conductor 328 electrically connected to the transistor 200, a conductor 330, and the like. The conductor 328 and the conductor 330 function as plugs or wirings.
  • the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape below the insulator.
  • the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are laminated in this order.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 functions as a plug or wiring.
  • the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor (conductor 205) constituting the transistor 200, and the like.
  • the conductor 218 has a function as a plug or wiring for electrically connecting to the capacitance element 100 or the transistor 300.
  • an insulator 150 is provided on the conductor 120 and the insulator 130.
  • the insulator 217 is provided in contact with the side surface of the conductor 218 that functions as a plug.
  • the insulator 217 is provided in contact with the side wall of the opening formed in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. That is, the insulator 217 is provided between the conductor 218 and the insulator 210, the insulator 212, the insulator 214, and the insulator 216. Since the conductor 205 can be formed in parallel with the conductor 218, the insulator 217 may be formed in contact with the side surface of the conductor 205.
  • an insulator such as silicon nitride, aluminum oxide, or silicon nitride may be used. Since the insulator 217 is provided in contact with the insulator 212, the insulator 214, and the insulator 222, impurities such as water or hydrogen from the insulator 210 or the insulator 216 or the like are mixed into the oxide 230 through the conductor 218. Can be suppressed.
  • silicon nitride is suitable because it has a high blocking property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.
  • the insulator 217 can be formed in the same manner as the insulator 241.
  • the PEALD method may be used to form a film of silicon nitride, and anisotropic etching may be used to form an opening that reaches the conductor 356.
  • Examples of the insulator that can be used as the interlayer film include oxides, nitrides, oxide nitrides, nitride oxides, metal oxides, metal oxide nitrides, and metal nitride oxides having insulating properties.
  • the material may be selected according to the function of the insulator.
  • the insulator 150, the insulator 210, the insulator 352, the insulator 354, and the like have an insulator having a low relative permittivity.
  • the insulator may have silicon nitride, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide or resin having pores, and the like.
  • the insulator may be silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores.
  • silicon oxide and silicon oxide nitride are thermally stable, they can be combined with a resin to form a laminated structure that is thermally stable and has a low relative permittivity.
  • the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.
  • a transistor using an oxide semiconductor can stabilize the electrical characteristics of the transistor by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, as the insulator 214, the insulator 212, the insulator 350, and the like, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.
  • Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators containing, lanthanum, neodymium, hafnium or tantalum may be used in single layers or in layers.
  • an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or Metal oxides such as tantalum oxide, silicon nitride oxide, silicon nitride and the like can be used.
  • Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium.
  • a material containing one or more metal elements selected from ruthenium and the like can be used.
  • a semiconductor having high electric conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and silicide such as nickel silicide may be used.
  • the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like include a metal material, an alloy material, a metal nitride material, a metal oxide material, and the like formed of the above materials.
  • a metal material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten.
  • it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
  • an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In that case, it is preferable to provide an insulator having a barrier property between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
  • an insulator 241 between the insulator 224 and the insulator 280 having excess oxygen and the conductor 240 it is preferable to provide an insulator 241 between the insulator 224 and the insulator 280 having excess oxygen and the conductor 240.
  • the insulator 241 in contact with the insulator 222, the insulator 282, the insulator 287, and the insulator 283, the insulator 224 and the transistor 200 are sealed by the insulator having a barrier property. It can be a structure.
  • the insulator 241 it is possible to suppress the excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Further, by having the insulator 241, it is possible to suppress the diffusion of hydrogen, which is an impurity, to the transistor 200 via the conductor 240.
  • an insulating material having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide or hafnium oxide.
  • silicon nitride is preferable because it has a high blocking property against hydrogen.
  • metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide can be used.
  • the transistor 200 is preferably sealed with an insulator 212, an insulator 214, an insulator 282, an insulator 287, and an insulator 283.
  • impurities particularly hydrogen and water
  • the conductor 240 penetrates through the insulator 283, the insulator 287, and the insulator 282, and the conductor 218 penetrates through the insulator 214 and the insulator 212.
  • the insulator 241 penetrates. It is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. Thereby, hydrogen mixed in the insulator 212, the insulator 214, the insulator 282, the insulator 287, and the insulator 283 can be reduced through the conductor 240 and the conductor 218.
  • the transistor 200 is more reliably sealed by the insulator 212, the insulator 214, the insulator 282, the insulator 287, the insulator 283, the insulator 241 and the insulator 217, and is included in the insulator 274 and the like. It is possible to reduce the mixing of impurities such as hydrogen with the transistor 200.
  • the insulator 216, the insulator 224, the insulator 280, the insulator 250, and the insulator 274 are formed by a film forming method using a gas in which hydrogen atoms are reduced or removed, as shown in the previous embodiment. It is preferably formed. Thereby, the hydrogen concentration of the insulator 216, the insulator 224, the insulator 280, the insulator 250, and the insulator 274 can be reduced.
  • the hydrogen concentration of the silicon-based insulating film in the vicinity of the transistor 200 can be reduced, and the hydrogen concentration of the oxide 230 can be reduced.
  • a dicing line (sometimes referred to as a scribe line, a division line, or a cutting line) provided when a plurality of semiconductor devices are taken out in a chip shape by dividing a large-area substrate into semiconductor elements will be described. ..
  • a dividing method for example, there is a case where a groove (dicing line) for dividing a semiconductor element is first formed on a substrate, then the dicing line is cut, and the semiconductor device is divided (divided) into a plurality of semiconductor devices.
  • the region in contact with the insulator 287 and the insulator 283 and the insulator 212 overlaps with the dicing line. That is, in the vicinity of the region serving as the dicing line provided on the outer edge of the memory cell having the plurality of transistors 200, the insulator 282, the insulator 280, the insulator 254, the insulator 224, the insulator 222, the insulator 216, and the insulator.
  • An opening is provided in 214.
  • the insulator 212 and the insulator 287 or the insulator 283 may be formed by using the same material and the same method.
  • the adhesion can be improved. For example, it is preferable to use silicon nitride.
  • the transistor 200 can be wrapped by the insulator 212, the insulator 214, the insulator 282, the insulator 287, and the insulator 283. Since at least one of the insulator 212, the insulator 214, the insulator 282, the insulator 287, and the insulator 283 has a function of suppressing the diffusion of oxygen, hydrogen, and water, it is shown in the present embodiment.
  • impurities such as hydrogen or water are mixed from the side surface direction of the divided substrate and diffuse to the transistor 200. You can prevent that.
  • the structure can prevent the excess oxygen of the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen of the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which the channel is formed in the transistor 200.
  • the oxygen can reduce the oxygen deficiency of the oxide in which the channel is formed in the transistor 200.
  • the oxide in which the channel is formed in the transistor 200 can be made into an oxide semiconductor having a low defect level density and stable characteristics. That is, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 and improve reliability.
  • the shape of the capacitance element 100 is a planar type, but the storage device shown in the present embodiment is not limited to this.
  • the shape of the capacitance element 100 may be a cylinder type.
  • the storage device shown in FIG. 21 has the same configuration as the semiconductor device shown in FIG. 20 in the configuration below the insulator 150.
  • the insulator 150 is provided on the insulator 130, and the insulator 142 is provided on the insulator 150. An opening is formed in the insulator 150 and the insulator 142.
  • the capacitive element 100 shown in FIG. 21 has a conductor 115, an insulator 145 on the conductor 115 and the insulator 142, and a conductor 125 on the insulator 145.
  • a conductor 115, the insulator 145, and the conductor 125 is arranged in the opening.
  • the conductor 115 functions as a lower electrode of the capacitance element 100
  • the conductor 125 functions as an upper electrode of the capacitance element 100
  • the insulator 145 functions as a dielectric of the capacitance element 100.
  • the capacitance element 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched not only on the bottom surface but also on the side surface at the openings of the insulator 150 and the insulator 142, and the capacitance per unit area.
  • the capacity can be increased. Therefore, the deeper the depth of the opening, the larger the capacitance of the capacitance element 100 can be.
  • An insulator 152 is provided on the conductor 125 and the insulator 145.
  • an insulator that can be used for the insulator 280 may be used.
  • the insulator 142 preferably functions as an etching stopper when forming an opening of the insulator 150, and an insulator that can be used for the insulator 214 may be used.
  • the shape of the openings formed in the insulator 150 and the insulator 142 as viewed from the upper surface may be a quadrangle, a polygonal shape other than the quadrangle, or a polygonal shape with curved corners. , It may be a circular shape including an ellipse.
  • it is preferable that the area where the opening and the transistor 200 overlap is large. With such a configuration, the occupied area of the semiconductor device having the capacitance element 100 and the transistor 200 can be reduced.
  • the conductor 115 is arranged in contact with the insulator 142 and the opening formed in the insulator 150. It is preferable that the upper surface of the conductor 115 substantially coincides with the upper surface of the insulator 142. Further, the lower surface of the conductor 115 is in contact with the conductor 110 through the opening of the insulator 130.
  • the conductor 115 is preferably formed by using an ALD method, a CVD method, or the like, and for example, a conductor that can be used for the conductor 205 may be used.
  • the insulator 145 is arranged so as to cover the conductor 115 and the insulator 142.
  • Insulator 145 includes, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, zirconium oxide, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium nitride, and the like.
  • Hafnium nitride or the like may be used, and it can be provided in a laminated or single layer.
  • an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used.
  • a material having a large dielectric strength such as silicon oxide or a material having a high dielectric constant (high-k) for the insulator 145.
  • a laminated structure of a material having a large dielectric strength and a high dielectric constant (high-k) material may be used.
  • high-k materials materials having a high specific dielectric constant
  • examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, nitride nitrides having aluminum and hafnium, silicon, and the like.
  • oxides having hafnium, nitrides having silicon and hafnium, and nitrides having silicon and hafnium By using such a high-k material, it is possible to sufficiently secure the capacitance of the capacitance element 100 even if the insulator 145 is thickened. By increasing the thickness of the insulator 145, the leakage current generated between the conductor 115 and the conductor 125 can be suppressed.
  • silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and pores are used as materials having high insulation strength.
  • silicon oxide, resin, etc. an insulating film laminated in the order of silicon nitride formed by the ALD method, silicon oxide formed by the PEALD method, and silicon nitride formed by the ALD method can be used.
  • an insulating film laminated in the order of silicon nitride formed by the ALD method, silicon oxide formed by the PEALD method, and silicon nitride formed by the ALD method can be used.
  • the conductor 125 is arranged so as to fill the openings formed in the insulator 142 and the insulator 150. Further, the conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153.
  • the conductor 125 is preferably formed by using an ALD method, a CVD method, or the like, and for example, a conductor that can be used for the conductor 205 may be used.
  • the conductor 153 is provided on the insulator 154 and is covered with the insulator 156.
  • a conductor that can be used for the conductor 112 may be used, and as the insulator 156, an insulator that can be used for the insulator 152 may be used.
  • the conductor 153 is in contact with the upper surface of the conductor 140, and functions as a terminal of the capacitive element 100, the transistor 200, or the transistor 300.
  • FIG. 22 shows an example of the semiconductor device (storage device) in the present embodiment.
  • FIG. 22 is a cross-sectional view of a semiconductor device having a memory device 290.
  • the memory device 290 shown in FIG. 22 has a capacitive device 292 in addition to the transistor 200 shown in FIGS. 4A to 4D.
  • FIG. 22 corresponds to a cross-sectional view of the transistor 200 in the channel length direction.
  • the same reference numerals are added to the structures having the same functions as the structures constituting the semiconductor devices shown in the previous embodiment.
  • the materials described in detail in the previous embodiment can be used as the constituent materials of the semiconductor device.
  • the memory device 290 is preferably sealed with the insulator 283 and the insulator 212. With such a configuration, it is possible to suppress the mixing of impurities (particularly hydrogen and water) into the memory device 290.
  • the insulator 287 may be provided between the memory device 290 and the insulator 283.
  • the capacitance device 292 includes a conductor 242b, an insulator 293 provided on the conductor 242b, and a conductor 294 provided on the insulator 293. That is, the capacitance device 292 constitutes a MIM (Metal-Insulator-Metal) capacitance.
  • One of the pair of electrodes of the capacitive device 292, that is, the conductor 242b, can also serve as a source electrode or a drain electrode of the transistor. Therefore, in the manufacturing process of the capacitive device 292, a part of the manufacturing process of the transistor can also be used, so that the semiconductor device can be highly productive. Further, it is possible to reduce the area in which the transistor and the capacitive device are arranged.
  • a material that can be used for the conductor 240 may be used.
  • insulator 293 for example, a laminated structure of zirconium oxide, aluminum oxide, and zirconium oxide may be used. Further, for example, a material that can be used for the insulator 130 may be used, and it may be provided in a laminated or single layer.
  • a wiring layer may be provided on the memory device 290.
  • an insulator 160 that functions as an interlayer film is provided on the transistor 200 and the capacitive device 292.
  • a conductor 166 that is electrically connected to the transistor 200 is embedded in the insulator 283 and the insulator 160. The conductor 166 functions as a plug or wiring.
  • a wiring layer may be provided on the insulator 160 and the conductor 166.
  • the insulator 162 and the insulator 164 are laminated in this order.
  • a conductor 168 is embedded in the insulator 162 and the insulator 164.
  • the conductor 168 functions as a plug or wiring.
  • the insulator 160 and the insulator 164 have an insulator having a low relative permittivity.
  • an insulator that can be used for the insulator 352 or the like may be used as the insulator 160 and the insulator 164.
  • an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.
  • an insulator that can be used for the insulator 350 or the like may be used.
  • the memory devices 290 may be stacked.
  • FIG. 23 shows a cross-sectional view of a storage device in which five layers having a memory device 290 are laminated. As shown in FIG. 23, the memory device 290 is electrically connected to a different memory device 290 via the conductor 240 and the conductor 166.
  • a plurality of memory devices may be included and sealed with the insulator 283 and the insulator 212.
  • the hydrogen concentration of the transistor 200 can be lowered by forming a film on a part of the structure constituting the transistor 200 and a part of the structure provided around the transistor 200 by using a sputtering method. Therefore, even when a different transistor 200 is manufactured above the transistor 200, the hydrogen concentration of the transistor 200 located below can be kept low. Therefore, in the case where the memory devices 290 are stacked, the hydrogen concentration in the transistor 200 can be lowered by comprehensively sealing the plurality of memory devices without individually sealing the memory devices 290. Can be done.
  • the sealing of the plurality of memory devices by the insulator 283 and the insulator 212 may be performed comprehensively for all of the plurality of memory devices, or may be performed comprehensively for each part.
  • the insulator 214 and the insulator 282 may not be provided. As a result, the number of manufacturing steps of the storage device can be reduced.
  • the memory devices can be integrated and arranged without increasing the occupied area of the memory devices. That is, a 3D memory device can be configured.
  • each layer may have a plurality of memory devices, and the plurality of memory devices may be arranged in the channel length direction or in the channel width direction. They may be arranged side by side or arranged in a matrix. Further, depending on the design, they may be arranged without regularity.
  • FIGS. 24A, 24B, and 25 a semiconductor device having a transistor 200 and a capacitance device 292 according to the present embodiment, which is different from the semiconductor device shown in the above ⁇ configuration example of a memory device>.
  • FIGS. 24A, 24B, and 25 the same reference numerals are given to the structures having the same functions as those of the previous embodiment and the structures constituting the semiconductor devices shown in FIG. 22.
  • the constituent materials of the transistor 200 and the capacitive device 292 the materials described in detail in the above-described embodiment and the above ⁇ memory device configuration example> can be used.
  • the memory device 600 includes a transistor 200a, a transistor 200b, a capacitive device 292a, and a capacitive device 292b.
  • FIG. 24A is a top view of the semiconductor device having the memory device 600. Further, FIG. 24B is a cross-sectional view of a portion shown by a chain line of A1-A2 in FIG. 24A, and is also a cross-sectional view of the transistor 200a and the transistor 200b in the channel length direction. In the top view of FIG. 24A, some elements are omitted for the purpose of clarifying the figure.
  • the memory device 600 has a line-symmetrical configuration with the alternate long and short dash line of A3-A4 as the axis of symmetry.
  • One of the source electrode or the drain electrode of the transistor 200a and one of the source electrode or the drain electrode of the transistor 200b are configured by the conductor 242c.
  • the conductor 240c also serves as a conductor that is electrically connected to the transistor 200a and functions as a plug, and a conductor that is electrically connected to the transistor 200b and functions as a plug.
  • an insulator 241c is provided in contact with the side surface of the conductor 240c.
  • the configuration examples of the semiconductor devices shown in FIGS. 4A to 4D and 22 can be referred to.
  • FIG. 25 shows an example in which the memory unit 470 has a transistor layer 413 having a transistor 200T and four memory device layers 415 (memory device layer 415_1 to memory device layer 415_4).
  • the memory device layer 415_1 to the memory device layer 415_1 each have a plurality of memory devices 420.
  • the memory device 420 for example, the memory device 290 shown in FIG. 22 or the memory device 600 shown in FIGS. 24A and 24B can be used.
  • the memory device 420 is electrically connected to the memory device 420 of the different memory device layers 415 and the transistor 200T of the transistor layer 413 via the conductor 424 and the conductor 166.
  • the memory unit 470 is sealed by an insulator 212, an insulator 214, an insulator 282, and an insulator 283 (for convenience, hereinafter referred to as a sealing structure).
  • An insulator 274 is provided around the insulator 283. Further, the insulator 274, the insulator 283, and the insulator 212 are provided with a conductor 440, which is electrically connected to the element layer 411.
  • An insulator 287 may be provided between the memory unit 470 and the insulator 283.
  • the insulator 212 and the insulator 283 are preferably materials having a function of having a high blocking property against hydrogen. Further, the insulator 214 and the insulator 282 are preferably materials having a function of capturing hydrogen or fixing hydrogen.
  • the material having a high blocking property against hydrogen includes silicon nitride, silicon nitride, and the like.
  • Examples of the material having a function of capturing hydrogen or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
  • the crystal structure of the materials used for the insulator 212, the insulator 214, the insulator 282, and the insulator 283 is not particularly limited, but may be an amorphous or crystalline structure.
  • Amorphous aluminum oxide may capture and adhere more hydrogen than highly crystalline aluminum oxide.
  • the insulator 282 and the insulator 214 are also provided between the transistor layer 413 and the memory device layer 415_1, or between each memory device layer 415. Further, it is preferable that the insulator 296 is provided between the insulator 282 and the insulator 214.
  • the same material as the insulator 283 can be used. Alternatively, silicon oxide or silicon oxide nitride can be used. Alternatively, a known insulating material may be used.
  • an insulator 280 is provided inside the sealing structure.
  • the insulator 280 has a function of releasing oxygen by heating.
  • the insulator 280 has an excess oxygen region.
  • the excess oxygen in the insulator 280 can be considered as the following model for the diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280.
  • Hydrogen present in the oxide semiconductor diffuses into other structures via the insulator 280 in contact with the oxide semiconductor.
  • the hydrogen forms an OH bond with excess oxygen in the insulator 280 and diffuses in the insulator 280 as OH.
  • a hydrogen atom having an OH bond reaches a material having a function of capturing hydrogen or fixing hydrogen (typically, an insulator 282), an atom in the insulator 282 (for example, a metal atom or the like) ), Reacts with the oxygen atom and is captured or fixed in the insulator 282.
  • excess oxygen having an OH bond is presumed to remain in the insulator 280 as excess oxygen. That is, it is highly probable that excess oxygen in the insulator 280 plays a bridging role in the diffusion of hydrogen.
  • an insulator 280 having excess oxygen is formed on an oxide semiconductor, and then an insulator 282 is formed. After that, it is preferable to perform heat treatment. Specifically, the heat treatment is carried out in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen at a temperature of 350 ° C. or higher, preferably 400 ° C. or higher.
  • the heat treatment time is 1 hour or longer, preferably 4 hours or longer, and more preferably 8 hours or longer.
  • hydrogen in the oxide semiconductor can be diffused to the outside through the insulator 280 and the insulator 282. That is, the absolute amount of the oxide semiconductor and hydrogen existing in the vicinity of the oxide semiconductor can be reduced.
  • an insulator 283 is formed. Since the insulator 283 is a material having a function of having a high blocking property against hydrogen, hydrogen diffused to the outside or hydrogen existing on the outside is transferred to the inside, specifically, an oxide semiconductor or the insulator 280. It is possible to prevent it from entering the side.
  • the step performed after forming the insulator 282 has been illustrated, but the present invention is not limited to this.
  • the heat treatment may be performed after the transistor layer 413 is formed or after the memory device layer 415_1 to the memory device layer 415_3 are formed.
  • hydrogen is diffused outward by the above heat treatment, hydrogen is diffused above or in the lateral direction of the transistor layer 413.
  • hydrogen is diffused upward or laterally.
  • the insulator 212 and the insulator 283 are adhered to each other to form the above-mentioned sealing structure.
  • a transistor using an oxide as a semiconductor (hereinafter, may be referred to as an OS transistor) according to one aspect of the present invention.
  • a storage device to which a capacitive element is applied (hereinafter, may be referred to as an OS memory device) will be described.
  • the OS memory device is a storage device having at least a capacitance element and an OS transistor that controls charging / discharging of the capacitance element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a non-volatile memory.
  • FIG. 26A shows an example of the configuration of the OS memory device.
  • the storage device 1400 has a peripheral circuit 1411 and a memory cell array 1470.
  • the peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
  • the column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a writing circuit, and the like.
  • the precharge circuit has a function of precharging the wiring.
  • the sense amplifier has a function of amplifying a data signal read from a memory cell.
  • the wiring is the wiring connected to the memory cell of the memory cell array 1470, and will be described in detail later.
  • the amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440.
  • the row circuit 1420 has, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.
  • a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the storage device 1400 from the outside as power supply voltages. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside.
  • the address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.
  • the control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for row decoders and column decoders.
  • the control signal CE is a chip enable signal
  • the control signal WE is a write enable signal
  • the control signal RE is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.
  • the memory cell array 1470 has a plurality of memory cell MCs arranged in a matrix and a plurality of wirings.
  • the number of wires connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cell MCs in a row, and the like. Further, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one row, and the like.
  • FIG. 26A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this.
  • the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411.
  • a sense amplifier may be provided so as to overlap under the memory cell array 1470.
  • FIGS. 27A to 27H An example of a memory cell configuration applicable to the above-mentioned memory cell MC will be described with reference to FIGS. 27A to 27H.
  • [DOSRAM] 27A to 27C show an example of a circuit configuration of a DRAM memory cell.
  • a DRAM using a memory cell of a 1OS transistor and 1 capacitance element type may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).
  • the memory cell 1471 shown in FIG. 27A has a transistor M1 and a capacitive element CA.
  • the transistor M1 has a gate (sometimes called a top gate) and a back gate.
  • the first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1. Is connected to the wiring BGL.
  • the second terminal of the capacitive element CA is connected to the wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. It is preferable to apply a low level potential to the wiring CAL when writing and reading data.
  • the wiring BGL functions as wiring for applying a potential to the back gate of the transistor M1.
  • the threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.
  • the memory cell 1471 shown in FIG. 27A corresponds to the storage device shown in FIG. 22. That is, the transistor M1 corresponds to the transistor 200, and the capacitive element CA corresponds to the capacitive device 292.
  • the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed.
  • the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 27B.
  • the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M1 having no back gate, as in the memory cell 1473 shown in FIG. 27C.
  • a transistor 200 can be used as the transistor M1 and a capacitance element 100 can be used as the capacitance element CA.
  • an OS transistor as the transistor M1
  • the leakage current of the transistor M1 can be made very small. That is, since the written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cells can be reduced. Alternatively, the memory cell refresh operation can be eliminated. Further, since the leak current is very small, multi-valued data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.
  • the sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. As a result, the bit line capacity is reduced, and the holding capacity of the memory cell can be reduced.
  • [NOSRAM] 27D to 27G show a circuit configuration example of a gain cell type memory cell having two transistors and one capacitance element.
  • the memory cell 1474 shown in FIG. 27D includes a transistor M2, a transistor M3, and a capacitance element CB.
  • the transistor M2 has a top gate (sometimes referred to simply as a gate) and a back gate.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • the first terminal of the transistor M2 is connected to the first terminal of the capacitive element CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2. Is connected to the wiring BGL.
  • the second terminal of the capacitive element CB is connected to the wiring CAL.
  • the first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitance element CB. It is preferable to apply a low level potential to the wiring CAL during data writing, data retention, and data reading.
  • the wiring BGL functions as wiring for applying an electric potential to the back gate of the transistor M2.
  • the threshold voltage of the transistor M2 can be increased or decreased by applying an arbitrary potential to the wiring BGL.
  • the memory cell 1474 shown in FIG. 27D corresponds to the storage device shown in FIG. 20. That is, the transistor M2 is in the transistor 200, the capacitive element CB is in the capacitive element 100, the transistor M3 is in the transistor 300, the wiring WBL is in the wiring 1003, the wiring WOL is in the wiring 1004, the wiring BGL is in the wiring 1006, and the wiring CAL is in the wiring 1006.
  • the wiring RBL corresponds to the wiring 1002
  • the wiring SL corresponds to the wiring 1001.
  • the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be appropriately changed.
  • the memory cell MC may have a configuration in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 27E.
  • the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M2 having no back gate, as in the memory cell 1476 shown in FIG. 27F.
  • the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined as one wiring BIL, as in the memory cell 1477 shown in FIG. 27G.
  • a transistor 200 can be used as the transistor M2
  • a transistor 300 can be used as the transistor M3
  • a capacitance element 100 can be used as the capacitance element CB.
  • OS transistor an OS transistor
  • the leakage current of the transistor M2 can be made very small.
  • the written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cells can be reduced.
  • the memory cell refresh operation can be eliminated.
  • the leak current is very small, multi-valued data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.
  • the transistor M3 may be a transistor having silicon in the channel forming region (hereinafter, may be referred to as a Si transistor).
  • the conductive type of the Si transistor may be an n-channel type or a p-channel type.
  • the Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 that functions as a readout transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be provided by stacking on the transistor M3, so that the occupied area of the memory cell can be reduced and the storage device can be highly integrated.
  • the transistor M3 may be an OS transistor.
  • an OS transistor is used for the transistor M2 and the transistor M3, the circuit can be configured by using only the n-type transistor in the memory cell array 1470.
  • FIG. 27H shows an example of a gain cell type memory cell having a 3-transistor and 1-capacity element.
  • the memory cell 1478 shown in FIG. 27H includes transistors M4 to M6 and a capacitive element CC.
  • the capacitive element CC is appropriately provided.
  • the memory cell 1478 is electrically connected to the wiring BIL, the wiring RWL, the wiring WWL, the wiring BGL, and the wiring GNDL.
  • Wiring GNDL is a wiring that gives a low level potential. Note that the memory cell 1478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.
  • Transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL.
  • the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not have to have a back gate.
  • the transistor M5 and the transistor M6 may be an n-channel Si transistor or a p-channel Si transistor, respectively.
  • the transistor M4 to the transistor M6 may be an OS transistor.
  • the memory cell array 1470 can be configured by using only n-type transistors.
  • the transistor 200 can be used as the transistor M4
  • the transistor 300 can be used as the transistor M5 and the transistor M6, and the capacitance element 100 can be used as the capacitance element CC.
  • the leakage current of the transistor M4 can be made very small.
  • the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in the present embodiment are not limited to the above.
  • the arrangement or function of these circuits and the wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.
  • FIG. 28 shows various storage devices for each layer.
  • a storage device located in the upper layer is required to have a faster access speed, and a storage device located in the lower layer is required to have a large storage capacity and a high recording density.
  • FIG. 28 shows a memory, a SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), and a 3D NAND memory, which are mixedly loaded as registers in an arithmetic processing unit such as a CPU, in order from the top layer.
  • SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • 3D NAND memory which are mixedly loaded as registers in an arithmetic processing unit such as a CPU, in order from the top layer.
  • the memory that is mixedly loaded as a register in an arithmetic processing unit such as a CPU is used for temporary storage of arithmetic results, and therefore is frequently accessed from the arithmetic processing unit. Therefore, an operation speed faster than the storage capacity is required.
  • the register also has a function of holding setting information of the arithmetic processing unit.
  • SRAM is used for cache, for example.
  • the cache has a function of duplicating and holding a part of the information held in the main memory. By replicating frequently used data to the cache, the access speed to the data can be increased.
  • DRAM is used, for example, in main memory.
  • the main memory has a function of holding programs and data read from the storage.
  • the recording density of the DRAM is approximately 0.1 to 0.3 Gbit / mm 2 .
  • the 3D NAND memory is used, for example, for storage.
  • the storage has a function of holding data that needs to be stored for a long period of time and various programs used in the arithmetic processing unit. Therefore, the storage is required to have a storage capacity larger than the operating speed and a high recording density.
  • the recording density of the storage device used for storage is approximately 0.6 to 6.0 Gbit / mm 2 .
  • the storage device of one aspect of the present invention has a high operating speed and can retain data for a long period of time.
  • the storage device of one aspect of the present invention can be suitably used as a storage device located in the boundary area 901 including both the layer in which the cache is located and the layer in which the main memory is located.
  • the storage device of one aspect of the present invention can be suitably used as a storage device located in the boundary area 902 including both the layer in which the main memory is located and the layer in which the storage is located.
  • FIGS. 29A and 29B An example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown with reference to FIGS. 29A and 29B.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • SoC system on chip
  • the chip 1200 includes a CPU 1211, GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
  • a bump (not shown) is provided on the chip 1200, and as shown in FIG. 29B, the chip 1200 is connected to the first surface of a printed circuit board (Printed Circuit Board: PCB) 1201. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the motherboard 1203.
  • PCB printed Circuit Board
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222.
  • a storage device such as a DRAM 1221 and a flash memory 1222.
  • the DOSRAM shown in the previous embodiment can be used for the DRAM 1221.
  • the NO SRAM shown in the above embodiment can be used for the flash memory 1222.
  • the CPU 1211 preferably has a plurality of CPU cores.
  • the GPU 1212 preferably has a plurality of GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200.
  • the above-mentioned NOSRAM or DOSRAM can be used.
  • GPU1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing and product-sum calculation. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor of the present invention and a product-sum calculation circuit, image processing and product-sum calculation can be executed with low power consumption.
  • the wiring between the CPU 1211 and the GPU 1212 can be shortened, and the data transfer from the CPU 1211 to the GPU 1212, the data transfer between the memory of the CPU 1211 and the GPU 1212, And, after the calculation by the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
  • the analog arithmetic unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the product-sum calculation circuit may be provided in the analog calculation unit 1213.
  • the memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222.
  • the interface 1215 has an interface circuit with an externally connected device such as a display device, a speaker, a microphone, a camera, and a controller.
  • the controller includes a mouse, a keyboard, a game controller, and the like.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface High-Definition Multimedia Interface
  • the network circuit 1216 has a circuit for a network such as a LAN (Local Area Network). It may also have a circuit for network security.
  • a network such as a LAN (Local Area Network). It may also have a circuit for network security.
  • the above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
  • the PCB 1201, the DRAM 1221 provided with the chip 1200 having the GPU 1212, and the motherboard 1203 provided with the flash memory 1222 can be referred to as the GPU module 1204.
  • the GPU module 1204 Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. Further, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (take-out) game machines.
  • a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), and a deep belief network (DEM) are provided by a product-sum calculation circuit using GPU1212. Since a method such as DBN) can be executed, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.
  • the present embodiment shows an example of an electronic component and an electronic device in which the storage device and the like shown in the above embodiment are incorporated.
  • FIG. 30A shows a perspective view of the electronic component 700 and the substrate on which the electronic component 700 is mounted (mounting substrate 704).
  • the electronic component 700 shown in FIG. 30A has a storage device 720 in the mold 711. In FIG. 30A, a part is omitted in order to show the inside of the electronic component 700.
  • the electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the storage device 720 by a wire 714.
  • the electronic component 700 is mounted on, for example, the printed circuit board 702. A plurality of such electronic components are combined and each is electrically connected on the printed circuit board 702 to complete the mounting board 704.
  • the storage device 720 has a drive circuit layer 721 and a storage circuit layer 722.
  • FIG. 30B shows a perspective view of the electronic component 730.
  • the electronic component 730 is an example of SiP (System in package) or MCM (Multi Chip Module).
  • the electronic component 730 is provided with an interposer 731 on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 are provided on the interposer 731.
  • the electronic component 730 shows an example in which the storage device 720 is used as a wideband memory (HBM: High Bandwidth Memory). Further, as the semiconductor device 735, an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA can be used.
  • HBM High Bandwidth Memory
  • the package substrate 732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
  • the interposer 731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
  • the plurality of wirings are provided in a single layer or multiple layers.
  • the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrode provided on the package substrate 732.
  • the interposer may be referred to as a "rewiring board” or an "intermediate board”.
  • a through electrode may be provided on the interposer 731, and the integrated circuit and the package substrate 732 may be electrically connected using the through electrode.
  • TSV Three Silicon Via
  • interposer 731 It is preferable to use a silicon interposer as the interposer 731. Since it is not necessary to provide an active element in the silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with a resin interposer.
  • the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer on which the HBM is mounted.
  • the reliability is unlikely to decrease due to the difference in the expansion coefficient between the integrated circuit and the interposer. Further, since the surface of the silicon interposer is high, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
  • a heat sink may be provided so as to be overlapped with the electronic component 730.
  • the heat sink it is preferable that the heights of the integrated circuits provided on the interposer 731 are the same.
  • the heights of the storage device 720 and the semiconductor device 735 are the same.
  • an electrode 733 may be provided on the bottom of the package substrate 732.
  • FIG. 30B shows an example in which the electrode 733 is formed of solder balls.
  • BGA Ball Grid Array
  • the electrode 733 may be formed of a conductive pin.
  • PGA Peripheral Component Interconnect
  • the electronic component 730 can be mounted on another substrate by using various mounting methods, not limited to BGA and PGA.
  • BGA Band-GPU
  • PGA Stimble Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN QuadNeged
  • the semiconductor device shown in the above embodiment is, for example, a storage device for various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.).
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor device shown in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive).
  • 31A to 31E schematically show some configuration examples of the removable storage device.
  • the semiconductor device shown in the above embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.
  • FIG. 31A is a schematic diagram of the USB memory.
  • the USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104.
  • the substrate 1104 is housed in the housing 1101.
  • a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like.
  • FIG. 31B is a schematic view of the appearance of the SD card
  • FIG. 31C is a schematic view of the internal structure of the SD card.
  • the SD card 1110 has a housing 1111 and a connector 1112 and a substrate 1113.
  • the substrate 1113 is housed in the housing 1111.
  • a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113.
  • the capacity of the SD card 1110 can be increased.
  • a wireless chip having a wireless communication function may be provided on the substrate 1113.
  • data on the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1114 or the like.
  • FIG. 31D is a schematic view of the appearance of the SSD
  • FIG. 31E is a schematic view of the internal structure of the SSD.
  • the SSD 1150 has a housing 1151, a connector 1152 and a substrate 1153.
  • the substrate 1153 is housed in the housing 1151.
  • a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153.
  • the memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used.
  • the capacity of the SSD 1150 can be increased.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1154 or the like.
  • the semiconductor device according to one aspect of the present invention can be used for a processor such as a CPU or GPU, or a chip.
  • 32A to 32H show specific examples of an electronic device including a processor such as a CPU or GPU or a chip according to one aspect of the present invention.
  • the GPU or chip according to one aspect of the present invention can be mounted on various electronic devices.
  • electronic devices include relatively large screens such as television devices, monitors for desktop or notebook information terminals, digital signage (electronic signage), and large game machines such as pachinko machines.
  • digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, sound reproduction devices, and the like can be mentioned.
  • artificial intelligence can be mounted on the electronic device.
  • the electronic device of one aspect of the present invention may have an antenna.
  • the display unit can display images, information, and the like.
  • the antenna may be used for non-contact power transmission.
  • the electronic device of one aspect of the present invention includes sensors (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It may have the ability to measure voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays).
  • the electronic device of one aspect of the present invention can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, and the like.
  • 32A to 32H show examples of electronic devices.
  • FIG. 32A illustrates a mobile phone (smartphone) which is a kind of information terminal.
  • the information terminal 5100 has a housing 5101 and a display unit 5102, and as an input interface, a touch panel is provided in the display unit 5102 and buttons are provided in the housing 5101.
  • the information terminal 5100 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention.
  • Examples of the application using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5102, and recognizes characters and figures input by the user on the touch panel provided in the display unit 5102.
  • Examples include an application displayed on the display unit 5102, an application for performing biometric authentication such as a fingerprint and a voice print, and the like.
  • FIG. 32B illustrates a notebook type information terminal 5200.
  • the notebook-type information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.
  • the notebook-type information terminal 5200 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention.
  • applications using artificial intelligence include design support software, text correction software, and menu automatic generation software. Further, by using the notebook type information terminal 5200, it is possible to develop a new artificial intelligence.
  • a smartphone and a notebook-type information terminal are taken as examples of electronic devices, which are shown in FIGS. 32A and 32B, respectively, but information terminals other than the smartphone and the notebook-type information terminal can be applied.
  • information terminals other than smartphones and notebook-type information terminals include PDAs (Personal Digital Assistants), desktop-type information terminals, workstations, and the like.
  • FIG. 32C shows a portable game machine 5300, which is an example of a game machine.
  • the portable game machine 5300 has a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, an operation key 5306, and the like.
  • the housing 5302 and the housing 5303 can be removed from the housing 5301 by attaching the connection portion 5305 provided in the housing 5301 to another housing (not shown), thereby displaying the display unit 5304.
  • the video output to can be output to another video device (not shown).
  • the housing 5302 and the housing 5303 can each function as operation units. This allows a plurality of players to play the game at the same time.
  • the chips shown in the previous embodiment can be incorporated into the chips provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.
  • FIG. 32D shows a stationary game machine 5400, which is an example of a game machine.
  • a controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.
  • a low power consumption game machine can be realized by applying the GPU or chip of one aspect of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • the portable game machine 5300 having artificial intelligence can be realized.
  • expressions such as the progress of the game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are defined by the program that the game has, but by applying artificial intelligence to the handheld game machine 5300.
  • Expressions that are not limited to game programs are possible. For example, it is possible to express the content of questions asked by the player, the progress of the game, the timing of events in the game, the behavior of the characters appearing in the game, etc., without being limited to the program of the game. ..
  • the game player can be constructed anthropomorphically by artificial intelligence. Therefore, by setting the opponent as a game player by artificial intelligence, even one player can play the game. You can play the game.
  • FIGS. 32C and 32D a portable game machine and a stationary game machine are illustrated as examples of the game machine, but the game machine to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
  • Examples of the game machine to which the GPU or chip of one aspect of the present invention is applied include an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a throwing machine for batting practice installed in a sports facility, and the like. Can be mentioned.
  • the GPU or chip of one aspect of the present invention can be applied to a large computer.
  • FIG. 32E is a diagram showing a supercomputer 5500, which is an example of a large computer.
  • FIG. 32F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.
  • the supercomputer 5500 has a rack 5501 and a plurality of rack mount type computers 5502.
  • the plurality of computers 5502 are stored in the rack 5501. Further, the computer 5502 is provided with a plurality of substrates 5504, and the GPU or chip described in the above embodiment can be mounted on the substrate.
  • the supercomputer 5500 is a large computer mainly used for scientific and technological calculations. In scientific and technological calculations, it is necessary to process a huge amount of calculations at high speed, so power consumption is high and the heat generated by the chip is large.
  • the GPU or chip of one aspect of the present invention to the supercomputer 5500, a supercomputer having low power consumption can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • a supercomputer is illustrated as an example of a large computer, but the large computer to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
  • Examples of the large computer to which the GPU or chip of one aspect of the present invention is applied include a computer (server) that provides a service, a large general-purpose computer (mainframe), and the like.
  • the GPU or chip of one aspect of the present invention can be applied to a moving vehicle and around the driver's seat of the vehicle.
  • FIG. 32G is a diagram showing the periphery of the windshield in the interior of an automobile, which is an example of a moving body.
  • the display panel 5701 attached to the dashboard, the display panel 5702, the display panel 5703, and the display panel 5704 attached to the pillar are shown.
  • the display panel 5701 to the display panel 5703 can provide various other information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, an air conditioner setting, and the like.
  • the display items and layout displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved.
  • the display panel 5701 to 5703 can also be used as a lighting device.
  • the field of view (blind spot) blocked by the pillars can be complemented. That is, by displaying the image from the image pickup device provided on the outside of the automobile, the blind spot can be supplemented and the safety can be enhanced. In addition, by projecting an image that complements the invisible part, safety confirmation can be performed more naturally and without discomfort.
  • the display panel 5704 can also be used as a lighting device.
  • the GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence
  • the chip can be used, for example, in an automatic driving system of an automobile.
  • the chip can be used in a system for road guidance, danger prediction, and the like.
  • the display panel 5701 to the display panel 5704 may be configured to display information such as road guidance and danger prediction.
  • moving objects may include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc., and the chip of one aspect of the present invention is applied to these moving objects. Therefore, a system using artificial intelligence can be provided.
  • FIG. 32H shows an electric refrigerator / freezer 5800, which is an example of an electric appliance.
  • the electric refrigerator / freezer 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the electric freezer / refrigerator 5800 has a function of automatically generating a menu based on the foodstuffs stored in the electric freezer / refrigerator 5800 and the expiration date of the foodstuffs, and is stored in the electric freezer / refrigerator 5800. It can have a function of automatically adjusting the temperature according to the food.
  • electric refrigerators and freezers have been described as an example of electric appliances
  • other electric appliances include, for example, vacuum cleaners, microwave ovens, microwave ovens, rice cookers, water heaters, IH cookers, water servers, and air conditioners including air conditioners. Examples include washing machines, dryers, and audiovisual equipment.
  • the electronic device described in the present embodiment the function of the electronic device, the application example of artificial intelligence, its effect, etc. can be appropriately combined with the description of other electronic devices.
  • a laminated structure having an oxide which is one aspect of the present invention, was prepared and analyzed using a constant photocurrent method (CPM) measurement.
  • CPM constant photocurrent method
  • Samples 1A to 1E include the substrate 911, the insulator 912 on the substrate 911, the insulator 913 on the insulator 912, the oxide 914 on the insulator 913, the conductor 915a on the oxide 914, and It has a conductor 915b and an insulator 916 on the oxide 914, on the conductor 915a, and on the conductor 915b.
  • a quartz substrate was prepared as the substrate 911.
  • aluminum oxide having a film thickness of 10 nm was formed on the substrate 911 as an insulator 912 by the ALD method.
  • silicon oxide having a film thickness of 100 nm was formed on the insulator 912 as the insulator 913 by the CVD method.
  • the film formation pressure was 0.7 Pa
  • the film formation power was 500 W
  • the substrate temperature was 130 ° C.
  • the distance between the target and the substrate was 60 mm.
  • Table 1 shows the temperature of the heat treatment in Samples 1A to 1E.
  • a tungsten film having a film thickness of 30 nm was formed on the oxide 914 as a conductive film to be a conductor 915a and a conductor 915b by a sputtering method. Subsequently, the conductive film was processed to form a conductor 915a and a conductor 915b that function as electrodes.
  • an insulator 916 functioning as a protective film was formed on the conductor 915a, the conductor 915b, and the oxide 914.
  • an insulating film to be the insulator 916 a silicon oxide film having a film thickness of 100 nm was formed by a CVD method.
  • a part of the insulating film was opened so as to expose a part of the conductor 915a and a part of the conductor 915b to form the insulator 916.
  • the amount of light absorption at the localized level can be measured with high sensitivity, and the density of the localized level or the absorption caused by the localized level can be relatively compared between the samples.
  • the terminals so that the value of the photocurrent is constant while a voltage is applied between the conductor 915a and the conductor 915b, which function as a pair of electrodes provided in contact with the oxide 914.
  • the amount of monochromatic light to be applied to the sample surface was adjusted, and the absorption coefficient was derived from the amount of monochromatic light to be irradiated.
  • the monochromatic light was swept from a long wavelength to a short wavelength in 10 nm increments and irradiated in a wavelength range of 350 nm or more and 750 nm or less.
  • the transition of the absorption coefficient with respect to the wavelength obtained by the CPM measurement may be referred to as a CPM spectrum.
  • the absorption coefficient was derived at each wavelength of monochromatic light.
  • the absorption coefficient in energy increases with the localized level density.
  • the region of the curve of the CPM spectrum where the absorption coefficient is larger than the light absorption (also referred to as the arback tail) caused by the band tail on the valence band side the localization level of the sample is measured. Absorption due to valence band can be derived.
  • the absorption ⁇ due to the localized level of the sample can be calculated from the following formula.
  • E energy
  • ⁇ CPM the absorption coefficient obtained by CPM measurement
  • ⁇ U the absorption coefficient of the arbor tail.
  • FIG. 34 shows the measurement results of the CPM measurement of Samples 1A to 1E.
  • the vertical axis was the absorption due to the localized level [cm -1 ], and the horizontal axis was the temperature [° C.] of the heat treatment after the oxide 914 film was formed on each sample.
  • sample 1A, sample 1C, sample 1D, and sample 1E two samples were measured, respectively.
  • sample 1B one sample was measured.
  • the localized level density changes depending on the conditions of the heat treatment after the oxide 914 is formed.
  • the temperature of the heat treatment is in the range of 400 ° C. or higher and 550 ° C. or lower, the localized level density tends to decrease as the temperature increases.
  • the temperature of the heat treatment was 600 ° C.
  • the localized level density increased at least as compared with the case where the temperature of the heat treatment was 550 ° C.
  • the localized level density in the oxide semiconductor can be reduced by performing heat treatment under appropriate conditions after forming the oxide semiconductor film.
  • the oxide semiconductor film after forming the oxide semiconductor film, it is preferable to perform heat treatment at 450 ° C. or higher and 600 ° C. or lower. By this treatment, the absorption by the localized level in the oxide semiconductor film can be reduced to 1.0 ⁇ 10 -2 cm -1 or less.
  • the oxide semiconductor in the channel forming region of the transistor the carrier concentration in the channel forming region is reduced, and the channel forming region can be i-shaped (intrinsicized) or substantially i-shaped. Therefore, a semiconductor device including a transistor having good electrical characteristics can be manufactured.
  • sample 2A group (sample 2A-1, sample 2A-2, sample 2A-3, and sample 2A-4) and sample 2B group (sample 2B-1, sample 2B-2, sample 2B).
  • sample 2C group (sample 2C-1, sample 2C-2, sample 2C-3, and sample 2C-4), sample 2D group (sample 2D-1, sample 2D-2, Samples 2D-3 and 2D-4) and sample 2E groups (Sample 2E-1, Sample 2E-2, Sample 2E-3, and Sample 2E-4) were prepared.
  • sample 2A-1, sample 2B-1, sample 2C-1, sample 2D-1 and sample 2E-1 may be referred to as a sample 2-1 group.
  • sample 2-2 group (sample 2A-2, sample 2B-2, sample 2C-2, sample 2D-2 and sample 2E-2), sample 2-3 group (sample 2A-3, sample 2B-3).
  • Sample 2C-3, Sample 2D-3 and Sample 2E-3) Sample 2-4 group (Sample 2A-4, Sample 2B-4, Sample 2C-4, Sample 2D-4 and Sample 2E-4). ..
  • the sample 2A group to the sample 2E group consist of a substrate 921, an insulator 922 on the substrate 921, an insulator 923 on the insulator 922, an oxide 924 on the insulator 923, and an insulator 925 on the oxide 924. And an insulator 926 on the insulator 925.
  • each sample was subjected to the first heat treatment and the second heat treatment under different conditions.
  • the heat treatment performed after the oxide 924 is formed is defined as the first heat treatment.
  • the heat treatment performed after the insulator 926 is formed is referred to as the second heat treatment.
  • Table 2 shows the temperatures of the first heat treatment and the second heat treatment performed on each sample.
  • "-" in Table 2 indicates that the corresponding heat treatment was not performed.
  • a silicon substrate was prepared as the substrate 921. Subsequently, a thermal oxide film having a film thickness of 100 nm was formed on the substrate 921 as an insulator 922.
  • silicon nitride having a film thickness of 20 nm was formed on the insulator 922 as the insulator 923 by using a sputtering method.
  • the silicon nitride has a function of suppressing diffusion with respect to hydrogen. Therefore, it is assumed that the mixing of hydrogen from the substrate 921 side is negligible.
  • an oxide containing 300 nm In, Ga, and Zn was formed on the insulator 923 as the oxide 924 by a sputtering method.
  • the film formation pressure was 0.7 Pa
  • the film formation power was 500 W
  • the substrate temperature was 200 ° C.
  • the distance between the target and the substrate was 60 mm.
  • the first heat treatment was performed on the sample 2B group to the sample 2E group.
  • the heat treatment was carried out for 1 hour at the predetermined temperature shown in Table 2 under a nitrogen atmosphere, then switched to an oxygen atmosphere, and under an oxygen atmosphere, at the predetermined temperature shown in Table 2. The heat treatment was carried out for 1 hour.
  • silicon oxide having a film thickness of 50 nm and containing deuterium (D) was formed on the oxide 924 as an insulator 925 by a CVD method.
  • the insulator 925 uses silane (SiH 4 ) having a flow rate of 2 sccm, dinitrogen monoxide (N2 O) having a flow rate of 800 sccm, and deuterium (D 2 ) having a flow rate of 200 sccm as the film forming gas, and the substrate temperature is 160 ° C.
  • the film was formed with a film forming pressure of 200 Pa and a film forming power of 150 W.
  • an insulator 926 was formed on the insulator 925.
  • Silicon nitride having a film thickness of 20 nm was formed on the insulator 926 by using a sputtering method.
  • the silicon nitride has a function of suppressing diffusion with respect to hydrogen. Therefore, it is assumed that the mixing of hydrogen from above the insulator 926 is negligible.
  • the sample 2-2 group to the sample 2-4 group were subjected to the second heat treatment.
  • the second heat treatment was carried out in a nitrogen atmosphere at a predetermined temperature shown in Table 2 for 1 hour.
  • SIMS measurement results for each sample> SIMS analysis was performed from the substrate 921 side to detect the deuterium (D) concentration in the oxide 924.
  • a quadrupole secondary ion mass spectrometer PHI ADEPT 1010 manufactured by ULVAC-PHI, Inc. was used as an analyzer for the evaluation of the deuterium concentration.
  • FIGS. 36A, 36B, 37A, 37B, and 38 The depth profile of the deuterium concentration in the membrane in each sample is shown in FIGS. 36A, 36B, 37A, 37B, and 38. All the SIMS analysis results of this example are quantified using a standard sample prepared with an oxide containing the same In, Ga, and Zn as the oxide 924.
  • the horizontal axis is the vertical depth [nm] from the sample surface, and the vertical axis is the deuterium (D) in the oxide 924.
  • FIG. 36A shows the analysis result of the sample 2A group (first heat treatment: none), and FIG. 36B shows the analysis result of the sample 2B group (first heat treatment temperature: 400 ° C.).
  • FIG. 37A shows the analysis results of the sample 2C group (first heat treatment temperature: 450 ° C.), and FIG. 37B shows the analysis results of the sample 2D group (first heat treatment temperature: 500 ° C.).
  • FIG. 38 shows the analysis results of the sample 2E group (temperature of the first heat treatment: 550 ° C.).
  • FIGS. 36A, 36B, 37A, 37B, and 38 the depth direction profile of the deuterium (D) concentration in the membrane of the sample 2-1 group (second heat treatment: none) is shown. Shown by the dotted line.
  • the depth direction profile of the deuterium (D) concentration in the membrane of the sample 2-2 group (temperature of the second heat treatment: 300 ° C.) is shown by a dashed line.
  • the depth direction profile of the deuterium (D) concentration in the membrane of the sample 2-3 group (temperature of the second heat treatment: 350 ° C.) is shown by a chain double-dashed line.
  • the depth direction profile of the deuterium (D) concentration in the membrane of the sample 2-4 group (temperature of the second heat treatment: 400 ° C.) is shown by a solid line.
  • the diffusion lengths of deuterium in the sample 2A group, the sample 2B group, the sample 2C group, the sample 2D group, and the sample 2E group are calculated using the measurement results of the SIMS analysis. did.
  • the deuterium concentration C (x, T, t) at a distance x [nm] from the surface of the oxide 924, a temperature T, and a time t is a complementary error function erfc (y) (y is a variable) as shown in the following equation. It is assumed that it can be expressed using.).
  • C s is the concentration of deuterium on the surface
  • D (T) is the diffusion coefficient at temperature T
  • c is a constant.
  • the profile of the deuterium concentration C (x, T, t) with respect to the distance x obtained by SIMS measurement is fitted by the least squares method using the above formula. At this time, the fitting parameters, and C s and D (T).
  • the diffusion length of deuterium was calculated with the temperature T as 400 ° C. and the time t as 1 hour.
  • FIG. 39 shows the calculation results of the diffusion length of deuterium in the sample 2A group, the sample 2B group, the sample 2C group, the sample 2D group, and the sample 2E group.
  • the diffusion length of deuterium calculated by the above method is 1953 nm in the sample 2A group, 218 nm in the sample 2B group, 46 nm in the sample 2C group, 43 nm in the sample 2D group, and is 43 nm in the sample 2E group. It was 23 nm.
  • the diffusion length of deuterium was small. Therefore, in FIG. 39, the diffusion length of deuterium in the sample 2E group is described as being equal to or less than the lower limit of calculation. ing.
  • the diffusion length of deuterium in the sample 2C group is estimated to be larger than 46 nm. .. Specifically, the diffusion length of deuterium in the sample 2C group is estimated to be in the range of 46 nm to 128 nm.
  • sample 3A group (sample 3A-1, sample 3A-2, and sample 3A-3), sample 3B group (sample 3B-1, sample 3B-2, and sample 3B-3), Sample 3C group (Sample 3C-1, Sample 3C-2, and Sample 3C-3), Sample 3D group (Sample 3D-1, Sample 3D-2, and Sample 3D-3), and Sample 3E group (Sample 3E- 1. Sample 3E-2 and Sample 3E-3) were prepared.
  • sample 3A-1, sample 3B-1, sample 3C-1, sample 3D-1, and sample 3E-1 may be referred to as a sample 3-1 group.
  • sample 3-2 group sample 3A-2, sample 3B-2, sample 3C-2, sample 3D-2, and sample 3E-2
  • sample 3-3 group sample 3A-3, sample 3B-. 3. Sample 3C-3, sample 3D-3, and sample 3E-3).
  • the sample 3A group to the sample 3E group consist of a substrate 931, an insulator 932 on the substrate 931, an insulator 933 on the insulator 932, an oxide 934 on the insulator 933, and an insulator 935 on the oxide 934. And an insulator 936 on the insulator 935.
  • each sample was subjected to the first heat treatment and the second heat treatment under different conditions.
  • the heat treatment performed after the oxide 934 is formed is defined as the first heat treatment.
  • the heat treatment performed after the insulator 936 is formed is referred to as the second heat treatment.
  • Table 3 shows the temperatures of the first heat treatment and the second heat treatment performed on each sample.
  • "-" in Table 3 indicates that the corresponding heat treatment was not performed.
  • a silicon substrate was prepared as the substrate 931. Subsequently, a thermal oxide film having a film thickness of 100 nm was formed on the substrate 931 as an insulator 932.
  • aluminum oxide having a film thickness of 20 nm was formed on the insulator 932 as the insulator 933 by using a sputtering method.
  • the aluminum oxide has a function of suppressing the diffusion of oxygen. Therefore, it is assumed that the mixing of oxygen from the substrate 931 side is negligible.
  • the film formation pressure was 0.7 Pa
  • the film formation power was 500 W
  • the substrate temperature was 200 ° C.
  • the distance between the target and the substrate was 60 mm.
  • the first heat treatment was performed on the sample 3B group to the sample 3E group.
  • the first heat treatment is carried out in a nitrogen atmosphere at a predetermined temperature shown in Table 3 for 1 hour, then switched to an oxygen atmosphere, and in an oxygen atmosphere at a predetermined temperature shown in Table 3.
  • the heat treatment was carried out for 1 hour.
  • silicon oxide containing an oxygen stable isotope (denoted as 18 O) having a film thickness of 50 nm and a mass number of 18 was formed as an insulator 935 by a sputtering method. ..
  • the insulator 935 uses a silicon oxide (SiO 2 ) target, oxygen (O 2 ) containing 18 O at a flow rate of 25 sccm as a film forming gas, a film forming pressure of 0.7 Pa, and a film forming power of 2.
  • the film was formed with 5.5 kW (RF), a substrate temperature of 100 ° C., and a target-substrate distance of 60 mm.
  • an insulator 936 was formed on the insulator 935.
  • the insulator 936 was formed by forming aluminum oxide having a film thickness of 20 nm by a sputtering method.
  • the aluminum oxide has a function of suppressing the diffusion of oxygen. Therefore, it is assumed that the mixing of oxygen from above the insulator 936 is negligible.
  • the sample 3-2 group and the sample 3-3 group were subjected to the second heat treatment.
  • the second heat treatment was carried out in a nitrogen atmosphere at a predetermined temperature shown in Table 3 for 1 hour.
  • SIMS measurement results for each sample> using the oxide 934 of the sample 3A group to the sample 3E group as a quantitative layer, SIMS analysis was performed from the substrate 931 side, and the 18 O concentration in the oxide 934 was detected.
  • a quadrupole secondary ion mass spectrometer PHI ADEPT 1010 manufactured by ULVAC-PHI, Inc. was used as an analyzer for the concentration evaluation of 18 O.
  • FIGS. 41A, 41B, 42A, 42B, and 43 The depth profile of the 18 O concentration in the membrane in each sample is shown in FIGS. 41A, 41B, 42A, 42B, and 43. All the SIMS analysis results of this example are quantified using a standard sample prepared with an oxide containing the same In, Ga, and Zn as the oxide 934.
  • the horizontal axis is the vertical depth [nm] from the sample surface, and the vertical axis is the 18 O concentration in oxide 934 [ atoms / cm 3 ].
  • FIG. 41A shows the analysis result of the sample 3A group (first heat treatment: none), and FIG. 41B shows the analysis result of the sample 3B group (first heat treatment temperature: 400 ° C.).
  • FIG. 42A shows the analysis result of the sample 3C group (first heat treatment temperature: 450 ° C.), and FIG. 42B shows the analysis result of the sample 3D group (first heat treatment temperature: 500 ° C.).
  • FIG. 43 shows the analysis results of the sample 3E group (temperature of the first heat treatment: 550 ° C.).
  • FIGS. 41A, 41B, 42A, 42B, and 43 the depth direction profile of the 18 O concentration in the film of the sample 3-1 group (second heat treatment: none) is shown by a dotted line. ..
  • the depth-direction profile of the 18 O concentration in the film of the sample 3-2 group (temperature of the second heat treatment: 400 ° C.) is shown by a dashed line.
  • the depth profile of the 18 O concentration in the film of the sample 3-3 group is shown by a solid line.

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PCT/IB2020/055353 2019-06-21 2020-06-08 金属酸化物、金属酸化物の形成方法、半導体装置、および半導体装置の作製方法 Ceased WO2020254910A1 (ja)

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