WO2021009589A1 - 半導体装置、および半導体装置の作製方法 - Google Patents
半導体装置、および半導体装置の作製方法 Download PDFInfo
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- WO2021009589A1 WO2021009589A1 PCT/IB2020/056149 IB2020056149W WO2021009589A1 WO 2021009589 A1 WO2021009589 A1 WO 2021009589A1 IB 2020056149 W IB2020056149 W IB 2020056149W WO 2021009589 A1 WO2021009589 A1 WO 2021009589A1
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- oxide
- insulator
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Images
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Definitions
- One aspect of the present invention relates to transistors, semiconductor devices, and electronic devices. Alternatively, one aspect of the present invention relates to a method for manufacturing a semiconductor device. Alternatively, one aspect of the present invention relates to a semiconductor wafer and a module.
- the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics.
- a semiconductor device such as a transistor, a semiconductor circuit, an arithmetic unit, and a storage device are one aspect of the semiconductor device. It may be said that a display device (liquid crystal display device, light emission display device, etc.), projection device, lighting device, electro-optical device, power storage device, storage device, semiconductor circuit, image pickup device, electronic device, and the like have a semiconductor device.
- One aspect of the present invention is not limited to the above technical fields.
- One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method.
- one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter).
- a CPU is an aggregate of semiconductor elements having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and having electrodes as connection terminals formed therein.
- IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, for example, printed wiring boards, and are used as one of various electronic device components.
- a technique for constructing a transistor by using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention.
- the transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices).
- ICs integrated circuits
- image display devices also simply referred to as display devices.
- Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
- a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state.
- a low power consumption CPU that applies the characteristic that the leakage current of a transistor using an oxide semiconductor is low is disclosed (see Patent Document 1).
- a storage device capable of holding a storage content for a long period of time by applying the characteristic that a transistor using an oxide semiconductor has a low leakage current is disclosed (see Patent Document 2).
- One aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration. Alternatively, one aspect of the present invention is to provide a semiconductor device having a large storage capacity. Alternatively, one aspect of the present invention is to provide a semiconductor device having little variation in transistor characteristics. Alternatively, one aspect of the present invention is to provide a semiconductor device having good reliability. Alternatively, one aspect of the present invention is to provide a semiconductor device having good electrical characteristics. Alternatively, one aspect of the present invention is to provide a semiconductor device having a large on-current. Alternatively, one aspect of the present invention is to provide a semiconductor device having low power consumption. Alternatively, one aspect of the present invention is to provide a novel semiconductor device.
- One aspect of the present invention includes a first conductor arranged on a substrate, an oxide arranged in contact with the upper surface of the first conductor, and a second conductor arranged on the oxide.
- a first insulator arranged on a third conductor, a fourth conductor, and a second conductor to a fourth conductor, and formed with a first opening and a second opening.
- a second insulator placed in the first opening, a fifth conductor placed on top of the second insulator, and a third conductor placed in the second opening.
- It has an insulator and a sixth conductor arranged on top of the third insulator, the third conductor is arranged superimposed on the first conductor, and the first opening is , The second opening is formed by superimposing on the region between the second conductor and the third conductor, and the second opening is formed by superimposing on the region between the third conductor and the fourth conductor. It is a semiconductor device.
- the first capacitive element and the second capacitive element are included, the first capacitive element is electrically connected to the second conductor, and the second capacitive element is the fourth. It may be electrically connected to the conductor. Further, in the above, it is preferable that the first capacitive element is arranged on the second conductor and the second capacitive element is arranged on the fourth conductor.
- the first conductor is connected to the wiring provided under the first conductor.
- the second insulator is in contact with the upper surface of the oxide and the side surface of the first insulator
- the third insulator is in contact with the upper surface of the oxide and the side surface of the first insulator. , Is preferable.
- the oxide has a first oxide and a second oxide on the first oxide, and the first oxide and the second oxide are indium.
- the element M M is one or more selected from gallium, aluminum, yttrium, and tin
- the atomic number ratio of indium to the element M of the first oxide is It is preferably smaller than the atomic number ratio of indium to the element M of the second oxide.
- a first conductor is formed on a substrate, an oxide film is formed in contact with the upper surface of the first conductor, and a first conductive film is formed on the oxide film.
- the film, the oxide film, and the first conductive film are processed into an island shape to form an oxide and a second conductor, and the oxide and the second conductor are covered with the first insulator.
- a part of the first insulator is removed, and the first opening and the second opening are formed by superimposing on the second conductor, and the first opening and the second opening are formed.
- a part of the second conductor superposed on the conductor is removed to form a third conductor, a fourth conductor, and a fifth conductor, and the fourth conductor is the first conductor.
- the oxide is arranged so as to be superimposed on the third to fifth conductors, and the region not overlapped with the third to fifth conductors is exposed, and is in contact with the upper surface of the oxide to form a first insulating film, which contains oxygen.
- Microwave treatment is performed in an atmosphere to form a second conductive film on the first insulating film, and the upper surface of the first insulating material is exposed to the first insulating film and the second conductive film.
- CMP treatment is performed to form a second insulator and a sixth conductor in the first opening, and a third insulator and a seventh conductor are formed in the second opening. This is a method for manufacturing a semiconductor device.
- one aspect of the present invention it is possible to provide a semiconductor device capable of miniaturization or high integration.
- one aspect of the present invention can provide a semiconductor device having a large storage capacity.
- one aspect of the present invention can provide a semiconductor device with good reliability.
- one aspect of the present invention can provide a semiconductor device having good electrical characteristics.
- one aspect of the present invention can provide a semiconductor device having a large on-current.
- one aspect of the present invention can provide a semiconductor device capable of miniaturization or high integration.
- one aspect of the present invention can provide a low power consumption semiconductor device.
- one aspect of the present invention can provide a novel semiconductor device.
- FIG. 1A, 1B, 1C, and 1D are a top view and a cross-sectional view of a semiconductor device according to an aspect of the present invention.
- FIG. 2 is a cross-sectional view of the semiconductor device according to one aspect of the present invention.
- FIG. 3A is a diagram illustrating classification of the crystal structure of IGZO.
- FIG. 3B is a diagram illustrating an XRD spectrum of a CAAC-IGZO film.
- FIG. 3C is a diagram for explaining the microelectron diffraction pattern of the CAAC-IGZO film.
- 4A, 4B, 4C, and 4D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
- 5A, 5B, 5C, and 5D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
- 6A, 6B, 6C, and 6D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
- 7A, 7B, 7C, and 7D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
- 8A, 8B, 8C, and 8D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
- 9A, 9B, 9C, and 9D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
- 10A, 10B, 10C, and 10D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
- 11A, 11B, 11C, and 11D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
- 12A, 12B, 12C, and 12D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
- FIG. 13 is a top view illustrating a microwave processing apparatus according to an aspect of the present invention.
- FIG. 14 is a cross-sectional view illustrating a microwave processing apparatus according to an aspect of the present invention.
- FIG. 15 is a cross-sectional view illustrating a microwave processing apparatus according to an aspect of the present invention.
- 16A, 16B, 16C, and 16D are a top view and a cross-sectional view of the semiconductor device according to one aspect of the present invention.
- 17A and 17B are cross-sectional views of the semiconductor device according to one aspect of the present invention.
- FIG. 18 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention.
- FIG. 19 is a cross-sectional view showing a configuration of a storage device according to an aspect of the present invention.
- 20A and 20B are cross-sectional views of the semiconductor device according to one aspect of the present invention.
- FIG. 21 is a cross-sectional view of the semiconductor device according to one aspect of the present invention.
- FIG. 22 is a cross-sectional view of the semiconductor device according to one aspect of the present invention.
- 23A and 23B are block diagrams showing a configuration example of a storage device according to one aspect of the present invention.
- 24A, 24B, and 24C are circuit diagrams showing a configuration example of a storage device according to one aspect of the present invention.
- 25A and 25B are schematic views of a semiconductor device according to one aspect of the present invention.
- 26A and 26B are diagrams illustrating an example of an electronic component according to one aspect of the present invention.
- 27A and 27B are schematic views of a storage device according to an aspect of the present invention.
- 28A, 28B, 28C, 28D, 28E, 28F, 28G, and 28H are diagrams showing an electronic device according to an aspect of the present invention.
- the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.
- the drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but they may not be reflected in the figure for the sake of easy understanding. Further, in the drawings, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted. Further, when referring to the same function, the hatch pattern may be the same and no particular sign may be added.
- a top view also referred to as a "plan view”
- a perspective view the description of some components may be omitted.
- some hidden lines may be omitted.
- the ordinal numbers attached as the first, second, etc. are used for convenience, and do not indicate the process order or the stacking order. Therefore, for example, the "first” can be appropriately replaced with the “second” or “third” for explanation.
- the ordinal numbers described in the present specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.
- X and Y are connected, the case where X and Y are electrically connected and the case where X and Y function. It is assumed that the case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification and the like. Therefore, it is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text, and other than the connection relationship shown in the figure or text, it is assumed that the connection relationship is disclosed in the figure or text.
- X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
- a transistor is an element having at least three terminals including a gate, a drain, and a source. It also has a region (hereinafter, also referred to as a channel forming region) in which a channel is formed between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode). A current can flow between the source and the drain through the channel formation region.
- the channel forming region means a region in which a current mainly flows.
- source and drain functions may be interchanged when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in the present specification and the like, the terms source and drain may be used interchangeably.
- the channel length is, for example, the source in the top view of the transistor, the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other, or the channel formation region.
- the channel length does not always take the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in the present specification, the channel length is set to any one value, the maximum value, the minimum value, or the average value in the channel formation region.
- the channel width is, for example, the channel length direction in the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other in the top view of the transistor, or the channel formation region. Refers to the length of the channel formation region in the vertical direction with reference to. In one transistor, the channel width does not always take the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in the present specification, the channel width is set to any one value, the maximum value, the minimum value, or the average value in the channel formation region.
- the channel width in the region where the channel is actually formed (hereinafter, also referred to as “effective channel width”) and the channel width shown in the top view of the transistor. (Hereinafter, also referred to as “apparent channel width”) and may be different.
- the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible.
- the proportion of the channel forming region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.
- channel width may refer to the apparent channel width.
- channel width may refer to an effective channel width.
- the channel length, channel width, effective channel width, apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
- the semiconductor impurity means, for example, a component other than the main components constituting the semiconductor.
- an element having a concentration of less than 0.1 atomic% can be said to be an impurity. Due to the inclusion of impurities, for example, the defect level density of the semiconductor may increase or the crystallinity may decrease.
- the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxide semiconductors.
- transition metals other than the main component such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water may also function as an impurity.
- the oxide semiconductor to an oxygen vacancy V O: also referred to as oxygen vacancy
- silicon oxide nitriding has a higher oxygen content than nitrogen as its composition. Further, silicon nitride has a higher nitrogen content than oxygen in its composition.
- the term “insulator” can be paraphrased as an insulating film or an insulating layer.
- the term “conductor” can be rephrased as a conductive film or a conductive layer.
- semiconductor can be paraphrased as a semiconductor film or a semiconductor layer.
- parallel means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included.
- approximately parallel means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
- vertical means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.
- approximately vertical means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
- a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used in the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when it is described as an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
- normally off means that when a potential is not applied to the gate or a ground potential is applied to the gate, the drain current per 1 ⁇ m of the channel width flowing through the transistor is 1 ⁇ 10 ⁇ at room temperature. It means that it is 20 A or less, 1 ⁇ 10 -18 A or less at 85 ° C, or 1 ⁇ 10 -16 A or less at 125 ° C.
- Embodiment 1 In the present embodiment, an example of a semiconductor device having a transistor 200a and a transistor 200b according to one aspect of the present invention, and a method for manufacturing the same will be described with reference to FIGS. 1 to 17.
- the transistor 200a and the transistor 200b may be collectively referred to as a transistor 200.
- FIG. 1A is a top view of the semiconductor device.
- 1B to 1D are cross-sectional views of the semiconductor device.
- FIG. 1B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200a and the transistor 200b in the channel length direction.
- FIG. 1C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG.
- FIG. 1A is also a cross-sectional view of the transistor 200a in the channel width direction.
- FIG. 1D is a cross-sectional view of the portion shown by the alternate long and short dash line in FIG. 1A.
- FIG. 1A In the top view of FIG. 1A, some elements are omitted for the purpose of clarifying the figure.
- the semiconductor device of one aspect of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, and an insulator 280 on the transistor 200. It has an insulator 282 on an insulator 280 and an insulator 283 on an insulator 282.
- the insulator 212, the insulator 214, the insulator 280, the insulator 282, and the insulator 283 function as an interlayer film.
- a conductor 248 (conductor 248a and conductor 248b) is provided so as to be embedded between the insulator 212, the insulator 214, and the transistor 200a and the transistor 200b.
- the conductor 248 is electrically connected to the transistor 200a and the transistor 200b and functions as a plug. It is preferable to provide the insulator 249 in contact with the side surface of the conductor 248 that functions as a plug.
- the transistor 200a includes an insulator 216 on the insulator 214 and a conductor 205 (conductor 205a, conductor 205b, and conductor 205) arranged so as to be embedded in the insulator 216. 205c), the insulator 222 on the insulator 216 and the conductor 205, the insulator 224 on the insulator 222, the oxide 230a on the insulator 224, and the oxide 230b on the oxide 230a.
- the oxide 230b On the oxide 230b, the oxide 243a and the oxide 243b, the conductor 242a on the oxide 243a, the conductor 242b on the oxide 243b, the insulator 250 on the oxide 230b, and the insulator 250. It has a conductor 260 (conductor 260a, and a conductor 260b) that is located and overlaps a part of the oxide 230b.
- the transistor 200b is on the insulator 216 on the insulator 214, the conductor 205 arranged so as to be embedded in the insulator 214 or the insulator 216, and the insulator 216.
- oxide 243b and oxide 243c conductor 242b on oxide 243b, conductor 242c on oxide 243c, insulator 250 on oxide 230b, located on insulator 250, one of oxide 230b It has a conductor 260 that overlaps with the portion.
- the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230.
- the oxide 243a, the oxide 243b, and the oxide 243c may be collectively referred to as an oxide 243.
- the conductor 242a, the conductor 242b, and the conductor 242c may be collectively referred to as the conductor 242.
- the insulator 275 is provided so as to cover the insulator 224, the oxide 230, the oxide 243, and the conductor 242. Further, as shown in FIGS. 1B and 1C, the upper surface of the conductor 260 is arranged so as to substantially coincide with the upper surface of the insulator 250 and the upper surface of the insulator 280. Further, the insulator 282 is in contact with the upper surface of each of the conductor 260 and the insulator 280, and the uppermost portion of the insulator 250.
- the transistor 200b is provided on the opposite side of the transistor 200a with the conductor 248 interposed therebetween, and has the same structure as the transistor 200a except for the conductor 242 and the oxide 243. Has.
- the insulator 212, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the oxide 230a, the oxide 230b, the insulator 275, the insulator 280, the insulator 282, and the insulator. 283 is commonly used.
- the conductor 205, the insulator 250, and the conductor 260 are provided in the transistor 200a and the transistor 200b, respectively.
- the conductor 205, the insulator 250, and the conductor 260 each have the same structure as the transistor 200a, and are therefore designated by the same reference numerals.
- the conductors 242a to 242c and the oxides 243a to 243c are linearly arranged in the channel length direction (A1-A2 direction) on the oxide 230.
- the conductor 242b is arranged so as to superimpose on the conductor 248.
- openings are provided so as to overlap the region between the conductor 242a and the conductor 242b and the region between the conductor 242b and the conductor 242c. In each of the openings, an insulator 250 and a conductor 260 arranged on the insulator 250 are provided.
- the insulator 280 and the insulator 275 are provided with two openings reaching the oxide 230b, and the insulator 250 and the conductor 260 are arranged in the openings. That is, in the transistor 200a, the insulator 250 includes the upper surface of the oxide 230b, the side surfaces of the oxide 243a and the oxide 243b, the side surfaces of the conductor 242a and the conductor 242b, the side surface of the insulator 275, and the insulator 280. It is provided in contact with the side surface of.
- the insulator 250 includes the upper surface of the oxide 230b, the side surfaces of the oxide 243b and the oxide 243c, the side surfaces of the conductor 242b and the conductor 242c, the side surface of the insulator 275, and the insulator 280. It is provided in contact with the side surface of. Further, in the transistor 200a and the transistor 200b, the respective conductors 260 are provided in contact with the upper surface and the side surface of the respective insulator 250.
- the conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode.
- the insulator 250 functions as a first gate insulator, and the insulator 222 and the insulator 224 function as a second gate insulator.
- the conductor 242a functions as one of the source and drain of the transistor 200a.
- the conductor 242b functions as one of the source or drain of the transistor 200a and one of the source or drain of the transistor 200b.
- the conductor 242c functions as the source or drain of the transistor 200b.
- at least a part of the region of the oxide 230 overlapping with the conductor 260 functions as a channel forming region of the transistor 200a or the transistor 200b.
- the oxide 230 is provided so as to sandwich a region 232d that functions as a channel forming region of the transistor 200a and a region 232d, and functions as a source region or a drain region of the transistor 200a, and the regions 232a and 232b.
- the region 232d and the region 232e overlaps with the conductor 260.
- the region 232d is provided so as to overlap the region between the conductors 242a and the conductor 242b
- the region 232e is provided so as to overlap the region between the conductors 242b and the conductor 242c.
- the region 232a is provided so as to be superimposed on the conductor 242a
- the region 232b is provided so as to be superimposed on the conductor 242b
- the region 232c is provided so as to be superimposed on the conductor 242c.
- the region 232d and the region 232e that function as the channel formation region are high resistance regions having a low carrier concentration because they have less oxygen deficiency or a lower impurity concentration than the regions 232a, 232b, and 232c. Therefore, it can be said that the region 232d and the region 232e are i-type (intrinsic) or substantially i-type.
- the carrier concentration increases due to a large amount of oxygen deficiency or a high concentration of impurities such as hydrogen, nitrogen, and metal elements. This is a region with low resistance. That is, the regions 232a, 232b, and 232c are n-type regions having a high carrier concentration and low resistance as compared with the regions 232d and 232e.
- the carrier concentration of the region 232d and the region 232e that function as the channel forming region is preferably 1 ⁇ 10 18 cm -3 or less, more preferably less than 1 ⁇ 10 17 cm -3. It is more preferably less than 10 16 cm -3 , even more preferably less than 1 ⁇ 10 13 cm -3 , and even more preferably less than 1 ⁇ 10 12 cm -3 .
- the lower limit of the carrier concentration of the region 232d and the region 232e that function as the channel forming region is not particularly limited, but may be, for example, 1 ⁇ 10 -9 cm -3 .
- the carrier concentration between the region 232d and the region 232a or the region 232b, or between the region 232e and the region 232b or the region 232c is equal to or equal to the carrier concentration of the region 232a, the region 232b, and the region 232c.
- Regions may be formed that are lower than that and equal to or higher than the carrier concentrations of regions 232d and 232e. That is, the region functions as a junction region between the region 232d or the region 232e and the region 232a, the region 232b, or the region 232c.
- the hydrogen concentration may be equal to or lower than the hydrogen concentration in the regions 232a, 232b, and 232c, and equal to or higher than the hydrogen concentration in the regions 232d and 232e. .. Further, when the oxygen deficiency in the junction region is equal to or less than the oxygen deficiency in the regions 232a, 232b, and 232c, and equal to or greater than the oxygen deficiency in the regions 232d and 232e. There is.
- concentrations of the metal elements detected in each region and the impurity elements such as hydrogen and nitrogen are not limited to the stepwise changes in each region, but may be continuously changed in each region. That is, the closer the region is to the channel formation region, the lower the concentration of metal elements and impurity elements such as hydrogen and nitrogen is sufficient.
- the region 232b functions as a source region or a drain region of both the transistor 200a and the transistor 200b, and is shared by the transistor 200a and the transistor 200b.
- the transistor 200a and the transistor 200b have a structure in which the source and the drain are connected in series.
- the oxide 230 is in contact with at least a part of the upper surface of the conductor 248 in the region 232b.
- the conductor 242b is arranged so as to be superimposed on at least a part of the conductor 248.
- the conductor 248 is arranged so as to be exposed from the upper surface of the insulator 224.
- the conductor 248 may be arranged so as to be embedded in the openings formed in the insulator 212, the insulator 214, the insulator 216, the insulator 222, and the insulator 224. It is preferable that at least a part of the upper surface of the conductor 248 is exposed from the insulator 224, and the upper surface of the conductor 248 and the upper surface of the insulator 224 substantially coincide with each other.
- the conductor 248 is a wiring, an electrode, a terminal, or a circuit element (switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, etc.) provided below the insulator 212, and the transistor 200a and the transistor 200a. It functions as a plug for electrically connecting the transistor 200b.
- the conductor 248 may be configured to be connected to a wiring provided below the insulator 212.
- the conductor 248 and the wiring provided in contact with the conductor 248 are bit wires.
- the conductor 260 of the transistor 200 corresponds to a word line.
- the conductor 248 is provided under the oxide 230
- the parasitic capacitance generated in the conductor 248 and the conductor 260 is compared with the case where the conductor 248 is provided on the oxide 230.
- the conductor 248 is provided under the oxide 230, the bit wire can be shortened as compared with the case where the conductor 248 is provided on the oxide 230. Therefore, the parasitic capacitance generated in the bit line can be reduced.
- the capacitance element can be miniaturized, so that the storage device can be miniaturized or highly integrated.
- the wiring, electrode, terminal, or circuit element electrically connected to the conductor 248 is the oxide 230. It is preferable to superimpose. As a result, the occupied area of the transistor 200, the wiring, the electrodes, the terminals, or the circuit element in the top view can be reduced, so that the semiconductor device according to the present embodiment can be miniaturized or highly integrated. ..
- the conductor 248 is provided in contact with the lower surface of the region 232b, but the present invention is not limited to this.
- the conductor 248 may be provided in contact with the lower surface of the region 232a, or the conductor 248 may be provided in contact with the lower surface of the region 232c.
- the oxide 230 preferably has an oxide 230a arranged on the insulator 224 and an oxide 230b arranged on the oxide 230a.
- the metal oxide that functions as a semiconductor it is preferable to use a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more.
- the off-current of the transistor can be reduced.
- the off-current of the transistor 200 can be reduced.
- the off-current of the transistor 200 it is possible to retain the stored contents for a long period of time when the transistor 200 is used as a memory cell of the storage device. That is, the storage device does not require a refresh operation, or the frequency of the refresh operation may be extremely low. Further, as a result, the power consumption of the storage device can be sufficiently reduced.
- an In-M-Zn oxide having indium, element M and zinc (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium).
- Zinc, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. (one or more) and the like may be used.
- an In-Ga-Zn oxide may be used, or an oxide obtained by adding tin to the In-Ga-Zn oxide may be used.
- an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.
- the metal oxide can be formed on a substrate by using a sputtering method or the like. Therefore, the transistor 200 can be provided on top of a peripheral circuit such as a drive circuit formed on a silicon substrate. Therefore, when the transistor 200 is used as a memory cell of a storage device, the occupied area of the memory cell array that can be provided on one chip can be increased, so that the storage capacity of the storage device can be increased. Further, by laminating a plurality of the metal oxides to form a film, the memory cell array can be laminated and provided. As a result, cells can be integrated and arranged without increasing the occupied area of the memory cell array. That is, a laminated structure of a memory cell array (hereinafter, may be referred to as a 3D cell array) can be constructed. As described above, it is possible to achieve high integration of memory cells and provide a semiconductor device having a large storage capacity.
- the semiconductor device using the above metal oxide, particularly In-Ga-Zn oxide has very good heat resistance as the temperature range in which the semiconductor device can be operated normally is -40 ° C or higher and 190 ° C or lower. ..
- This is the heat resistance of phase change memory (PCM: Phase Change Memory) (-40 ° C or more and 150 ° C or less), and the heat resistance of resistance change memory (ReRAM: Resistance Random Access Memory) (-40 ° C or more and 125 ° C or less).
- PCM Phase Change Memory
- ReRAM Resistance Random Access Memory
- MRAM Magnetoresistive Random Access Memory
- the atomic number ratio of In to the element M in the metal oxide used for the oxide 230b is larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 230a.
- the oxide 230a By arranging the oxide 230a under the oxide 230b, it is possible to suppress the diffusion of impurities and oxygen with respect to the oxide 230b from the structure formed below the oxide 230a.
- the oxide 230 is not limited to a configuration in which two layers of the oxide 230a and the oxide 230b are laminated.
- a single layer of the oxide 230b or a laminated structure of three or more layers may be provided, or each of the oxide 230a and the oxide 230b may have a laminated structure.
- the oxide 230 may be composed of a single layer of the oxide 230b so that the region 232b can be easily formed up to the bottom surface of the oxide 230.
- the oxide 230a and the oxide 230b have a common element (main component) other than oxygen, the defect level density at the interface between the oxide 230a and the oxide 230b can be lowered. Since the defect level density at the interface between the oxide 230a and the oxide 230b can be lowered, the influence of interfacial scattering on carrier conduction is small, and a high on-current can be obtained.
- each oxide 230b has crystallinity.
- CAAC-OS c-axis aligned crystalline semiconductor semiconductor
- CAAC-OS is a metal oxide having a highly crystalline and dense structure and having few impurities and defects (for example, oxygen deficiency ( VO )).
- the CAAC-OS is subjected to heat treatment at a temperature at which the metal oxide does not undergo polycrystallization (for example, 400 ° C. or higher and 600 ° C. or lower), whereby CAAC-OS has a more crystalline and dense structure. Can be.
- a temperature at which the metal oxide does not undergo polycrystallization for example, 400 ° C. or higher and 600 ° C. or lower
- the metal oxide having CAAC-OS has stable physical properties. Therefore, the metal oxide having CAAC-OS is resistant to heat and has high reliability.
- Transistors using oxide semiconductors may have poor electrical characteristics and poor reliability if impurities and oxygen deficiencies are present in the region where channels are formed in the oxide semiconductor.
- the hydrogen of oxygen vacancies near defects containing the hydrogen to the oxygen deficiency (hereinafter, may be referred to as V O H.) Was formed, the carrier even when no voltage is applied to the gate electrode of the transistor May generate electrons. Therefore, if oxygen deficiency is contained in the region where the channel is formed in the oxide semiconductor, the transistor has normal-on characteristics (the channel exists even if no voltage is applied to the gate electrode, and the current is applied to the transistor. Flowing characteristics).
- the carrier concentration is reduced in the state where no voltage is applied to the gate electrode of the transistor, and it is i-type (intrinsic) or substantially i-type. It is preferable to have.
- excess oxygen an insulator containing oxygen desorbed by heating
- the oxide semiconductor is separated from the insulator.
- oxygen is supplied, it is possible to reduce oxygen vacancies, and V O H to.
- the on-current of the transistor 200 may decrease or the field effect mobility may decrease.
- the oxygen supplied to the source region or the drain region varies in the surface of the substrate, so that the characteristics of the semiconductor device having the transistor vary.
- the region 232d and the region 232e that function as the channel forming region preferably have a reduced carrier concentration and are i-type or substantially i-type, but function as a source region or a drain region.
- the region 232a, the region 232b, and the region 232c have a high carrier concentration and are preferably n-type.
- the oxygen deficiency in the region 232d and the region 232e of the oxide semiconductor and reduces V O H, region 232a, the region 232b, and it is preferable that an excessive amount of oxygen in the region 232c to not be supplied.
- microwave treatment is performed in an atmosphere containing oxygen, and oxygen deficiency in the regions 232d and 232e is performed. , and reduced V O H.
- the microwave processing refers to processing using, for example, a device having a power source that generates high-density plasma using microwaves.
- oxygen gas By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequencies such as RF, and the oxygen plasma can be allowed to act. At this time, the region 232d and the region 232e can be irradiated with a high frequency such as a microwave or RF. Plasma, by the action such as a microwave, and divide the V O H region 232d and the region 232 e, the hydrogen H is removed from the region 232d and the region 232 e, it is possible to fill oxygen vacancies V O in oxygen. That is, in the region 232d and the region 232 e, happening reaction of "V O H ⁇ H + V O", it is possible to reduce the hydrogen concentration in the region 232d and the region 232 e. Therefore, to reduce oxygen vacancies, and V O H in the region 232d and the region 232 e, the carrier concentration can be decreased.
- the action of microwaves, high frequencies such as RF, oxygen plasma, etc. is shielded by the conductors 242a, 242b, and 242c, and the regions 232a and regions. It does not reach 232b and region 232c.
- the action of the oxygen plasma can be reduced by the insulator 275 and the insulator 280 provided overlying the oxide 230b and the conductor 242.
- the side surface of the opening in which the conductor 260 and the like are embedded is substantially perpendicular to the surface to be formed of the oxide 230b, including the groove portion of the oxide 230b. It is not limited to this.
- the bottom of the opening may have a gently curved surface and may have a U-shape.
- the side surface of the opening may be inclined with respect to the surface to be formed of the oxide 230b.
- a curved surface may be provided between the side surface of the oxide 230b and the upper surface of the oxide 230b in a cross-sectional view of the transistor 200 in the channel width direction. That is, the end of the side surface and the end of the upper surface may be curved (hereinafter, also referred to as a round shape).
- the radius of curvature on the curved surface is preferably larger than 0 nm, smaller than the film thickness of the oxide 230b in the region overlapping the conductor 242, or smaller than half the length of the region having no curved surface.
- the radius of curvature on the curved surface is larger than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less.
- the oxide 230 preferably has a laminated structure of a plurality of oxide layers having different chemical compositions.
- the atomic number ratio of the element M to the metal element as the main component is the ratio of the element M to the metal element as the main component in the metal oxide used for the oxide 230b. It is preferably larger than the atomic number ratio.
- the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 230b.
- the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 230a.
- the oxide 230b is preferably an oxide having crystallinity such as CAAC-OS.
- Crystalline oxides such as CAAC-OS have a dense structure with high crystallinity with few impurities and defects (oxygen deficiency, etc.). Therefore, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. As a result, oxygen can be reduced from being extracted from the oxide 230b even if heat treatment is performed, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in the manufacturing process.
- the lower end of the conduction band changes gently.
- the lower end of the conduction band at the junction between the oxide 230a and the oxide 230b is continuously changed or continuously bonded. In order to do so, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b.
- the oxide 230a and the oxide 230b have a common element other than oxygen as a main component, a mixed layer having a low defect level density can be formed.
- the oxide 230b is an In-M-Zn oxide
- the oxide 230a is an In-M-Zn oxide, an M-Zn oxide, an element M oxide, an In-Zn oxide, or an indium oxide. Etc. may be used.
- a metal oxide having a composition in the vicinity thereof may be used.
- a metal oxide having a composition may be used.
- the composition in the vicinity includes a range of ⁇ 30% of the desired atomic number ratio.
- the above atomic number ratio is not limited to the atomic number ratio of the formed metal oxide, but is the atomic number ratio of the sputtering target used for forming the metal oxide. It may be.
- the defect level density at the interface between the oxide 230a and the oxide 230b can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.
- At least one of the insulator 212, the insulator 214, the insulator 275, the insulator 282, and the insulator 283 has impurities such as water and hydrogen diffused into the transistor 200 from the substrate side or from above the transistor 200. It is preferable that it functions as a barrier insulating film that suppresses the above.
- the insulator 212, the insulator 214, the insulator 275, at least one insulator 282, and the insulator 283 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O)
- an insulating material having a function of suppressing the diffusion of impurities such as NO, NO 2
- copper atoms the above impurities are difficult to permeate
- it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen for example, at least one oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate).
- the barrier insulating film refers to an insulating film having a barrier property.
- the barrier property refers to a function of suppressing the diffusion of the corresponding substance (also referred to as low permeability). Alternatively, it refers to the function of capturing and fixing (also called gettering) the corresponding substance.
- the insulator 212, the insulator 214, the insulator 275, the insulator 282, and the insulator 283, for example, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride, or the like is used. be able to.
- the insulator 214, the insulator 275, and the insulator 282 it is preferable to use aluminum oxide having a high function of capturing hydrogen and fixing hydrogen and having a high oxygen barrier property.
- the transistor 200 is surrounded by an insulator 212, an insulator 214, an insulator 275, an insulator 282, and an insulator 283 having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. Is preferable.
- the film formation of the insulator 212, the insulator 214, the insulator 275, the insulator 282, and the insulator 283 may be performed by using, for example, a sputtering method. Since it is not necessary to use hydrogen as the film forming gas in the sputtering method, the hydrogen concentration of the insulator 212, the insulator 214, the insulator 275, the insulator 282, and the insulator 283 can be reduced.
- the film forming method is not limited to the sputtering method, but is limited to a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, and a pulsed laser deposition (PLD: Pulsed Laser Deposition) method. ) Method, atomic layer deposition (ALD: Atomic Layer Deposition) method and the like may be appropriately used.
- the resistivity of the insulator 212 and the insulator 283 is preferably 1 ⁇ 10 10 ⁇ cm or more and 1 ⁇ 10 15 ⁇ cm or less.
- the insulator 216 and the insulator 280 have a lower dielectric constant than the insulator 214.
- a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.
- the conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260. As shown in FIG. 1A, the conductor 205 may be provided so as to extend in the A3-A4 direction. Here, it is preferable that the conductor 205 is embedded in the opening formed in the insulator 216. A part of the conductor 205 may be provided so as to be embedded in the insulator 214.
- the conductor 205 has a conductor 205a, a conductor 205b, and a conductor 205c.
- the conductor 205a is provided in contact with the bottom surface and the side wall of the opening.
- the conductor 205b is provided so as to be embedded in the recess formed in the conductor 205a.
- the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216.
- the conductor 205c is provided in contact with the upper surface of the conductor 205b and the side surface of the conductor 205a.
- the height of the upper surface of the conductor 205c is substantially the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216. That is, the conductor 205b is wrapped in the conductor 205a and the conductor 205c.
- the conductors 205a and conductors 205c are hydrogen atoms, hydrogen molecules, water molecules, nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O, NO, etc. NO 2), the diffusion of impurities such as copper atoms It is preferable to use a conductive material having a suppressing function. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.).
- the conductor 205a and the conductor 205c By using a conductive material having a function of reducing the diffusion of hydrogen for the conductor 205a and the conductor 205c, impurities such as hydrogen contained in the conductor 205b are transferred to the oxide 230 via the insulator 224 and the like. It can be prevented from spreading. Further, by using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 205a and the conductor 205c, it is possible to prevent the conductor 205b from being oxidized and the conductivity from being lowered.
- the conductive material having a function of suppressing the diffusion of oxygen for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used. Therefore, as the conductor 205a and the conductor 205c, the conductive material may be a single layer or a laminate. For example, titanium nitride may be used for the conductor
- the conductor 205b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
- tungsten may be used for the conductor 205b.
- the conductor 205 may function as a second gate electrode.
- the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without interlocking with it.
- Vth threshold voltage
- the electrical resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the film thickness of the conductor 205 is set according to the electrical resistivity. Further, the film thickness of the insulator 216 is almost the same as that of the conductor 205. Here, it is preferable to reduce the film thickness of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205. By reducing the film thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so that the impurities can be reduced from diffusing into the oxide 230. ..
- the conductor 205 may be provided larger than the size of the region that does not overlap with the conductor 242a and the conductor 242b of the oxide 230.
- the conductor 205 is also stretched in a region outside the end where the oxide 230a and the oxide 230b intersect in the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 are superposed on each other via an insulator on the outside of the side surface of the oxide 230 in the channel width direction.
- the channel forming region of the oxide 230 is electrically surrounded by the electric field of the conductor 260 that functions as the first gate electrode and the electric field of the conductor 205 that functions as the second gate electrode. Can be done.
- the structure of the transistor that electrically surrounds the channel formation region by the electric fields of the first gate and the second gate is referred to as a surroundd channel (S-channel) structure.
- the transistor having the S-channel structure represents the structure of the transistor that electrically surrounds the channel formation region by the electric fields of one and the other of the pair of gate electrodes.
- the S-channel structure disclosed in the present specification and the like is different from the Fin type structure and the planar type structure.
- the conductor 205 is stretched to function as wiring.
- the present invention is not limited to this, and a conductor that functions as wiring may be provided under the conductor 205. Further, it is not always necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by a plurality of transistors.
- the conductor 205 may be provided as a single-layer, two-layer, or four-layer or higher laminated structure.
- the conductor 205c may not be provided, and the upper surface of the conductor 205a and the upper surface of the conductor 205b may coincide with each other.
- the conductor 248 may also have a conductor 248a and a conductor 248b arranged inside the conductor 248a.
- a conductor that can be used for the conductor 205a may be used, and a conductor that reduces the permeation of impurities such as water or hydrogen and oxygen is preferable.
- impurities such as water or hydrogen and oxygen
- titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like can be used.
- a conductor having good adhesion to the conductor 248b may be used.
- a conductor that can be used for the conductor 205b may be used, and it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
- the shape of the conductor 248 in FIG. 1A is circular in the top view, but the shape is not limited to this.
- the conductor 248 may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a polygonal shape such as a quadrangle with rounded corners when viewed from above.
- the conductor 248 may be provided as a single layer or a laminated structure having three or more layers.
- a conductor similar to the conductor 205a may be arranged between the upper surface of the conductor 248b and the oxide 230.
- the insulator 249 is provided in contact with the inner wall of the opening of the insulator 212, the insulator 214, the insulator 216, the insulator 222, and the insulator 224, and the conductor 248 is provided in contact with the side surface of the insulator 249. ing.
- the insulator 249 it is preferable to use an insulator that reduces the diffusion of impurities such as hydrogen and water and oxygen, and for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride may be used. As a result, impurities such as water and hydrogen contained in the insulator 216 and the like can be suppressed from being mixed into the oxide 230 through the conductor 248.
- silicon nitride is suitable because it has a high barrier property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 216 from being absorbed by the conductor 248.
- the configuration is not limited to the above, and the insulator 249 may not be provided.
- the insulator 222 and the insulator 224 function as gate insulators.
- the insulator 222 has a function of suppressing the diffusion of hydrogen (for example, at least one hydrogen atom, hydrogen molecule, etc.). Further, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.
- the insulator 222 it is preferable to use an insulator containing oxides of one or both of aluminum and hafnium, which are insulating materials.
- the insulator it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like.
- the insulator 222 releases oxygen from the oxide 230 to the substrate side and diffuses impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Functions as a layer that suppresses.
- the insulator 222 it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and suppress the generation of oxygen deficiency in the oxide 230. Further, it is possible to suppress the conductor 205 from reacting with the oxygen contained in the insulator 224 and the oxide 230.
- aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to the insulator.
- these insulators may be nitrided.
- the insulator 222 may be used by laminating silicon oxide, silicon oxide or silicon nitride on these insulators.
- the insulator 222 includes, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTIO 3 ), (Ba, Sr) TiO 3 (BST) and the like. Insulators containing so-called high-k materials may be used in single layers or in layers. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for an insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
- the insulator 224 in contact with the oxide 230 preferably contains excess oxygen (desorbs oxygen by heating).
- excess oxygen desorbs oxygen by heating
- silicon oxide, silicon oxide nitride, or the like may be appropriately used for the insulator 224.
- an oxide material in which a part of oxygen is desorbed by heating in other words, an insulator material having an excess oxygen region.
- Oxides that desorb oxygen by heating are those in which the amount of desorbed oxygen molecules is 1.0 ⁇ 10 18 molecules / cm 3 or more, preferably 1.0 ⁇ 10 19 molecules, as determined by TDS (Thermal Desorption Spectroscopy) analysis.
- the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
- the heat treatment may be performed, for example, at 100 ° C. or higher and 600 ° C. or lower, more preferably 350 ° C. or higher and 550 ° C. or lower.
- the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
- the heat treatment is preferably performed in an oxygen atmosphere.
- oxygen can be supplied to the oxide 230 to reduce oxygen deficiency ( VO ).
- the heat treatment may be performed in a reduced pressure state.
- the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or an inert gas.
- the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of the oxidizing gas, and then the heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.
- the insulator 222 and the insulator 224 may have a laminated structure of two or more layers.
- the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
- the insulator 224 may be formed in an island shape by superimposing on the oxide 230a. In this case, the insulator 275 is in contact with the side surface of the insulator 224 and the upper surface of the insulator 222.
- Oxide 243a, oxide 243b and oxide 243c are provided on oxide 230b.
- the oxide 243a, the oxide 243b, and the oxide 243c are arranged in the A1-A2 direction, and are provided apart from each other with the conductor 260 interposed therebetween.
- Oxide 243 (oxide 243a, oxide 243b and oxide 243c) preferably has a function of suppressing oxygen permeation.
- the oxide 243 having a function of suppressing the permeation of oxygen between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, electricity between the conductor 242 and the oxide 230b can be obtained. This is preferable because the resistance is reduced. With such a configuration, the electrical characteristics of the transistor 200 and the reliability of the transistor 200 can be improved. If the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, the oxide 243 may not be provided.
- a metal oxide having an element M may be used.
- the element M aluminum, gallium, yttrium, or tin may be used.
- Oxide 243 preferably has a higher concentration of element M than oxide 230b.
- gallium oxide may be used as the oxide 243.
- a metal oxide such as In—M—Zn oxide may be used.
- the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 230b.
- the film thickness of the oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and further preferably 1 nm or more and 2 nm or less. Further, the oxide 243 is preferably crystalline. When the oxide 243 has crystallinity, the release of oxygen in the oxide 230 can be suitably suppressed. For example, as the oxide 243, if it has a crystal structure such as a hexagonal crystal, the release of oxygen in the oxide 230 may be suppressed.
- the conductor 242a is provided in contact with the upper surface of the oxide 243a
- the conductor 242b is provided in contact with the upper surface of the oxide 243b
- the conductor 242c is provided in contact with the upper surface of the oxide 243c.
- the conductor 242a, the conductor 242b, and the conductor 242c are arranged in the A1-A2 direction, and are provided apart from each other with the conductor 260 in between.
- the conductor 242a, the conductor 242b, and the conductor 242c function as a source electrode or a drain electrode of the transistor 200a or the transistor 200b, respectively.
- Examples of the conductor 242 include nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, tantalum and aluminum. It is preferable to use a nitride containing, a nitride containing titanium and aluminum, and the like. In one aspect of the invention, tantalum-containing nitrides are particularly preferred. Further, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxygen is absorbed.
- hydrogen contained in the oxide 230b or the like may diffuse into the conductor 242a, the conductor 242b, and the conductor 242c.
- hydrogen contained in the oxide 230b and the like diffuses into the conductor 242a, the conductor 242b, and the conductor 242c.
- the diffused hydrogen may combine with the nitrogen contained in the conductors 242a, 242b, and 242c. That is, hydrogen contained in the oxide 230b or the like may be absorbed by the conductor 242a, the conductor 242b, and the conductor 242c.
- a curved surface may not be formed between the side surface of the conductor 242 and the upper surface of the conductor 242.
- the insulator 275 is provided so as to cover the insulator 224, the oxide 230, the oxide 243, and the conductor 242, and an opening is formed in the region where the insulator 250 and the conductor 260 are provided.
- the insulator 275 is preferably provided in contact with the upper surface of the insulator 224, the side surface of the oxide 230, the side surface of the oxide 243, the side surface of the conductor 242, and the upper surface of the conductor 242. Further, the insulator 275 preferably functions as a barrier insulating film that suppresses the permeation of oxygen.
- the insulator 275 preferably functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing into the insulator 224 or the oxide 230 from above, and has a function of capturing impurities such as hydrogen. It is preferable to have.
- an insulator such as aluminum oxide or silicon nitride may be used.
- Insulator 280 is provided by providing insulator 275 which has a function of capturing impurities such as hydrogen in contact with insulator 280 and insulator 224 in the region sandwiched between the insulator 212 and the insulator 283. , And impurities such as hydrogen contained in the insulator 224 and the like can be captured, and the amount of hydrogen in the region can be set to a constant value. In this case, it is preferable to use aluminum oxide or the like as the insulator 275.
- the insulator 250 is provided so as to extend in the A3-A4 direction, and functions as a gate insulator for the transistors 200a and the transistors 200b.
- the insulator 250 is arranged in contact with the upper surface and the side surface of the oxide 230b, respectively.
- the insulator 250 includes silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, and the like. Can be used.
- silicon oxide and silicon nitride nitride are preferable because they are stable against heat.
- the insulator 250 preferably has a reduced concentration of impurities such as water and hydrogen in the insulator 250.
- the film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.
- the insulator 250 is shown as a single layer in FIGS. 1B and 1C, it may have a laminated structure of two or more layers.
- the lower layer of the insulator 250 is formed by using an insulator that releases oxygen by heating, and the upper layer of the insulator 250 has a function of suppressing the diffusion of oxygen. It is preferably formed using an insulator having. With such a configuration, oxygen contained in the lower layer of the insulator 250 can be suppressed from diffusing into the conductor 260. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230.
- the lower layer of the insulator 250 can be provided by using a material that can be used for the insulator 250 described above, and the upper layer of the insulator 250 can be provided by using the same material as the insulator 222.
- an insulating material which is a high-k material having a high relative permittivity may be used for the upper layer of the insulator 250.
- the gate insulator By forming the gate insulator into a laminated structure of the lower layer of the insulator 250 and the upper layer of the insulator 250, it is possible to obtain a laminated structure that is stable against heat and has a high relative permittivity. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator.
- the equivalent oxide film thickness (EOT) of an insulator that functions as a gate insulator can be thinned.
- a thing or a metal oxide that can be used as the oxide 230 can be used.
- hafnium oxide may be used as the upper layer of the insulator 250.
- a metal oxide may be provided between the insulator 250 and the conductor 260.
- the metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260.
- the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230.
- the oxidation of the conductor 260 by oxygen of the insulator 250 can be suppressed.
- the metal oxide may be configured to function as a part of the first gate electrode.
- a metal oxide that can be used as the oxide 230 can be used as the metal oxide.
- the electric resistance value of the metal oxide can be lowered to form a conductor. This can be called an OC (Oxide Controller) electrode.
- the metal oxide By having the metal oxide, it is possible to improve the on-current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Further, by keeping the distance between the conductor 260 and the oxide 230 due to the physical thickness of the insulator 250 and the metal oxide, the leakage current between the conductor 260 and the oxide 230 is maintained. Can be suppressed. Further, by providing the insulator 250 and the laminated structure with the metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be determined. It can be easily adjusted as appropriate.
- the conductor 260 is provided so as to extend in the A3-A4 direction, and functions as a first gate electrode of the transistor 200a and the transistor 200b.
- the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a, respectively.
- the conductor 260a is preferably arranged so as to wrap the bottom surface and the side surface of the conductor 260b.
- the upper surface of the conductor 260 substantially coincides with the upper surface of the insulator 250.
- the conductor 260 is shown as a two-layer structure of the conductor 260a and the conductor 260b in FIGS. 1B and 1C, it may be a single-layer structure or a laminated structure of three or more layers.
- the conductor 260a it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule and copper atom.
- impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule and copper atom.
- a conductive material having a function of suppressing the diffusion of oxygen for example, at least one oxygen atom, oxygen molecule, etc.
- the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 260b from being oxidized by the oxygen contained in the insulator 250 to reduce the conductivity.
- the conductive material having a function of suppressing the diffusion of oxygen for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
- the conductor 260 also functions as wiring, it is preferable to use a conductor having high conductivity.
- a conductor having high conductivity for example, as the conductor 260b, a conductive material containing tungsten, copper, or aluminum as a main component can be used.
- the conductor 260b may have a laminated structure, for example, titanium or a laminated structure of titanium nitride and the conductive material.
- the conductor 260 is self-aligned so as to fill the opening formed in the insulator 280 or the like.
- the conductor 260 does not need to be aligned with the region between the conductor 242a and the conductor 242b and the region between the conductor 242b and the conductor 242c. Can be placed.
- the height is preferably lower than the height of the bottom surface of the oxide 230b.
- the conductor 260 which functions as a gate electrode, covers the side surface and the upper surface of the channel forming region of the oxide 230b via the insulator 250, so that the electric field of the conductor 260 is applied to the entire channel forming region of the oxide 230b. It becomes easier to act on. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.
- the difference is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.
- the insulator 280 is provided on the insulator 275, and an opening is formed in a region where the insulator 250 and the conductor 260 are provided. Further, the upper surface of the insulator 280 may be flattened.
- the insulator 280 that functions as an interlayer film preferably has a low dielectric constant.
- a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.
- the insulator 280 is provided by using the same material as the insulator 216, for example.
- silicon oxide and silicon oxide nitride are preferable because they are thermally stable.
- materials such as silicon oxide, silicon oxide nitride, and silicon oxide having pores are preferable because a region containing oxygen desorbed by heating can be easily formed.
- the insulator 280 preferably has an excess oxygen region or excess oxygen. Further, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced.
- the insulator 280 an oxide containing silicon such as silicon oxide and silicon oxide nitride may be appropriately used. By providing an insulator having excess oxygen in contact with the oxide 230, oxygen deficiency in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.
- the insulator 282 is arranged in contact with the upper surfaces of the conductor 260 and the insulator 280, and the uppermost portion of the insulator 250.
- the insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above, and preferably has a function of capturing impurities such as hydrogen. Further, the insulator 282 preferably functions as a barrier insulating film that suppresses the permeation of oxygen.
- an insulator such as aluminum oxide may be used as the insulator 282, for example.
- the insulator 282 which has a function of capturing impurities such as hydrogen in contact with the insulator 280 in the region sandwiched between the insulator 212 and the insulator 283, hydrogen contained in the insulator 280 and the like, etc. Impurities can be captured and the amount of hydrogen in the region can be kept constant.
- the insulator 283 functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing into the insulator 280 from above.
- the insulator 283 is placed on top of the insulator 282.
- a nitride containing silicon such as silicon nitride or silicon nitride oxide.
- silicon nitride formed by a sputtering method may be used as the insulator 283.
- silicon nitride formed by the CVD method may be further laminated on the silicon nitride formed by the sputtering method.
- an insulator substrate for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
- the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria-stabilized zirconia substrate, etc.), a resin substrate, and the like.
- the semiconductor substrate include a semiconductor substrate made of silicon and germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide.
- the conductor substrate includes a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
- a substrate having a metal nitride a substrate having a metal oxide, and the like.
- a substrate in which a conductor or a semiconductor is provided in an insulator substrate a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like.
- those substrates provided with elements may be used.
- Elements provided on the substrate include capacitive elements, resistance elements, switch elements, light emitting elements, storage elements, and the like.
- Insulator examples include oxides, nitrides, oxide nitrides, nitride oxides, metal oxides, metal oxide nitrides, and metal nitride oxides having insulating properties.
- the material may be selected according to the function of the insulator.
- Examples of the insulator having a high specific dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, nitrides having aluminum and hafnium, oxides having silicon and hafnium, silicon and hafnium. There are nitrides having oxides, or nitrides having silicon and hafnium.
- Examples of insulators having a low specific dielectric constant include silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, and empty. There are silicon oxide having holes, resin, and the like.
- the electric characteristics of the transistor can be stabilized by surrounding the transistor using the metal oxide with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen.
- the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulations containing, lanthanum, neodymium, hafnium, or tantalum may be used in single layers or in layers.
- an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen
- Metal oxides such as tantalum oxide and metal nitrides such as aluminum nitride, silicon nitride and silicon nitride can be used.
- the insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating.
- the oxygen deficiency of the oxide 230 can be compensated.
- Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, berylium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like.
- tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. are used. Is preferable.
- tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
- a plurality of conductive layers formed of the above materials may be laminated and used.
- a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined.
- a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined.
- a laminated structure may be formed in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
- the conductor functioning as the gate electrode shall have a laminated structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. Is preferable.
- a conductive material containing oxygen may be provided on the channel forming region side.
- a conductor that functions as a gate electrode it is preferable to use a conductive material containing a metal element and oxygen contained in a metal oxide in which a channel is formed.
- the above-mentioned conductive material containing a metal element and nitrogen may be used.
- a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
- indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
- Indium tin oxide may be used.
- indium gallium zinc oxide containing nitrogen may be used.
- Metal Oxide As the oxide 230, it is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor.
- a metal oxide oxide semiconductor
- the metal oxide applicable to the oxide 230 according to the present invention will be described.
- the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, it is preferable that aluminum, gallium, yttrium, tin and the like are contained. Further, one or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like may be contained.
- the metal oxide is an In-M-Zn oxide having indium, the element M, and zinc.
- the element M may be one or more selected from aluminum, gallium, yttrium, and tin.
- elements applicable to the other element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.
- the element M a plurality of the above-mentioned elements may be combined in some cases.
- a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.
- FIG. 3A is a diagram illustrating the classification of crystal structures of oxide semiconductors, typically IGZO (metal oxides containing In, Ga, and Zn).
- IGZO metal oxides containing In, Ga, and Zn
- oxide semiconductors are roughly classified into “Amorphous (amorphous)”, “Crystalline (crystallinity)", and “Crystal (crystal)”.
- Amorphous includes “completable amorphous”.
- the "Crystalline” includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned crystal) (extracting single crystal crystal).
- single crystal, poly crystal, and single crystal amorphous are excluded from the classification of "Crystalline”.
- “Crystal” includes single crystal and poly crystal.
- the structure in the thick frame shown in FIG. 3A is an intermediate state between "Amorphous” and “Crystal", and belongs to a new boundary region (New crystal line phase). .. That is, the structure can be rephrased as a structure completely different from the energetically unstable "Amorphous” and "Crystal".
- the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Evaluation) spectrum.
- XRD X-ray diffraction
- FIG. 3B the XRD spectrum obtained by GIXD (Glazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline" is shown in FIG. 3B.
- the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
- the XRD spectrum obtained by the GIXD measurement shown in FIG. 3B will be simply referred to as an XRD spectrum.
- the thickness of the CAAC-IGZO film shown in FIG. 3B is 500 nm.
- a peak showing clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film.
- the crystal structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a microelectron beam diffraction pattern) observed by a micro electron beam diffraction method (NBED: Nano Beam Electron Diffraction).
- the diffraction pattern of the CAAC-IGZO film is shown in FIG. 3C.
- FIG. 3C is a diffraction pattern observed by the NBED in which the electron beam is incident parallel to the substrate.
- electron beam diffraction is performed with the probe diameter set to 1 nm.
- oxide semiconductors may be classified differently from FIG. 3A.
- oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
- the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS.
- the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.
- CAAC-OS CAAC-OS
- nc-OS nc-OS
- a-like OS the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.
- CAAC-OS is an oxide semiconductor having a plurality of crystal regions, the plurality of crystal regions having the c-axis oriented in a specific direction.
- the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film.
- the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region in which the lattice arrangement is aligned. Further, the CAAC-OS has a region in which a plurality of crystal regions are connected in the ab plane direction, and the region may have distortion.
- the strain refers to a region in which a plurality of crystal regions are connected in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another grid arrangement is aligned.
- CAAC-OS is an oxide semiconductor that is c-axis oriented and not clearly oriented in the ab plane direction.
- Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
- the maximum diameter of the crystal region is less than 10 nm.
- the size of the crystal region may be about several tens of nm.
- CAAC-OS has indium (In) and oxygen. It tends to have a layered crystal structure (also referred to as a layered structure) in which a layer (hereinafter, In layer) and a layer having elements M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are laminated. There is. Indium and element M can be replaced with each other. Therefore, the (M, Zn) layer may contain indium. In addition, the In layer may contain the element M. In addition, Zn may be contained in the In layer.
- the layered structure is observed as a lattice image in, for example, a high-resolution TEM image.
- the position of the peak indicating the c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.
- a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that a certain spot and another spot are observed at point-symmetrical positions with the spot of the incident electron beam passing through the sample (also referred to as a direct spot) as the center of symmetry.
- the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit lattice is not limited to a regular hexagon and may be a non-regular hexagon. Further, in the above strain, it may have a lattice arrangement such as a pentagon or a heptagon.
- a clear grain boundary cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the replacement of metal atoms. It is thought that this is the reason.
- CAAC-OS for which no clear crystal grain boundary is confirmed, is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor.
- a configuration having Zn is preferable.
- In-Zn oxide and In-Ga-Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
- CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries. Further, since the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures in the manufacturing process (so-called thermal budget). Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
- nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
- nc-OS has tiny crystals. Since the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also referred to as a nanocrystal.
- nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
- the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method.
- a peak indicating crystallinity is not detected in the Out-of-plane XRD measurement using a ⁇ / 2 ⁇ scan.
- electron beam diffraction also referred to as limited field electron diffraction
- a diffraction pattern such as a halo pattern is performed. Is observed.
- electron beam diffraction also referred to as nanobeam electron diffraction
- an electron beam having a probe diameter for example, 1 nm or more and 30 nm or less
- An electron diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be acquired.
- the a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.
- the a-like OS has a void or low density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.
- a-like OS has a higher hydrogen concentration in the membrane than nc-OS and CAAC-OS.
- CAC-OS relates to the material composition.
- CAC-OS is, for example, a composition of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
- the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
- the mixed state is also called a mosaic shape or a patch shape.
- CAC-OS has a structure in which the material is separated into a first region and a second region to form a mosaic shape, and the first region is distributed in the membrane (hereinafter, also referred to as a cloud shape). It says.). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
- the atomic number ratios of In, Ga, and Zn with respect to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively.
- the first region is a region in which [In] is larger than [In] in the composition of the CAC-OS film.
- the second region is a region in which [Ga] is larger than [Ga] in the composition of the CAC-OS film.
- the first region is a region in which [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
- the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
- the first region is a region in which indium oxide, indium zinc oxide, or the like is the main component.
- the second region is a region in which gallium oxide, gallium zinc oxide, or the like is the main component. That is, the first region can be rephrased as a region containing In as a main component. Further, the second region can be rephrased as a region containing Ga as a main component.
- a region containing In as a main component (No. 1) by EDX mapping acquired by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region (1 region) and the region containing Ga as a main component (second region) have a structure in which they are unevenly distributed and mixed.
- EDX Energy Dispersive X-ray spectroscopy
- CAC-OS When CAC-OS is used for a transistor, the conductivity caused by the first region and the insulating property caused by the second region act in a complementary manner to switch the switching function (On / Off function). Can be added to the CAC-OS. That is, the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS as a transistor, high on-current ( Ion ), high field effect mobility ( ⁇ ), and good switching operation can be realized.
- Ion on-current
- ⁇ high field effect mobility
- Oxide semiconductors have various structures, and each has different characteristics.
- the oxide semiconductor according to one aspect of the present invention has two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS. You may.
- the oxide semiconductor as a transistor, a transistor with high field effect mobility can be realized. Moreover, a highly reliable transistor can be realized.
- the carrier concentration in the channel formation region of the oxide semiconductor is preferably 1 ⁇ 10 18 cm -3 or less, more preferably less than 1 ⁇ 10 17 cm -3 , and 1 ⁇ 10 16 cm -3. It is more preferably less than 1 ⁇ 10 13 cm -3 , even more preferably less than 1 ⁇ 10 12 cm -3 .
- the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
- a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
- An oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
- the trap level density may also be low.
- the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel forming region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.
- Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
- the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon near the interface with the channel formation region of the oxide semiconductor is 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
- the oxide semiconductor contains an alkali metal or an alkaline earth metal
- a defect level may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less. ..
- the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms. / Cm 3 or less, more preferably 5 ⁇ 10 17 atoms / cm 3 or less.
- hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency.
- oxygen deficiency When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated.
- a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the channel forming region of the oxide semiconductor is reduced as much as possible.
- the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 5 ⁇ 10 19 atoms / cm 3 , more preferably 1 ⁇ 10. It should be less than 19 atoms / cm 3 , more preferably less than 5 ⁇ 10 18 atoms / cm 3 , and even more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
- the semiconductor material that can be used for the oxide 230 is not limited to the above-mentioned metal oxide.
- a semiconductor material having a bandgap (a semiconductor material that is not a zero-gap semiconductor) may be used.
- a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, and a layered substance (also referred to as an atomic layer substance or a two-dimensional material) that functions as a semiconductor as a semiconductor material.
- a layered substance that functions as a semiconductor as a semiconductor material it is preferable to use a layered substance that functions as a semiconductor as a semiconductor material.
- the layered substance is a general term for a group of materials having a layered crystal structure.
- a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are laminated via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces.
- the layered material has high electrical conductivity in the unit layer, that is, high two-dimensional electrical conductivity.
- a chalcogenide is a compound containing a chalcogen.
- chalcogen is a general term for elements belonging to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
- Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides.
- oxide 230 for example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor.
- Specific transition metal chalcogenides applicable as oxide 230 include molybdenum sulfide (typically MoS 2 ), molybdenum selenate (typically MoSe 2 ), and molybdenum tellurium (typically MoTe 2 ).
- Tungsten sulfide typically WS 2
- Tungsten disulfide typically WSe 2
- Tungsten tellurium typically WTe 2
- Hafnium sulfide typically HfS 2
- Hafnium serene typically typically
- Typical examples include HfSe 2 ), zirconium sulfide (typically ZrS 2 ), and zirconium selenium (typically ZrSe 2 ).
- FIGS. 1A to 1D the method of manufacturing the semiconductor device according to one aspect of the present invention shown in FIGS. 1A to 1D is shown in FIGS. 4A to 12A, 4B to 12B, 4C to 12C, and 4D to 12D. It will be described using.
- FIGS. 4A to 12A shows a top view.
- each of FIGS. 4B to 12B is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in FIGS. 4A to 12A, and is also a cross-sectional view of the transistor 200a and the transistor 200b in the channel length direction.
- each of FIGS. 4C to 12C is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line in FIGS. 4A to 12A, and is also a cross-sectional view of the transistor 200a in the channel width direction.
- 4D to 12D is a cross-sectional view of a portion shown by a alternate long and short dash line of A5-A6 in FIGS. 4A to 12A.
- FIGS. 4A to 12A In the top views of FIGS. 4A to 12A, some elements are omitted for the purpose of clarifying the drawings.
- the insulating material for forming an insulator, the conductive material for forming a conductor, or the semiconductor material for forming a semiconductor is a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Etc. can be used as appropriate to form a film.
- the sputtering method includes an RF sputtering method that uses a high-frequency power source as a sputtering power source, a DC sputtering method that uses a DC power source, and a pulse DC sputtering method that changes the voltage applied to the electrodes in a pulsed manner.
- the RF sputtering method is mainly used when forming an insulating film
- the DC sputtering method is mainly used when forming a metal conductive film.
- the pulse DC sputtering method is mainly used when a compound such as an oxide, a nitride, or a carbide is formed into a film by the reactive sputtering method.
- the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, an optical CVD (Photo CVD) method using light, and the like. .. Further, depending on the raw material gas used, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal organic CVD) method.
- PECVD Plasma Enhanced CVD
- TCVD Thermal CVD
- Photo CVD Photo CVD
- MCVD Metal CVD
- the plasma CVD method can obtain a high quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film forming method capable of reducing plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) and the like included in a semiconductor device may be charged up by receiving electric charges from plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased. Further, in the thermal CVD method, plasma damage does not occur during film formation, so that a film having few defects can be obtained.
- a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactor is performed only by thermal energy, a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactor, or the like can be used.
- the ALD method utilizes the self-regulating properties of atoms and allows atoms to be deposited layer by layer, so ultra-thin film formation is possible, and film formation into structures with a high aspect ratio is possible. It has the effects of being able to form a film with few defects such as holes, being able to form a film with excellent coverage, and being able to form a film at a low temperature.
- the PEALD method it may be preferable to use plasma because it is possible to form a film at a lower temperature.
- Some precursors used in the ALD method contain impurities such as carbon. Therefore, the film provided by the ALD method may contain a large amount of impurities such as carbon as compared with the film provided by other film forming methods.
- the quantification of impurities can be performed by using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).
- the CVD method and the ALD method are different from the film forming method in which particles emitted from a target or the like are deposited, and are film forming methods in which a film is formed by a reaction on the surface of an object to be treated. Therefore, it is a film forming method that is not easily affected by the shape of the object to be treated and has good step coverage.
- the ALD method has excellent step covering property and excellent thickness uniformity, and is therefore suitable for covering the surface of an opening having a high aspect ratio.
- the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method having a high film formation rate.
- the composition of the obtained film can be controlled by the flow rate ratio of the raw material gas.
- a film having an arbitrary composition can be formed depending on the flow rate ratio of the raw material gas.
- a film having a continuously changed composition can be formed by changing the flow rate ratio of the raw material gas while forming the film.
- a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate (see FIGS. 4A to 4D).
- the film formation of the insulator 212 is preferably performed by using a sputtering method.
- a sputtering method that does not require hydrogen to be used as the film-forming gas, the hydrogen concentration in the insulator 212 can be reduced.
- the film formation of the insulator 212 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be appropriately used.
- silicon nitride is formed as the insulator 212 by the pulse DC sputtering method using a silicon target in an atmosphere containing nitrogen gas.
- the pulse DC sputtering method it is possible to suppress the generation of particles due to the arcing of the target surface, so that the film thickness distribution can be made more uniform.
- the pulse voltage the rise and fall of the discharge can be made steeper than the high frequency voltage. As a result, electric power can be supplied to the electrodes more efficiently to improve the sputtering rate and film quality.
- an insulator such as silicon nitride that is difficult for impurities such as water and hydrogen to permeate it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212. Further, by using an insulator such as silicon nitride that does not easily allow copper to permeate as the insulator 212, even if a metal such as copper that easily diffuses is used for the conductor in the layer below the insulator 212 (not shown), the metal is used. Can be suppressed from diffusing upward through the insulator 212.
- the insulator 214 is formed on the insulator 212 (see FIGS. 4A to 4D).
- the film formation of the insulator 214 is preferably performed by using a sputtering method.
- a sputtering method that does not require hydrogen to be used as the film-forming gas, the hydrogen concentration in the insulator 214 can be reduced.
- the film formation of the insulator 214 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be appropriately used.
- aluminum oxide is formed as the insulator 214 by the pulse DC sputtering method using an aluminum target in an atmosphere containing oxygen gas.
- the pulse DC sputtering method By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
- the insulator 216 is formed on the insulator 214.
- the film formation of the insulator 216 is preferably performed by using a sputtering method.
- a sputtering method that does not require hydrogen to be used as the film-forming gas, the hydrogen concentration in the insulator 216 can be reduced.
- the film formation of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be appropriately used.
- silicon oxide is formed as the insulator 216 by a pulse DC sputtering method using a silicon target in an atmosphere containing oxygen gas.
- the pulse DC sputtering method By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
- the insulator 212, the insulator 214, and the insulator 216 are continuously formed without being exposed to the atmosphere.
- a multi-chamber type film forming apparatus may be used.
- the insulator 212, the insulator 214, and the insulator 216 are formed by reducing the amount of hydrogen in the film, and further, the amount of hydrogen mixed in the film between the film forming steps is reduced. Can be done.
- the insulator 216 is formed by extending two openings reaching the insulator 214 in the A3-A4 direction.
- the opening also includes, for example, a groove and a slit.
- the area where the opening is formed may be referred to as the opening.
- Wet etching may be used to form the openings, but dry etching is preferable for microfabrication.
- the insulator 214 it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove.
- silicon oxide or silicon oxide nitride is used for the insulator 216 forming the groove
- silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214.
- a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate type electrodes can be used.
- the capacitively coupled plasma etching apparatus having the parallel plate type electrodes may be configured to apply a high frequency voltage to one of the parallel plate type electrodes.
- a plurality of different high frequency voltages may be applied to one of the parallel plate type electrodes.
- a high frequency voltage having the same frequency may be applied to each of the parallel plate type electrodes.
- a high frequency voltage having a different frequency may be applied to each of the parallel plate type electrodes.
- a dry etching apparatus having a high-density plasma source can be used.
- an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching apparatus or the like can be used.
- the conductive film to be the conductor 205a preferably contains a conductor having a function of suppressing the permeation of oxygen.
- a conductor having a function of suppressing the permeation of oxygen for example, tantalum nitride, tungsten nitride, titanium nitride and the like can be used. Alternatively, it can be a laminated film of a conductor having a function of suppressing oxygen permeation and a tantalum, tungsten, titanium, molybdenum, aluminum, copper or molybdenum tungsten alloy.
- the film formation of the conductive film to be the conductor 205a can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- titanium nitride is formed as a conductive film to be the conductor 205a.
- a metal nitride as the lower layer of the conductor 205b, it is possible to suppress the oxidation of the conductor 205b by the insulator 216 or the like. Further, even if a metal such as copper that easily diffuses is used as the conductor 205b, it is possible to prevent the metal from diffusing out from the conductor 205a.
- a conductive film to be the conductor 205b is formed.
- the conductive film serving as the conductor 205b tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy or the like can be used.
- the film formation of the conductive film can be performed by using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- tungsten is formed as a conductive film to be the conductor 205b.
- a part of the conductive film to be the conductor 205a and a part of the conductive film to be the conductor 205b is removed, and the insulator 216 is exposed.
- the conductor 205a and the conductor 205b remain only in the opening.
- a part of the insulator 216 may be removed by the CMP treatment.
- etching is performed to remove the upper part of the conductor 205b.
- the upper surface of the conductor 205b becomes lower than the upper surface of the conductor 205a and the upper surface of the insulator 216.
- Dry etching or wet etching may be used for etching the conductor 205b, but it is preferable to use dry etching for microfabrication.
- a conductive film to be the conductor 205c is formed on the insulator 216, the conductor 205a, and the conductor 205b. It is desirable that the conductive film to be the conductor 205c contains a conductor having a function of suppressing the permeation of oxygen, similarly to the conductive film to be the conductor 205a.
- titanium nitride is formed as a conductive film to be the conductor 205c.
- a metal nitride as the upper layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 222 or the like. Further, even if a metal that easily diffuses such as copper is used as the conductor 205b, it is possible to prevent the metal from diffusing out from the conductor 205c.
- impurities such as hydrogen are prevented from diffusing from the conductor 205b to the outside of the conductor 205a and the conductor 205c, and oxygen is mixed from the outside of the conductor 205a and the conductor 205c to oxidize the conductor 205b. Can be prevented.
- a part of the insulator 216 may be removed by the CMP treatment.
- the insulator 222 is formed on the insulator 216 and the conductor 205.
- an insulator containing an oxide of one or both of aluminum and hafnium may be formed.
- the insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and the like. Insulators containing oxides of one or both of aluminum and hafnium have barrier properties against oxygen, hydrogen, and water.
- the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in the structure provided around the transistor 200 are suppressed from diffusing into the inside of the transistor 200 through the insulator 222. , The formation of oxygen deficiency in the oxide 230 can be suppressed.
- the film formation of the insulator 222 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- hafnium oxide is formed as the insulator 222 by using a sputtering method.
- a sputtering method that does not require hydrogen to be used as the film-forming gas, the hydrogen concentration in the insulator 222 can be reduced.
- the heat treatment may be carried out at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, and more preferably 320 ° C. or higher and 450 ° C. or lower.
- the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
- the oxygen gas may be set to about 20%.
- the heat treatment may be performed in a reduced pressure state.
- the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then the heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement the desorbed oxygen. You may.
- the gas used in the above heat treatment is preferably highly purified.
- the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
- the flow rate ratio of nitrogen gas and oxygen gas is set to 4 slm: 1 slm, and the treatment is performed at a temperature of 400 ° C. for 1 hour.
- impurities such as water and hydrogen contained in the insulator 222 can be removed.
- the heat treatment can be performed at a timing such as after the film formation of the insulator 224 is performed.
- the insulator 224 is formed on the insulator 222.
- the film formation of the insulator 224 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- silicon oxide is formed as the insulator 224 by using a sputtering method.
- a sputtering method that does not require hydrogen to be used as the film-forming gas, the hydrogen concentration in the insulator 224 can be reduced. Since the insulator 224 comes into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this way.
- openings are formed in the insulator 224, the insulator 222, the insulator 216, the insulator 214, and the insulator 212.
- the opening is formed between the two conductors 205. Wet etching may be used to form the openings, but dry etching is preferable for microfabrication.
- the shape of the opening is circular in the top view, but the shape is not limited to this.
- the opening may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a polygonal shape such as a quadrangle with rounded corners in a top view.
- an insulating film to be the insulator 249 is formed, and the insulating film is anisotropically etched to form the insulator 249.
- the film formation of the insulating film to be the insulator 249 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- As the insulating film to be the insulator 249 it is preferable to use an insulating film having a function of reducing oxygen permeation. For example, it is preferable to form an aluminum oxide film by using the ALD method. Alternatively, it is preferable to form silicon nitride by using the PEALD method. Silicon nitride is preferable because it has a high barrier property against hydrogen.
- the anisotropic etching of the insulating film to be the insulator 249 for example, a dry etching method or the like may be used.
- a dry etching method or the like By providing the insulator 249 on the side wall portion of the opening, it is possible to reduce the permeation of oxygen from the outside and prevent the oxidation of the conductor 248 to be formed next. Further, it is possible to prevent impurities such as water and hydrogen from entering the conductor 248 from the outside.
- a conductive film to be a conductor 248 is formed.
- the film formation of the conductive film to be the conductor 248 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the conductor 248 is formed in the same structure as the conductor 205. Therefore, if the conductive film to be the conductor 248a is formed by the same method as the conductive film to be the conductor 205a, and the conductive film to be the conductor 248b is formed by the same method as the conductive film to be the conductor 205b. Good.
- plasma treatment containing oxygen may be performed in a reduced pressure state.
- the plasma treatment containing oxygen for example, it is preferable to use an apparatus having a power source for generating high-density plasma using microwaves.
- the substrate side may have a power supply for applying RF (Radio Frequency).
- RF Radio Frequency
- high-density plasma high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224. it can.
- plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, the heat treatment does not have to be performed.
- CMP treatment may be performed until the insulator 224 is reached.
- the surface of the insulator 224 can be flattened and smoothed.
- a part of the insulator 224 may be polished by the CMP treatment to reduce the film thickness of the insulator 224, but the film thickness may be adjusted when the insulator 224 is formed.
- oxygen can be added to the insulator 224 by forming aluminum oxide on the insulator 224 by a sputtering method.
- the oxide film 230A and the oxide film 230B are formed on the insulator 224 and the conductor 248 in this order (see FIGS. 6A to 6D). It is preferable that the oxide film 230A and the oxide film 230B are continuously formed without being exposed to the atmospheric environment. By forming the film without opening it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.
- the oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the oxide film 230A and the oxide film 230B are formed by a sputtering method
- oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas.
- excess oxygen in the oxide film formed can be increased.
- the above oxide film is formed by a sputtering method
- the above In—M—Zn oxide target or the like can be used.
- the proportion of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.
- the oxide film 230B is formed by a sputtering method, if the ratio of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, the oxygen excess type oxidation A physical semiconductor is formed. Transistors using oxygen-rich oxide semiconductors in the channel formation region can obtain relatively high reliability. However, one aspect of the present invention is not limited to this.
- the oxide film 230B is formed by a sputtering method and the ratio of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. To. A transistor using an oxygen-deficient oxide semiconductor in the channel formation region can obtain a relatively high field-effect mobility. Further, the crystallinity of the oxide film can be improved by forming a film while heating the substrate.
- an oxide film 243A is formed on the oxide film 230B (see FIGS. 6A to 6D).
- the oxide film 243A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the atomic number ratio of Ga to In is preferably larger than the atomic number ratio of Ga to In in the oxide film 230B.
- the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A are formed by a sputtering method without being exposed to the atmosphere.
- a multi-chamber type film forming apparatus may be used.
- the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A are formed by reducing the hydrogen in the film, and further, hydrogen is formed in the film between each film forming step. Can be reduced.
- the heat treatment may be performed in a temperature range in which the oxide film 230A, the oxide film 230B, and the oxide film 243A do not polycrystallize, and may be performed at 250 ° C. or higher and 650 ° C. or lower, preferably 400 ° C. or higher and 600 ° C. or lower.
- the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
- the oxygen gas may be set to about 20%.
- the heat treatment may be performed in a reduced pressure state.
- the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then the heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement the desorbed oxygen. You may.
- the gas used in the above heat treatment is preferably highly purified.
- the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
- the treatment after performing the treatment at a temperature of 550 ° C. for 1 hour in a nitrogen atmosphere, the treatment is continuously performed at a temperature of 550 ° C. for 1 hour in an oxygen atmosphere.
- impurities such as water and hydrogen in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be removed.
- the heat treatment can improve the crystallinity of the oxide film 230B to obtain a denser and more dense structure. Thereby, the diffusion of oxygen or impurities in the oxide film 230B can be reduced.
- a conductive film 242A is formed on the oxide film 243A (see FIGS. 6A to 6D).
- the film formation of the conductive film 242A can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a sputtering method for example, as the conductive film 242A, tantalum nitride may be formed by using a sputtering method.
- the heat treatment may be performed before the film formation of the conductive film 242A.
- the heat treatment may be carried out under reduced pressure to continuously form a conductive film 242A without exposing it to the atmosphere.
- the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower. In the present embodiment, the temperature of the heat treatment is set to 200 ° C.
- the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are processed into an island shape by using a lithography method to form an oxide 230a, an oxide 230b, an oxide layer 243B, and a conductive layer 242B.
- a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for microfabrication.
- the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A may be processed under different conditions. In this step, the film thickness of the region that does not overlap with the oxide 230a of the insulator 224 may be reduced. Further, in the step, the insulator 224 may be superposed on the oxide 230a and processed into an island shape.
- the resist is first exposed through a mask. Next, the exposed region is removed or left with a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask.
- a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, instead of the above-mentioned light, an electron beam or an ion beam may be used.
- the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
- a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
- a hard mask made of an insulator or a conductor may be used under the resist mask.
- a hard mask an insulating film or a conductive film to be a hard mask material is formed on the conductive film 242A, a resist mask is formed on the insulating film or a conductive film, and the hard mask material is etched to form a hard mask having a desired shape. can do.
- Etching of the conductive film 242A or the like may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching.
- the hard mask may be removed by etching after etching the conductive film 242A or the like.
- the material of the hard mask does not affect the post-process or can be used in the post-process, it is not always necessary to remove the hard mask.
- the hard mask may remain and be used as a barrier insulating film.
- the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are formed so that at least a part thereof overlaps with the conductor 248 and the two conductors 205. Further, it is preferable that the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are substantially perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are substantially perpendicular to the upper surface of the insulator 222, the area is reduced and the height is increased when a plurality of transistors 200 are provided. It is possible to increase the density.
- the angle formed by the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B and the upper surface of the insulator 222 may be low.
- the angle formed by the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B and the upper surface of the insulator 222 is preferably 60 degrees or more and less than 70 degrees.
- the by-products generated in the etching step may be formed in layers on the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B.
- the layered by-product will be formed between the oxide 230a, the oxide 230b, the oxide 243, and the conductor 242 and the insulator 275.
- layered by-products may be formed on the insulator 224. Even if the insulator 275 is formed in a state where the layered by-product is formed on the insulator 224, the layered by-product interferes with the addition of oxygen to the insulator 224. Therefore, it is preferable to remove the layered by-product formed in contact with the upper surface of the insulator 224.
- the insulator 275 is formed on the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B. (See FIGS. 8A-8D.).
- the film formation of the insulator 275 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- As the insulator 275 it is preferable to use an insulating film having a function of suppressing the permeation of oxygen.
- aluminum oxide may be deposited as the insulator 275 by the ALD method or the sputtering method.
- silicon nitride may be formed into a film by a sputtering method.
- Oxygen can be added to the insulator 224 by forming the insulator 275 by the sputtering method.
- an insulating film to be the insulator 280 is formed on the insulator 275.
- the film formation of the insulating film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a silicon oxide film may be formed by using a sputtering method.
- An insulator 280 containing excess oxygen can be formed by forming an insulating film to be an insulator 280 by a sputtering method in an atmosphere containing oxygen. Further, by using a sputtering method in which hydrogen does not have to be used as the film forming gas, the hydrogen concentration in the insulator 280 can be reduced.
- heat treatment may be performed before the film formation of the insulating film.
- the heat treatment may be carried out under reduced pressure to continuously form the insulating film without exposing it to the atmosphere.
- water and hydrogen adsorbed on the surface of the insulator 275 and the like are removed, and further, the water concentration and the water concentration in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224 are obtained.
- the hydrogen concentration can be reduced.
- the above-mentioned heat treatment conditions can be used for the heat treatment.
- the insulating film to be the insulator 280 is subjected to CMP treatment to form an insulator 280 having a flat upper surface (see FIGS. 8A to 8D).
- silicon nitride may be formed on the insulator 280 by, for example, a sputtering method, and the silicon nitride may be subjected to CMP treatment until it reaches the insulator 280.
- the insulator 280 two parts of the insulator 280, a part of the insulator 275, a part of the conductive layer 242B, a part of the oxide layer 243B, and a part of the oxide 230b are removed to reach the oxide 230b.
- Form an opening It is preferable that the two openings are formed so as to overlap the conductor 205.
- a conductor 242a, a conductor 242b, a conductor 242c, an oxide 243a, an oxide 243b, and an oxide 243c are formed (see FIGS. 9A to 9D).
- the conductor 242b is preferably formed so as to be superimposed on the conductor 248. Further, the region of the oxide 230b that does not overlap with the conductor 242a, the conductor 242b, and the conductor 242c is exposed.
- the upper part of the oxide 230b is removed.
- a groove is formed in the oxide 230b.
- the groove may be formed in the opening forming step, or may be formed in a step different from the opening forming step.
- a dry etching method or a wet etching method is used for processing a part of the insulator 280, a part of the insulator 275, a part of the conductive layer 242B, a part of the oxide layer 243B, and a part of the oxide 230b.
- a dry etching method or a wet etching method is used for processing a part of the insulator 280, a part of the insulator 275, a part of the conductive layer 242B, a part of the oxide layer 243B, and a part of the oxide 230b.
- a part may be processed by a dry etching method.
- a dry etching method first, two openings are formed in the insulator 280, and the openings are formed in the insulator 275, the oxide layer 243B, and the conductive layer 242B by superimposing on the two openings. Further, the processing of a part of the oxide layer 243B and a part of the conductive layer 242B and the processing of a part of the oxide 230b may be performed under different conditions.
- the impurities include the components contained in the insulator 280, the insulator 275 and the conductive layer 242B, the components contained in the member used in the apparatus used for forming the opening, and the gas or liquid used for etching. Examples include those caused by the contained components and the like. Examples of the impurities include aluminum, silicon, tantalum, fluorine, chlorine and the like.
- impurities such as aluminum or silicon inhibit the conversion of oxide 230b to CAAC-OS. Therefore, it is preferable that impurity elements such as aluminum and silicon that inhibit CAAC-OS conversion are reduced or removed.
- the concentration of aluminum atoms in the oxide 230b and its vicinity may be 5.0 atomic% or less, preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, and 1.0. It is more preferably atomic% or less, still more preferably less than 0.3 atomic%.
- the region of the metal oxide that has become a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor) due to the inhibition of CAAC-OS by impurities such as aluminum or silicon is defined as the non-CAAC region. May be called.
- the non CAAC region since the compactness of the crystal structure is reduced, V O H has a large amount of formation, the transistor tends to be normally on reduction. Therefore, the non-CAAC region of the oxide 230b is preferably reduced or removed.
- the oxide 230b has a layered CAAC structure.
- the conductor 242a, the conductor 242b, or the conductor 242c, and the vicinity thereof function as a drain. That is, it is preferable that the conductor 242a, the conductor 242b, or the oxide 230b near the lower end of the conductor 242c has a CAAC structure.
- the damaged region of the oxide 230b is removed, and by having the CAAC structure, the fluctuation of the electrical characteristics of the transistor 200 can be further suppressed. Moreover, the reliability of the transistor 200 can be improved.
- the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleanings may be appropriately combined.
- the cleaning treatment may deepen the groove.
- the cleaning treatment may be performed using an aqueous solution obtained by diluting ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid or the like with carbonated water or pure water, pure water, carbonated water or the like.
- ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water.
- these washings may be appropriately combined.
- a commercially available aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid
- a commercially available aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water.
- concentration, temperature, etc. of the aqueous solution may be appropriately adjusted depending on the impurities to be removed, the configuration of the semiconductor device to be washed, and the like.
- the ammonia concentration of the diluted ammonia water may be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less.
- the hydrogen fluoride concentration of the diluted hydrofluoric acid may be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.
- a frequency of 200 kHz or higher, preferably 900 kHz or higher for ultrasonic cleaning it is preferable to use a frequency of 200 kHz or higher, preferably 900 kHz or higher for ultrasonic cleaning. By using this frequency, damage to the oxide 230b and the like can be reduced.
- the above cleaning treatment may be performed a plurality of times, and the cleaning liquid may be changed for each cleaning treatment.
- a treatment using diluted hydrofluoric acid or diluted aqueous ammonia may be performed as the first cleaning treatment
- a treatment using pure water or carbonated water may be performed as the second cleaning treatment.
- wet cleaning is performed using diluted hydrofluoric acid, and then wet cleaning is performed using pure water or carbonated water.
- impurities adhering to or diffused inside the surface such as oxide 230a and oxide 230b can be removed.
- the crystallinity of the oxide 230b can be enhanced.
- the heat treatment may be performed after the etching or the cleaning.
- the heat treatment may be performed at 100 ° C. or higher and 450 ° C. or lower, preferably 350 ° C. or higher and 400 ° C. or lower.
- the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
- the heat treatment is preferably performed in an oxygen atmosphere.
- oxygen is supplied to the oxide 230a and oxides 230b, it is possible to reduce the oxygen vacancies V O. Further, by performing such a heat treatment, the crystallinity of the oxide 230b can be improved.
- the heat treatment may be performed in a reduced pressure state.
- the heat treatment may be continuously performed in a nitrogen atmosphere without being exposed to the atmosphere.
- an insulating film 250A is formed (see FIGS. 10A to 10D).
- the heat treatment may be performed before the film formation of the insulating film 250A, and the heat treatment may be performed under reduced pressure to continuously form the insulating film 250A without exposure to the atmosphere. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, the water and hydrogen adsorbed on the surface of the oxide 230b and the like can be removed, and the water concentration and the hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced.
- the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower.
- the insulating film 250A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the insulating film 250A is preferably formed by a film forming method using a gas in which hydrogen atoms have been reduced or removed. Thereby, the hydrogen concentration of the insulating film 250A can be reduced. Since the insulating film 250A becomes an insulator 250 in contact with the oxide 230b in a later step, it is preferable that the hydrogen concentration is reduced in this way.
- the insulating film 250A is formed by using the ALD method. It is necessary that the film thickness of the insulator 250 of the miniaturized transistor 200, which functions as the gate insulating film, is extremely thin (for example, about 5 nm or more and 30 nm or less) and the variation is small.
- the ALD method is a film-forming method in which a precursor and a reactor (oxidizing agent) are alternately introduced, and the film thickness can be adjusted by the number of times this cycle is repeated, so that the film thickness is precise. It can be adjusted. Therefore, the accuracy of the thickness of the gate insulating film required by the miniaturized transistor 200 can be achieved. Further, as shown in FIGS.
- the insulating film 250A needs to be formed on the bottom surface and the side surface of the opening formed by the insulator 280 or the like with good coverage. Since layers of atoms can be deposited layer by layer on the bottom surface and the side surface of the opening, the insulating film 250A can be formed with good coverage on the opening.
- the film-forming gas containing hydrogen is decomposed in the plasma and a large amount of hydrogen radicals are generated.
- the reduction reaction of hydrogen radicals the oxygen is withdrawn by V O H in the oxide 230b is formed, the concentration of hydrogen in the oxide 230b is increased.
- the insulating film 250A is formed by using the ALD method, the generation of hydrogen radicals can be suppressed both when the precursor is introduced and when the reactor is introduced. Therefore, by forming the insulating film 250A using the ALD method, it is possible to prevent the hydrogen concentration in the oxide 230b from increasing.
- a silicon oxide film such as silicon oxide may be formed by using the ALD method.
- the insulating film 250A is shown as a single layer in FIGS. 10B, 10C, and 10D, it may have a laminated structure of two or more layers.
- the lower layer of the insulating film 250A is formed by using an insulator that releases oxygen by heating, and the upper layer of the insulating film 250A has a function of suppressing the diffusion of oxygen. It is preferable to form using an insulator having. With such a configuration, oxygen contained in the lower layer of the insulator 250 can be suppressed from diffusing into the conductor 260. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230.
- the lower layer of the insulating film 250A can be provided by using a material that can be used for the insulator 250 described above, and the upper layer of the insulating film 250A can be provided by using the same material as the insulator 222.
- a thing or a metal oxide that can be used as the oxide 230 can be used.
- the insulating film 250A has a two-layer laminated structure, silicon oxide is formed as a lower layer by the PEALD method, and hafnium oxide is formed as an upper layer by the thermal ALD method.
- the insulating film that is the lower layer of the insulating film 250A and the insulating film that is the upper layer of the insulating film 250A should be continuously formed without being exposed to the atmospheric environment. Is preferable.
- impurities such as hydrogen or moisture from the atmospheric environment from adhering to the insulating film that is the lower layer of the insulating film 250A and the insulating film that is the upper layer of the insulating film 250A.
- the vicinity of the interface between the insulating film that is the lower layer of the insulating film 250A and the insulating film that is the upper layer of the insulating film 250A can be kept clean.
- microwave treatment is performed in an atmosphere containing oxygen (see FIGS. 10A to 10D).
- the dotted lines shown in FIGS. 10B, 10C, and 10D indicate microwaves, high frequencies such as RF, oxygen plasma, oxygen radicals, and the like.
- the microwave processing apparatus may have a power source for applying RF to the substrate side.
- high-density plasma high-density oxygen radicals can be generated.
- oxygen ions generated by the high-density plasma can be efficiently guided into the oxide 230b.
- the microwave treatment is preferably performed under reduced pressure, and the pressure may be 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and further preferably 400 Pa or more.
- the oxygen flow rate ratio (O 2 / O 2 + Ar) is 50% or less, preferably 10% or more and 30% or less.
- the treatment temperature may be 750 ° C. or lower, preferably 500 ° C. or lower, for example, about 400 ° C.
- the heat treatment may be continuously performed without exposing to the outside air.
- oxygen gas is turned into plasma using a high frequency such as microwave or RF, and the oxygen plasma is converted into an oxide. It can act on the region between the conductor 242a and the conductor 242b of 230b and the region between the conductor 242b and the conductor 242c. At this time, it is also possible to irradiate a high frequency such as microwave or RF. That is, microwaves, high frequencies such as RF, oxygen plasma, and the like can be applied to the regions 232d and 232e shown in FIG.
- Plasma by the action such as a microwave, and divide the V O H region 232d and the region 232 e, hydrogen H can be removed from the region 232d and a region 232 e. That is, in the region 232d and the region 232 e, happening reaction of "V O H ⁇ H + V O", it is possible to reduce the hydrogen concentration in the region 232d and the region 232 e. Therefore, to reduce oxygen vacancies, and V O H in the region 232d and the region 232 e, the carrier concentration can be decreased.
- the oxygen deficiency in the region 232d and the region 232e is further eliminated. It can be reduced and the carrier concentration can be lowered.
- a conductor 242a, a conductor 242b, and a conductor 242c are provided on the region 232a, the region 232b, and the region 232c.
- the conductors 242a, 242b, and 242c shield the action of microwaves, high frequencies such as RF, oxygen plasma, and the like. It does not reach the regions 232a, 232b, and 232c.
- the microwave treatment, the area 232a, area 232b, and the region 232c, the reduction of V O H, and excessive amount of oxygen supply does not occur, it is possible to prevent a decrease in carrier concentration.
- the conductor 248 is provided so as to be superimposed on the conductor 242b, the upper surface of the conductor 248 is in contact with the region 232b in a self-aligned manner, so that the transistor 200a and the transistor 200b and the conductor 248 are in good contact with each other. Can be formed.
- microwave treatment was performed after the insulating film 250A was formed, but the present invention is not limited to this.
- the microwave treatment may be performed before the film formation of the insulating film 250A, or the microwave treatment may be performed both before and after the film formation of the insulating film 250A.
- microwave treatment is performed to form silicon oxide in the lower layer of the insulating film 250A by the PEALD method, and hafnium oxide in the upper layer of the insulating film 250A is formed by the thermal ALD method.
- the film may be formed with.
- the microwave treatment, the PEALD film formation of silicon oxide, and the thermal ALD film formation of hafnium oxide are continuously treated without being exposed to the atmosphere.
- a multi-chamber type processing device may be used.
- the microwave treatment may be replaced by the treatment of the plasma-excited reactor (oxidizer) of the PEALD apparatus.
- oxygen gas may be used as the reactor (oxidizing agent).
- the heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment.
- hydrogen in the insulating film 250A, the oxide 230b, and the oxide 230a can be efficiently removed.
- a part of hydrogen may be gettered on the conductor 242 (conductor 242a and conductor 242b).
- the step of performing the heat treatment may be repeated a plurality of times while maintaining the reduced pressure state after the microwave treatment. By repeating the heat treatment, hydrogen in the insulating film 250A, the oxide 230b, and the oxide 230a can be removed more efficiently.
- the heat treatment temperature is preferably 300 ° C. or higher and 500 ° C. or lower.
- the diffusion of hydrogen, water, impurities, etc. can be suppressed by modifying the film quality of the insulating film 250A by performing microwave treatment. Therefore, hydrogen, water, impurities, etc. are diffused to the oxide 230b, the oxide 230a, etc. through the insulator 250 by a post-process such as film formation of a conductive film to be a conductor 260 or a post-treatment such as heat treatment. It can be suppressed.
- a conductive film to be the conductor 260a and a conductive film to be the conductor 260b are formed in this order.
- the film formation of the conductive film to be the conductor 260a and the conductive film to be the conductor 260b can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the ALD method is used to form a conductive film to be the conductor 260a
- the CVD method is used to form the conductive film to be the conductor 260b.
- the insulating film 250A, the conductive film to be the conductor 260a, and the conductive film to be the conductor 260b are polished until the insulator 280 is exposed, thereby insulating the transistor 200a and the transistor 200b.
- a body 250 and a conductor 260 (conductor 260a and conductor 260b) are formed, respectively (see FIGS. 11A to 11D).
- the transistor 200a and the insulator 250 of the transistor 200b are arranged so as to cover the inner wall (side wall and bottom surface) of the two openings reaching the oxide 230b and the groove of the oxide 230b.
- the transistor 200a and the conductor 260 of the transistor 200b are arranged so as to embed the two openings and the groove portion via the insulator 250.
- the heat treatment may be performed under the same conditions as the above heat treatment.
- the treatment is carried out in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour.
- the heat treatment the water concentration and the hydrogen concentration in the insulator 250 and the insulator 280 can be reduced.
- the insulator 282 may be continuously formed without being exposed to the atmosphere.
- the insulator 282 is formed on the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 12A to 12D).
- the film formation of the insulator 282 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the film formation of the insulator 282 is preferably performed by using a sputtering method. By using a sputtering method that does not require hydrogen to be used as the film forming gas, the hydrogen concentration in the insulator 282 can be reduced.
- the insulator 282 in an atmosphere containing oxygen by using the sputtering method, oxygen can be added to the insulator 280 while forming the film. As a result, the insulator 280 can contain excess oxygen. At this time, it is preferable to form the insulator 282 while heating the substrate.
- aluminum oxide is formed as the insulator 282 by the pulse DC sputtering method using an aluminum target in an atmosphere containing oxygen gas.
- the pulse DC sputtering method By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
- the insulator 283 is formed on the insulator 282 (see FIGS. 1A to 1D).
- the film formation of the insulator 283 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- the film formation of the insulator 283 is preferably performed by using a sputtering method.
- a sputtering method that does not require hydrogen to be used as the film-forming gas, the hydrogen concentration in the insulator 283 can be reduced.
- the insulator 283 may have multiple layers.
- silicon nitride may be deposited by using a sputtering method, and silicon nitride may be deposited on the silicon nitride by a CVD method.
- a sputtering method silicon nitride may be deposited on the silicon nitride by a CVD method.
- heat treatment may be performed.
- the treatment is carried out in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour.
- the oxygen added by the film formation of the insulator 282 is diffused into the insulator 280 and the insulator 250, and selectively supplied to the channel forming region of the oxide 230.
- the heat treatment may be performed not only after the formation of the insulator 283 but also after the film formation of the insulator 282.
- the semiconductor device having the transistor 200 shown in FIGS. 1A to 1D can be manufactured.
- the transistor 200 is manufactured by using the method for manufacturing the semiconductor device shown in the present embodiment. be able to.
- microwave processing device that can be used in the method for manufacturing the semiconductor device will be described.
- FIG. 13 schematically shows a top view of the single-wafer multi-chamber manufacturing apparatus 2700.
- the manufacturing apparatus 2700 has an atmosphere-side substrate supply chamber 2701 including a cassette port 2761 for accommodating the substrate and an alignment port 2762 for aligning the substrate, and an atmosphere-side substrate transport for transporting the substrate from the atmosphere-side substrate supply chamber 2701.
- Room 2702 and load lock chamber 2703a that carries in the substrate and switches the pressure in the room from atmospheric pressure to atmospheric pressure, or from reduced pressure to atmospheric pressure, and carries out the substrate and reduces the pressure in the room from reduced pressure to atmospheric pressure, or It has an unload lock chamber 2703b for switching from atmospheric pressure to depressurization, a transport chamber 2704 for transporting a substrate in vacuum, a chamber 2706a, a chamber 2706b, a chamber 2706c, and a chamber 2706d.
- atmospheric side substrate transport chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transport chamber 2704, and the transport chamber 2704 is connected to the chamber 2706a. , Connects to chamber 2706b, chamber 2706c and chamber 2706d.
- a gate valve GV is provided at the connection portion of each chamber, and each chamber can be independently held in a vacuum state except for the atmospheric side substrate supply chamber 2701 and the atmospheric side substrate transport chamber 2702. Further, a transfer robot 2763a is provided in the atmospheric side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. The transfer robot 2763a and the transfer robot 2763b can transfer the substrate in the manufacturing apparatus 2700.
- the back pressure (total pressure) of the transport chamber 2704 and each chamber is, for example, 1 ⁇ 10 -4 Pa or less, preferably 3 ⁇ 10 -5 Pa or less, and more preferably 1 ⁇ 10 -5 Pa or less.
- the partial pressure of gas molecules (atoms) having a mass-to-charge ratio (m / z) of 18 in the transport chamber 2704 and each chamber is, for example, 3 ⁇ 10 -5 Pa or less, preferably 1 ⁇ 10 -5 Pa or less. , More preferably 3 ⁇ 10 -6 Pa or less.
- the partial pressure of the gas molecules (atoms) having an m / z of 28 in the transport chamber 2704 and each chamber is, for example, 3 ⁇ 10 -5 Pa or less, preferably 1 ⁇ 10 -5 Pa or less, more preferably 3. ⁇ 10-6 Pa or less.
- the partial pressure of the gas molecules (atoms) having an m / z of 44 in the transport chamber 2704 and each chamber is, for example, 3 ⁇ 10 -5 Pa or less, preferably 1 ⁇ 10 -5 Pa or less, more preferably 3. ⁇ 10-6 Pa or less.
- the total pressure and partial pressure in the transport chamber 2704 and each chamber can be measured using a mass spectrometer.
- a mass spectrometer for example, a quadrupole mass spectrometer (also referred to as Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. may be used.
- the transport chamber 2704 and each chamber have a configuration in which there are few external leaks or internal leaks.
- the leakage rate of the transport chamber 2704 and each chamber is 3 ⁇ 10-6 Pa ⁇ m 3 / s or less, preferably 1 ⁇ 10-6 Pa ⁇ m 3 / s or less.
- the leak rate of the gas molecule (atom) having m / z of 18 is set to 1 ⁇ 10 -7 Pa ⁇ m 3 / s or less, preferably 3 ⁇ 10 -8 Pa ⁇ m 3 / s or less.
- the leak rate of a gas molecule (atom) having m / z of 28 is 1 ⁇ 10-5 Pa ⁇ m 3 / s or less, preferably 1 ⁇ 10-6 Pa ⁇ m 3 / s or less.
- the leak rate of the gas molecule (atom) having m / z of 44 is set to 3 ⁇ 10 -6 Pa ⁇ m 3 / s or less, preferably 1 ⁇ 10 -6 Pa ⁇ m 3 / s or less.
- the leak rate may be derived from the total pressure and partial pressure measured using the above-mentioned mass spectrometer.
- the leak rate depends on external and internal leaks.
- An external leak is a gas flowing in from outside the vacuum system due to a minute hole or a defective seal.
- Internal leaks are caused by leaks from partitions such as valves in the vacuum system and gases released from internal members. In order to keep the leak rate below the above value, it is necessary to take measures from both the external leak and the internal leak.
- the transport chamber 2704 and the opening and closing parts of each chamber may be sealed with a metal gasket.
- a metal gasket it is preferable to use a metal coated with iron fluoride, aluminum oxide, or chromium oxide.
- the metal gasket has higher adhesion than the O-ring and can reduce external leakage. Further, by using the passivation of the metal coated with iron fluoride, aluminum oxide, chromium oxide or the like, the released gas containing impurities released from the metal gasket can be suppressed, and the internal leak can be reduced.
- a member constituting the manufacturing apparatus 2700 aluminum, chromium, titanium, zirconium, nickel or vanadium containing impurities and having a small amount of emitted gas is used. Further, the above-mentioned member may be used by coating it with an alloy containing iron, chromium, nickel and the like. Alloys containing iron, chromium, nickel, etc. are rigid, heat resistant and suitable for processing. Here, if the surface unevenness of the member is reduced by polishing or the like in order to reduce the surface area, the released gas can be reduced.
- the members of the manufacturing apparatus 2700 described above may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.
- the members of the manufacturing apparatus 2700 are preferably made of only metal as much as possible.
- the surface thereof is made of iron fluoride, aluminum oxide, or oxide in order to suppress the emitted gas. It is recommended to coat it thinly with chrome or the like.
- the adsorbents present in the transport chamber 2704 and each chamber do not affect the pressure of the transport chamber 2704 and each chamber because they are adsorbed on the inner wall and the like, but cause gas release when the transport chamber 2704 and each chamber are exhausted. It becomes. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to use a pump having a high exhaust capacity to remove the adsorbents existing in the transport chamber 2704 and each chamber as much as possible and exhaust them in advance.
- the transport chamber 2704 and each chamber may be baked in order to promote the desorption of adsorbed substances. By baking, the desorption rate of the adsorbent can be increased by about 10 times. Baking may be performed at 100 ° C. or higher and 450 ° C. or lower.
- the desorption rate of water or the like which is difficult to desorb only by exhausting, can be further increased.
- the desorption rate of the adsorbent can be further increased.
- an inert gas such as a heated rare gas or oxygen
- the adsorbents in the transport chamber 2704 and each chamber can be desorbed, and the impurities present in the transport chamber 2704 and each chamber can be reduced. It is effective to repeat this treatment 2 times or more and 30 times or less, preferably 5 times or more and 15 times or less.
- an inert gas or oxygen having a temperature of 40 ° C. or higher and 400 ° C. or lower, preferably 50 ° C. or higher and 200 ° C.
- the pressure in the transport chamber 2704 and each chamber is 0.1 Pa or higher and 10 kPa or lower.
- the pressure may be preferably 1 Pa or more and 1 kPa or less, more preferably 5 Pa or more and 100 Pa or less, and the pressure holding period may be 1 minute or more and 300 minutes or less, preferably 5 minutes or more and 120 minutes or less.
- the transfer chamber 2704 and each chamber are exhausted for a period of 5 minutes or more and 300 minutes or less, preferably 10 minutes or more and 120 minutes or less.
- Chambers 2706b and 2706c are, for example, chambers capable of performing microwave treatment on an object to be processed. It should be noted that the chamber 2706b and the chamber 2706c differ only in the atmosphere when microwave processing is performed. Since other configurations are common, they will be described together below.
- the chamber 2706b and the chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Further, outside the chamber 2706b and the chamber 2706c, a gas supply source 2801, a valve 2802, a high frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas tube 2806, and a waveguide 2807 are provided outside the chamber 2706b and the chamber 2706c.
- a matching box 2815, a high frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided.
- the high frequency generator 2803 is connected to the mode converter 2805 via a waveguide 2804.
- the mode converter 2805 is connected to the slot antenna plate 2808 via a waveguide 2807.
- the slot antenna plate 2808 is arranged in contact with the dielectric plate 2809.
- the gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Then, gas is sent to the chamber 2706b and the chamber 2706c by the mode converter 2805, the waveguide 2807, and the gas tube 2806 passing through the dielectric plate 2809.
- the vacuum pump 2817 has a function of exhausting gas or the like from the chamber 2706b and the chamber 2706c via the valve 2818 and the exhaust port 2819.
- the high frequency power supply 2816 is connected to the substrate holder 2812 via the matching box 2815.
- the board holder 2812 has a function of holding the board 2811. For example, it has a function of electrostatically chucking or mechanically chucking the substrate 2811. It also functions as an electrode to which power is supplied from the high frequency power supply 2816. Further, it has a heating mechanism 2813 inside and has a function of heating the substrate 2811.
- the vacuum pump 2817 for example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, a turbo molecular pump, or the like can be used. Further, in addition to the vacuum pump 2817, a cryotrap may be used. It is particularly preferable to use a cryopump and a cryotrap because water can be efficiently exhausted.
- the heating mechanism 2813 may be, for example, a heating mechanism that heats using a resistance heating element or the like. Alternatively, it may be a heating mechanism that heats by heat conduction or heat radiation from a medium such as a heated gas.
- RTA Rapid Thermal Analing
- GRTA Gas Rapid Thermal Annealing
- LRTA Riv Rapid Thermal Annealing
- GRTA is heat-treated using a high-temperature gas. As the gas, an inert gas is used.
- the gas supply source 2801 may be connected to the refiner via a mass flow controller.
- the gas it is preferable to use a gas having a dew point of ⁇ 80 ° C. or lower, preferably ⁇ 100 ° C. or lower.
- oxygen gas, nitrogen gas, and rare gas argon gas, etc. may be used.
- the dielectric plate 2809 for example, silicon oxide (quartz), aluminum oxide (alumina), yttrium oxide (itria), or the like may be used. Further, another protective layer may be formed on the surface of the dielectric plate 2809. As the protective layer, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, yttrium oxide and the like may be used. Since the dielectric plate 2809 is exposed to a particularly high-density region of the high-density plasma 2810 described later, damage can be mitigated by providing a protective layer. As a result, it is possible to suppress an increase in particles during processing.
- the high frequency generator 2803 has, for example, a function of generating microwaves of 0.3 GHz or more and 3.0 GHz or less, 0.7 GHz or more and 1.1 GHz or less, or 2.2 GHz or more and 2.8 GHz or less.
- the microwave generated by the high frequency generator 2803 is transmitted to the mode converter 2805 via the waveguide 2804.
- the microwave transmitted as the TE mode is converted into the TEM mode.
- the microwave is transmitted to the slot antenna plate 2808 via the waveguide 2807.
- the slot antenna plate 2808 is provided with a plurality of slot holes, and microwaves pass through the slot holes and the dielectric plate 2809. Then, an electric field can be generated below the dielectric plate 2809 to generate high-density plasma 2810.
- ions and radicals corresponding to the gas type supplied from the gas supply source 2801 are present. For example, there are oxygen radicals and the like.
- the substrate 2811 can modify the film and the like on the substrate 2811 by the ions and radicals generated by the high-density plasma 2810. It may be preferable to apply a bias to the substrate 2811 side by using the high frequency power supply 2816.
- the high frequency power supply 2816 for example, an RF (Radio Frequency) power supply having a frequency such as 13.56 MHz or 27.12 MHz may be used.
- the ions in the high-density plasma 2810 can be efficiently reached deep into the openings such as the film on the substrate 2811.
- oxygen radical treatment using the high-density plasma 2810 can be performed by introducing oxygen from the gas supply source 2801.
- Chambers 2706a and 2706d are, for example, chambers capable of irradiating an object to be processed with electromagnetic waves. It should be noted that the chamber 2706a and the chamber 2706d differ only in the type of electromagnetic wave. Since there are many common parts about other configurations, they will be explained together below.
- Chambers 2706a and 2706d have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Further, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the chamber 2706a and the chamber 2706d.
- the gas supply source 2821 is connected to the gas introduction port 2823 via a valve 2822.
- the vacuum pump 2828 is connected to the exhaust port 2830 via a valve 2829.
- the lamp 2820 is arranged to face the substrate holder 2825.
- the substrate holder 2825 has a function of holding the substrate 2824. Further, the substrate holder 2825 has a heating mechanism 2826 inside, and has a function of heating the substrate 2824.
- a light source having a function of radiating electromagnetic waves such as visible light or ultraviolet light
- a light source having a function of emitting an electromagnetic wave having a peak at a wavelength of 10 nm or more and 2500 nm or less, 500 nm or more and 2000 nm or less, or 40 nm or more and 340 nm or less may be used.
- a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp may be used.
- the electromagnetic wave radiated from the lamp 2820 can be partially or completely absorbed by the substrate 2824 to modify the film or the like on the substrate 2824.
- defects can be created or reduced, or impurities can be removed. If the substrate 2824 is heated, defects can be efficiently generated or reduced, or impurities can be removed.
- the substrate holder 2825 may be heated by the electromagnetic waves radiated from the lamp 2820 to heat the substrate 2824.
- the heating mechanism 2826 does not have to be provided inside the substrate holder 2825.
- the vacuum pump 2828 refers to the description about the vacuum pump 2817.
- the heating mechanism 2826 refers to the description about the heating mechanism 2813.
- the gas supply source 2821 refers to the description about the gas supply source 2801.
- FIG. 16A shows a top view of the semiconductor device.
- FIG. 16B is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in FIG. 16A.
- FIG. 16C is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line in FIG. 16A.
- FIG. 16D is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line in FIG. 16A.
- some elements are omitted for the sake of clarity.
- the same reference numerals are added to the structures having the same functions as the structures constituting the semiconductor devices shown in ⁇ Semiconductor device configuration example>.
- the constituent material of the semiconductor device the material described in detail in ⁇ Semiconductor device configuration example> can be used.
- the semiconductor device shown in FIGS. 16A to 16D is a modification of the semiconductor device shown in FIGS. 1A to 1D.
- the semiconductor device shown in FIGS. 16A to 16D is different from the semiconductor device shown in FIGS. 1A to 1D in that it has an oxide 230c and an oxide 230d. It is also different in that it has an insulator 271, an insulator 272, and an insulator 273.
- the transistor 200a and the transistor 200b have an oxide 230c on the oxide 230b and an oxide 230d on the oxide 230c, respectively.
- the oxide 230c and the oxide 230d are provided in the openings formed in the insulator 280 and the insulator 275.
- the oxide 230c is the upper surface of the insulator 224, the side surface of the oxide 230a, the upper surface and the side surface of the oxide 230b, the side surface of the oxide 243, the side surface of the conductor 242, the side surface of the insulator 271, and the side surface of the insulator 273.
- the side surface of the insulator 275, and the side surface of the insulator 280 respectively.
- the uppermost portion of the oxide 230c and the uppermost portion of the oxide 230d are in contact with the insulator 282.
- the oxide 230d By arranging the oxide 230d on the oxide 230c, it is possible to suppress the diffusion of impurities to the oxide 230b or the oxide 230c from the structure formed above the oxide 230d. Further, by arranging the oxide 230d on the oxide 230c, the upward diffusion of oxygen from the oxide 230b or the oxide 230c can be suppressed.
- the oxide 230c is arranged so as to cover the inner wall (side wall and bottom surface) of the groove.
- the film thickness of the oxide 230c is preferably about the same as the depth of the groove.
- the atomic number ratio of In to the element M in the metal oxide used for the oxide 230c is larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 230a or the oxide 230d. ..
- the atomic number ratio of indium to the main component metal element in the oxide 230c is the indium atom to the main component metal element in the oxide 230b. It is preferably larger than the number ratio. Further, it is preferable that the atomic number ratio of In to the element M in the oxide 230c is larger than the atomic number ratio of In to the element M in the oxide 230b.
- the atomic number ratio of indium to the metal element which is the main component is made larger than the atomic number ratio of indium to the metal element which is the main component in the oxide 230b, so that the oxide 230c is carried. Can be the main route of. Further, it is preferable that the lower end of the conduction band of the oxide 230c is separated from the vacuum level from the lower end of the conduction band of the oxide 230a and the oxide 230b. In other words, the electron affinity of the oxide 230c is preferably larger than the electron affinity of the oxides 230a and 230b. At this time, the main path of the carrier is the oxide 230c.
- M: Zn 4: 2: 3 [atomic number ratio] or a composition in the vicinity thereof
- M: Zn 5: 1: 3 [atomic number ratio] or its vicinity.
- CAAC-OS As the oxide 230c, and it is preferable that the c-axis of the crystal of the oxide 230c is oriented substantially perpendicular to the surface to be formed or the upper surface of the oxide 230c.
- CAAC-OS has the property of easily moving oxygen in the direction perpendicular to the c-axis. Therefore, the oxygen contained in the oxide 230c can be efficiently supplied to the oxide 230b.
- the oxide 230d preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230c, and more preferably contains all the metal elements.
- the oxide 230c In-M-Zn oxide, In-Zn oxide, or indium oxide is used as the oxide 230c, and In-M-Zn oxide, M-Zn oxide, or element M is used as the oxide 230d. It is advisable to use the oxide of. As a result, the defect level density at the interface between the oxide 230c and the oxide 230d can be lowered.
- the lower end of the conduction band of the oxide 230d is closer to the vacuum level than the lower end of the conduction band of the oxide 230c.
- the electron affinity of the oxide 230d is preferably smaller than the electron affinity of the oxide 230c.
- the oxide 230d it is preferable to use a metal oxide that can be used for the oxide 230a or the oxide 230b.
- the main path of the carrier is the oxide 230c.
- the composition in the vicinity includes a range of ⁇ 30% of the desired atomic number ratio.
- gallium it is preferable to use gallium as the element M.
- the oxide 230d is more preferably a metal oxide that suppresses the diffusion or permeation of oxygen than the oxide 230c.
- the atomic number ratio of In to the metal element as the main component is smaller than the atomic number ratio of In to the metal element as the main component in the metal oxide used for the oxide 230c.
- the atomic number ratio of In to the element M may be smaller than the atomic number ratio of In to the element M in the oxide 230c.
- the insulator 250 functions as a gate insulator, if In is mixed in the insulator 250 or the like, the characteristics of the transistor become poor. Therefore, by providing the oxide 230d between the oxide 230c and the insulator 250, it is possible to provide a highly reliable semiconductor device.
- the oxide 230c may be provided for each transistor 200. That is, the oxide 230c of the transistor 200 and the oxide 230c of the transistor 200 adjacent to the transistor 200 in the channel width direction do not have to be in contact with each other. Further, the oxide 230c of the transistor 200 and the oxide 230c of the transistor 200 adjacent to the transistor 200 in the channel width direction may be separated from each other. In other words, the oxide 230c may not be arranged between the transistor 200 and the transistor 200 adjacent to the transistor 200 in the channel width direction.
- the oxide 230c is independently provided on the transistors 200 by the above configuration. Therefore, it is possible to suppress the occurrence of a parasitic transistor between the transistor 200 and the transistor 200 adjacent to the transistor 200 in the channel width direction, and to suppress the occurrence of the leak path. Therefore, it is possible to provide a semiconductor device having good electrical characteristics and capable of miniaturization or high integration.
- the semiconductor devices shown in FIGS. 16A to 16D include an insulator 271 on the conductor 242, an insulator 273 on the insulator 271, a side surface of the oxide 230b, a side surface of the oxide 243, and the conductor 242. It has an insulator 272 in contact with the side surface.
- the insulator 271 functions at least as a barrier insulating film against oxygen. Therefore, it is preferable that the insulator 271 has a function of suppressing the diffusion of oxygen.
- the insulator 271 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280.
- the insulator 271 for example, a nitride containing silicon such as silicon nitride may be used.
- the insulator 273 preferably has an excess oxygen region or excess oxygen. Further, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 273 is reduced.
- an oxide containing silicon such as silicon oxide and silicon oxide nitride may be appropriately used.
- the insulator 272 functions at least as a barrier insulating film against oxygen. Therefore, the insulator 272 preferably has a function of suppressing the diffusion of oxygen. For example, the insulator 272 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280.
- a nitride containing silicon such as silicon nitride may be used.
- the conductor 242 can be wrapped with an insulator having a barrier property against oxygen. That is, it is possible to prevent oxygen added at the time of forming the insulator 275 or oxygen contained in the insulator 273 from diffusing into the conductor 242. As a result, the conductor 242 is directly oxidized by oxygen added at the time of forming the insulator 275 or oxygen contained in the insulator 273 to increase the resistivity and suppress the decrease in the on-current. it can.
- FIG. 1B and the like show the configuration in which the insulator 272 is in contact with the side surfaces of the oxide 230a, the oxide 230b, the oxide 243, the conductor 242, the insulator 271, and the insulator 273, the insulator 272 is shown. , At least in contact with the side surfaces of the insulator 271 and the conductor 242.
- the insulator 272 may be in contact with the side surfaces of the oxide 230a, the oxide 230b, the oxide 243, the conductor 242, and the insulator 271 and not in contact with the insulator 273. In this case, the side surface of the insulator 273 comes into contact with the insulator 275.
- one aspect of the present invention it is possible to provide a semiconductor device capable of miniaturization or high integration.
- one aspect of the present invention can provide a semiconductor device having a large storage capacity.
- one aspect of the present invention can provide a semiconductor device with good reliability.
- one aspect of the present invention can provide a semiconductor device having good electrical characteristics.
- one aspect of the present invention can provide a semiconductor device having a large on-current.
- one aspect of the present invention can provide a semiconductor device capable of miniaturization or high integration.
- one aspect of the present invention can provide a low power consumption semiconductor device.
- one aspect of the present invention can provide a novel semiconductor device.
- FIG. 17A An example of a semiconductor device (storage device) according to one aspect of the present invention is shown in FIG. 17A.
- the capacitive element 100a is arranged on the transistor 200a, and the capacitive element 100b is arranged on the transistor 200b.
- the capacitive element 100a and the capacitive element 100b may be collectively referred to as the capacitive element 100.
- the transistor 200a and the transistor 200b the transistor 200a and the transistor 200b described in the previous embodiment can be used. That is, the semiconductor device shown in FIG. 17A has a configuration in which the capacitance element 100a and the capacitance element 100b are provided on the semiconductor device shown in FIG. Regarding the configurations of the transistor 200a and the transistor 200b, the description relating to the transistor 200a and the transistor 200b shown in the previous embodiment can be referred to.
- one of the source and drain of the transistor 200a is electrically connected to the first electrode of the capacitive element 100a
- the other of the source and drain of the transistor 200a is electrically connected to one of the source and drain of the transistor 200b.
- the other of the source and drain of the transistor 200b is electrically connected to the first electrode of the capacitive element 100b.
- the transistor 200a and the capacitive element 100a and the transistor 200b and the capacitive element 100b connected in this way can each function as a memory cell of the storage device. Therefore, in the following, a semiconductor device having a transistor 200a, a transistor 200b, a capacitance element 100a, and a capacitance element 100b as shown in FIG. 17A may be referred to as a memory unit 400.
- the capacitance element 100 By providing the conductor 248 under the oxide 230 in the memory unit 400, it is possible to reduce the parasitic capacitance of the conductor 248 and the bit wire provided in contact with the conductor 248. As a result, the capacitance required for the capacitive element 100 is reduced, and the capacitive element 100 can be miniaturized.
- the capacitance element 100a may be superimposed on the transistor 200a, and the capacitance element 100b may be superimposed on the transistor 200b.
- the memory unit 400 can be miniaturized or highly integrated. Further, by miniaturizing or highly integrating the memory unit 400, it is possible to provide a semiconductor device having a large storage capacity.
- the capacitance of the capacitance element 100a and the capacitance element 100b can be increased without increasing the occupied area of the memory unit 400.
- the capacitance element 100 is provided on the insulator 283.
- the capacitive element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric.
- a conductor that can be used for the conductor 205 or the like may be used.
- the conductor 110 and the conductor 120 show a single-layer structure in FIG. 17, the structure is not limited to this, and a laminated structure of two or more layers may be used.
- a conductor having a barrier property and a conductor having a high adhesion to a conductor having a high conductivity may be formed between a conductor having a barrier property and a conductor having a high conductivity.
- the insulator 130 includes, for example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium oxide, hafnium nitride. Etc. may be used, and it can be provided in a laminated or single layer.
- the capacitive element 100 can secure a sufficient capacitance by having an insulator having a high dielectric constant (high-k), and by having an insulator having a large dielectric strength, the dielectric strength is improved and the capacitance is improved. Electrostatic destruction of the element 100 can be suppressed.
- gallium oxide As an insulator of a high dielectric constant (high-k) material (material having a high specific dielectric constant), gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, and nitrides having aluminum and hafnium. , Oxides with silicon and hafnium, nitrides with silicon and hafnium or nitrides with silicon and hafnium.
- silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon and nitrogen are used as materials with high dielectric strength (materials with low dielectric strength).
- silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon and nitrogen are used as materials with high dielectric strength (materials with low dielectric strength).
- silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon and nitrogen are used as materials with high dielectric strength (materials with low dielectric strength).
- a conductor 240 that functions as a plug that electrically connects the transistor 200a and the capacitance element 100a and a plug that electrically connects the transistor 200b and the capacitance element 100b is provided.
- the lower surface of the conductor 240 provided between the transistor 200a and the capacitive element 100a is in contact with the conductor 242a, and the upper surface is in contact with the conductor 110 of the capacitive element 100a.
- the conductor 240 provided between the transistor 200b and the capacitance element 100b has a lower surface in contact with the conductor 242c and an upper surface in contact with the conductor 110 of the capacitance element 100b.
- the insulator 241 is provided in contact with the side surface of the conductor 240 that functions as a plug.
- the insulator 241 is provided in contact with the inner wall of the opening of the insulator 275, the insulator 280, the insulator 282, and the insulator 283, and the first conductor of the conductor 240 is provided in contact with the side surface of the insulator 241. Further, a second conductor of the conductor 240 is provided inside. Note that FIG. 17 shows a configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are laminated, but the present invention is not limited to this.
- the conductor 240 may be provided as a single layer or a laminated structure having three or more layers.
- the conductor 240 it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor 240 may have a laminated structure. When the conductor 240 has a laminated structure, the conductor in contact with the insulator 283, the insulator 282, the insulator 280, and the insulator 275 is a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen. Is preferably used. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide and the like are preferably used.
- the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated state. As a result, impurities such as water and hydrogen contained in the layer above the insulator 283 can be suppressed from being mixed into the oxide 230 through the conductor 240.
- an insulator such as silicon nitride, aluminum oxide, or silicon nitride may be used. Since the insulator 241 is provided in contact with the insulator 283, the insulator 282, and the insulator 275, impurities such as water and hydrogen contained in the insulator 280 and the like are mixed into the oxide 230 through the conductor 240. Can be suppressed.
- silicon nitride is suitable because it has a high barrier property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240.
- the memory unit 400 and the memory unit 401 having the same configuration as the memory unit 400 may be arranged in the channel length direction.
- an insulator 210 is provided under the insulator 212, and a conductor 288 is provided under the insulator 210.
- the upper surface of the conductor 288 is in contact with the lower surface of the memory unit 400 and the conductor 248 of the memory unit 401.
- an insulator that can be used for the insulator 280 may be used.
- the conductor 288, a conductor that can be used for the conductor 205 may be used as the conductor 288, a conductor that can be used for the conductor 205 may be used.
- the conductor 288 functions as wiring. That is, the memory unit 400 and the memory unit 401 are electrically connected to the conductor 288, which functions as wiring, via the conductor 248, respectively.
- the conductor 288 that functions as a bit line and the conductor 260 that functions as a word line are arranged orthogonally to each other.
- a transistor 200 and a capacitance element 100 are formed in a region where the conductor 288 and the conductor 260 intersect, and memory cells including the transistor 200 and the capacitance element 100 are arranged in a matrix.
- a cell array (also referred to as a memory unit layer) can be configured.
- the distance between adjacent cells can be reduced, so that the projected area of the cell array can be reduced, and high integration is possible.
- FIG. 17A an example of a semiconductor device (storage device) according to one aspect of the present invention is shown in FIG.
- the memory unit 400 shown in FIG. 17A is provided above the transistor 300. That is, the transistor 200a and the transistor 200b are provided above the transistor 300, and the capacitive element 100a and the capacitive element 100b are provided above the transistor 200a and the transistor 200b.
- the capacitive element 100 and the transistor 200 the above-mentioned capacitive element 100 and the transistor 200 can be used, and a detailed structure can be taken into consideration.
- the transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200 has a small off-current, it is possible to retain the stored contents for a long period of time by using the transistor 200 as a storage device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.
- the metal oxide such as In-M-Zn oxide can be formed on the substrate by using a sputtering method or the like. Therefore, the memory unit 400 formed of the transistor 200 and the capacitance element 100 can be provided on the drive circuit or the like formed of the transistor 300 or the like formed on the silicon substrate. As a result, the occupied area of the peripheral circuit provided on one chip can be reduced and the occupied area of the memory cell array can be increased, so that the storage capacity of the semiconductor device can be increased.
- the storage devices shown in FIG. 18 can form a memory cell array by arranging them in a matrix.
- the transistor 300 is provided on the substrate 311 and functions as a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311 and a low that functions as a source region or a drain region. It has a resistance region 314a and a low resistance region 314b.
- the transistor 300 may be either a p-channel type or an n-channel type.
- the semiconductor region 313 (a part of the substrate 311) on which the channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered with the conductor 316 via the insulator 315.
- the conductor 316 may be made of a material that adjusts the work function. Since such a transistor 300 utilizes a convex portion of a semiconductor substrate, it is also called a FIN type transistor. It should be noted that an insulator that is in contact with the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Further, although the case where a part of the semiconductor substrate is processed to form a convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.
- transistor 300 shown in FIG. 18 is an example, and the transistor 300 is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method.
- a wiring layer provided with an interlayer film, wiring, a plug, etc. may be provided between the structures. Further, a plurality of wiring layers can be provided according to the design.
- the conductor having a function as a plug or wiring may collectively give a plurality of structures the same reference numerals. Further, in the present specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
- an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order on the transistor 300 as an interlayer film. Further, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitance element 100, a conductor 328 electrically connected to the transistor 200, a conductor 330, and the like. The conductor 328 and the conductor 330 function as plugs or wirings.
- the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape below the insulator.
- the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
- CMP chemical mechanical polishing
- a wiring layer may be provided on the insulator 326 and the conductor 330.
- the insulator 350, the insulator 352, and the insulator 354 are laminated in this order.
- a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring.
- An insulator 358 is provided on the insulator 354 and the conductor 356, and a conductor 288 that functions as wiring is provided on the insulator 358. Further, an insulator 210 is provided on the conductor 288. On the insulator 210, the insulator 212, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, the insulator 282, and the insulator 283, which are shown in the previous embodiment, are provided. A transistor 200a and a transistor 200b are formed in these insulators.
- a conductor 248 and an insulator 249 are embedded in the insulator 210, the insulator 212, the insulator 214, the insulator 216, the insulator 222, and the insulator 224.
- the conductor 248 is provided in contact with the conductor 288 in contact with the upper surface.
- the conductor 240 that functions as a plug is provided in contact with the upper surface of the conductor 242.
- An insulator 241 is provided in contact with the side surface of the conductor 240 that functions as a plug.
- the conductor 110 is provided on the insulator 283 and on the conductor 240 in contact with the conductor 240.
- the insulator 274 is provided on the insulator 283 in a region that does not overlap with the insulator 280.
- the above-mentioned capacitance element 100a and capacitance element 100b are formed on the insulator 283. Further, an insulator 150 is provided on the conductor 120 and the insulator 130 forming the capacitance element 100.
- Examples of the insulator that can be used as the interlayer film include oxides, nitrides, oxide nitrides, nitride oxides, metal oxides, metal oxide nitrides, and metal nitride oxides having insulating properties.
- the material may be selected according to the function of the insulator.
- the insulator 150, the insulator 274, the insulator 210, the insulator 358, the insulator 352, the insulator 354, and the like preferably have an insulator having a low relative permittivity.
- the insulator may have silicon nitride, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide or resin having pores, and the like. preferable.
- the insulator may be silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores.
- silicon oxide and silicon oxide nitride are thermally stable, they can be combined with a resin to form a laminated structure that is thermally stable and has a low relative permittivity.
- the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.
- a transistor using an oxide semiconductor can stabilize the electrical characteristics of the transistor by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, as the insulator 283, the insulator 282, the insulator 214, the insulator 212, the insulator 350, and the like, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.
- Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, tantalum, and zirconium. Insulations containing, lanthanum, neodymium, hafnium or tantalum may be used in single layers or in layers.
- an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or Metal oxides such as tantalum oxide, silicon nitride oxide, silicon nitride and the like can be used.
- Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium.
- a material containing one or more metal elements selected from ruthenium and the like can be used.
- a semiconductor having high electric conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and silicide such as nickel silicide may be used.
- the conductor 328, the conductor 330, the conductor 356, the conductor 288, the conductor 110, the conductor 120, and the like include a metal material, an alloy material, a metal nitride material, or a metal formed of the above materials.
- Conductive materials such as oxide materials can be used in a single layer or in layers. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten.
- it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
- an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In that case, it is preferable to provide an insulator having a barrier property between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
- an insulator 241 between the insulator 280 having excess oxygen and the conductor 240.
- the insulator 241 in contact with the insulator 275, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 are configured to be sealed by an insulator having a barrier property. Can be done.
- the insulator 241 it is possible to suppress the excess oxygen contained in the insulator 280 from being absorbed by the conductor 240. Further, by having the insulator 241, it is possible to suppress the diffusion of hydrogen, which is an impurity, to the transistor 200 via the conductor 240.
- an insulating material having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide or hafnium oxide.
- silicon nitride is preferable because it has a high barrier property against hydrogen.
- metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide can be used.
- the insulator 280 or the like may be patterned so that the insulator 212 and the insulator 283 are in contact with each other. That is, the transistor 200 may be configured to be sealed with an insulator 212, an insulator 214, an insulator 282, and an insulator 283. With such a configuration, it is possible to reduce the mixing of hydrogen contained in the insulator 274, the insulator 150 and the like into the insulator 280 and the like.
- the conductor 240 penetrates through the insulator 283 and the insulator 282, and as described above, the insulator 241 is provided in contact with the conductor 240. Thereby, hydrogen mixed in the insulator 212, the insulator 214, the insulator 282, and the insulator 283 can be reduced through the conductor 240. In this way, the transistor 200 is sealed with the insulator 212, the insulator 214, the insulator 282, the insulator 283, and the insulator 241, and impurities such as hydrogen contained in the insulator 274 and the like are mixed from the outside. Can be reduced.
- a dicing line (sometimes referred to as a scribe line, a division line, or a cutting line) provided when a plurality of semiconductor devices are taken out in a chip shape by dividing a large-area substrate into semiconductor elements will be described. ..
- a dividing method for example, there is a case where a groove (dicing line) for dividing a semiconductor element is first formed on a substrate, then the dicing line is cut, and the semiconductor device is divided (divided) into a plurality of semiconductor devices.
- the region where the insulator 283 and the insulator 212 are in contact overlap with the dicing line it is preferable to design so that the region where the insulator 283 and the insulator 212 are in contact overlap with the dicing line. That is, in the vicinity of the region serving as the dicing line provided on the outer edge of the plurality of memory units 400, the insulator 282, the insulator 280, the insulator 275, the insulator 224, the insulator 222, the insulator 216, and the insulator 214 are opened. Is provided.
- the insulator 212 and the insulator 283 come into contact with each other at the openings provided in the insulator 282, the insulator 280, the insulator 275, the insulator 224, the insulator 222, the insulator 216, and the insulator 214.
- the insulator 212 and the insulator 283 may be formed by using the same material and the same method.
- the adhesion can be improved. For example, it is preferable to use silicon nitride.
- the transistor 200 can be wrapped by the insulator 212, the insulator 214, the insulator 282, and the insulator 283. Since at least one of the insulator 212, the insulator 214, the insulator 282, and the insulator 283 has a function of suppressing the diffusion of oxygen, hydrogen, and water, the semiconductor element shown in the present embodiment is formed. By dividing the substrate for each circuit region, even if it is processed into a plurality of chips, impurities such as hydrogen or water are prevented from being mixed in from the side surface direction of the divided substrate and diffused to the transistor 200. Can be done.
- the structure can prevent the excess oxygen of the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen of the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which the channel is formed in the transistor 200.
- the oxygen can reduce the oxygen deficiency of the oxide in which the channel is formed in the transistor 200.
- the oxide in which the channel is formed in the transistor 200 can be made into an oxide semiconductor having a low defect level density and stable characteristics. That is, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 and improve reliability.
- the shapes of the capacitance element 100a and the capacitance element 100b are planar types, but the storage device shown in the present embodiment is not limited to this.
- the shape of the capacitance element 100a and the capacitance element 100b may be a cylinder type.
- the storage device shown in FIG. 19 has the same configuration as the semiconductor device shown in FIG. 18 in the configuration below the insulator 150.
- the capacitive element 100a and the capacitive element 100b shown in FIG. 19 are arranged in the insulator 150 on the insulator 130, the insulator 142 on the insulator 150, and the openings formed in the insulator 150 and the insulator 142. It has a conductor 115, an insulator 145 on the insulator 115 and the insulator 142, a conductor 125 on the insulator 145, and an insulator 152 on the insulator 125 and the insulator 145, respectively.
- at least a part of the conductor 115, the insulator 145, and the conductor 125 is arranged in the two openings formed in the insulator 150 and the insulator 142.
- the insulator 154 is arranged on the insulator 152, and the conductor 153 and the insulator 156 are arranged on the insulator 154. Further, the conductor 140 is provided in the openings formed in the insulator 152 and the insulator 154.
- the conductor 115 functions as a lower electrode of the capacitance element 100
- the conductor 125 functions as an upper electrode of the capacitance element 100
- the insulator 145 functions as a dielectric of the capacitance element 100.
- the capacitance element 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched not only on the bottom surface but also on the side surface at the openings of the insulator 150 and the insulator 142, and the capacitance per unit area.
- the capacity can be increased. Therefore, the deeper the depth of the opening, the larger the capacitance of the capacitance element 100 can be.
- an insulator that can be used for the insulator 280 may be used.
- the insulator 142 preferably functions as an etching stopper when forming an opening of the insulator 150, and an insulator that can be used for the insulator 214 may be used.
- the shape of the openings formed in the insulator 150 and the insulator 142 as viewed from the upper surface may be a quadrangle, a polygonal shape other than the quadrangle, or a polygonal shape with curved corners. , It may be a circular shape including an ellipse.
- it is preferable that the area where the opening and the transistor 200 overlap is large. With such a configuration, the occupied area of the semiconductor device having the capacitance element 100 and the transistor 200 can be reduced.
- the conductor 115 is arranged in contact with the insulator 142 and the opening formed in the insulator 150. It is preferable that the upper surface of the conductor 115 substantially coincides with the upper surface of the insulator 142. Further, the lower surface of the conductor 115 is in contact with the conductor 110 through the opening of the insulator 130.
- the conductor 115 is preferably formed by using an ALD method, a CVD method, or the like, and for example, a conductor that can be used for the conductor 205 may be used.
- the insulator 145 is arranged so as to cover the conductor 115 and the insulator 142.
- the insulator 145 includes, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium oxide, and nitride.
- Hafnium or the like may be used, and it can be provided in a laminated or single layer.
- an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used.
- a material having a large dielectric strength such as silicon oxide or a material having a high dielectric constant (high-k) for the insulator 145.
- a laminated structure of a material having a large dielectric strength and a high dielectric constant (high-k) material may be used.
- insulator of a high dielectric constant (high-k) material material having a high specific dielectric constant
- silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and pores are used as materials having high insulation strength.
- silicon oxide, resin, etc. laminated in the order of silicon nitride was deposited using ALD (SiN x), silicon oxide was deposited using PEALD method (SiO x), silicon nitride was deposited using ALD (SiN x) Insulation film can be used.
- the conductor 125 is arranged so as to fill the openings formed in the insulator 142 and the insulator 150. Further, the conductor 125 is electrically connected to the conductor 153 that functions as a wiring via the conductor 140.
- the conductor 125 is preferably formed by using an ALD method, a CVD method, or the like, and for example, a conductor that can be used for the conductor 205 may be used.
- the conductor 153 is provided on the insulator 154 and is covered with the insulator 156.
- a conductor that can be used for the conductor 110 may be used, and as the insulator 156, an insulator that can be used for the insulator 152 may be used.
- the conductor 153 is in contact with the upper surface of the conductor 140.
- FIGS. 20 and 21 An example of a semiconductor device (storage device) according to one aspect of the present invention is shown in FIGS. 20 and 21.
- the memory unit 400 shown in FIG. 20A differs from the memory unit 400 shown in FIG. 17A in the shapes of the capacitance element 100a and the capacitance element 100b.
- the capacitive element 100a has a conductor 242a, an insulator 275 provided so as to cover the conductor 242a, and a conductor 294a on the insulator 275.
- the capacitive element 100b has a conductor 242c, an insulator 275 provided so as to cover the conductor 242c, and a conductor 294b on the insulator 275. That is, the capacitive element 100a and the capacitive element 100b constitute a MIM (Metal-Insulator-Metal) capacitance.
- MIM Metal-Insulator-Metal
- one of the pair of electrodes of the capacitive element 100 can also serve as the source electrode or the drain electrode of the transistor 200.
- the dielectric layer of the capacitive element 100 can also serve as a protective layer provided on the transistor 200, that is, an insulator 275. Therefore, in the manufacturing process of the capacitive element 100, a part of the manufacturing process of the transistor can also be used, so that the semiconductor device can be highly productive. Further, since one of the pair of electrodes of the capacitance element 100, that is, the conductor 242 also serves as the source electrode or the drain electrode of the transistor 200, the area where the transistor 200 and the capacitance element 100 are arranged can be reduced. Is possible.
- conductor 294a and the conductor 294b for example, materials that can be used for the conductor 242 may be used.
- the memory unit 400 and the memory unit 401 having the same configuration as the memory unit 400 may be connected via the capacitance unit.
- the memory unit 400 and the memory unit 401 shown in FIG. 20B have the same structure as the memory unit 400 shown in FIG. 20A. Therefore, the details of the structures of the memory unit 400 and the memory unit 401 shown in FIG. 20B can refer to the description relating to the memory unit 400 shown in FIG. 20A.
- FIG. 20B is a cross-sectional view in which a memory unit 400 having a transistor 200a, a transistor 200b, a capacitance element 100a, and a capacitance element 100b and a memory unit 401 having the same configuration as the memory unit 400 are connected via a capacitance section. is there.
- the conductor 294b that functions as one electrode of the capacitance element 100b included in the memory unit 400 also serves as one electrode of the capacitance device included in the memory unit 401 having the same configuration as the memory unit 400. It has become.
- the conductor 294a, which functions as one electrode of the capacitance element 100a of the memory unit 400 is on the left side of the memory unit 400, that is, one of the capacitance devices of the semiconductor device adjacent to the memory unit 400 in the A1 direction. Also serves as an electrode.
- the cell on the right side of the memory unit 401, that is, in FIG. 20B has the same configuration for the cell in the A2 direction.
- the array can be configured by arranging the memory units in a matrix on the same layer.
- the distance between adjacent cells can be reduced, so that the projected area of the cell array can be reduced, and high integration is possible.
- an insulator 210 is provided under the insulator 212, and a conductor 288 is provided under the insulator 210.
- the upper surface of the conductor 288 is in contact with the lower surface of the memory unit 400 and the conductor 248 of the memory unit 401. Therefore, the memory unit 400 and the memory unit 401 are electrically connected to the conductor 288, which functions as wiring, via the conductor 248, respectively.
- the conductor 288 that functions as a bit line and the conductor 260 that functions as a word line are arranged orthogonally to each other.
- FIG. 21 shows a cross-sectional view of a configuration in which n layers of cell array 610 having a memory unit 400 are stacked.
- FIG. 21 by stacking a plurality of cell cells (series cell array 610_1 to cell array 610_n), cells can be integrated and arranged without increasing the occupied area of the cell array. That is, a 3D cell array can be constructed. Further, since the capacitance element 100 having the structure shown in FIGS.
- each cell array 20A and 20B can be formed at a position lower than the upper surface of the conductor 260, the height of each cell array is higher than that when the capacitance element having a cylinder structure is used. Can be lowered. As a result, a plurality of cell arrays can be laminated relatively easily. In this way, it is possible to achieve high integration of memory cells and provide a semiconductor device having a large storage capacity.
- FIG. 22 shows an example of a semiconductor device (storage device) according to one aspect of the present invention.
- FIG. 22 shows an example in which the memory 470 has a transistor layer 413 having a transistor 200T and four memory unit layers 415 (memory unit layer 415_1 to memory unit layer 415_4).
- the transistor 200T has the same structure as the transistor 200 shown in the previous embodiment.
- the memory unit layer 415_1 to the memory unit layer 415_1 each have a plurality of memory units 400.
- the memory unit 400 included in the memory unit layer 415_1 to the memory unit layer 415_1 has a structure similar to that of the memory unit 400 shown in FIG. 20A. Therefore, for the details of the memory unit 400, the description related to FIG. 20A and the like can be referred to.
- the conductor 248_1 provided in the memory unit layer 415_1 is electrically connected to the transistor 200T, and the conductor 248_2 provided in the memory unit layer 415_2 is connected to the conductor 242b provided in the memory unit layer 415_1.
- the conductor 248_3 connected and provided in the memory unit layer 415_3 is connected to the conductor 242b provided in the memory unit layer 415_2, and the conductor 248_4 provided in the memory unit layer 415_4 is provided in the memory unit layer 415_3. It is connected to the conductor 242b.
- the conductor 248_1 is connected to the gate electrode of the transistor 200T, but the present invention is not limited to this, and the connection of the conductor 248_1 is appropriately adapted to the circuit configuration of the memory 470 and the like. You can set it.
- the region 232b of the oxide 230b overlaps with the conductor 242b, the carrier concentration is high and the region 232b has electrical conductivity. Therefore, with the above configuration, the region 232b of the memory unit 400 provided in each memory unit layer 415 and the transistor 200T can be electrically connected via the conductor 248.
- memory cells can be integrated and arranged without increasing the occupied area of the cell array. Therefore, it is possible to provide a semiconductor device having a large storage capacity by increasing the integration of memory cells.
- the memory 470 is sealed by the insulator 212, the insulator 214, the insulator 282, and the insulator 283 (for convenience, hereinafter referred to as a sealing structure).
- An insulator 274 is provided around the insulator 283. Further, the insulator 274, the insulator 283, and the insulator 212 are provided with a conductor 440, which is electrically connected to the element layer 411.
- an insulator 280 is provided inside the sealing structure.
- the insulator 280 has a function of releasing oxygen by heating.
- the insulator 280 has an excess oxygen region.
- the insulator 212 and the insulator 283 are preferably materials having a function of having a high barrier property against hydrogen. Further, the insulator 214 and the insulator 282 are preferably materials having a function of capturing hydrogen or fixing hydrogen.
- the material having a function of having a high barrier property against hydrogen includes silicon nitride, silicon nitride, and the like.
- Examples of the material having a function of capturing hydrogen or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
- the crystal structure of the materials used for the insulator 212, the insulator 214, the insulator 282, and the insulator 283 is not particularly limited, but may be an amorphous or crystalline structure.
- Amorphous aluminum oxide may capture and adhere more hydrogen than highly crystalline aluminum oxide.
- the insulator 282 and the insulator 214 are provided between the transistor layer 413 and the memory unit layer 415, or also between each memory unit layer 415. Further, it is preferable that the insulator 296 is provided between the insulator 282 and the insulator 214.
- the excess oxygen in the insulator 280 can be considered as the following model for the diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280.
- Hydrogen present in the oxide semiconductor diffuses into other structures via the insulator 280 in contact with the oxide semiconductor. Due to the diffusion of the hydrogen, the excess oxygen in the insulator 280 reacts with the hydrogen in the oxide semiconductor to form an OH bond, and diffuses in the insulator 280.
- a hydrogen atom having an OH bond reaches a material having a function of capturing hydrogen or fixing hydrogen (typically, an insulator 282)
- the hydrogen atom becomes an atom in the insulator 282 (for example, an insulator 282). It reacts with oxygen atoms bonded to metal atoms, etc.) and is captured or fixed in the insulator 282.
- an insulator 280 having excess oxygen is formed on an oxide semiconductor, and then an insulator 282 is formed. After that, it is preferable to perform heat treatment. Specifically, the heat treatment is carried out in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen at a temperature of 350 ° C. or higher, preferably 400 ° C. or higher.
- the heat treatment time is 1 hour or longer, preferably 4 hours or longer, and more preferably 8 hours or longer.
- hydrogen in the oxide semiconductor can be diffused to the outside through the insulator 280 and the insulator 282. That is, the absolute amount of the oxide semiconductor and hydrogen existing in the vicinity of the oxide semiconductor can be reduced.
- an insulator 283 is formed. Since the insulator 283 is a material having a function of having a high barrier property against hydrogen, hydrogen diffused to the outside or hydrogen existing on the outside is transferred to the inside, specifically, an oxide semiconductor or the insulator 280. It can be suppressed from entering the side.
- the configuration performed after forming the insulator 282 has been illustrated, but the present invention is not limited to this.
- the above heat treatment may be performed after the transistor layer 413 is formed or after the memory unit layer 415_1 to the memory unit layer 415_3 are formed.
- hydrogen is diffused outward by the above heat treatment, hydrogen is diffused above or in the lateral direction of the transistor layer 413.
- hydrogen is diffused upward or laterally.
- the insulator 212 and the insulator 283 are adhered to each other to form the above-mentioned sealing structure.
- a transistor using an oxide as a semiconductor (hereinafter, may be referred to as an OS transistor) according to one aspect of the present invention.
- a storage device to which a capacitive element is applied (hereinafter, may be referred to as an OS memory device) will be described.
- the OS memory device is a storage device having at least a capacitance element and an OS transistor that controls charging / discharging of the capacitance element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a non-volatile memory.
- FIG. 23A shows an example of the configuration of the OS memory device.
- the storage device 1400 has a peripheral circuit 1411 and a memory cell array 1470.
- the peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
- the column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a writing circuit, and the like.
- the precharge circuit has a function of precharging the wiring.
- the sense amplifier has a function of amplifying a data signal read from a memory cell.
- the wiring is the wiring connected to the memory cell of the memory cell array 1470, and will be described in detail later.
- the amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440.
- the row circuit 1420 has, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.
- a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the storage device 1400 from the outside as power supply voltages. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside.
- the address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.
- the control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for row decoders and column decoders.
- the control signal CE is a chip enable signal
- the control signal WE is a write enable signal
- the control signal RE is a read enable signal.
- the signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.
- the memory cell array 1470 has a plurality of memory cells MCa and memory cells MCb arranged in a matrix, and a plurality of wirings.
- the memory cell MCa and the memory cell MCb are combined to form one memory unit.
- the memory cell MCa and the memory cell MCb may be collectively referred to as a memory cell MC.
- the number of wires connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cell MCs in a row, and the like.
- the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one row, and the like.
- FIG. 23A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane
- the present embodiment is not limited to this.
- the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411.
- a sense amplifier may be provided so as to overlap under the memory cell array 1470.
- the metal oxide such as In-M-Zn oxide can be formed on the substrate by using a sputtering method or the like. Therefore, the memory cell array 1470 can be provided on the peripheral circuit 1411 formed on the silicon substrate. As a result, the occupied area of the memory cell array that can be provided on one chip can be increased, so that the storage capacity of the semiconductor device can be increased.
- a plurality of memory cell array 1470s may be stacked. By stacking a plurality of memory cell arrays 1470, memory cells can be integrated and arranged without increasing the occupied area of the memory cell array 1470. That is, a 3D cell array can be constructed. In this way, it is possible to achieve high integration of memory cells and provide a semiconductor device having a large storage capacity.
- 24A to 24C show a configuration example of a memory cell applicable to the above-mentioned memory cell MCa and memory cell MCb.
- [DOSRAM] 24A to 24C show an example of a circuit configuration of a DRAM memory cell.
- a DRAM using a memory cell of a 1OS transistor and 1 capacitance element type may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).
- the memory unit 1471 shown in FIG. 24A has a memory cell MCa and a memory cell MCb.
- the memory cell MCa has a transistor M1a and a capacitance element CAa
- the memory cell MCb has a transistor M1b and a capacitance element CAb.
- the transistor M1a and the transistor M1b have a gate (sometimes called a top gate) and a back gate.
- the first terminal of the transistor M1a is connected to the first terminal of the capacitive element CAa, the second terminal of the transistor M1a is connected to the wiring BIL, the gate of the transistor M1a is connected to the wiring WOLa, and the back gate of the transistor M1a. Is connected to the wiring BGLa.
- the second terminal of the capacitive element CAa is connected to the wiring CAL.
- the first terminal of the transistor M1b is connected to the first terminal of the capacitive element CAb
- the second terminal of the transistor M1b is connected to the wiring BIL
- the gate of the transistor M1b is connected to the wiring WOLb
- the transistor M1b The back gate of is connected to the wiring BGLb.
- the second terminal of the capacitive element CAb is connected to the wiring CAL.
- the wiring BIL functions as a bit line
- the wiring WOLa and the wiring WOLb function as a word line.
- the wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitance element CAa and the capacitance element CAb. It is preferable to apply a low level potential to the wiring CAL when writing and reading data.
- the wiring BGLa functions as a wiring for applying a potential to the back gate of the transistor M1a
- the wiring BGLb functions as a wiring for applying a potential to the back gate of the transistor M1b.
- the threshold voltage of the transistor M1a (transistor M1b) can be increased or decreased by applying an arbitrary potential to the wiring BGLa (wiring BGLb).
- the memory unit 1471 shown in FIG. 24A corresponds to the memory unit 400 shown in FIG. 17A and the like. That is, the transistor M1a corresponds to the transistor 200a, the capacitive element CAa corresponds to the capacitive element 100a, the transistor M1b corresponds to the transistor 200b, and the capacitive element CAb corresponds to the capacitive element 100b. Further, the wiring WOLa corresponds to the conductor 260 of the transistor 200a, the wiring WOLb corresponds to the conductor 260 of the transistor 200b, and the wiring BIL corresponds to the conductor 248 and the conductor 288.
- the storage device according to the present embodiment is not limited to the memory unit 1471, and the circuit configuration can be changed.
- the back gate of the transistor M1a is not the wiring BGLa, but the back gate of the transistor M1b is not the wiring BGLb.
- the storage device according to the present embodiment may be composed of a transistor having a single gate structure, that is, a transistor M1a having no back gate and a transistor M1b, as in the memory unit 1473 shown in FIG. 24C.
- the transistor 200a is used as the transistor M1a
- the transistor 200b is used as the transistor M1b
- the capacitance element 100a is used as the capacitance element CAa
- the capacitance element 100b is used as the capacitance element CAb.
- an OS transistor as the transistor M1a and the transistor M1b
- the leakage current of the transistor M1a and the transistor M1b can be made very small. That is, since the written data can be held by the transistors M1a and M1b for a long time, the frequency of refreshing the memory cells can be reduced. Moreover, the refresh operation of the memory cell can be eliminated. Further, since the leak current is very small, multi-valued data or analog data can be held in the memory unit 1471, the memory unit 1472, and the memory unit 1473.
- the bit line can be shortened.
- the bit wire can be made shorter than by providing the conductor 248 on the oxide 230. As a result, the bit line capacity is reduced, and the holding capacity of the memory cell can be reduced.
- the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in the present embodiment are not limited to the above.
- the arrangement or function of these circuits and the wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.
- FIGS. 25A and 25B An example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown with reference to FIGS. 25A and 25B.
- a plurality of circuits (systems) are mounted on the chip 1200.
- SoC system on chip
- the chip 1200 has a CPU 1211, GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
- a bump (not shown) is provided on the chip 1200, and as shown in FIG. 25B, it is connected to the first surface of the printed circuit board (Printed Circuit Board: PCB) 1201. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the motherboard 1203.
- PCB printed Circuit Board
- the motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222.
- a storage device such as a DRAM 1221 and a flash memory 1222.
- the DOSRAM shown in the previous embodiment can be used for the DRAM 1221.
- the storage capacity of the DRAM 1221 can be increased.
- the CPU 1211 preferably has a plurality of CPU cores.
- the GPU 1212 preferably has a plurality of GPU cores.
- the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
- a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200.
- the memory the above-mentioned DOSRAM or the like can be used.
- GPU1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing and product-sum calculation. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor according to the present invention and a product-sum calculation circuit, image processing and product-sum calculation can be executed with low power consumption.
- the wiring between the CPU 1211 and the GPU 1212 can be shortened, and the data transfer from the CPU 1211 to the GPU 1212, the data transfer between the memory of the CPU 1211 and the GPU 1212, And after the calculation on the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
- the analog arithmetic unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the product-sum calculation circuit may be provided in the analog calculation unit 1213.
- the memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222.
- the interface 1215 has an interface circuit with an externally connected device such as a display device, a speaker, a microphone, a camera, and a controller.
- the controller includes a mouse, a keyboard, a game controller, and the like.
- USB Universal Serial Bus
- HDMI registered trademark
- High-Definition Multimedia Interface High-Definition Multimedia Interface
- the network circuit 1216 has a function of controlling a connection with a LAN (Local Area Network) or the like. It may also have a circuit for network security.
- LAN Local Area Network
- the above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
- the PCB 1201, the DRAM 1221 provided with the chip 1200 having the GPU 1212, and the motherboard 1203 provided with the flash memory 1222 can be referred to as the GPU module 1204.
- the GPU module 1204 Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. Further, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (take-out) game machines.
- a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), and a deep belief network (DEM) are provided by a product-sum calculation circuit using GPU1212. Since a method such as DBN) can be executed, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.
- the present embodiment shows an example of an electronic component and an electronic device in which the storage device and the like shown in the above embodiment are incorporated.
- FIG. 26A shows a perspective view of the electronic component 700 and the substrate on which the electronic component 700 is mounted (mounting substrate 704).
- the electronic component 700 shown in FIG. 26A has a storage device 720 in the mold 711. In FIG. 26A, a part is omitted in order to show the inside of the electronic component 700.
- the electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the storage device 720 by a wire 714.
- the electronic component 700 is mounted on, for example, the printed circuit board 702. A plurality of such electronic components are combined and each is electrically connected on the printed circuit board 702 to complete the mounting board 704.
- the storage device 720 has a drive circuit layer 721 and a storage circuit layer 722.
- the storage circuit layer 722 can be formed by using the 3D cell array shown in the previous embodiment.
- FIG. 26B shows a perspective view of the electronic component 730.
- the electronic component 730 is an example of SiP (System in package) or MCM (Multi Chip Module).
- the electronic component 730 is provided with an interposer 731 on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 are provided on the interposer 731.
- the electronic component 730 shows an example in which the storage device 720 is used as a wideband memory (HBM: High Bandwidth Memory). Further, as the semiconductor device 735, an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA can be used.
- HBM High Bandwidth Memory
- the package substrate 732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
- the interposer 731 a silicon interposer, a resin interposer, or the like can be used.
- the interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
- the plurality of wirings are provided in a single layer or multiple layers.
- the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrode provided on the package substrate 732.
- the interposer may be referred to as a "rewiring board” or an "intermediate board”.
- a through electrode may be provided on the interposer 731, and the integrated circuit and the package substrate 732 may be electrically connected using the through electrode.
- TSV Three Silicon Via
- interposer 731 It is preferable to use a silicon interposer as the interposer 731. Since it is not necessary to provide an active element in the silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with a resin interposer.
- the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer on which the HBM is mounted.
- the reliability is unlikely to decrease due to the difference in the expansion coefficient between the integrated circuit and the interposer. Further, since the surface of the silicon interposer is high, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
- a heat sink may be provided so as to be overlapped with the electronic component 730.
- the heat sink it is preferable that the heights of the integrated circuits provided on the interposer 731 are the same.
- the heights of the storage device 720 and the semiconductor device 735 are the same.
- an electrode 733 may be provided on the bottom of the package substrate 732.
- FIG. 26B shows an example in which the electrode 733 is formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. Further, the electrode 733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.
- the electronic component 730 can be mounted on another substrate by using various mounting methods, not limited to BGA and PGA.
- BGA Band-GPU
- PGA Stimble Pin Grid Array
- LGA Land Grid Array
- QFP Quad Flat Package
- QFJ Quad Flat J-leaded package
- QFN QuadFNeged
- the semiconductor device shown in the above embodiment is, for example, a storage device for various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.).
- the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
- the semiconductor device shown in the above embodiment can be applied to various removable storage devices such as SSD (Solid State Drive).
- 27A and 27B schematically show a configuration example of the removable storage device.
- the semiconductor device shown in the above embodiment can be processed into a packaged memory chip and used for various storage devices and removable memories.
- FIG. 27A is a schematic view of the appearance of the SSD
- FIG. 27B is a schematic view of the internal structure of the SSD.
- the SSD 1150 has a housing 1151, a connector 1152 and a substrate 1153.
- the substrate 1153 is housed in the housing 1151.
- a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153.
- the memory chip 1155 is a work memory of the controller chip 1156, and for example, the DOSRAM chip shown in the previous embodiment may be used.
- the capacity of the SSD 1150 can be increased.
- the semiconductor device according to one aspect of the present invention can be used for a processor such as a CPU or GPU, or a chip.
- 28A to 28H show specific examples of electronic devices including a processor such as a CPU or GPU, or a chip according to one aspect of the present invention.
- the GPU or chip according to one aspect of the present invention can be mounted on various electronic devices.
- electronic devices include relatively large screens such as television devices, monitors for desktop or notebook information terminals, digital signage (electronic signage), and large game machines such as pachinko machines.
- digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, sound reproduction devices, and the like can be mentioned.
- artificial intelligence can be mounted on the electronic device.
- the electronic device of one aspect of the present invention may have an antenna.
- the display unit can display images, information, and the like.
- the antenna may be used for non-contact power transmission.
- the electronic device of one aspect of the present invention includes sensors (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It may have the ability to measure voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays).
- the electronic device of one aspect of the present invention can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, and the like.
- 28A to 28H show examples of electronic devices.
- FIG. 28A illustrates a mobile phone (smartphone) which is a kind of information terminal.
- the information terminal 5100 has a housing 5101 and a display unit 5102, and as an input interface, a touch panel is provided in the display unit 5102 and buttons are provided in the housing 5101.
- the information terminal 5100 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention.
- Examples of the application using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5102, and recognizes characters and figures input by the user on the touch panel provided in the display unit 5102.
- Examples include an application displayed on the display unit 5102, an application for performing biometric authentication such as a fingerprint and a voice print, and the like.
- FIG. 28B illustrates the notebook type information terminal 5200.
- the notebook-type information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.
- the notebook-type information terminal 5200 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention.
- applications using artificial intelligence include design support software, text correction software, and menu automatic generation software. Further, by using the notebook type information terminal 5200, it is possible to develop a new artificial intelligence.
- a smartphone and a notebook-type information terminal are taken as examples of electronic devices, which are shown in FIGS. 28A and 28B, respectively, but information terminals other than the smartphone and the notebook-type information terminal can be applied.
- information terminals other than smartphones and notebook-type information terminals include PDAs (Personal Digital Assistants), desktop-type information terminals, workstations, and the like.
- FIG. 28C shows a portable game machine 5300, which is an example of a game machine.
- the portable game machine 5300 has a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, an operation key 5306, and the like.
- the housing 5302 and the housing 5303 can be removed from the housing 5301.
- the connection unit 5305 provided in the housing 5301 to another housing (not shown)
- the video output to the display unit 5304 can be output to another video device (not shown). it can.
- the housing 5302 and the housing 5303 can each function as operation units. This allows a plurality of players to play the game at the same time.
- the chips shown in the previous embodiment can be incorporated into the chips provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.
- FIG. 28D shows a stationary game machine 5400, which is an example of a game machine.
- a controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.
- a low power consumption game machine can be realized by applying the GPU or chip of one aspect of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
- the portable game machine 5300 having artificial intelligence can be realized.
- expressions such as the progress of the game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are defined by the program that the game has, but by applying artificial intelligence to the handheld game machine 5300.
- Expressions that are not limited to game programs are possible. For example, it is possible to express what the player asks, the progress of the game, the time, and the behavior of the characters appearing in the game.
- the game player can be constructed anthropomorphically by artificial intelligence. Therefore, by setting the opponent as a game player by artificial intelligence, even one player can play the game. You can play the game.
- FIGS. 28C and 28D a portable game machine and a stationary game machine are illustrated as examples of the game machine, but the game machine to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
- Examples of the game machine to which the GPU or chip of one aspect of the present invention is applied include an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a throwing machine for batting practice installed in a sports facility, and the like. Can be mentioned.
- the GPU or chip of one aspect of the present invention can be applied to a large computer.
- FIG. 28E is a diagram showing a supercomputer 5500, which is an example of a large computer.
- FIG. 28F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.
- the supercomputer 5500 has a rack 5501 and a plurality of rack mount type computers 5502.
- the plurality of computers 5502 are stored in the rack 5501. Further, the computer 5502 is provided with a plurality of substrates 5504, and the GPU or chip described in the above embodiment can be mounted on the substrate.
- the supercomputer 5500 is a large computer mainly used for scientific and technological calculations. In scientific and technological calculations, it is necessary to process a huge amount of calculations at high speed, so power consumption is high and the heat generated by the chip is large.
- the GPU or chip of one aspect of the present invention to the supercomputer 5500, a supercomputer having low power consumption can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
- a supercomputer is illustrated as an example of a large computer, but the large computer to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
- Examples of the large computer to which the GPU or chip of one aspect of the present invention is applied include a computer (server) that provides services, a large general-purpose computer (mainframe), and the like.
- the GPU or chip of one aspect of the present invention can be applied to a moving vehicle and around the driver's seat of the vehicle.
- FIG. 28G is a diagram showing the periphery of the windshield in the interior of an automobile, which is an example of a moving body.
- the display panel 5701 attached to the dashboard, the display panel 5702, the display panel 5703, and the display panel 5704 attached to the pillar are shown.
- the display panel 5701 to the display panel 5703 can provide various other information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, an air conditioner setting, and the like.
- the display items and layout displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved.
- the display panel 5701 to 5703 can also be used as a lighting device.
- the display panel 5704 can supplement the field of view (blind spot) blocked by the pillars by projecting an image from an imaging device (not shown) provided in the automobile. That is, by displaying the image from the image pickup device provided on the outside of the automobile, the blind spot can be supplemented and the safety can be enhanced. In addition, by projecting an image that complements the invisible part, safety confirmation can be performed more naturally and without discomfort.
- the display panel 5704 can also be used as a lighting device.
- the GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence
- the chip can be used, for example, in an automatic driving system of an automobile.
- the chip can be used in a system for road guidance, danger prediction, and the like.
- the display panel 5701 to the display panel 5704 may be configured to display information such as road guidance and danger prediction.
- moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc., and the chip of one aspect of the present invention is applied to these moving objects. Therefore, a system using artificial intelligence can be provided.
- FIG. 28H shows an electric refrigerator / freezer 5800, which is an example of an electric appliance.
- the electric refrigerator / freezer 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
- the electric refrigerator / freezer 5800 having artificial intelligence can be realized.
- the electric freezer / refrigerator 5800 has a function of automatically generating a menu based on the foodstuffs stored in the electric freezer / refrigerator 5800 and the expiration date of the foodstuffs, and is stored in the electric freezer / refrigerator 5800. It can have a function of automatically adjusting the temperature according to the food.
- electric refrigerators and freezers have been described as an example of electric appliances
- other electric appliances include, for example, vacuum cleaners, microwave ovens, microwave ovens, rice cookers, water heaters, IH cookers, water servers, and air conditioners including air conditioners. Examples include washing machines, dryers, and audiovisual equipment.
- the electronic device described in the present embodiment the function of the electronic device, the application example of artificial intelligence, its effect, etc. can be appropriately combined with the description of other electronic devices.
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Abstract
Description
図2は本発明の一態様に係る半導体装置の断面図である。
図3AはIGZOの結晶構造の分類を説明する図である。図3BはCAAC−IGZO膜のXRDスペクトルを説明する図である。図3CはCAAC−IGZO膜の極微電子線回折パターンを説明する図である。
図4A、図4B、図4C、図4Dは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図5A、図5B、図5C、図5Dは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図6A、図6B、図6C、図6Dは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図7A、図7B、図7C、図7Dは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図8A、図8B、図8C、図8Dは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図9A、図9B、図9C、図9Dは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図10A、図10B、図10C、図10Dは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図11A、図11B、図11C、図11Dは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図12A、図12B、図12C、図12Dは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図13は本発明の一態様に係るマイクロ波処理装置を説明する上面図である。
図14は本発明の一態様に係るマイクロ波処理装置を説明する断面図である。
図15は本発明の一態様に係るマイクロ波処理装置を説明する断面図である。
図16A、図16B、図16C、図16Dは本発明の一態様に係る半導体装置の上面図、および断面図である。
図17A、図17Bは本発明の一態様に係る半導体装置の断面図である。
図18は本発明の一態様に係る記憶装置の構成を示す断面図である。
図19は本発明の一態様に係る記憶装置の構成を示す断面図である。
図20A、図20Bは本発明の一態様に係る半導体装置の断面図である。
図21は本発明の一態様に係る半導体装置の断面図である。
図22は本発明の一態様に係る半導体装置の断面図である。
図23A、図23Bは本発明の一態様に係る記憶装置の構成例を示すブロック図である。
図24A、図24B、図24Cは本発明の一態様に係る記憶装置の構成例を示す回路図である。
図25A、図25Bは本発明の一態様に係る半導体装置の模式図である。
図26A、図26Bは本発明の一態様に係る電子部品の一例を説明する図である。
図27A、図27Bは本発明の一態様に係る記憶装置の模式図である。
図28A、図28B、図28C、図28D、図28E、図28F、図28G、図28Hは本発明の一態様に係る電子機器を示す図である。
本実施の形態では、図1乃至図17を用いて、本発明の一態様に係るトランジスタ200aおよびトランジスタ200bを有する半導体装置の一例、およびその作製方法について説明する。なお、以下において、トランジスタ200aとトランジスタ200bをまとめてトランジスタ200と呼ぶ場合がある。
図1A乃至図1Dを用いて、トランジスタ200aとトランジスタ200bを有する半導体装置の構成を説明する。図1Aは、当該半導体装置の上面図である。また、図1B乃至図1Dは、当該半導体装置の断面図である。ここで、図1Bは、図1AにA1−A2の一点鎖線で示す部位の断面図であり、トランジスタ200aおよびトランジスタ200bのチャネル長方向の断面図でもある。また、図1Cは、図1AにA3−A4の一点鎖線で示す部位の断面図であり、トランジスタ200aのチャネル幅方向の断面図でもある。また、図1Dは、図1AにA5−A6の一点鎖線で示す部位の断面図である。なお、図1Aの上面図では、図の明瞭化のために一部の要素を省いている。
図1A乃至図1Dに示すように、トランジスタ200aは、絶縁体214上の絶縁体216と、絶縁体216に埋め込まれるように配置された導電体205(導電体205a、導電体205b、および導電体205c)と、絶縁体216上、および導電体205上の絶縁体222と、絶縁体222上の絶縁体224と、絶縁体224上の酸化物230aと、酸化物230a上の酸化物230bと、酸化物230b上の、酸化物243aおよび酸化物243bと、酸化物243a上の導電体242aと、酸化物243b上の導電体242bと、酸化物230b上の絶縁体250と、絶縁体250上に位置し、酸化物230bの一部と重なる導電体260(導電体260a、および導電体260b)と、を有する。
以下では、半導体装置に用いることができる構成材料について説明する。
トランジスタ200を形成する基板としては、例えば、絶縁体基板、半導体基板、または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板(イットリア安定化ジルコニア基板など)、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムを材料とした半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えば、SOI(Silicon On Insulator)基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。
導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウム、イリジウム、ストロンチウム、ランタンなどから選ばれた金属元素、または上述した金属元素を成分とする合金か、上述した金属元素を組み合わせた合金等を用いることが好ましい。例えば、窒化タンタル、窒化チタン、タングステン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物などを用いることが好ましい。また、窒化タンタル、窒化チタン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物は、酸化しにくい導電性材料、または、酸素を吸収しても導電性を維持する材料であるため、好ましい。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。
酸化物230として、半導体として機能する金属酸化物(酸化物半導体)を用いることが好ましい。以下では、本発明に係る酸化物230に適用可能な金属酸化物について説明する。
まず、酸化物半導体における、結晶構造の分類について、図3Aを用いて説明を行う。図3Aは、酸化物半導体、代表的にはIGZO(Inと、Gaと、Znと、を含む金属酸化物)の結晶構造の分類を説明する図である。
なお、酸化物半導体は、結晶構造に着目した場合、図3Aとは異なる分類となる場合がある。例えば、酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、上述のCAAC−OS、及びnc−OSがある。また、非単結晶酸化物半導体には、多結晶酸化物半導体、擬似非晶質酸化物半導体(a−like OS:amorphous−like oxide semiconductor)、非晶質酸化物半導体、などが含まれる。
CAAC−OSは、複数の結晶領域を有し、当該複数の結晶領域はc軸が特定の方向に配向している酸化物半導体である。なお、特定の方向とは、CAAC−OS膜の厚さ方向、CAAC−OS膜の被形成面の法線方向、またはCAAC−OS膜の表面の法線方向である。また、結晶領域とは、原子配列に周期性を有する領域である。なお、原子配列を格子配列とみなすと、結晶領域とは、格子配列の揃った領域でもある。さらに、CAAC−OSは、a−b面方向において複数の結晶領域が連結する領域を有し、当該領域は歪みを有する場合がある。なお、歪みとは、複数の結晶領域が連結する領域において、格子配列の揃った領域と、別の格子配列の揃った領域と、の間で格子配列の向きが変化している箇所を指す。つまり、CAAC−OSは、c軸配向し、a−b面方向には明らかな配向をしていない酸化物半導体である。
nc−OSは、微小な領域(例えば、1nm以上10nm以下の領域、特に1nm以上3nm以下の領域)において原子配列に周期性を有する。別言すると、nc−OSは、微小な結晶を有する。なお、当該微小な結晶の大きさは、例えば、1nm以上10nm以下、特に1nm以上3nm以下であることから、当該微小な結晶をナノ結晶ともいう。また、nc−OSは、異なるナノ結晶間で結晶方位に規則性が見られない。そのため、膜全体で配向性が見られない。したがって、nc−OSは、分析方法によっては、a−like OSや非晶質酸化物半導体と区別が付かない場合がある。例えば、nc−OS膜に対し、XRD装置を用いて構造解析を行うと、θ/2θスキャンを用いたOut−of−plane XRD測定では、結晶性を示すピークが検出されない。また、nc−OS膜に対し、ナノ結晶よりも大きいプローブ径(例えば50nm以上)の電子線を用いる電子線回折(制限視野電子線回折ともいう。)を行うと、ハローパターンのような回折パターンが観測される。一方、nc−OS膜に対し、ナノ結晶の大きさと近いかナノ結晶より小さいプローブ径(例えば1nm以上30nm以下)の電子線を用いる電子線回折(ナノビーム電子線回折ともいう。)を行うと、ダイレクトスポットを中心とするリング状の領域内に複数のスポットが観測される電子線回折パターンが取得される場合がある。
a−like OSは、nc−OSと非晶質酸化物半導体との間の構造を有する酸化物半導体である。a−like OSは、鬆又は低密度領域を有する。即ち、a−like OSは、nc−OS及びCAAC−OSと比べて、結晶性が低い。また、a−like OSは、nc−OS及びCAAC−OSと比べて、膜中の水素濃度が高い。
次に、上述のCAC−OSの詳細について、説明を行う。なお、CAC−OSは材料構成に関する。
CAC−OSとは、例えば、金属酸化物を構成する元素が、0.5nm以上10nm以下、好ましくは、1nm以上3nm以下、またはその近傍のサイズで偏在した材料の一構成である。なお、以下では、金属酸化物において、一つまたは複数の金属元素が偏在し、該金属元素を有する領域が、0.5nm以上10nm以下、好ましくは、1nm以上3nm以下、またはその近傍のサイズで混合した状態をモザイク状、またはパッチ状ともいう。
続いて、上記酸化物半導体をトランジスタに用いる場合について説明する。
ここで、酸化物半導体中における各不純物の影響について説明する。
酸化物230に用いることができる半導体材料は、上述の金属酸化物に限られない。酸化物230として、バンドギャップを有する半導体材料(ゼロギャップ半導体ではない半導体材料)を用いてもよい。例えば、シリコンなどの単体元素の半導体、ヒ化ガリウムなどの化合物半導体、半導体として機能する層状物質(原子層物質、2次元材料などともいう。)などを半導体材料に用いることが好ましい。特に、半導体として機能する層状物質を半導体材料に用いると好適である。
次に、図1A乃至図1Dに示す、本発明の一態様である半導体装置の作製方法を、図4A乃至図12A、図4B乃至図12B、図4C乃至図12C、および図4D乃至図12Dを用いて説明する。
以下では、上記半導体装置の作製方法に用いることができる、マイクロ波処理装置について説明する。
以下では、図16A乃至図16Dを用いて、本発明の一態様である半導体装置の一例について説明する。
本実施の形態では、記憶装置として用いることができる半導体装置の一形態を、図17乃至図22を用いて説明する。
本発明の一態様に係る半導体装置(記憶装置)の一例を図17Aに示す。図17Aに示す半導体装置は、トランジスタ200aの上に容量素子100aが配置され、トランジスタ200bの上に容量素子100bが配置される。なお、以下において、容量素子100aおよび容量素子100bをまとめて容量素子100とよぶ場合がある。
次に、本発明の一態様に係る半導体装置(記憶装置)の一例を図18に示す。本発明の一態様の半導体装置は、図17Aに示したメモリユニット400がトランジスタ300の上方に設けられている。つまり、トランジスタ300の上方に、トランジスタ200aおよびトランジスタ200bが設けられ、トランジスタ200aおよびトランジスタ200bの上方に容量素子100aおよび容量素子100bが設けられている。なお、容量素子100、およびトランジスタ200として、上述した容量素子100、およびトランジスタ200を用いることができ、詳細な構造を参酌することができる。
トランジスタ300は、基板311上に設けられ、ゲートとして機能する導電体316、ゲート絶縁体として機能する絶縁体315、基板311の一部からなる半導体領域313、およびソース領域またはドレイン領域として機能する低抵抗領域314a、および低抵抗領域314bを有する。トランジスタ300は、pチャネル型、あるいはnチャネル型のいずれでもよい。
各構造体の間には、層間膜、配線、およびプラグ等が設けられた配線層が設けられていてもよい。また、配線層は、設計に応じて複数層設けることができる。ここで、プラグまたは配線としての機能を有する導電体は、複数の構造をまとめて同一の符号を付与する場合がある。また、本明細書等において、配線と、配線と電気的に接続するプラグとが一体物であってもよい。すなわち、導電体の一部が配線として機能する場合、および導電体の一部がプラグとして機能する場合もある。
なお、トランジスタ200に、酸化物半導体を用いる場合、酸化物半導体の近傍に過剰酸素領域を有する絶縁体が設けることがある。その場合、該過剰酸素領域を有する絶縁体と、該過剰酸素領域を有する絶縁体に設ける導電体との間に、バリア性を有する絶縁体を設けることが好ましい。
以下では、大面積基板を半導体素子ごとに分断することによって、複数の半導体装置をチップ状で取り出す場合に設けられるダイシングライン(スクライブライン、分断ライン、又は切断ラインと呼ぶ場合がある)について説明する。分断方法としては、例えば、まず、基板に半導体素子を分断するための溝(ダイシングライン)を形成した後、ダイシングラインにおいて切断し、複数の半導体装置に分断(分割)する場合がある。
本発明の一態様に係る半導体装置(記憶装置)の一例を図20、および図21に示す。
本発明の一態様に係る半導体装置(記憶装置)の一例を図22に示す。
本実施の形態では、図23A、図23Bおよび図24A乃至図24Cを用いて、本発明の一態様に係る、酸化物を半導体に用いたトランジスタ(以下、OSトランジスタと呼ぶ場合がある。)、および容量素子が適用されている記憶装置(以下、OSメモリ装置と呼ぶ場合がある。)について説明する。OSメモリ装置は、少なくとも容量素子と、容量素子の充放電を制御するOSトランジスタを有する記憶装置である。OSトランジスタのオフ電流は極めて小さいので、OSメモリ装置は優れた保持特性をもち、不揮発性メモリとして機能させることができる。
図23AにOSメモリ装置の構成の一例を示す。記憶装置1400は、周辺回路1411、およびメモリセルアレイ1470を有する。周辺回路1411は、行回路1420、列回路1430、出力回路1440、およびコントロールロジック回路1460を有する。
図24A乃至図24Cに、DRAMのメモリセルの回路構成例を示す。本明細書等において、1OSトランジスタ1容量素子型のメモリセルを用いたDRAMを、DOSRAM(Dynamic Oxide Semiconductor Random Access Memory)と呼ぶ場合がある。図24Aに示す、メモリユニット1471は、メモリセルMCaおよびメモリセルMCbを有する。ここで、メモリセルMCaはトランジスタM1aと、容量素子CAaと、を有し、メモリセルMCbは、トランジスタM1bと、容量素子CAbと、を有する。なお、トランジスタM1aおよびトランジスタM1bは、ゲート(トップゲートと呼ぶ場合がある。)、及びバックゲートを有する。
本実施の形態では、図25Aおよび図25Bを用いて、本発明の半導体装置が実装されたチップ1200の一例を示す。チップ1200には、複数の回路(システム)が実装されている。このように、複数の回路(システム)を一つのチップに集積する技術を、システムオンチップ(System on Chip:SoC)と呼ぶ場合がある。
本実施の形態は、上記実施の形態に示す記憶装置などが組み込まれた電子部品および電子機器の一例を示す。
まず、記憶装置720が組み込まれた電子部品の例を、図26Aおよび図26Bを用いて説明を行う。
本実施の形態では、先の実施の形態に示す半導体装置を用いた記憶装置の応用例について説明する。先の実施の形態に示す半導体装置は、例えば、各種電子機器(例えば、情報端末、コンピュータ、スマートフォン、電子書籍端末、デジタルカメラ(ビデオカメラも含む)、録画再生装置、ナビゲーションシステムなど)の記憶装置に適用できる。なお、ここで、コンピュータとは、タブレット型のコンピュータ、ノート型のコンピュータ、デスクトップ型のコンピュータの他、サーバシステムのような大型のコンピュータを含むものである。または、先の実施の形態に示す半導体装置は、SSD(ソリッド・ステート・ドライブ)等の各種のリムーバブル記憶装置に適用することができる。図27Aおよび図27Bにリムーバブル記憶装置の構成例を模式的に示す。例えば、先の実施の形態に示す半導体装置は、パッケージングされたメモリチップに加工され、様々なストレージ装置、リムーバブルメモリに用いることができる。
本発明の一態様に係る半導体装置は、CPUやGPUなどのプロセッサ、またはチップに用いることができる。図28A乃至図28Hに、本発明の一態様に係るCPUやGPUなどのプロセッサ、またはチップを備えた電子機器の具体例を示す。
本発明の一態様に係るGPUまたはチップは、様々な電子機器に搭載することができる。電子機器の例としては、例えば、テレビジョン装置、デスクトップ型またはノート型の情報端末用などのモニタ、デジタルサイネージ(Digital Signage:電子看板)、パチンコ機などの大型ゲーム機、などの比較的大きな画面を備える電子機器の他、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、電子ブックリーダー、携帯電話機、携帯型ゲーム機、携帯情報端末、音響再生装置、などが挙げられる。また、本発明の一態様に係るGPUまたはチップを電子機器に設けることにより、電子機器に人工知能を搭載することができる。
図28Aには、情報端末の一種である携帯電話(スマートフォン)が図示されている。情報端末5100は、筐体5101と、表示部5102と、を有しており、入力用インターフェースとして、タッチパネルが表示部5102に備えられ、ボタンが筐体5101に備えられている。
図28Cは、ゲーム機の一例である携帯ゲーム機5300を示している。携帯ゲーム機5300は、筐体5301、筐体5302、筐体5303、表示部5304、接続部5305、操作キー5306等を有する。筐体5302、および筐体5303は、筐体5301から取り外すことが可能である。筐体5301に設けられている接続部5305を別の筐体(図示せず)に取り付けることで、表示部5304に出力される映像を、別の映像機器(図示せず)に出力することができる。このとき、筐体5302、および筐体5303は、それぞれ操作部として機能することができる。これにより、複数のプレイヤーが同時にゲームを行うことができる。筐体5301、筐体5302、および筐体5303の基板に設けられているチップなどに先の実施の形態に示すチップを組み込むことができる。
本発明の一態様のGPUまたはチップは、大型コンピュータに適用することができる。
本発明の一態様のGPUまたはチップは、移動体である自動車、および自動車の運転席周辺に適用することができる。
図28Hは、電化製品の一例である電気冷凍冷蔵庫5800を示している。電気冷凍冷蔵庫5800は、筐体5801、冷蔵室用扉5802、冷凍室用扉5803等を有する。
Claims (7)
- 基板上に配置された第1の導電体と、
前記第1の導電体の上面に接して配置された酸化物と、
前記酸化物上に配置された第2の導電体、第3の導電体、および第4の導電体と、
前記第2の導電体乃至前記第4の導電体の上に配置され、第1の開口、および第2の開口が形成された第1の絶縁体と、
前記第1の開口の中に配置された第2の絶縁体と、
前記第2の絶縁体の上に配置された第5の導電体と、
前記第2の開口の中に配置された第3の絶縁体と、
前記第3の絶縁体の上に配置された第6の導電体と、を有し、
前記第3の導電体は、前記第1の導電体に重畳して配置され、
前記第1の開口は、前記第2の導電体と前記第3の導電体の間の領域に重畳して形成され、
前記第2の開口は、前記第3の導電体と前記第4の導電体の間の領域に重畳して形成される、半導体装置。 - 請求項1において、
第1の容量素子と、第2の容量素子と、を有し、
前記第1の容量素子は、前記第2の導電体と電気的に接続され、
前記第2の容量素子は、前記第4の導電体と電気的に接続される、半導体装置。 - 請求項2において、
前記第1の容量素子は、前記第2の導電体の上に配置され、
前記第2の容量素子は、前記第4の導電体の上に配置される、半導体装置。 - 請求項1乃至請求項3のいずれか一項において、
前記第1の導電体は、当該第1の導電体の下に設けられた配線に接続される、半導体装置。 - 請求項1乃至請求項4のいずれか一項において、
前記第2の絶縁体は、前記酸化物の上面、および前記第1の絶縁体の側面に接し、
前記第3の絶縁体は、前記酸化物の上面、および前記第1の絶縁体の側面に接する、半導体装置。 - 請求項1乃至請求項5のいずれか一項において、
前記酸化物は、第1の酸化物と、当該第1の酸化物上の第2の酸化物と、を有し、
前記第1の酸化物、および前記第2の酸化物は、インジウムと、元素M(Mは、ガリウム、アルミニウム、イットリウム、および錫の中から選ばれる一または複数)と、亜鉛と、を有し、
前記第1の酸化物の元素Mに対するインジウムの原子数比は、前記第2の酸化物の元素Mに対するインジウムの原子数比より小さい、半導体装置。 - 基板上に第1の導電体を形成し、
前記第1の導電体の上面に接して酸化膜を成膜し、
前記酸化膜の上に第1の導電膜を成膜し、
前記酸化膜、および前記第1の導電膜を島状に加工して、酸化物、および第2の導電体を形成し、
前記酸化物、および前記第2の導電体を覆って第1の絶縁体を形成し、
前記第1の絶縁体の一部を除去して、前記第2の導電体に重畳して第1の開口、および第2の開口を形成し、
前記第1の開口、および前記第2の開口に重畳する前記第2の導電体の一部を除去し、第3の導電体、第4の導電体、および第5の導電体を形成し、
前記第4の導電体は、前記第1の導電体に重畳して配置され、
前記酸化物は、前記第3乃至第5の導電体と重畳していない領域が露出され、
前記酸化物の上面に接して、第1の絶縁膜を成膜し、
酸素を含む雰囲気でマイクロ波処理を行い、
前記第1の絶縁膜の上に第2の導電膜を成膜し、
前記第1の絶縁膜、および前記第2の導電膜に、前記第1の絶縁体の上面が露出するまで、CMP処理を行って、前記第1の開口の中に第2の絶縁体および第6の導電体を形成し、前記第2の開口の中に第3の絶縁体および第7の導電体を形成する、半導体装置の作製方法。
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