WO2020253807A1 - 一种p/n型碳化硅欧姆接触的制备方法 - Google Patents

一种p/n型碳化硅欧姆接触的制备方法 Download PDF

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WO2020253807A1
WO2020253807A1 PCT/CN2020/096975 CN2020096975W WO2020253807A1 WO 2020253807 A1 WO2020253807 A1 WO 2020253807A1 CN 2020096975 W CN2020096975 W CN 2020096975W WO 2020253807 A1 WO2020253807 A1 WO 2020253807A1
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layer
sic
tic
silicon carbide
3tic
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PCT/CN2020/096975
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French (fr)
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夏经华
张文婷
田丽欣
吴沛飞
安运来
田亮
查祎英
吴军民
潘艳
杨霏
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全球能源互联网研究院有限公司
国家电网有限公司
国网江苏省电力有限公司电力科学研究院
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation

Definitions

  • the application belongs to the technical field of silicon carbide preparation, and relates to a method for preparing p/n-type silicon carbide ohmic contacts.
  • silicon carbide semiconductor materials have a wider forbidden band width (the theoretical value of 4H ⁇ SiC is 3.2eV), a higher breakdown electric field strength (2.2MV/cm), and High saturated electron migration rate (2.0 ⁇ 10 7 cm/s), high thermal conductivity (5.0W/cm K), excellent physical and chemical stability and other characteristics, suitable for high-power, high-voltage, Materials for manufacturing power semiconductor devices with high operating temperature and high operating frequency.
  • TiC based on both p-type and n-type silicon carbide has produced good Ohmic contact characteristics, its deposition on p-type silicon carbide directly produces ohmic contact characteristics and maintains this characteristic in the subsequent alloying heat treatment, while TiC on n-type silicon carbide also undergoes conventional alloying heat treatment. Good ohmic contact characteristics are obtained.
  • the specific contact resistances of both are within the order of 10 to 5 ⁇ cm 2 , and relatively consistent results are obtained. According to reports, the TiC/SiC ohmic contact maintains a stable state below 1400°C.
  • TiC/SiC ohmic contact was not understood. After a detailed analysis and study of the TiC/SiC ohmic contact interface, it is found that there is a Ti 3 SiC 2 component at the interface. After theoretical research, it is found that the presence of Ti 3 SiC 2 helps reduce the TiC/SiC interface With regard to the barrier height, it is believed that the generation of Ti 3 SiC 2 is the cause of the formation of TiC/SiC ohmic contact.
  • TiC deposition is obtained by sputtering Ti and C simultaneously by reactive ion co-sputtering, followed by alloying heat treatment, and forming Ti 3 SiC 2 at the TiC/SiC interface.
  • the technical problems to be solved by this application include overcoming the defects of the prior art TiC/SiC ohmic contact in terms of film uniformity and compactness, high film stress and poor step coverage, thereby providing a p /n-type silicon carbide ohmic contact preparation method.
  • This application provides a method for preparing p/n type silicon carbide ohmic contacts, including:
  • 3TiC/SiC layer, 3TiC/xSiC layer and TiC layer are sequentially formed on the silicon carbide epitaxial wafer by atomic layer deposition process;
  • a Ti 3 SiC 2 layer, a transition layer and a TiC layer are sequentially formed to obtain p/n type silicon carbide with ohmic contact characteristics;
  • 3:1 is the molar ratio of TiC to SiC in the 3TiC/SiC layer
  • x is not greater than 1, and 3:x is the molar ratio of TiC and SiC in the 3TiC/xSiC layer.
  • the 3TiC/SiC layer undergoes alloying heat treatment to form a Ti 3 SiC 2 layer; the 3TiC/xSiC layer undergoes alloying heat treatment to form a transition layer.
  • the 3TiC/SiC layer and the 3TiC/xSiC are prepared by alternately depositing TiC nano-layers and SiC nano-layers;
  • the TiC layer is prepared by depositing a TiC nano layer
  • the deposition temperature of the TiC nano-layer is 150-350°C
  • the reaction precursor A is tetrakis (dimethylamino) titanium
  • the reaction precursor B is hydrogen
  • the thickness of the TiC nano-layer is 0.1-1 nm, wherein the reaction precursor Body A and reaction precursor B react to form a TiC nano-layer;
  • the deposition temperature of the SiC nano-layer is 150-350°C
  • the reaction precursor A is dichlorodihydrosilane
  • the reaction precursor B is ethylene or acetylene
  • the thickness of the SiC nano-layer is 0.1-1 nm, wherein the reaction precursor The body A and the reaction precursor B react to form a SiC nano layer.
  • the thickness of the TiC layer is 10-100 nm
  • the thickness of the 3TiC/xSiC layer is 10-100 nm;
  • the thickness of the 3TiC/SiC layer is 10-100 nm.
  • the 3TiC/xSiC layer is adjusted by adjusting the molar ratio of TiC and SiC, according to x from 1 to 0, linearly reducing or gradient reducing the amount of SiC, alternately depositing TiC nano-layers and SiC nano-layers
  • the 3TiC/xSiC layer is obtained, and the 3TiC/SiC layer of the silicon carbide epitaxial wafer is continuously transitioned to the TiC layer.
  • the method for preparing the p/n-type silicon carbide ohmic contact further includes depositing a barrier layer on the TiC layer by an atomic layer deposition process, and the barrier layer has a thickness of 30-100 nm ;
  • the barrier layer is titanium nitride, tantalum carbide, tantalum nitride, tantalum silicide, tungsten carbide, tungsten nitride, tungsten silicide, zirconium carbide, zirconium nitride, zirconium silicide, niobium carbide or niobium nitride;
  • the deposition temperature of the barrier layer is 150-350°C;
  • the reaction precursor A is TiCl 4
  • the reaction precursor B is NH 3
  • the reaction precursor A and the reaction precursor B react to form a TiN nano-layer
  • the pretreatment includes performing sacrificial oxidation on the cleaned silicon carbide epitaxial wafer to form a sacrificial oxide layer, and then etching the sacrificial oxide layer until the sacrificial oxide on the epitaxial wafer is completely removed Finally, the surface of the epitaxial wafer after the sacrificial oxide layer is removed is subjected to a high-temperature surface treatment to form a smooth passivation surface.
  • the treatment step of the sacrificial oxidation may be, but is not limited to, performing conventional thermal dry oxygen oxidation or rapid thermal oxidation at 1100-1300°C, and the sacrificial oxidation is performed in a pure oxidizing environment,
  • the purity of O 2 is 6N;
  • the thickness of the sacrificial oxide layer (SiO 2 ) is 10-20 nm;
  • the step of etching the sacrificial oxide layer includes, at room temperature, immersing the sacrificial oxide layer in 1-50% DHF solution or BOE etching solution until the sacrificial oxide layer is completely etched and removed .
  • the high-temperature surface treatment includes performing high-temperature surface treatment on the surface of the epitaxial wafer in a H 2 or HCl gas environment; the temperature of the high-temperature surface treatment is 1200-1400° C., and the time is 0.1- 4h, the purity of H 2 or HCl is 6N.
  • the alloying heat treatment before the alloying heat treatment, it further includes the step of etching the 3TiC/SiC layer, the 3TiC/xSiC layer, the TiC layer and the barrier layer;
  • the etching method is photolithography technology, plasma dry etching technology or chemical solution wet etching technology.
  • the step of alloying heat treatment is to perform rapid alloying heat treatment at 400-1200° C. for 30-300 s under vacuum or inert atmosphere conditions.
  • the p/n type silicon carbide epitaxial wafer includes a substrate and an epitaxial layer
  • the substrate is n-type 4H-SiC or 6H-SiC, with a thickness of 300-1000 ⁇ m;
  • the substrate is a silicon carbide substrate heavily doped with nitrogen or phosphorus, with a resistivity of 0.001-0.1 ⁇ cm; or the substrate is a silicon carbide substrate doped with vanadium or not doped with any ions, with a resistivity Greater than 10 5 ⁇ cm;
  • the epitaxial layer is n-type 4H-SiC or 6H-SiC, with a thickness of 2 to 300 ⁇ m;
  • the epitaxial layer is a silicon carbide epitaxial layer doped with nitrogen or phosphorus, and the doping concentration is 1 ⁇ 10 13 to 1 ⁇ 10 16 cm -3 .
  • the steps of ion implantation and activation annealing are further included between the pre-cleaning and pre-treatment of the silicon carbide epitaxial wafer;
  • the ions injected by the ion implantation process are aluminum ions, boron ions, nitrogen ions or phosphorus ions, the ion implantation concentration is 10 18 -10 20 cm -3 , and the ion implantation depth is 0.01 to 0.1 ⁇ m;
  • the activation annealing process is to perform activation annealing activation at 1500-2000°C under an inert atmosphere, and the annealing time is 1-60 min;
  • the protective film on the surface of the silicon carbide is a carbon film with a thickness of 1-50 nm or a photoresist with a thickness of 1 to 2 ⁇ m after an ashing process.
  • the pre-cleaning includes successively performing Piranha cleaning, RCA cleaning and DHF cleaning on the silicon carbide epitaxial wafer;
  • the Piranha cleaning step includes cleaning in a Piranha solution of H 2 SO 4 and H 2 O 2 with a volume ratio of 1: (1 to 3) for 10 to 30 minutes, and the cleaning temperature is 90 to 150°C;
  • the RCA cleaning step includes cleaning in a mixed solution of NH 4 OH, H 2 O 2 and H 2 O with a volume ratio of 1:1:4 to 1:1:6 for 10 to 30 minutes, and the cleaning temperature is 60 to 80°C; or,
  • the DHF cleaning step includes cleaning in a 5-20 wt% HF aqueous solution at room temperature for 5-10 minutes.
  • the Ti 3 SiC 2 layer in this application is formed by alternately depositing TiC nano-layers and SiC nano-layers by an atomic layer deposition process, and then undergoing alloying heat treatment; the transition layer is formed by alternately depositing TiC nano-layers and SiC nano-layers by atomic layer deposition. It is formed by linearly reducing the molar ratio x of the SiC nanolayer in the TiC nanolayer and the SiC nanolayer in turn, and then undergoing alloying heat treatment;
  • the p/n-type silicon carbide ohmic contacts provided in this application can be applied to power devices with a MOS structure, including various types of power MOSFETs, IGBT devices, and PiN diodes.
  • the preparation method of p/n silicon carbide ohmic contact includes pre-cleaning and pretreatment of silicon carbide epitaxial wafers, and then using atomic layer deposition (ALD) to sequentially form 3TiC/SiC on the silicon carbide epitaxial wafers Layer, 3TiC/xSiC layer and TiC layer, after alloying heat treatment, Ti 3 SiC 2 layer, transition layer and TiC layer are sequentially formed to obtain p/n type silicon carbide with ohmic contact characteristics; this application adopts ALD, by controlling mole Compared with forming a 3TiC/SiC layer on a silicon carbide epitaxial wafer and forming a Ti 3 SiC 2 layer after alloying heat treatment, it can reduce the height of the barrier (Schottky barrier) at the interface and form an ohmic contact with the silicon carbide epitaxial wafer.
  • ALD atomic layer deposition
  • the method avoids the alloying reaction between the deposition process and the SiC wafer in the silicon carbide epitaxial wafer, and reduces the occurrence of problems such as carbon enrichment and voids; the ALD used in this application can accurately determine the composition of each layer on the atomic level. Controlled, therefore, the obtained p/n type silicon carbide ohmic contact layer has a finer structure, better film density and step coverage.
  • a 3TiC/xSiC layer can be formed between the 3TiC/SiC layer and the TiC layer, so that the 3TiC/SiC layer continuously transitions to the TiC layer, and the transition layer is formed after alloying heat treatment, which reduces The interfacial stress formed between the Ti 3 SiC 2 layer and the TiC layer due to the difference in structure improves the stability and reliability of the ohmic contact.
  • the p/n silicon carbide ohmic contact provided by the present application remains stable at a high temperature of 600° C., and has high temperature stability and reliability under long-term high temperature operation.
  • the Ti 3 SiC 2 layer is formed by alternately depositing TiC and SiC layers on the surface of the silicon carbide epitaxial wafer after alloying and heat treatment, which can avoid contact with
  • the SiC wafer in the silicon carbide epitaxial wafer undergoes alloying reaction, which reduces the occurrence of problems such as carbon enrichment and voids; after alloying heat treatment, it forms p-type and n-type silicon carbide ohmic contacts with silicon carbide.
  • the contact does not react with the silicon carbide epitaxial layer, and remains stable at a high temperature of 600°C, with high temperature stability and reliability under long-term high temperature work.
  • the preparation method of p/n silicon carbide ohmic contact provided in this application, this application adjusts the molar ratio of TiC and SiC, and linearly decreases or gradient decreases the amount of SiC according to x from 1 to 0, and alternately deposits TiC nano-layers And SiC nano layer to obtain the 3TiC/xSiC layer, so that the 3TiC/SiC layer of the silicon carbide epitaxial wafer is continuously transitioned to the TiC layer, and the transition layer is formed after alloying heat treatment, so that the Ti 3 SiC 2 layer is continuously transitioned to the TiC layer.
  • the method can reduce the interface stress formed between the Ti 3 SiC 2 layer and the TiC layer due to different structures, and improve the stability and reliability of the ohmic contact.
  • the pretreatment of silicon carbide epitaxial wafer includes sacrificial oxidation and high-temperature surface treatment, which greatly eliminates the lattice damage on the surface and near surface of silicon carbide epitaxial wafer And improve the surface smoothness, and passivate the various dangling bonds that exist on the surface, so that after the ohmic contact is formed, the interface state density at the interface is greatly reduced, the pinning effect of the Fermi level is eliminated, and the contact potential is reduced
  • the barrier height and specific contact resistance improve the ohmic (linear) contact characteristics.
  • the preparation method of p/n silicon carbide ohmic contact provided by this application can achieve a specific contact resistance of the order of 10 -5 ⁇ cm -2 by controlling the doping concentration of ions, which is especially suitable for silicon carbide
  • the source and base of power MOSFET and IGBT need to form p/n type ohmic contact at the same time, and the contact resistance is not much different.
  • This application provides that your preparation method is completed at one time in the ALD chamber, which simplifies the process, prevents harmful factors such as pollution and oxidation caused by the external environment during the process, and improves the process yield and performance stability and consistency .
  • Figure 1 is a flowchart of the preparation method in Example 1 of the present application.
  • Example 2 is a schematic diagram of the structure of the silicon carbide epitaxial layer in Example 1 of the present application;
  • FIG. 3 is a schematic diagram of the structure of silicon carbide after ion implantation and annealing in Embodiment 1 of the present application;
  • FIG. 4 is a schematic diagram of the structure of silicon carbide after a sacrificial layer is formed in Embodiment 1 of the present application;
  • Example 5 is a schematic diagram of the structure of silicon carbide after high-temperature surface treatment in Example 1 of the present application;
  • FIG. 6 is a schematic diagram of the structure of silicon carbide after completing the gate control part process in Embodiment 1 of the present application;
  • Example 7 is a schematic diagram of the structure of silicon carbide after the Ti 3 SiC 2 layer, the transition layer, the TiC layer, and the TiN barrier layer in Example 1 of the present application;
  • Embodiment 8 is a schematic diagram of the structure of silicon carbide after etching in Embodiment 1 of the present application;
  • Example 9 is a schematic diagram of the structure of silicon carbide after heat treatment in Example 1 of the present application.
  • FIG. 10 is a schematic diagram of the structure of the silicon carbide epitaxial layer in Embodiment 2 of the present application.
  • FIG. 11 is a schematic diagram of the structure of silicon carbide after ion implantation and annealing in Embodiment 2 of the present application;
  • FIG. 12 is a schematic diagram of the structure of silicon carbide after the sacrificial layer is formed in Embodiment 2 of the present application;
  • FIG. 13 is a schematic diagram of the structure of silicon carbide after high-temperature surface treatment in Embodiment 2 of the present application;
  • FIG. 14 is a schematic diagram of the structure of silicon carbide after the Ti 3 SiC 2 layer, the transition layer, the TiC layer, and the TiN barrier layer in Embodiment 2 of the present application;
  • Example 16 is a schematic diagram of the structure of silicon carbide after heat treatment in Example 2 of the present application.
  • Figure 17 is a test structure of the linear transmission length method (TLM) of specific contact resistance in the test example
  • Figure 19 is an optical microscope photograph of an n-/p-type ohmic contact TLM pattern sample in the test example
  • Figure 20 is the I-V characteristics of the n-/p-type ohmic contact TLM pattern sample in the test example
  • Fig. 21 is the R T -d characteristic of the n-/p-type ohmic contact TLM pattern in the test example.
  • This embodiment provides a method for preparing a p/n type silicon carbide ohmic contact.
  • the preparation method flow is shown in Figure 1.
  • the p/n type silicon carbide ohmic contact in this embodiment is used for a silicon carbide power DMOSFET device.
  • the specific preparation steps are include,
  • the silicon carbide epitaxial wafer 110 includes a substrate 101 and an epitaxial layer 102, as shown in Figure 2.
  • the substrate is n+ type nitrogen-doped 4H-SiC with a thickness of 380 ⁇ m and a resistivity of 0.02 ⁇ cm;
  • the epitaxial layer is an n-type phosphorus doped Doped 4H-SiC, doping concentration is 5 ⁇ 10 15 cm -3 , thickness is 10 ⁇ m;
  • the silicon carbide epitaxial wafer is pre-cleaned.
  • the pre-cleaning includes the Piranha cleaning process, the RCA cleaning process and the final DHF cleaning process.
  • the Piranha cleaning process includes H 2 SO 4 with a volume ratio of 1:1 at 90°C. Wash in a mixed solution of H 2 O 2 and H 2 O 2 for 10 minutes; the standard RCA cleaning process includes washing in a mixed solution of NH 4 OH, H 2 O 2 and H 2 O at a volume ratio of 1:1:4 at 60°C for 10 minutes; DHF The cleaning process includes cleaning in 20% HF solution for 5 minutes at room temperature;
  • Ion implantation is performed on the silicon carbide epitaxial wafer to form a well region 111, a p + base contact region (base region) 113 and an n + source contact region (source region) 112 in the epitaxial layer, as shown in Figure 3; among them, the well region 111.
  • the ion implantation is aluminum ion implantation, the implantation depth is 0.2 ⁇ m, and the implantation concentration is 1 ⁇ 10 15 cm -3 ;
  • the source region 112 is the nitrogen ion implantation area, the implantation depth is 0.05 ⁇ m, and the implantation ion concentration is 10 18 cm -3 ;
  • the base region 113 is a boron ion implantation region, the implantation depth is 0.05 ⁇ m, and the implantation ion concentration is 10 18 cm -3 ;
  • the well region, base region, and source region are protected by 30nm carbon film and argon atmosphere at 1500°C Implantation, then activation annealing, annealing time is 30min, complete ion implantation and activation annealing process; after completing the activation annealing process, use oxygen plasma etching to remove the carbon film protection;
  • the pretreatment of the silicon carbide after the ion implantation process specifically includes thermal and dry oxygen oxidation at 1100°C and pure oxygen to obtain a 10nm sacrificial oxide layer (SiO 2 ) 121, as shown in Figure 4, the oxygen purity is 6N; Then, the sacrificial oxide layer 121 is corroded in a 5% DHF solution until the sacrificial oxide layer is completely removed; then, the upper surface of the epitaxial wafer after the sacrificial oxide layer is removed is subjected to high-temperature HCl etching.
  • the HCl purity is 6N and the temperature is 1400 °C, the time is 3h, the mirror-level H passivation surface 131 with almost no physical defects is obtained, as shown in Figure 5;
  • the process includes growing through a thermal oxidation process under pure oxygen
  • the gate oxide (SiO 2 ) dielectric layer 141 obtained by annealing in a NO atmosphere, the doped polysilicon 142 grown by LPCVD, and the silicon oxide 143 obtained by oxidizing the polysilicon are finally processed by dry plasma etching or wet etching.
  • Method The gate oxide (SiO 2 ) dielectric layer 141 (in this embodiment adopts dry plasma etching), doped polysilicon 142 and silicon oxide 143 are patterned, as shown in FIG. 6, and the source region 112 and the base region are opened 113 contact window;
  • the atomic layer deposition process is used to alternately deposit SiC nano-layers 151 and TiC nano-layers 152 on the silicon carbide epitaxial wafer, as shown in Figure 7.
  • 3TiC/SiC layers 155 are formed separately from the SiC surface , 3TiC/xSiC layer 156 and TiC layer 153, see Figure 7; among them, the 3TiC/SiC layer 155 is prepared by alternately depositing TiC nano-layers 152 and SiC nano-layers 151, the number of alternations is 20 times, each deposition of 3.0nm Thick SiC/TiC nano-layer, and the molar ratio of TiC to SiC is 3:1, the thickness of the 3TiC/SiC layer 155 is 60 nm; the deposition temperature of the TiC nano-layer 152 in the 3TiC/SiC layer is 200 °C, and the reaction precursor A is Tetra(dimethyla
  • the 3TiC/xSiC layer 156 is adjusted to alternately deposit TiC nano-layers 152 and SiC nano-layers 151, and the amount of SiC is gradually reduced during the deposition process, so that the 3TiC/SiC layer 155 and TiC layer 153 on the silicon carbide epitaxial wafer
  • a transition layer 3TiC/xSiC layer 156 is formed between, and the amount of SiC is linearly reduced according to x from 0.8, 0.6, 0.4, 0.2, so that the 3TiC/xSiC layer 156 continuously transitions from the 3TiC/SiC layer 155 to the TiC layer 153;
  • 3TiC/ The thickness of the xSiC layer is 80nm; the total number of alternate depositions is 20, among which, when x is 0.8, the number of alternates is 5, each time the SiC/TiC nano-layer is 4nm thick, and the molar ratio of SiC to TiC is 4:15;
  • the deposition temperature of the TiC layer 153 is 200°C
  • the reaction precursor A is tetrakis (dimethylamino) titanium
  • the reaction precursor B is hydrogen
  • the thickness of the TiC layer 153 is 50 nm;
  • a TiN barrier layer 154 is deposited on the TiC layer 153, the reaction precursor A is TiCl 4 , the reaction precursor B is NH 3 , the deposition temperature is 200° C., and the thickness of the TiN barrier layer 154 is 100 nm;
  • the deposited silicon carbide epitaxial wafer is patterned by photolithography, as shown in Figure 8; then under vacuum conditions, the rapid alloying heat treatment is performed at 950°C for 120s to make the SiC nano-layer and TiC nano-layers interpenetrate and react to obtain single-phase homogeneous reactants Ti 3 SiC 2 layer 161 and transition layer 162, which are formed with TiC layer 163 and TiN layer 164 to obtain alloyed TiN/TiC/transition layer/Ti 3 SiC 2 Membrane 160, see Figure 9.
  • This embodiment provides a method for preparing a p/n type silicon carbide ohmic contact.
  • the p/n type silicon carbide ohmic contact in this embodiment is used for a silicon carbide power DMOSFET device.
  • the specific preparation steps include:
  • the silicon carbide epitaxial wafer 110 includes a substrate 101 and an epitaxial layer 102, as shown in Figure 2.
  • the substrate is n+ type nitrogen-doped 4H-SiC with a thickness of 380 ⁇ m and a resistivity of 0.02 ⁇ cm;
  • the epitaxial layer is an n-type phosphorus doped Doped 4H-SiC, doping concentration is 5 ⁇ 10 15 cm -3 , thickness is 10 ⁇ m;
  • the pre-cleaning includes the Piranha cleaning process, the RCA cleaning process and the final DHF cleaning process in sequence.
  • the Piranha cleaning process includes H 2 SO 4 with a volume ratio of 1:1 at 90°C. Wash in a mixed solution of H 2 O 2 and H 2 O 2 for 10 minutes; the standard RCA cleaning process includes washing in a mixed solution of NH 4 OH, H 2 O 2 and H 2 O at a volume ratio of 1:1:4 at 60°C for 10 minutes; DHF
  • the cleaning process includes cleaning in 20% HF solution for 5 minutes at room temperature;
  • Ion implantation is performed on the silicon carbide epitaxial wafer to form a well region 111, a p + base contact region (base region) 113 and an n + source contact region (source region) 112 in the epitaxial layer, as shown in Figure 3; among them, the well region 111.
  • the ion implantation is aluminum ion implantation, the implantation depth is 0.2 ⁇ m, and the implantation concentration is 1 ⁇ 10 15 cm -3 ;
  • the source region 112 is the nitrogen ion implantation area, the implantation depth is 0.05 ⁇ m, and the implantation ion concentration is 10 18 cm -3 ;
  • the base region 113 is a boron ion implantation region, the implantation depth is 0.05 ⁇ m, and the implantation ion concentration is 10 18 cm -3 ;
  • the well region, base region, and source region are protected by 30nm carbon film and argon atmosphere at 1500°C Implantation, then activation annealing, annealing time is 30min, complete ion implantation and activation annealing process; after completing the activation annealing process, use oxygen plasma etching to remove the carbon film protection;
  • the pretreatment of the silicon carbide after the ion implantation process specifically includes thermal and dry oxygen oxidation at 1100°C and pure oxygen to obtain a 10nm sacrificial oxide layer (SiO 2 ) 121, as shown in Figure 4, the oxygen purity is 6N; Then, the sacrificial oxide layer 121 is corroded in a 5% DHF solution until the sacrificial oxide layer is completely removed; then, the upper surface of the epitaxial wafer after the sacrificial oxide layer is removed is subjected to high-temperature HCl etching.
  • the HCl purity is 6N and the temperature is 1400 °C, the time is 3h, the mirror-level H passivation surface 131 with almost no physical defects is obtained, as shown in Figure 5;
  • the process includes growing through a thermal oxidation process under pure oxygen
  • the gate oxide (SiO 2 ) dielectric layer 141 obtained by annealing in a NO atmosphere, the doped polysilicon 142 grown by LPCVD, and the silicon oxide 143 obtained by oxidizing the polysilicon are finally processed by dry plasma etching or wet etching.
  • the gate oxide (SiO 2 ) dielectric layer 141 in this embodiment adopts dry plasma etching), doped polysilicon 142 and silicon oxide 143 are patterned, as shown in FIG. 6, and the source region 112 and the base region are opened 113 contact window;
  • the atomic layer deposition process is used to alternately deposit SiC nano-layers 151 and TiC nano-layers 152 on the silicon carbide epitaxial wafer, as shown in Figure 7.
  • 3TiC/SiC layers 155 are formed separately from the SiC surface , 3TiC/xSiC layer 156 and TiC layer 153, see Figure 7; among them, the 3TiC/SiC layer 155 is prepared by alternately depositing TiC nano-layers 152 and SiC nano-layers 151, the number of alternations is 20 times, each deposition of 3.0nm Thick SiC/TiC nano-layer, and the molar ratio of TiC to SiC is 3:1, the thickness of the 3TiC/SiC layer 155 is 60 nm; the deposition temperature of the TiC nano-layer 152 in the 3TiC/SiC layer is 200 °C, and the reaction precursor A is Tetra(dimethyla
  • the 3TiC/xSiC layer 156 is adjusted to alternately deposit TiC nanolayers 152 and SiC nanolayers 151 to linearly reduce the amount of SiC during the deposition process, so that the 3TiC/SiC layer 155 and TiC layer 153 on the silicon carbide epitaxial wafer
  • the transition layer 3TiC/xSiC layer 156 is formed between; the thickness of the 3TiC/xSiC layer is 80nm, the total number of alternate deposition is 20 times, x changes linearly according to 1-1/20n, n is the number of depositions;
  • the deposition temperature of the TiC nanolayer is At 200°C, the reaction precursor A is tetra(dimethylamino)titanium, and the reaction precursor B is hydrogen; the deposition temperature of the SiC nano-layer is 200°C, the reaction precursor A is SiCl 2 H 2 , and the reaction precursor B is ethylene;
  • the deposition temperature of the TiC layer 153 is 200°C
  • the reaction precursor A is tetrakis (dimethylamino) titanium
  • the reaction precursor B is hydrogen
  • the thickness of the TiC layer 153 is 50 nm;
  • a TiN barrier layer 154 is deposited on the TiC layer 153, the reaction precursor A is TiCl 4 , the reaction precursor B is NH 3 , the deposition temperature is 200° C., and the thickness of the TiN barrier layer 154 is 100 nm;
  • the deposited silicon carbide epitaxial wafer is patterned by photolithography, as shown in Figure 8; then under vacuum conditions, the rapid alloying heat treatment is performed at 950°C for 120s to make the SiC nano-layer and TiC nano-layers interpenetrate and react to obtain single-phase homogeneous reactants Ti 3 SiC 2 layer 161 and transition layer 162, which are formed with TiC layer 163 and TiN layer 164 to obtain alloyed TiN/TiC/transition layer/Ti 3 SiC 2 Membrane 160, see Figure 9.
  • This embodiment provides a method for preparing a p/n type silicon carbide ohmic contact.
  • the p/n type silicon carbide ohmic contact in this embodiment is used for a PiN diode.
  • the specific preparation steps include:
  • the silicon carbide epitaxial wafer 210 includes a substrate 201 and an epitaxial layer 202, as shown in FIG. 10.
  • the substrate 201 is an n + type nitrogen-doped 4H-SiC, having a thickness of 380 ⁇ m, the resistance was 0.02 ⁇ ⁇ cm; an epitaxial layer 202 of n-type phosphorus-doped 4H-SiC, a doping concentration of 1 ⁇ 10 14 cm - 3.
  • the thickness is 100 ⁇ m;
  • the silicon carbide epitaxial wafer is pre-cleaned.
  • the pre-cleaning includes the Piranha cleaning process, the RCA cleaning process and the final DHF cleaning process.
  • the Piranha cleaning process includes H 2 SO 4 with a volume ratio of 1:2 at 100°C. Wash in a mixed solution of H 2 O 2 and H 2 O 2 for 20 minutes; standard RCA cleaning process includes cleaning in a mixed solution of HCl, H 2 O 2 and H 2 O at a volume ratio of 1:1:5 at 60°C for 20 minutes; DHF cleaning process Including washing in 10% HF solution for 8 minutes at room temperature;
  • Ion implantation is performed on the silicon carbide epitaxial wafer to form a p + region 211 in the epitaxial layer, as shown in FIG. 11.
  • the ion implantation is aluminum ion implantation, the implantation depth is 0.05 ⁇ m, and the implantation concentration is 1 ⁇ 10 19 cm -3 ;
  • the p + zone is implanted at 1500 °C under the protection of 30nm carbon film and argon atmosphere, then activation annealing and annealing The time is 30 minutes to complete the ion implantation and activation annealing process; after completing the activation annealing process, use oxygen plasma etching to remove the carbon film protection;
  • the pretreatment of the silicon carbide surface in the ion implantation process includes thermal and dry oxygen oxidation at 1100°C and pure oxygen, and a 10nm sacrificial oxide layer (SiO 2 ) 221 is obtained on the front and back of the silicon carbide, as shown in Figure 12.
  • the oxygen purity is 6N; then, the sacrificial oxide layer 221 is corroded in a 50% DHF solution until the sacrificial oxide layer is completely removed; then, the upper surface of the epitaxial wafer after the sacrificial oxide layer is removed is subjected to high-temperature H 2 etching,
  • the purity of H 2 is 6N, the temperature is 1400°C, and the time is 2h.
  • a mirror-grade H passivation surface 231 with almost no physical defects is obtained, as shown in Figure 13;
  • the atomic layer deposition process is used to alternately deposit SiC nano-layers 231 and TiC nano-layers 232 on the upper and lower surfaces of the silicon carbide epitaxial wafer, as shown in Fig. 14.
  • 3TiC/TiC is formed from the SiC surface.
  • SiC layer 233, 3TiC/xSiC layer 234 and TiC layer 235 are shown in Fig. 14; among them, 3TiC/SiC layer 233 is prepared by alternately depositing TiC nano-layers and SiC nano-layers.
  • the number of alternations is 20 times, and each deposition is 3.0 nm SiC/TiC nano-layer, and the molar ratio of TiC to SiC is 3:1, the thickness of the 3TiC/SiC layer 233 is 60nm; the deposition temperature of the TiC nano-layer in the 3TiC/SiC layer is 200 °C, reaction precursor A Is tetrakis(dimethylamino) titanium, the reaction precursor B is hydrogen; the deposition temperature of the SiC nano layer in the 3TiC/SiC layer is 200°C, the reaction precursor A is SiCl 2 H 2 , and the reaction precursor B is ethylene;
  • the 3TiC/xSiC layer 234 is adjusted to alternately deposit TiC nano-layers and SiC nano-layers, and gradually reduce the amount of SiC during the deposition process, so that the 3TiC/SiC layer 233 and the TiC layer 235 on the silicon carbide epitaxial wafer are formed between
  • the transition layer 3TiC/xSiC layer 234 linearly reduces the amount of SiC according to x from 0.8, 0.6, 0.4, 0.2, so that the 3TiC/xSiC layer 234 continuously transitions from the 3TiC/SiC layer 233 to the TiC layer 235; 3TiC/xSiC layer 234
  • the thickness of SiC/TiC is 80nm; the total number of alternating depositions is 20, among which, when x is 0.8, the number of alternating is 5, and the SiC/TiC nano-layer thickness is 4nm each time, and the molar ratio of SiC to TiC is 4:15;
  • the deposition temperature of the TiC layer 235 is 200°C
  • the reaction precursor A is tetrakis (dimethylamino) titanium
  • the reaction precursor B is hydrogen
  • the thickness of the TiC layer 235 is 50 nm
  • a TiN barrier layer 236 is deposited on the TiC layer 235, the reaction precursor A is TiCl 4 , the reaction precursor B is NH 3 , the deposition temperature is 200° C., and the thickness of the TiN barrier layer 236 is 100 nm;
  • the ohmic contact layer 230 on the front surface of the deposited silicon carbide epitaxial wafer is patterned by photolithography technology to obtain an ohmic contact layer that meets the requirements of the electrode shape, as shown in Figure 15; and then under vacuum conditions
  • the rapid alloying heat treatment is carried out at 950°C for 120s to make the SiC nano-layer 151 and the TiC nano-layer 152 interpenetrate and react to obtain a single-phase homogeneous reactant Ti 3 SiC 2 layer 241 and transition layer 242, which are combined with the TiC layer 243,
  • the TiN layer 244 is formed to obtain an alloyed TiN/TiC/transition layer/Ti 3 SiC 2 film 240, as shown in FIG. 16.
  • the test of contact resistivity requires a special test structure.
  • the most common structure is shown in Figure 17.
  • the measured resistance (R T ) includes two contact resistances and the resistance of the semiconductor, so it satisfies:
  • R sh is the sheet resistance of the semiconductor
  • d is the distance between contacts
  • w is the contact width
  • R C is the contact resistance determined by the intercept of R T.
  • the linear transmission length L T can be obtained from the intercept of d in the figure, as shown in Figure 18.
  • the specific contact resistance ( ⁇ C ) is expressed as follows:
  • this application simultaneously fabricated TiN/TiC/Ti 3 Si x C 1+x /Ti 3 SiC 2 /4H-SiC contact structure on n-type and p-type 4H-SiC, and its TiN/TiC
  • the thickness of /Ti 3 Si x C 1+x /Ti 3 SiC 2 is 100nm/50nm/40nm/60nm respectively.
  • the specific contact resistance obtained on n-type 4H-SiC is 7.5 ⁇ 10 -5 ⁇ cm 2
  • the specific contact resistance obtained on p-type 4H-SiC is 4.4 ⁇ 10 -5 ⁇ cm 2
  • the silicon carbide epitaxial wafer of the present application has good ohmic contact characteristics.

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Abstract

一种p/n型碳化硅欧姆接触的制备方法。该方法包括对碳化硅外延片（110）进行前清洗和预处理，然后采用原子层沉积工艺在碳化硅外延片（110）上依次形成3TiC/SiC层（155）、3TiC/xSiC层（156）和TiC层（153），经合金化热处理后依次形成Ti 3SiC 2层（161）、过渡层（162）和TiC层（163），得到具有欧姆接触特性的p/n型碳化硅。

Description

一种p/n型碳化硅欧姆接触的制备方法 技术领域
本申请属于碳化硅制备技术领域，涉及一种p/n型碳化硅欧姆接触的制备方法。
背景技术
作为第三代宽禁带半导体材料的典范，碳化硅半导体材料具有较宽的禁带宽度(4H～SiC的理论值为3.2eV)、较高的击穿电场强度(2.2MV/cm)、较高的高饱和电子迁移速率(2.0×10 7cm/s)、较高的高热导率(5.0W/cm K)、极好的物理化学稳定性等特性，适合于作为大功率、高电压、高工作温度、高工作频率功率半导体器件的制造材料。
由于碳化硅的宽禁带特性，没有金属有合适的功函数可以满足形成欧姆接触的要求，使得通常金属与n-型或者p-型碳化硅的接触有着很高的肖特基势垒，因而在导电性能上呈现单向导通的肖特基特性(整流特性)。通过高温合金化处理等方法降低肖特基势垒高度，或者减薄肖特基势垒以产生显著量子隧穿效应是目前在重掺杂碳化硅上形成欧姆接触的常规工艺手段，在此基础上，基于Ni、Ti等金属在n-型碳化硅上、基于Al、W等金属在p-型碳化硅上，人们研发出高稳定、高可靠的比接触电阻在10 -5Ω·cm 2以下的欧姆接触，在碳化硅功率器件中得到广泛应用。
新一代基于全碳化硅的功率MOSFET及IGBT的出现对于碳化硅欧姆接触工艺提出了新的要求，即在p +的基区和相邻的n +源区的金属欧姆接触在工艺上需要一次形成，这就要求用相同的材料同时在p +/n +碳化硅上形成欧姆接触；而由于碳化硅的宽禁带特性，使得通常用相同的材料同时在p +/n +碳化硅上形成欧姆接触产生的导电特性和比接触电阻值有着较大的差别。
目前，基于金属Ni和Ni/Ti/Al的组合金属等在p/n碳化硅同时形成欧姆接触工艺上得到了初步应用；基于TiC在p-型和n-型碳化硅上均产生了良好的欧 姆接触特性，其在p-型碳化硅上的沉积直接产生欧姆接触特性并在随后的合金化热处理中保持了这一特性，而TiC在n-型碳化硅上在经过常规合金化热处理后也得到了良好的欧姆接触特性。经过工艺优化，两者的比接触电阻均在10 ～5Ω·cm 2数量级范围内，得到了比较一致的结果。据报道，TiC/SiC欧姆接触在1400℃以下都保持着稳定的状态。
最初，对于TiC/SiC欧姆接触的形成机理并不了解。在对TiC/SiC欧姆接触界面进行详尽的分析研究后，发现在其界面处存在有Ti 3SiC 2成分，在经过理论研究发现，Ti 3SiC 2的存在有助于降低TiC/SiC界面处的势垒高度，随认为Ti 3SiC 2的产生是导致TiC/SiC欧姆接触的形成的原因。通常，TiC的淀积是通过反应性离子共溅同时溅射Ti和C，并在其后通过合金化热处理得到，并在TiC/SiC的界面处形成Ti 3SiC 2。也有人用高温反应性离子溅射Ti的方法在n-型和p-型SiC表面上成功欧姆接触，经分析表明在其界面上出现的Ti 3SiC 2是其产生欧姆接触的原因。但由于其是在高达960℃的温度下和1×10 -6Pa等极端工艺条件下通过反应性离子溅射进行的，本身并不具有工艺的通用性，且反应性离子溅射本身带来的缺点，包括较差的成膜均匀性、较低的台阶覆盖性、较低的致密性、较高的膜应力等。
发明内容
因此，本申请要解决的技术问题包括克服现有技术中的TiC/SiC欧姆接触的成膜均匀性和致密性较差，膜应力较高和台阶覆盖性较差等缺陷，从而提供一种p/n型碳化硅欧姆接触的制备方法。
为此，本申请提供了以下技术方案。
本申请提供了一种p/n型碳化硅欧姆接触的制备方法，包括，
对碳化硅外延片进行前清洗和预处理；
采用原子层沉积工艺在碳化硅外延片上依次形成3TiC/SiC层、3TiC/xSiC层和TiC层；
经合金化热处理后依次形成Ti 3SiC 2层、过渡层和TiC层，得到具有欧姆接 触特性的p/n型碳化硅；
所述3TiC/SiC层中，3:1是3TiC/SiC层中TiC和SiC的摩尔比；
所述3TiC/xSiC层中x不大于1，3:x是3TiC/xSiC层中的TiC和SiC的摩尔比。
所述3TiC/SiC层经合金化热处理后形成Ti 3SiC 2层；所述3TiC/xSiC层经合金化热处理后形成过渡层。
在本发明的一些实施方案中，所述3TiC/SiC层和所述3TiC/xSiC是通过交替沉积TiC纳米层和SiC纳米层制备得到；
所述TiC层是通过沉积TiC纳米层制备得到；
所述TiC纳米层的沉积温度为150～350℃，反应前驱体A为四(二甲氨基)钛、反应前驱体B为氢气，所述TiC纳米层的厚度为0.1～1nm，其中，反应前驱体A和反应前驱体B发生反应形成TiC纳米层；
所述SiC纳米层的沉积温度为150～350℃，反应前驱体A为二氯二氢硅、反应前驱体B为乙烯或乙炔，所述SiC纳米层的厚度为0.1～1nm，其中，反应前驱体A和反应前驱体B发生反应形成SiC纳米层。
在本发明的一些实施方案中，所述TiC层的厚度为10～100nm；
所述3TiC/xSiC层的厚度为10～100nm；
所述3TiC/SiC层的厚度为10～100nm。
在本发明的一些实施方案中，所述3TiC/xSiC层是通过调整TiC和SiC的摩尔比，按照x从1到0，线性降低或梯度降低SiC的用量，交替沉积TiC纳米层和SiC纳米层得到所述3TiC/xSiC层，使碳化硅外延片的3TiC/SiC层连续过渡到TiC层。
在本发明的一些实施方案中，所述p/n型碳化硅欧姆接触的制备方法还包括，采用原子层沉积工艺在所述TiC层上沉积阻挡层，所述阻挡层的厚度为30～100nm；
所述阻挡层为氮化钛、碳化钽、氮化钽、硅化钽、碳化钨、氮化钨、硅化 钨、碳化锆、氮化锆、硅化锆、碳化铌或氮化铌；
所述阻挡层的沉积温度为150～350℃；
当阻挡层为氮化钛时，反应前驱体A为TiCl 4，反应前驱体B为NH 3，反应前驱体A和反应前驱体B发生反应形成TiN纳米层；
在本发明的一些实施方案中，所述预处理包括对清洗后的碳化硅外延片进行牺牲氧化形成牺牲氧化层，然后对所述牺牲氧化层进行腐蚀，直至完全去除所述外延片上的牺牲氧化层，最后对所述去除牺牲氧化层后的外延片的表面进行高温表面化处理，形成光滑的钝化表面。
在本发明的一些实施方案中，所述牺牲氧化的处理步骤可以是但不限于，在1100～1300℃下进行常规热干氧氧化或快速热氧化，所述牺牲氧化在纯氧化环境中进行，O 2纯度为6N；所述牺牲氧化层(SiO 2)的厚度为10～20nm；
在本发明的一些实施方案中，对所述牺牲氧化层进行腐蚀的步骤包括，常温下，将所述牺牲氧化层浸入1～50％的DHF溶液或BOE腐蚀液，直到牺牲氧化层完全腐蚀去除。
在本发明的一些实施方案中，所述高温表面化处理包括在H 2或HCl气体环境下对外延片的表面进行高温表面化处理；所述高温表面化处理的温度为1200～1400℃，时间为0.1～4h，H 2或HCl的纯度为6N。
在本发明的一些实施方案中，所述合金化热处理前还包括对3TiC/SiC层、3TiC/xSiC层、TiC层和阻挡层进行刻蚀的步骤；
所述刻蚀的方法为光刻技术、等离子体干法刻蚀技术或化学溶液湿法腐蚀技术。
在本发明的一些实施方案中，所述合金化热处理的步骤为，在真空或者惰性气氛条件下，在400～1200℃下进行30～300s的快速合金化热处理。
在本发明的一些实施方案中，所述p/n型碳化硅外延片包括衬底和外延层；
所述衬底为n型4H-SiC或6H-SiC，厚度为300～1000μm；
所述衬底为重掺杂氮或磷的碳化硅衬底，电阻率为0.001～0.1Ω·cm；或者 所述衬底为掺杂钒或者不掺杂任何离子的碳化硅衬底，电阻率大于10 5Ω·cm；
所述外延层为n型4H-SiC或6H-SiC，厚度为2～300μm；
所述外延层为掺杂氮或磷的碳化硅外延层，掺杂浓度为1×10 13～1×10 16cm -3。
在本发明的一些实施方案中，所述碳化硅外延片前清洗和预处理之间还包括离子注入和活化退火的步骤；
所述离子注入工艺注入的离子为铝离子、硼离子、氮离子或磷离子，离子注入浓度为10 18～10 20cm -3，离子注入深度为0.01～0.1μm；
所述活化退火工艺为，在1500～2000℃、惰性气氛下，进行活化退火激活，退火时间为1～60min；
所述活化退火时，碳化硅表面的保护膜为1～50nm的碳膜或者经过灰化工艺的1～2μm的光刻胶。
所述前清洗包括对所述碳化硅外延片依次进行Piranha清洗、RCA清洗和DHF清洗；
所述Piranha清洗的步骤包括，在体积比为1:(1～3)的H 2SO 4和H 2O 2的Piranha溶液中清洗10～30min，清洗温度为90～150℃；
所述RCA清洗的步骤包括，在体积比为1:1:4～1:1:6的NH 4OH、H 2O 2和H 2O的混合溶液中清洗10～30min，清洗温度为60～80℃；或，
在体积比为1:1:4～1:1:6的HCl、H 2O 2和H 2O的混合溶液中清洗10～30min，清洗温度为60～80℃；
所述DHF清洗的步骤包括，在室温下，5～20wt％的HF水溶液中清洗5～10min。
本申请中的Ti 3SiC 2层是采用原子层沉积工艺交替沉积TiC纳米层和SiC纳米层后，再经过合金化热处理形成的；过渡层是采用原子层沉积工艺交替沉积TiC纳米层和SiC纳米层，且依次线性降低TiC纳米层与SiC纳米层中SiC纳米层的摩尔占比x，再经过合金化热处理后形成的；
本申请提供的p/n型碳化硅欧姆接触可以应用于具有MOS结构的功率器件，包括各种类型的功率MOSFET、IGBT器件和PiN二极管等。
本申请技术方案，具有如下优点：
1.本申请提供的p/n型碳化硅欧姆接触的制备方法，包括对碳化硅外延片进行前清洗和预处理，然后采用原子层沉积工艺(ALD)在碳化硅外延片上依次形成3TiC/SiC层、3TiC/xSiC层和TiC层，经合金化热处理后依次形成Ti 3SiC 2层、过渡层和TiC层，得到具有欧姆接触特性的p/n型碳化硅；本申请采用ALD，通过控制摩尔比在碳化硅外延片上形成3TiC/SiC层，经合金化热处理后形成Ti 3SiC 2层，可以降低界面处势垒(肖特基势垒)的高度，与碳化硅外延片形成欧姆接触，该方法避免了沉积过程与碳化硅外延片中的SiC晶圆发生合金化反应，减少了碳富集和空隙等问题的出现；本申请采用的ALD可以在原子量级上对各层的组分进行精确控制，因此得到的p/n型碳化硅欧姆接触各层的结构更为精细、膜的致密性和台阶覆盖性较好。本申请通过控制TiC、SiC的摩尔比例，可以在3TiC/SiC层和TiC层之间形成3TiC/xSiC层，使3TiC/SiC层连续过渡到TiC层，经合金化热处理后形成过渡层，降低了Ti 3SiC 2层和TiC层之间因结构不同而形成的界面应力，提高了欧姆接触的稳定性和可靠性。
此外，本申请提供的p/n型碳化硅欧姆接触在600℃的高温下保持稳定，具有高温稳定性和长期高温工作下的可靠性。
2.本申请提供的p/n型碳化硅欧姆接触的制备方法，Ti 3SiC 2层是在碳化硅外延片的表面交替沉积TiC层和SiC层后经合金化热处理后形成的，可以避免与碳化硅外延片中的SiC晶圆发生合金化反应，减少了碳富集和空隙等问题的出现；经合金化热处理后，与碳化硅形成p-型和n-型碳化硅欧姆接触，该欧姆接触不与碳化硅外延层发生反应，并在600℃的高温下保持稳定，具有高温稳定性和长期高温工作下的可靠性。
3.本申请提供的p/n型碳化硅欧姆接触的制备方法，本申请通过调整TiC和SiC的摩尔比，按照x从1到0，线性降低或梯度降低SiC的用量，交替沉 积TiC纳米层和SiC纳米层得到所述3TiC/xSiC层，使碳化硅外延片的3TiC/SiC层连续过渡到TiC层，经合金化热处理后形成过渡层，使Ti 3SiC 2层连续过渡到TiC层，该方法可以降低Ti 3SiC 2层和TiC层之间因结构不同而形成的界面应力，提高欧姆接触的稳定性和可靠性。
4.本申请提供的p/n型碳化硅欧姆接触的制备方法，通过采用ALD技术在TiC层上沉积阻挡层可以确保欧姆接触在高温或高电流密度下不与封装金属发生扩散或者化学反应，确保其高温和高电流密度下的接触稳定性和可靠性。
5.本申请提供的p/n型碳化硅欧姆接触的制备方法，对碳化硅外延片的预处理包括牺牲氧化和高温表面化处理，极大地消除了碳化硅外延片表面和近表面的晶格损伤和提高了表面光滑度，并钝化了表面存在的各种悬挂键，使得在形成欧姆接触后极大地降低了界面处的界面态密度，消除了费米能级的钉扎效应，降低接触势垒高度和比接触电阻，提高欧姆(线性)接触特性。
6.本申请提供的p/n型碳化硅欧姆接触的制备方法，通过控制离子的掺杂浓度，可以欧姆接触达到10 -5Ω·cm -2数量级的比接触电阻，特别适用于诸如碳化硅功率MOSFET和IGBT的源极和基极处等需要同时形成p/n型欧姆接触并且比接触电阻相差不大的情况。本申请提供您的制备方法在ALD腔室里一次完成，简化了工艺流程，防止了工艺过程中外界环境造成的污染、氧化等有害因素，提高了工艺的良率和性能的稳定性和一致性。
附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例1中的制备方法的流程图；
图2是本申请实施例1中的碳化硅外延层的结构示意图；
图3是本申请实施例1中经离子注入工艺和退火后的碳化硅的结构示意图；
图4是本申请实施例1中形成牺牲层后的碳化硅的结构示意图；
图5是本申请实施例1中完成高温表面化处理后的碳化硅的结构示意图；
图6是本申请实施例1中的完成栅控制部分工艺后的碳化硅的结构示意图；
图7是本申请实施例1中Ti 3SiC 2层、过渡层、TiC层和TiN阻挡层后的碳化硅的结构示意图；
图8是本申请实施例1中刻蚀后的碳化硅的结构示意图；
图9是本申请实施例1中热处理后的碳化硅的结构示意图；
图10是本申请实施例2中的碳化硅外延层的结构示意图；
图11是本申请实施例2中经离子注入工艺和退火后的碳化硅的结构示意图；
图12是本申请实施例2中形成牺牲层后的碳化硅的结构示意图；
图13是本申请实施例2中完成高温表面化处理后的碳化硅的结构示意图；
图14是本申请实施例2中Ti 3SiC 2层、过渡层、TiC层和TiN阻挡层后的碳化硅的结构示意图；
图15是本申请实施例2中刻蚀后的碳化硅的结构示意图；
图16是本申请实施例2中热处理后的碳化硅的结构示意图；
图17是试验例中比接触电阻的线性传输长度方法(TLM)的测试结构；
图18是试验例中通过TLM标准测试方法测试得的相邻电极间的电阻R T与相邻电极间的间距d的关系示意图；
图19是试验例中n-/p-型欧姆接触TLM图形试样的光学显微镜照片；
图20是试验例中n-/p-型欧姆接触TLM图形试样的I-V特性；
图21是试验例中n-/p-型欧姆接触TLM图形的R T-d特性。
具体实施方式
提供下述实施例是为了更好地进一步理解本申请，并不局限于所述最佳实施方式，不对本申请的内容和保护范围构成限制。
实施例中未注明具体实验步骤或条件者，按照本领域内的文献所描述的常 规实验步骤的操作或条件即可进行。所用试剂或仪器未注明生产厂商者，均为可以通过市购获得的常规试剂产品。
实施例1
本实施例提供了一种p/n型碳化硅欧姆接触的制备方法，制备方法流程见图1，本实施例中的p/n型碳化硅欧姆接触用于碳化硅功率DMOSFET器件，具体制备步骤包括，
(1)对碳化硅外延片进行前清洗和预处理：
碳化硅外延片110包括衬底101和外延层102，见图2，衬底为n+型氮掺杂的4H-SiC，厚度为380μm，电阻率为0.02Ω·cm；外延层为n型磷掺杂的4H-SiC，掺杂浓度为5×10 15cm -3，厚度为10μm；
对碳化硅外延片进行前清洗，前清洗包括依次进行Piranha清洗工艺、RCA清洗工艺和最后DHF清洗工艺，其中，Piranha清洗工艺包括，在90℃下的体积比为1:1的H 2SO 4和H 2O 2的混合溶液中清洗10min；标准RCA清洗工艺包括在60℃下体积比为1:1:4的NH 4OH、H 2O 2和H 2O的混合溶液中清洗10min；DHF清洗工艺包括室温下在20％的HF溶液中清洗5min；
在碳化硅外延片进行离子注入，使外延层内形成阱区111、p +基极接触区(基区)113和n +源极接触区(源区)112，见图3；其中，阱区111，离子注入为铝离子注入，注入深度为0.2μm，注入浓度1×10 15cm -3；源区112为氮离子注入区域，注入深度为0.05μm，注入离子浓度为10 18cm -3；基区113为硼离子注入区域，注入深度为0.05μm，注入离子浓度为10 18cm -3；阱区、基区、源区在30nm的碳膜和氩气气氛保护下，在1500℃下进行注入，然后活化退火，退火时间为30min，完成离子注入和活化退火工艺；完成激活退火工艺后，用氧等离子体刻蚀去除碳膜保护；
对离子注入工艺后的碳化硅进行预处理，具体包括在1100℃、纯氧条件下进行热干氧氧化，得到10nm的牺牲氧化层(SiO 2)121，见图4，氧气的纯度为6N；然后，牺牲氧化层121在5％的DHF溶液中进行腐蚀反应直到完全去除 牺牲氧化层；再然后，去除牺牲氧化层后的外延片的上表面进行高温HCl腐蚀，HCl纯度在6N，温度为1400℃，时间为3h，得到表面近似无物理缺陷的镜面级H钝化表面131，见图5；
(2)采用原子层沉积工艺在碳化硅外延片上依次形成3TiC/SiC层、3TiC/xSiC层和TiC层：
因本实施例的p/n型碳化硅欧姆接触应用于SiC功率DMOSFET器件，因此需要在预处理后的碳化硅外延片上进行栅控制部分工艺，该工艺包括通过在纯氧下通过热氧化工艺生长并在NO气氛下退火得到的栅氧(SiO 2)介质层141，通过LPCVD生长的掺杂多晶硅142，以及对多晶硅氧化得到的氧化硅143，最终通过干法等离子体刻蚀或者湿法腐蚀的方法对栅氧(SiO 2)介质层141(本实施例采用干法等离子体刻蚀)、掺杂多晶硅142和氧化硅143进行图形化，如图6所示，并打开源区112和基区113接触窗口；
采用原子层沉积工艺在碳化硅外延片上交替沉积SiC纳米层151和TiC纳米层152，见图7；通过调整TiC/SiC的比例(摩尔比)，使得自SiC表面起分别形成3TiC/SiC层155、3TiC/xSiC层156和TiC层153，见图7；其中，3TiC/SiC层155是通过交替沉积TiC纳米层152和SiC纳米层151制备得到，交替次数为20次，每次淀积3.0nm厚SiC/TiC纳米层，且TiC与SiC的摩尔比为3:1，3TiC/SiC层155厚度为60nm；3TiC/SiC层中的TiC纳米层152的沉积温度为200℃，反应前驱体A为四(二甲氨基)钛、反应前驱体B为氢气；3TiC/SiC层中的SiC纳米层151的沉积温度为200℃，反应前驱体A为SiCl 2H 2、反应前驱体B为乙烯；
在图7中，3TiC/xSiC层156通过调整交替沉积TiC纳米层152和SiC纳米层151，在沉积的过程中梯度降低SiC的用量，使碳化硅外延片上的3TiC/SiC层155和TiC层153之间形成过渡层3TiC/xSiC层156，按照x从0.8、0.6、0.4、0.2，依次线性降低SiC的用量，使得3TiC/xSiC层156从3TiC/SiC层155连续过渡到TiC层153；3TiC/xSiC层的厚度为80nm；交替沉积总次数为20次，其 中，当x为0.8时，交替次数为5次，每次SiC/TiC纳米层厚4nm,SiC与TiC的摩尔比为4:15；当x为0.6时，交替次数为5次，每次SiC/TiC纳米层厚4nm,SiC与TiC的摩尔比为3:15；当x为0.4时，交替次数为5次，每次SiC/TiC纳米层厚4nm，SiC与TiC的摩尔比为2:15；当x为0.2时，交替次数为5次，每次SiC/TiC纳米层厚4nm，SiC与TiC的摩尔比为1:15；TiC纳米层的沉积温度为200℃，反应前驱体A为四(二甲氨基)钛、反应前驱体B为氢气；SiC纳米层的沉积温度为200℃，反应前驱体A为SiCl 2H 2、反应前驱体B为乙烯；
在图7中，TiC层153的沉积温度为200℃，反应前驱体A为四(二甲氨基)钛、反应前驱体B为氢气，TiC层153的厚度为50nm；
在图7中，在TiC层153上沉积TiN阻挡层154，反应前驱体A为TiCl 4、反应前驱体B为NH 3，沉积温度为200℃，TiN阻挡层154的厚度为100nm；
(3)经合金化热处理后依次形成Ti 3SiC 2层、过渡层和TiC层，得到具有欧姆接触的p/n型碳化硅：
按照接触电极形状的要求，采用光刻技术对沉积后的碳化硅外延片进行图形化处理，见图8；然后在真空条件下，950℃下进行120s的快速合金化热处理，使SiC纳米层和TiC纳米层相互渗透反应，得到单相均一的反应物Ti 3SiC 2层161和过渡层162，与TiC层163、TiN层164形成得到合金化后的TiN/TiC/过渡层/Ti 3SiC 2膜160，见图9。
实施例2
本实施例提供了一种p/n型碳化硅欧姆接触的制备方法，本实施例中的p/n型碳化硅欧姆接触用于碳化硅功率DMOSFET器件，具体制备步骤包括，
(1)对碳化硅外延片进行前清洗和预处理：
碳化硅外延片110包括衬底101和外延层102，见图2，衬底为n+型氮掺杂的4H-SiC，厚度为380μm，电阻率为0.02Ω·cm；外延层为n型磷掺杂的4H-SiC，掺杂浓度为5×10 15cm -3，厚度为10μm；
对碳化硅外延片进行前清洗，前清洗包括依次进行Piranha清洗工艺、RCA 清洗工艺和最后DHF清洗工艺，其中，Piranha清洗工艺包括，在90℃下的体积比为1:1的H 2SO 4和H 2O 2的混合溶液中清洗10min；标准RCA清洗工艺包括在60℃下体积比为1:1:4的NH 4OH、H 2O 2和H 2O的混合溶液中清洗10min；DHF清洗工艺包括室温下在20％的HF溶液中清洗5min；
在碳化硅外延片进行离子注入，使外延层内形成阱区111、p +基极接触区(基区)113和n +源极接触区(源区)112，见图3；其中，阱区111，离子注入为铝离子注入，注入深度为0.2μm，注入浓度1×10 15cm -3；源区112为氮离子注入区域，注入深度为0.05μm，注入离子浓度为10 18cm -3；基区113为硼离子注入区域，注入深度为0.05μm，注入离子浓度为10 18cm -3；阱区、基区、源区在30nm的碳膜和氩气气氛保护下，在1500℃下进行注入，然后活化退火，退火时间为30min，完成离子注入和活化退火工艺；完成激活退火工艺后，用氧等离子体刻蚀去除碳膜保护；
对离子注入工艺后的碳化硅进行预处理，具体包括在1100℃、纯氧条件下进行热干氧氧化，得到10nm的牺牲氧化层(SiO 2)121，见图4，氧气的纯度为6N；然后，牺牲氧化层121在5％的DHF溶液中进行腐蚀反应直到完全去除牺牲氧化层；再然后，去除牺牲氧化层后的外延片的上表面进行高温HCl腐蚀，HCl纯度在6N，温度为1400℃，时间为3h，得到表面近似无物理缺陷的镜面级H钝化表面131，见图5；
(2)采用原子层沉积工艺在碳化硅外延片上依次形成3TiC/SiC层、3TiC/xSiC层和TiC层：
因本实施例的p/n型碳化硅欧姆接触应用于SiC功率DMOSFET器件，因此需要在预处理后的碳化硅外延片上进行栅控制部分工艺，该工艺包括通过在纯氧下通过热氧化工艺生长并在NO气氛下退火得到的栅氧(SiO 2)介质层141，通过LPCVD生长的掺杂多晶硅142，以及对多晶硅氧化得到的氧化硅143，最终通过干法等离子体刻蚀或者湿法腐蚀的方法对栅氧(SiO 2)介质层141(本实施例采用干法等离子体刻蚀)、掺杂多晶硅142和氧化硅143进行图形化， 如图6所示，并打开源区112和基区113接触窗口；
采用原子层沉积工艺在碳化硅外延片上交替沉积SiC纳米层151和TiC纳米层152，见图7；通过调整TiC/SiC的比例(摩尔比)，使得自SiC表面起分别形成3TiC/SiC层155、3TiC/xSiC层156和TiC层153，见图7；其中，3TiC/SiC层155是通过交替沉积TiC纳米层152和SiC纳米层151制备得到，交替次数为20次，每次淀积3.0nm厚SiC/TiC纳米层，且TiC与SiC的摩尔比为3:1，3TiC/SiC层155厚度为60nm；3TiC/SiC层中的TiC纳米层152的沉积温度为200℃，反应前驱体A为四(二甲氨基)钛、反应前驱体B为氢气；3TiC/SiC层中的SiC纳米层151的沉积温度为200℃，反应前驱体A为SiCl 2H 2、反应前驱体B为乙烯；
在图7中，3TiC/xSiC层156通过调整交替沉积TiC纳米层152和SiC纳米层151，在沉积的过程中线性降低SiC的用量，使碳化硅外延片上的3TiC/SiC层155和TiC层153之间形成过渡层3TiC/xSiC层156；3TiC/xSiC层的厚度为80nm，交替沉积总次数为20次，x按照1-1/20n线性变化，n为沉积次数；TiC纳米层的沉积温度为200℃，反应前驱体A为四(二甲氨基)钛、反应前驱体B为氢气；SiC纳米层的沉积温度为200℃，反应前驱体A为SiCl 2H 2、反应前驱体B为乙烯；
在图7中，TiC层153的沉积温度为200℃，反应前驱体A为四(二甲氨基)钛、反应前驱体B为氢气，TiC层153的厚度为50nm；
在图7中，在TiC层153上沉积TiN阻挡层154，反应前驱体A为TiCl 4、反应前驱体B为NH 3，沉积温度为200℃，TiN阻挡层154的厚度为100nm；
(3)经合金化热处理后依次形成Ti 3SiC 2层、过渡层和TiC层，得到具有欧姆接触的p/n型碳化硅：
按照接触电极形状的要求，采用光刻技术对沉积后的碳化硅外延片进行图形化处理，见图8；然后在真空条件下，950℃下进行120s的快速合金化热处理，使SiC纳米层和TiC纳米层相互渗透反应，得到单相均一的反应物Ti 3SiC 2 层161和过渡层162，与TiC层163、TiN层164形成得到合金化后的TiN/TiC/过渡层/Ti 3SiC 2膜160，见图9。
实施例3
本实施例提供了一种p/n型碳化硅欧姆接触的制备方法，本实施例中的p/n型碳化硅欧姆接触用于PiN二极管，具体制备步骤包括，
(1)对碳化硅外延片进行前清洗和预处理：
碳化硅外延片210包括衬底201和外延层202，见图10。衬底201为n+型氮掺杂的4H-SiC，厚度为380μm，电阻率为0.02Ω·cm；外延层202为n型磷掺杂的4H-SiC，掺杂浓度为1×10 14cm -3，厚度为100μm；
对碳化硅外延片进行前清洗，前清洗包括依次进行Piranha清洗工艺、RCA清洗工艺和最后DHF清洗工艺，其中，Piranha清洗工艺包括，在100℃下的体积比为1:2的H 2SO 4和H 2O 2的混合溶液中清洗20min；标准RCA清洗工艺包括在60℃下体积比为1:1:5的HCl、H 2O 2和H 2O的混合溶液中清洗20min；DHF清洗工艺包括室温下在10％的HF溶液中清洗8min；
在碳化硅外延片进行离子注入，使外延层内形成p +区211，见图11。离子注入为铝离子注入，注入深度为0.05μm，注入浓度1×10 19cm -3；p +区在30nm的碳膜和氩气气氛保护下，在1500℃下进行注入，然后活化退火，退火时间为30min，完成离子注入和活化退火工艺；完成活化退火工艺后，用氧等离子体刻蚀去除碳膜保护；
对离子注入工艺的碳化硅表面进行预处理，具体包括在1100℃、纯氧条件下进行热干氧氧化，在碳化硅的正、反面得到10nm的牺牲氧化层(SiO 2)221，见图12，氧气的纯度为6N；然后，牺牲氧化层221在50％的DHF溶液中进行腐蚀反应直到完全去除牺牲氧化层；再然后，去除牺牲氧化层后的外延片的上表面进行高温H 2腐蚀，H 2纯度在6N，温度为1400℃，时间为2h，在碳化硅外延片正、背面上得到表面近似无物理缺陷的镜面级H钝化表面231，见图13；
(2)采用原子层沉积工艺在碳化硅外延片上依次形成3TiC/SiC层、 3TiC/xSiC层和TiC层：
采用原子层沉积工艺在碳化硅外延片上表面和下表面上分别交替沉积SiC纳米层231和TiC纳米层232，见图14；通过调整TiC/SiC的摩尔比，使得自SiC表面起分别形成3TiC/SiC层233、3TiC/xSiC层234和TiC层235，见图14；其中，3TiC/SiC层233是通过交替沉积TiC纳米层和SiC纳米层制备得到，交替次数为20次，每次淀积3.0nm的SiC/TiC纳米层，且满足TiC与SiC的摩尔比为3:1，3TiC/SiC层233厚度为60nm；3TiC/SiC层中的TiC纳米层的沉积温度为200℃，反应前驱体A为四(二甲氨基)钛、反应前驱体B为氢气；3TiC/SiC层中的SiC纳米层的沉积温度为200℃，反应前驱体A为SiCl 2H 2、反应前驱体B为乙烯；
图14中，3TiC/xSiC层234通过调整交替沉积TiC纳米层和SiC纳米层，在沉积的过程中逐渐降低SiC的用量，使碳化硅外延片上的3TiC/SiC层233和TiC层235之间形成过渡层3TiC/xSiC层234，按照x从0.8、0.6、0.4、0.2，依次线性降低SiC的用量，使得3TiC/xSiC层234从3TiC/SiC层233连续过渡到TiC层235；3TiC/xSiC层234的厚度为80nm；交替沉积总次数为20次，其中，当x为0.8时，交替次数为5次，每次SiC/TiC纳米层厚4nm，SiC与TiC的摩尔比为4:15；当x为0.6时，交替次数为5次，每次SiC/TiC纳米层厚4nm,SiC与TiC的摩尔比为3:15；当x为0.4时，交替次数为5次，每次SiC/TiC纳米层厚4nm,SiC与TiC的摩尔比为2:15；当x为0.2时，交替次数为5次，每次SiC/TiC纳米层厚4nm,SiC与TiC的摩尔比为1:15；TiC纳米层的沉积温度为200℃，反应前驱体A为四(二甲氨基)钛、反应前驱体B为氢气；SiC纳米层的沉积温度为200℃，反应前驱体A为SiCl 2H 2、反应前驱体B为乙烯；
图14中，TiC层235的沉积温度为200℃，反应前驱体A为四(二甲氨基)钛、反应前驱体B为氢气，TiC层235的厚度为50nm；
图14中，在TiC层235上沉积TiN阻挡层236，反应前驱体A为TiCl 4、反应前驱体B为NH 3，沉积温度为200℃，TiN阻挡层236的厚度为100nm；
(3)经合金化热处理后依次形成Ti 3SiC 2层、过渡层和TiC层，得到具有欧姆接触的p/n型碳化硅：
按照接触电极形状的要求，采用光刻技术对沉积后的碳化硅外延片在正表面的欧姆接触层230进行图形化处理，得到合乎电极形状要求的欧姆接触层，见图15；然后在真空条件下，950℃下进行120s的快速合金化热处理，使SiC纳米层151和TiC纳米层152相互渗透反应，得到单相均一的反应物Ti 3SiC 2层241和过渡层242，与TiC层243、TiN层244形成得到合金化后的TiN/TiC/过渡层/Ti 3SiC 2膜240，见图16。
试验例
欧姆接触性能的最直接的衡量方法是测试其表面接触电阻，通常用比接触电阻ρ C表征：
Figure PCTCN2020096975-appb-000001
接触电阻率的测试需要特殊的测试结构。最常见的结构如图17所示。在长方形台面结构上面，制作多个间距不同的长方形接触。用四探针(两个测量电流、两个测量电压)测量两个电极之间的电阻，并画出测得的电阻与接触间距的关系图，如图18所示。测量得到的电阻(R T)包括两个接触电阻和半导体的电阻，因此满足：
Figure PCTCN2020096975-appb-000002
其中R sh是半导体的方块电阻，d是接触之间的距离，w是接触宽度，R C是由R T的截距决定的接触电阻。线性传输长度L T可以从图中d的截距得到，如图18所示。比接触电阻(ρ C)表示如下：
ρ C＝R CL Tw
根据TLM测试方法，本申请在n-型和p-型4H-SiC上同时制作了TiN/TiC/Ti 3Si xC 1+x/Ti 3SiC 2/4H-SiC接触结构，其TiN/TiC/Ti 3Si xC 1+x/Ti 3SiC 2的厚度分别是100nm/50nm/40nm/60nm，经过图形化工艺和950℃，120s合金化热处理工 艺后，得到的欧姆接触TLM图形，其显微照片见图19。对其进行I-V特性测试，得到其I-V特性均表现为为线性的欧姆特性，如图20所示。根据TLM方法计算得到，其在n-型4H-SiC上得到的比接触电阻为7.5×10 -5Ω·cm 2，在p-型4H-SiC上得到的比接触电阻为4.4×10 -5Ω·cm 2，本申请的碳化硅外延片的欧姆接触特性好。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引申出的显而易见的变化或变动仍处于本申请创造的保护范围之中。

Claims (11)

  1. 一种p/n型碳化硅欧姆接触的制备方法，其包括，
    对碳化硅外延片进行前清洗和预处理；
    采用原子层沉积工艺在碳化硅外延片上依次形成3TiC/SiC层、3TiC/xSiC层和TiC层；和
    经合金化热处理后依次形成Ti 3SiC 2层、过渡层和TiC层，得到具有欧姆接触特性的p/n型碳化硅；
    其中所述3TiC/SiC层中，3TiC/SiC层中TiC和SiC的摩尔比是3:1；且
    所述3TiC/xSiC层中x不大于1，3TiC/xSiC层中的TiC和SiC的摩尔比是3:x。
  2. 根据权利要求1所述的方法，其中，所述3TiC/SiC层和所述3TiC/xSiC是通过交替沉积TiC纳米层和SiC纳米层制备得到；
    所述TiC层是通过沉积TiC纳米层制备得到；
    所述TiC纳米层的沉积温度为150～350℃，反应前驱体A为四(二甲氨基)钛、反应前驱体B为氢气，所述反应前驱体A和所述反应前驱体B发生反应形成所述TiC纳米层，所述TiC纳米层的厚度为0.1～1nm；
    所述SiC纳米层的沉积温度为150～350℃，反应前驱体A为二氯二氢硅、反应前驱体B为乙烯或乙炔，所述反应前驱体A和所述反应前驱体B发生反应形成所述SiC纳米层，所述SiC纳米层的厚度为0.1～1nm。
  3. 根据权利要求1或2所述的方法，其中，所述3TiC/xSiC层是通过调整TiC和SiC的摩尔比，按照x从1到0，线性降低或梯度降低SiC的用量，交替沉积TiC纳米层和SiC纳米层得到所述3TiC/xSiC层，使碳化硅外延片的3TiC/SiC层连续过渡到TiC层。
  4. 根据权利要求1-3任一项所述的方法，其中，所述TiC层的厚度为10～100nm；
    所述3TiC/xSiC层的厚度为10～100nm；
    所述3TiC/SiC层的厚度为10～100nm。
  5. 根据权利要求1-4任一项所述的方法，其还包括，采用原子层沉积工艺在所述TiC层上沉积阻挡层，所述阻挡层的厚度为30～100nm；
    所述阻挡层为氮化钛、碳化钽、氮化钽、硅化钽、碳化钨、氮化钨、硅化钨、碳化锆、氮化锆、硅化锆、碳化铌或氮化铌；
    所述阻挡层的沉积温度为150～350℃。
  6. 根据权利要求1-5任一项所述的方法，其中，所述预处理包括对清洗后的碳化硅外延片进行牺牲氧化形成牺牲氧化层，然后对所述牺牲氧化层进行腐蚀，直至完全去除所述外延片上的牺牲氧化层，最后对所述去除牺牲氧化层后的外延片的表面进行高温表面化处理，形成光滑的钝化表面。
  7. 根据权利要求6所述的方法，其中，所述高温表面化处理包括在H 2或HCl气体环境下对外延片的表面进行高温表面化处理；所述高温表面化处理的温度为1200～1400℃，时间为0.1～4h，H 2或HCl的纯度为6N。
  8. 根据权利要求1-7任一项所述的方法，其中，所述合金化热处理前还包括对3TiC/SiC层、3TiC/xSiC层、TiC层和阻挡层进行刻蚀的步骤；
    所述刻蚀的方法为光刻技术、等离子体干法刻蚀技术或化学溶液湿法腐蚀技术。
  9. 根据权利要求1-8任一项所述的方法，其中，所述合金化热处理的步骤为，在真空或者惰性气氛条件下，在400～1200℃下进行30～300s的快速合金化热处理。
  10. 根据权利要求1-9任一项所述的方法，其中，所述p/n型碳化硅外延片包括衬底和外延层；
    所述衬底为n型4H-SiC或6H-SiC，厚度为300～1000μm；
    所述衬底为重掺杂氮或磷的碳化硅衬底，电阻率为0.001～0.1Ω·cm；或者所述衬底为掺杂钒或者不掺杂任何离子的碳化硅衬底，电阻率大于10 5Ω·cm；
    所述外延层为n型4H-SiC或6H-SiC，厚度为2～300μm；
    所述外延层为掺杂氮或磷的碳化硅外延层，掺杂浓度为1×10 13～1×10 16cm -3。
  11. 根据权利要求1-10任一项所述的方法，其中，所述碳化硅外延片前清洗和预处理之间还包括离子注入和活化退火的步骤；
    所述离子注入工艺注入的离子为铝离子、硼离子、氮离子或磷离子，离子注入浓度为10 18～10 20cm -3，离子注入深度为0.01～0.1μm；
    所述活化退火工艺为，在1500～2000℃、惰性气氛下，进行活化退火激活，退火时间为1～60min；
    所述活化退火时，碳化硅表面的保护膜为1～50nm的碳膜或者经过灰化工艺的1～2μm的光刻胶。
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