WO2020248880A1 - 阵列基板及其制造方法以及显示装置 - Google Patents

阵列基板及其制造方法以及显示装置 Download PDF

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Publication number
WO2020248880A1
WO2020248880A1 PCT/CN2020/094123 CN2020094123W WO2020248880A1 WO 2020248880 A1 WO2020248880 A1 WO 2020248880A1 CN 2020094123 W CN2020094123 W CN 2020094123W WO 2020248880 A1 WO2020248880 A1 WO 2020248880A1
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Prior art keywords
transistor
wire
capacitor
gate
electrostatic protection
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PCT/CN2020/094123
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English (en)
French (fr)
Inventor
龙春平
李会
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京东方科技集团股份有限公司
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Priority to US17/255,978 priority Critical patent/US11901354B2/en
Publication of WO2020248880A1 publication Critical patent/WO2020248880A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present disclosure belongs to the field of display technology, and specifically relates to an array substrate, a manufacturing method thereof, and a display device.
  • TFT-LCD Thin Film Transistor liquid crystal display
  • an array substrate which includes: a plurality of wires on a substrate and an electrostatic protection circuit, at least some of the wires are connected by the electrostatic protection circuit, and the two wires connected to the electrostatic protection circuit are first Wire and second wire.
  • the electrostatic protection circuit includes a first transistor, a second transistor, and a first capacitor. The first electrode of the first transistor, the first electrode of the second transistor, and the gate of the second transistor are connected to the second wire, and the second electrode of the first transistor, the second electrode of the second transistor, and the gate of the first transistor are connected First wire.
  • the first capacitor is connected between the gate of the first transistor and the second wire.
  • the gate of the first transistor is located on one side of the substrate.
  • the gate insulating layer is located on a side of the gate of the first transistor away from the substrate.
  • the active layer of the first transistor is located on a side of the gate insulating layer away from the substrate.
  • the first extension of the second wire is located on the side of the active layer away from the substrate, so that the first extension of the second wire and a part of the gate of the first transistor constitute the A first capacitor, wherein the first extension of the first wire serves as the first pole piece of the first capacitor, and a part of the gate of the first transistor serves as the second pole piece of the first capacitor .
  • the electrostatic protection circuit further includes a second capacitor connected between the gate of the second transistor and the first wire.
  • the gate of the second transistor is located on one side of the substrate.
  • the gate insulating layer is located on a side of the gate of the second transistor away from the substrate.
  • the second extension portion of the first wire is located on the side of the gate insulating layer away from the substrate, so that the second extension portion of the first wire and a part of the gate of the second transistor form a joint.
  • the second capacitor wherein the second extension of the first wire is used as the first pole piece of the second capacitor, and a part of the gate of the second transistor is used as the second capacitor of the second capacitor. Pole piece.
  • the third extension of the first wire is used as the second electrode of the first transistor, and the fourth extension of the first wire is used as the second electrode of the second transistor,
  • the fifth extension of the second wire serves as the first pole of the first transistor, and the sixth extension of the second wire serves as the first pole of the second transistor.
  • the first pole of the first transistor of the electrostatic protection circuit includes a plurality of first interdigital fingers arranged at intervals and one end is electrically connected together
  • the second pole of the first transistor includes a plurality of interval arranged And a plurality of second fingers connected together at one end, each first finger is located between two adjacent second fingers, and each second finger is located between two adjacent first fingers.
  • the first pole of the second transistor of the electrostatic protection unit includes a plurality of third fingers arranged at intervals and one end is electrically connected together, and the second pole of the second transistor includes a plurality of intervals arranged. And a plurality of fourth fingers are electrically connected at one end, each third finger is located between two adjacent fourth fingers, and each fourth finger is located between two adjacent third fingers.
  • the array substrate includes a plurality of electrostatic protection circuits.
  • the first wire electrically connected to each electrostatic protection circuit is a first data line
  • the second wire electrically connected to each electrostatic protection circuit is a branch of the second data line.
  • the first data line is immediately adjacent.
  • One electrostatic protection circuit of the plurality of electrostatic protection circuits is connected between any two adjacent data lines.
  • two electrostatic protection circuits adjacent to any one data line are symmetrically arranged on both sides of the data line with the data line as a symmetry axis.
  • Two second wires branched from any data line are symmetrically arranged on both sides of the data line with the data line as a symmetry axis.
  • the array substrate includes a plurality of electrostatic protection circuits.
  • the plurality of wires also include discharge wires.
  • the first wire electrically connected to each electrostatic protection circuit is a data line, and each data line is connected to the discharge line through the electrostatic protection circuit.
  • the second wire is located between two adjacent data lines, and the multiple gates of each second transistor and the extensions of the multiple gates extend in a line to form the Discharge line, the second extension portion of each data line extends on the discharge line, so that the second extension portion of each data line and a part of the discharge line constitute a second capacitor of the electrostatic protection circuit, wherein each The second extension part of each data line serves as the first pole piece of the second capacitor, and a part of the discharge line serves as the second pole piece of the second capacitor.
  • the array substrate includes a plurality of electrostatic protection circuits.
  • the plurality of wires also include discharge wires and short-circuit bars.
  • the first wire electrically connected to each electrostatic protection circuit is a data wire or a discharge wire.
  • Each data line and the discharge line are respectively connected to the short-circuit bar through the electrostatic protection circuit.
  • one of the plurality of second conductive lines is located between the discharge line and the data line adjacent to the discharge line.
  • Each of the remaining second conductive lines in the plurality of second conductive lines is located between any two adjacent data lines.
  • the plurality of gates of each second transistor and each extension of the plurality of gates extend in a line to form the short-circuit bar.
  • the second extension part of the data line or the discharge line extends on the short-circuit bar, so that the second extension part of the data line or the discharge line and a part of the short-circuit bar constitute the second capacitor, wherein the The second extension part of the data line or the discharge line serves as the first pole piece of the second capacitor, and a part of the shorting bar serves as the second pole piece of the second capacitor.
  • the discharge line is a common electrode line.
  • a display device including the above-mentioned array substrate.
  • a method of manufacturing an array substrate wherein the array substrate includes a plurality of wires and an electrostatic protection circuit, and the electrostatic protection circuit includes a first transistor, a second transistor, and a first capacitor.
  • the method includes forming a first transistor and a second transistor such that the first electrode of the first transistor, the first electrode of the second transistor, and the gate of the second transistor are connected to a second wire of the plurality of wires, and The second electrode of the first transistor, the second electrode of the second transistor, and the gate of the first transistor are connected to the first wire of the plurality of wires; a first capacitor is formed so that the first capacitor is connected to the gate of the first transistor Between the pole and the second wire.
  • forming the first capacitor so that the first capacitor is connected between the gate of the first transistor and the second wire includes: forming the second wire so that the first extension of the second wire is Extends on the gate of the first transistor, so that the first extension of the second wire and a portion of the gate of the first transistor form the first capacitor, wherein the first extension of the second wire Part of it is used as the first pole piece of the first capacitor, and a part of the gate of the first transistor is used as the second pole piece of the first capacitor.
  • the method further includes forming a second capacitor of the electrostatic protection circuit such that the second capacitor is connected between the gate of the second transistor and the first wire.
  • forming the second capacitor so that the second capacitor is connected between the gate of the second transistor and the first wire includes forming the first wire so that the second extension of the first wire is in the second Extend on the gate of the transistor, so that the second extension of the first wire and a part of the gate of the second transistor form the second capacitor, wherein the second extension of the first wire serves as the first The first pole piece of the second capacitor, and a part of the gate of the second transistor is used as the second pole piece of the second capacitor.
  • Fig. 1a is a circuit diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 1b is a top view of the structure of the array substrate shown in FIG. 1a;
  • Fig. 1c is a circuit diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 1d is a top view of the structure of the array substrate shown in FIG. 1c;
  • FIG. 1e is a cross-sectional view of the array substrate shown in FIG. 1d taken along line AA';
  • Figure 1f is a cross-sectional view of the array substrate shown in Figure 1d taken along line BB';
  • Fig. 2a is a circuit diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 2b is a top view of the structure of the array substrate shown in FIG. 2a;
  • Fig. 2c is a circuit diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 2d is a top view of the structure of the array substrate shown in FIG. 2c;
  • Fig. 3a is a circuit diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 3b is a top view of the structure of the array substrate of FIG. 3a;
  • Fig. 4a is a circuit diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4b is a top view of the structure of the array substrate of FIG. 4a;
  • 5a to 5d are schematic diagrams of a method of manufacturing an array substrate.
  • the electrostatic protection circuit in the related art includes an electrostatic protection wire and at least one transistor.
  • the gate and drain of the transistor are both connected to a signal line in the liquid crystal display, and the source is connected to the electrostatic protection line.
  • the transistor is turned on, so that the voltage of the signal line is released to the electrostatic protection line, thereby ensuring the performance of the liquid crystal display.
  • the "same layer arrangement" of two structures means that they are formed by the same material layer, so they are in the same layer in the stacking relationship, but it does not mean that the distance between them and the substrate is equal, nor It means that they are exactly the same as the other layer structures between the substrates.
  • "unitary structure” or “unitary structure” means that the various components forming the "unitary structure” or “unitary structure” are formed of the same material as a whole or a block. Alternatively, the various parts of the "unitary structure” or the "integral structure” are in the same layer in a stacked relationship.
  • the transistors used in the electrostatic protection circuit of the array substrate of the present disclosure may all be thin film transistors.
  • the source and drain of all transistors are symmetrical, so the source and drain are interchangeable.
  • the source can be referred to as the first electrode and the drain can be referred to as the second electrode; alternatively, the drain is referred to as the first electrode and the source is referred to as the second electrode.
  • the drain of the first transistor is used as the first electrode, and the source of the first transistor is used as the second electrode; the source of the second transistor is used as the first electrode, and the drain of the second transistor is used as the second electrode. .
  • FIG. 1a is a circuit diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 1b is a top view of the structure of the array substrate shown in FIG. 1a.
  • an array substrate includes: a plurality of wires and an electrostatic protection circuit, at least some of the wires are connected by the electrostatic protection circuit, and the two wires connected to each electrostatic protection circuit are the first wires 221. And the second wire 222;
  • Each electrostatic protection circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1;
  • the first electrode of the first transistor T1, the first electrode of the second transistor T2, and the gate of the second transistor T2 are connected to the second wire 222, the second electrode of the first transistor T1, the second electrode of the second transistor T2, and the The gate of a transistor T1 is connected to the first wire 221;
  • the first capacitor C1 is connected between the gate of the first transistor T1 and the second wire 222.
  • the array substrate may include a plurality of electrostatic protection circuits, and each electrostatic protection circuit includes two transistors that are opposed and connected in parallel.
  • the two wires connected to each electrostatic protection circuit are the first wire 221 and the second wire 222 connected to the electrostatic protection circuit.
  • the electrostatic protection process of the electrostatic protection circuit is as follows: for an electrostatic protection circuit, if the second wire 222 connected to the electrostatic protection circuit is used as an electrostatic protection wire, since the electrostatic protection wire is generally grounded, the voltage of the electrostatic protection wire may be 0V. When the voltage of the first wire 221 suddenly changes greatly, the first transistor T1 or the second transistor T2 is turned on, and the voltage of the first wire 221 is released to the second wire 222 through the first transistor T1 or the second transistor T2, thereby The electrostatic protection of the first wire 221 of the electrostatic protection circuit is realized.
  • the electrostatic protection circuit shown in FIG. 1a when an instantaneously large voltage is generated in the signal line (for example, when the voltage of the first wire 221 suddenly rises), it is provided on the gate of the first transistor T1.
  • the coupling effect of the first capacitor C1 with the second wire 222 can increase the voltage of the first electrode of the first transistor T1 accordingly (but the voltage of the first electrode of the first transistor T1 cannot reach the second wire 222), thereby reducing the voltage difference between the first electrode and the second electrode of the first transistor T1, and avoiding the voltage difference between the first electrode and the second electrode of the first transistor T1 from being too large and causing the first A transistor T1 is damaged, thereby extending the life of the electrostatic protection circuit.
  • the working voltage of the first wire 221 is 5V
  • the voltage of the first electrode of the first transistor T1 becomes 4V
  • the voltage between the gate of the first transistor T1 and the first electrode The voltage difference (1V) is smaller than the threshold voltage (5V) of the first transistor T1, so the first transistor T1 is not turned on.
  • the voltage of the first electrode of the first transistor T1 is 10V
  • the voltage of the second electrode of the first transistor T1 is The voltage of the first transistor T1 is 20V
  • the voltage difference between the voltage of the gate of the first transistor T1 and the voltage of the first electrode is 10V, which is greater than the threshold voltage (5V) of the first transistor T1, so the first transistor T1 conducts
  • the voltage difference between the voltage of the first electrode and the voltage of the second electrode of the first transistor T1 is 10V, which is different from the case where the first capacitor C1 is not provided (in this case, the first electrode
  • the voltage difference between the voltage of the second electrode and the voltage of the second electrode is 20V).
  • the voltage difference between It is damaged because the voltage difference between the voltage of the first electrode and the voltage of the second electrode is too large.
  • the working voltage of the first wire 221 suddenly decreases to -20V. Due to the coupling effect of the first capacitor C1, the voltage of the gate of the second transistor T2 and the voltage of the first electrode are both -10V, and the second transistor T2 The second electrode voltage of the second transistor T2 is -20V; at this time, the voltage difference between the gate and the second electrode of the second transistor T2 is 10V, which is greater than the threshold voltage (5V) of the second transistor T2, and the second transistor T2 is turned on to achieve static electricity Protection; At this time, the voltage difference between the voltage of the first electrode and the voltage of the second electrode of the second transistor T2 is 10V, which is different from the case where the first capacitor C1 is not provided (in this case, the first electrode and the second electrode The voltage difference between the electrodes is 20V). Compared with the voltage difference between the voltage of the first electrode and the voltage of the second electrode of the second transistor T2, the voltage difference between the first electrode and the second electrode of the second transistor T2 is avoided. The voltage difference is too large and
  • FIG. 1b is a top view of the structure of the array substrate shown in FIG. 1a.
  • the first transistor T1 and the second transistor T2 shown in the block in FIG. 1b are structural diagrams of the first transistor T1 and the second transistor T2 in FIG. 1a, and the first capacitor C1 shown in the block in FIG. 1b is The structure diagram of the first capacitor C1 in FIG. 1a.
  • Fig. 1c is a circuit diagram of an array substrate according to an embodiment of the present disclosure. As shown in FIG. 1c, except that each electrostatic protection circuit also includes a second capacitor C2, the circuit diagram of the array substrate shown in FIG. 1c is basically the same as the circuit diagram of the array substrate shown in FIG. 1a.
  • the second capacitor C2 is connected between the gate of the second transistor T2 and the first wire 221.
  • Each electrostatic protection circuit includes two transistors T1, T2 and two capacitors C1, C2.
  • the working process of the electrostatic protection circuit including the two capacitors C1 and C2 is similar to the working process of the above electrostatic protection circuit, so it will not be described in detail.
  • the coupling effect of two capacitors is greater than that of one capacitor, so that the voltage difference between the first electrode and the second electrode of the first transistor T1 and the first electrode and the second electrode of the second transistor T2 can be better reduced.
  • the voltage difference therebetween realizes the protection of the first transistor T1 and the second transistor T2 to a greater extent, thereby further ensuring the performance of the electrostatic protection circuit.
  • FIG. 1d is a top view of the structure of the array substrate shown in FIG. 1c.
  • Fig. 1d shows the structure of the second capacitor C2. Except that the electrostatic protection circuit also includes a second capacitor C2, the structure of the array substrate shown in FIG. 1d is basically the same as that of the array substrate shown in FIG. 1b.
  • Fig. 1e is a cross-sectional view taken along the line AA' in Fig. 1d.
  • the electrostatic protection circuit of the array substrate of this embodiment includes: a substrate 1, a first transistor T1 and a second transistor T2 formed on the substrate 1.
  • the first gate 211d of the first transistor T1 and the second gate 212d of the second transistor T2 are both located on the substrate 1.
  • the gate insulating layer 2 is located on a side of the first gate 211d and the second gate 212d away from the substrate 1, and covers the first gate 211d and the second gate 212d;
  • the first active layer 211c of the first transistor T1 is located on the side of the gate insulating layer 2 away from the substrate 1, and the orthographic projection of the first active layer 211c on the substrate 1 is the same as that of the first gate 211d on the substrate 1.
  • the projections overlap (for example, complete overlap).
  • the second active layer 212c of the second transistor T2 is located on the side of the gate insulating layer 2 away from the substrate, and the orthographic projection of the second active layer 212c on the substrate 1 and the orthographic projection of the second gate 212d on the substrate 1 Overlap (for example, complete overlap).
  • the first electrode 211a of the first transistor T1 and the first electrode 212a of the second transistor T2 are connected to the second wire 222 and form an integral structure or a whole with the second wire 222.
  • an extension portion (ie, the fifth extension portion) of the second wire 222 extends to the left to form the first electrode 211a of the first transistor T1
  • another extension portion of the second wire 222 ie, The sixth extension part
  • the first electrode 211a of the first transistor T1 is located on the side of the first active layer 211c away from the substrate.
  • the second wire 222 is electrically connected to the second gate 212d of the second transistor T2 through the gate insulating layer 2, the data line 222, the through holes in the passivation layer 3 and the through holes in the passivation layer 3.
  • the first electrode 212a of the second transistor T2 is located on the side of the second active layer 212c away from the substrate, and passes through the gate insulating layer 2, the data line 222, the through holes in the passivation layer 3, and the through holes in the passivation layer 3.
  • the hole is electrically connected to the second gate 212d of the second transistor T2.
  • the second electrode 212b of the second transistor T2 is located on the side of the second active layer 212c away from the substrate 1.
  • the second electrode 211b of the first transistor T1 is located on the side of the first active layer 211c away from the substrate 1, and passes through the gate insulating layer 2 through the through hole in the passivation layer 3 and the first gate 211d of the first transistor T1 Electric connection.
  • the second electrode 211b of the first transistor T1 and the second electrode 212b of the second transistor T2 are connected to the first wire 221 and form an integral structure or an integral structure with the first wire 221.
  • an extension portion (ie, the third extension portion) of the first wire 221 extends to the right to form the second electrode 211b of the first transistor T1
  • another extension portion of the first wire 221 ie, The fourth extension portion
  • Fig. 1f is a cross-sectional view taken along the line BB' in Fig. 1d.
  • the first electrode 211a of the first transistor T1 is located on the side of the first active layer 211c away from the substrate 1.
  • the second wire 222 and the first electrode 211a of the first transistor T1 are an integral structure.
  • the extension portion of the second wire 222 (ie, the first extension portion E1) extends on the gate 211d of the first transistor T1.
  • the first extension portion E1 of the second wire 222 is located on the side of the first active layer 211c of the first transistor T1 away from the substrate 1.
  • the first extension E1 of the second wire 222 and a part of the gate 211d of the first transistor T1 form the first capacitor C1, as shown in the box.
  • the first extension E1 of the second wire 222 serves as the first pole piece of the first capacitor C1, and a part of the gate 211d of the first transistor T1 serves as the second pole of the first capacitor C1 sheet.
  • the second electrode 211b of the first transistor T1 is located on the side of the active layer 211c of the first transistor T1 away from the substrate 1.
  • the second electrode 211b of the first transistor T1 is connected to the gate 211d of the first transistor T1 through the gate insulating layer 2, the data line 222, the through holes in the passivation layer 3 and the through holes in the passivation layer 3.
  • the extension portion of the first wire 221 extends from the first wire 221 and extends on the gate 212d of the second transistor T2.
  • the second extension portion E2 of the first wire 221 is located on the side of the gate insulating layer 2 away from the substrate 1, so that the second extension portion E2 of the first wire 221 and the second transistor T2 A portion of the gate 212d of 212 forms the second capacitor C2, as shown in the box.
  • the second extension E2 of the first wire 221 serves as the first pole piece of the second capacitor C2, and a part of the gate 212d of the second transistor T2 serves as the second pole of the second capacitor C2 sheet.
  • the first electrode 211a of the first transistor includes a plurality of first interdigital fingers that are spaced apart and electrically connected to each other
  • the second electrode 211b of the first transistor includes spaced and In the plurality of second fingers that are electrically connected to each other, at least part of the first fingers is located between adjacent second fingers, and at least part of the second fingers is located between adjacent first fingers.
  • the plurality of first fingers and the plurality of second fingers are arranged alternately at intervals.
  • each first finger is located between two adjacent second fingers, and each second finger is located between two adjacent first fingers.
  • the first electrode 212a of the second transistor T2 includes a plurality of third fingers arranged at intervals and electrically connected to each other, and the second electrode 212b of the second transistor T2 includes a plurality of fourth fingers arranged at intervals and electrically connected to each other, at least partially
  • the third finger is located between adjacent fourth fingers, and at least part of the fourth finger is located between adjacent third fingers.
  • the plurality of third fingers and the plurality of fourth fingers are alternately arranged at intervals.
  • each third finger is located between adjacent fourth fingers, and each fourth finger is located between adjacent third fingers.
  • the first electrode 211a and the second electrode 211b of the first transistor are interdigitated electrode structures arranged to cross each other and spaced apart; the first electrode 212a and the second electrode 212b of the second transistor T2 are arranged to cross each other and are spaced apart Interdigital electrode structure.
  • the interdigital electrode structure of the first transistor T1 and the interdigital electrode structure of the second transistor T2 make the conduction of the first electrode 211a and the second electrode 211b of the first transistor T1 more uniform, and the first electrode 212a and the second electrode 212a of the second transistor T2
  • the conduction of the second pole 212b is more uniform, thereby avoiding damage to the transistor to a greater extent, and further improving the performance and service life of the electrostatic protection circuit.
  • the second wire 222, the first extension E1 of the second wire 222, the first electrode 211a of the first transistor T1, the first electrode 212a of the second transistor T2, and the first electrode of the first capacitor C1 The film is a one-piece structure.
  • the gate 211d of the first transistor T1 and the second pole piece of the first capacitor C1 have an integral structure.
  • the second pole 211b of the first transistor T1, the second pole 212b of the second transistor T2, the first wire 221, the first extension portion E1 of the first wire 221, and the first pole piece of the second capacitor C2 are an integral structure.
  • the gate 212d of the second transistor T2 and the second pole piece of the second capacitor C2 are integrated.
  • the second wire 222, the first extension E1 of the second wire 222, the first pole piece of the first capacitor C1, the first pole 211a of the first transistor T1, and the first pole 212a of the second transistor T2 are arranged in the same layer.
  • the second pole piece of the first capacitor C1 and the gate 211d of the first transistor T1 are arranged in the same layer.
  • the first wire 221, the second extension E2 of the first wire 221, the first pole piece of the second capacitor C2, the second pole 211b of the first transistor T1, and the second pole 212b of the second transistor T2 are arranged in the same layer.
  • the second pole piece of the second capacitor C2 and the gate 212d of the second transistor T2 are arranged in the same layer.
  • the first extension E1 of the second wire 222 is used as or formed as a first pole piece of the first capacitor C1, and a part of the gate 211d of the first transistor T1 is used or formed as a second pole piece of the first capacitor C1.
  • the second extension E2 of the first wire 221 is used as or formed as a first pole piece of the second capacitor C2, and a part of the gate 212d of the second transistor T2 is used or formed as a second pole piece of the second capacitor C2.
  • the above arrangement of the first capacitor C1 and the second capacitor C2 does not complicate the manufacturing steps of the array substrate of this embodiment, but enables the array substrate of this embodiment to be more complex without increasing the complexity of the manufacturing steps. Good to ensure the performance of the electrostatic protection circuit.
  • the wire may be a data wire.
  • Fig. 2a is a circuit diagram of an array substrate according to an embodiment of the present disclosure
  • Fig. 2b is a top view of a structure of an array substrate according to an embodiment of the present disclosure.
  • this embodiment provides an array substrate, which includes a plurality of wires and an electrostatic protection circuit.
  • Each of the multiple wires is a data line. At least part of the wires are connected by electrostatic protection circuits, and the two wires connected to each electrostatic protection circuit are the first data line 23-1 and the second data line 23-2.
  • each electrostatic protection circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1;
  • the first electrode 211a of the first transistor T1, the gate electrode 212d of the second transistor T2, and the first electrode of the second transistor T2 212a is connected to the second data line 23-2.
  • the second electrode 211b of the first transistor T1, the second electrode 212b of the second transistor T2, and the gate 211d of the first transistor T1 are connected to the first data line 23-1.
  • the first capacitor C1 is connected between the gate 211d of the first transistor T1 and the second data line 23-2.
  • the first electrode 211a of the first transistor T1, the gate electrode 211d of the first transistor T1, and the first electrode of the second transistor T2 212a is connected to the third data line 23-3;
  • the second electrode 211b of the first transistor T1, the second electrode 212b of the second transistor T2, and the gate 212d of the second transistor T2 are connected to the second data line 23-2.
  • the first capacitor C1 is connected between the gate 211d of the first transistor T1 and the second data line 23-2.
  • the structure of the electrostatic protection circuit between the third data line 23-3 and the fourth data line 23-4 is basically the same as the structure of the electrostatic protection circuit between the first data line 23-1 and the second data line 23-2 , So I won’t repeat it.
  • the two electrostatic protection circuits connected to any one data line take the data line as an axis and are arranged axisymmetrically on both sides of the data line.
  • each electrostatic protection circuit includes a first transistor T1, a second transistor T2, a first capacitor C1, and a second capacitor C2. Except that each electrostatic protection circuit includes a second capacitor C2, the electrostatic protection circuit in the array substrate shown in FIG. 2c is basically the same as the electrostatic protection circuit in the array substrate shown in FIG. 2a.
  • all the wires 23-1, 23-2, 23-3, and 23-4 are data lines.
  • FIGS. 2a and 2c The structure of the electrostatic protection circuit in the array substrate of FIG. 1 is basically the same as the structure of the electrostatic protection circuit in the array substrate shown in FIG. 1a and FIG.
  • the array substrate includes a plurality of electrostatic protection units and a plurality of data lines 23-1, 23-2, 23-3, 23-4 and so on.
  • a plurality of data lines are arranged in sequence according to the number, and an electrostatic protection circuit is connected between any two adjacent data lines.
  • the odd-numbered data lines 23-1, 23-3 are not branched, and the even-numbered data lines 23-2, 23-4 are branched into two second conductive lines 222.
  • An electrostatic protection unit is electrically connected between two adjacent second wires 222 and the data line 23-1.
  • the second wire 222 is located between any two adjacent data lines 23-1 and 23-2.
  • the extension portion (ie, the first extension portion E1) of the second wire 222 extends on the gate 211d of the first transistor T1, so that the first extension portion E1 of the second wire 222 is connected to the first extension portion E1 of the first transistor T1.
  • a part of the gate 211d of the transistor T1 constitutes the first capacitor C1, wherein the first extension E1 of the second wire 222 serves as the first pole piece of the first capacitor C1, and the first transistor T1 A part of the gate 211d is used as the second pole piece of the first capacitor C1.
  • the extension portion (ie, the second extension portion E2) of the data line 23-1 connected to the electrostatic protection circuit extends on the gate 212d of the second transistor T2, so that the data line 23-2
  • the second extension E2 and a part of the gate 212d of the second transistor T2 constitute the second capacitor C2, wherein the second extension E2 of the data line 23-2 serves as the second capacitor C2.
  • One pole piece, and a part of the gate 212d of the second transistor T2 serves as a second pole piece of the second capacitor C2.
  • One extension of the data line 23-1 (ie, the third extension E3) serves as the second electrode 211b of the first transistor T1, and the other extension of the data line 23-1 (ie, the second The four extension part E4) serves as the second pole 212b of the second transistor T2.
  • One extension of the second wire 222 (ie, the fifth extension E5) serves as the first electrode 211a of the first transistor T1, and the other extension of the second wire 222 (ie, the sixth extension)
  • the part E6) serves as the first pole 212a of the second transistor T2.
  • the data line 23-1, the second extension portion E2 of the data line 23-1, the second electrode 211b of the first transistor T1 of the electrostatic protection circuit, and the second electrode 212b of the second transistor T2 are an integral structure.
  • the second wire 2, the first extension portion E1 of the second wire electrically connected to the electrostatic protection circuit, the first electrode 211a of the first transistor T1, and the first electrode 212a of the second transistor T2 are integrated structure.
  • the main difference between the array substrate of this embodiment and the array substrate of the previous embodiment is that the multiple wires 23-1, 23-2, 23-3, 23-4 are all data lines, and any two adjacent data lines Connected via electrostatic protection circuit.
  • the electrostatic protection circuit is connected between two adjacent data lines 23. When the voltage of one of the data lines suddenly rises, the voltage will be discharged to the other data line connected to the electrostatic protection circuit through the first transistor T1 or the second transistor T2.
  • each data line can be used as an electrostatic protection line for another data line connected to it through an electrostatic protection circuit.
  • the array substrate of this embodiment does not need to be provided with a special electrostatic protection line, and can also be used for electrostatic protection.
  • the circuit achieves a good electrostatic protection effect.
  • the wiring arrangement of the electrostatic protection circuit of this embodiment is simpler, and the manufacturing is simpler.
  • Fig. 3a is a circuit diagram of an array substrate according to an embodiment of the present disclosure
  • Fig. 3b is a top view of the structure of the array substrate of Fig. 3a.
  • this embodiment provides an array substrate, which includes a plurality of data lines, discharge lines, and an electrostatic protection circuit. At least part of the wires are connected by electrostatic protection circuits, and the two wires connected to each electrostatic protection circuit are the data line 23 and the discharge line 24 respectively.
  • Each electrostatic protection circuit includes a first transistor T1, a second transistor T2, a first capacitor C1, and optionally a second capacitor C2.
  • 3a to 3b show the case where the electrostatic protection circuit includes a first capacitor C1 and a second capacitor C2.
  • the electrostatic protection circuit may also include only the first capacitor C1.
  • the first electrode 211a of the first transistor T1, the first electrode 212a of the second transistor T2, and the gate 212d of the second transistor T2 are electrically connected to the discharge line 24.
  • the second electrode 211b of the first transistor T1 and the second electrode 211b of the second transistor T2 are electrically connected to the discharge line 24.
  • the diode 212b and the gate 211d of the first transistor T1 are electrically connected to the data line 23;
  • the first capacitor C1 is connected between the gate of the first transistor T1 and the discharge line 24.
  • the second capacitor C2 is connected between the gate of the second transistor T2 and the data line 23.
  • the multiple wires include data lines 23 and discharge lines 24, and at least part of the data lines 23 (or each data line 23) passes through the electrostatic protection circuit and the discharge line. 24 connections.
  • the array substrate of this embodiment is basically the same as the array substrate of the previous embodiment.
  • each electrostatic protection circuit is connected between the adjacent data line 23 and the second wire 222, and the second wire 222 is located between the two adjacent data lines 23.
  • the first extension portion E1 of the second wire 222 extends on the gate 211d of the first transistor T1, so that the first extension portion E1 of the second wire 222 and the gate 211d of the first transistor T1 A part of the electrostatic protection circuit forms the first capacitor C1, wherein the first extension E1 of the second wire 222 serves as the first pole piece of the first capacitor C1, and the gate of the first transistor T1 A part of 211d is used as the second pole piece of the first capacitor C1.
  • the plurality of gates 212d of each second transistor T2 and each extension 7 of the plurality of gates 212d extend in a line to form the discharge line 24.
  • the plurality of gates 212d of each second transistor T2, the respective extension portions 7 of the plurality of gates, and the discharge line 24 are or are formed as an integral structure or a monolithic structure.
  • the second extension part E2 of each data line 23 extends on the discharge line 24, so that the second extension part E2 of the data line 23 and a part of the discharge line 24 constitute the first part of the electrostatic protection circuit Two capacitors C2, wherein the second extension E2 of the data line 23 is used as the first pole piece of the second capacitor C2, and a part of the discharge line 24 is used as the second pole of the second capacitor C2 sheet.
  • the third extension E3 of the data line 23 serves as the second electrode 211b of the first transistor T1
  • the fourth extension E4 of the data line 23 serves as the second electrode 211b of the second transistor T2.
  • the fifth extension E5 of the second wire 222 is used as the first electrode 211a of the first transistor T1
  • the sixth extension E6 of the second wire 222 is used as the first electrode of the second transistor T2. 212a.
  • the first electrode 211a of the first transistor T1, the first electrode 212a of the second transistor T2, the second wire 222, and the first extension E1 of the second wire 222 of the electrostatic protection circuit are an integral structure.
  • the second pole 211b of the first transistor T1, the second pole 212b of the second transistor T2, the data line 23, and the second extension E2 of the data line 23 of the electrostatic protection circuit are an integral structure.
  • the electrostatic protection circuit is connected between the data line 23 and the discharge line 24 to form a connection between the data line 23 and the discharge line 24.
  • the voltage of any one of the data lines 23 increases instantaneously, the voltage is discharged to the discharge line 24 through the first transistor T1 or the second transistor T2, thereby realizing the electrostatic protection of the electrostatic protection circuit.
  • the specific protection process of the electrostatic protection circuit in this embodiment is similar to the protection process in the foregoing embodiment, and will not be described in detail.
  • the discharge line 24 is a common electrode line, and the common electrode line can be grounded.
  • Fig. 4a is a circuit diagram of an array substrate according to an embodiment of the present disclosure
  • Fig. 4b is a top view of the structure of the array substrate of Fig. 4a.
  • this embodiment provides an array substrate, which includes a plurality of wires and a plurality of electrostatic protection circuits, and at least some of the wires are connected by the electrostatic protection circuit.
  • the plurality of wires includes a plurality of data lines 23, a discharge line 24, and a short-circuit bar 25.
  • the plurality of electrostatic protection circuits are arranged in sequence, and the discharge line 24 and the plurality of data lines 23 are arranged in sequence.
  • the first electrostatic protection circuit is connected between the discharge line 24 and the short-circuit bar 25.
  • Each of the remaining electrostatic protection circuits is connected between a data line 23 and a discharge line 25.
  • Each electrostatic protection circuit includes a first transistor T1, a second transistor T2, a first capacitor C1 and optionally a second capacitor C2;
  • the first electrode 211a of the first transistor, the gate 212d of the first transistor T2, and the first electrode 212a of the second transistor T2 are connected to the shorting bar 25 .
  • the second electrode 211b of the first transistor T1, the second electrode 212b of the second transistor T2, and the gate 211d of the first transistor T1 are connected to the discharge line 24.
  • the first capacitor C1 is connected between the gate 211d of the first transistor T1 and the shorting bar 25.
  • the second capacitor C2 is connected between the gate 212d of the second transistor T2 and the discharge line 24.
  • the first pole 211a of the first transistor T1, the gate 212d of the second transistor T2, and the first pole 212a of the second transistor are connected to the shorting bar 25 .
  • the second electrode 211b of the first transistor T1, the second electrode 212b of the second transistor, and the gate 211d of the first transistor T1 are connected to the data line 23;
  • the first capacitor C1 is connected to the gate 211d of the first transistor T1 and the shorting bar 25 between.
  • the second capacitor C2 is connected between the gate 212d of the second transistor T2 and the data line 23.
  • each of the plurality of electrostatic protection circuits is connected between the adjacent data line 23 and the second wire 222, or is connected between the discharge line 24 and the second wire 222.
  • the second wire 222 is located between the discharge line 24 and the data line 23 adjacent to the discharge line 24.
  • the other second conductive lines 222 are also located between two adjacent data lines 23.
  • the first extension portion E1 of the second wire 222 extends on the gate 211d of the first transistor T1, so that the first extension portion E1 of the second wire 222 and the gate 211d of the first transistor T1 A part of the first capacitor C1 is formed, wherein the first extension E1 of the second wire 222 is used as the first pole piece of the first capacitor C1, and a part of the gate 211d of the first transistor T1 Used as the second pole piece of the first capacitor C1.
  • the plurality of gates 212d of each second transistor T2 and each extension 7 of the plurality of gates extend in a line to form the short-circuit bar 25.
  • the plurality of gates 212d of each second transistor T2, each extension 7 of the plurality of gates, and the short-circuit bar 25 are an integrated structure or a monolithic structure or formed as an integrated structure or an integrated structure.
  • the second extension portion E2 of each data line 23 or discharge line 24 extends on the short-circuit bar 25, so that the second extension portion E2 of each data line 23 or the discharge line 24 and a part of the short-circuit bar 25 form a joint
  • the second capacitor C2 wherein the second extended portion E2 of the data line 23 or the discharge line 24 is used as the first pole piece of the second capacitor C2, and a part of the shorting bar 25 is used as the second The second pole piece of capacitor C2.
  • the third extension E3 of the data line 23 or the discharge line 24 serves as the second electrode 211b of the first transistor T1
  • the fourth extension E4 of the data line 23 or the discharge line 24 serves as the second
  • the fifth extension E5 of the second wire 222 serves as the first electrode 211a of the first transistor T1
  • the sixth extension E6 of the second wire 222 serves as the The first pole 212a of the second transistor T2.
  • the first pole 211a of the first transistor T1 of the electrostatic protection circuit, the first pole 212a of the second transistor T2, the second wire 222, and the first extension E1 of the second wire 222 are an integral structure.
  • the second electrode 211b of the first transistor T1 of the electrostatic protection circuit, the second electrode 212b of the second transistor T2, the data line 23 or the discharge line 24, and the second extension E2 of the data line 23 or the discharge line 24 are an integrated structure .
  • the multiple wires include a data line 23, a discharge line 24, and a short-circuit bar 25.
  • One short-circuit bar 25 is connected to multiple data lines through multiple electrostatic protection circuits. 23.
  • the discharge line 24 is connected to the short-circuit bar 25 through an electrostatic protection circuit.
  • the array substrate of this embodiment is basically the same as the array substrate of the previous embodiment.
  • the various electrostatic protection circuits are arranged in sequence, the first electrostatic protection circuit is connected to the discharge line 24, and the remaining electrostatic protection circuits are respectively connected to a plurality of data lines 23, and the gates of all the second transistors T2 are connected in a short circuit.
  • the discharge line 24 is a common electrode line.
  • the electrostatic voltage of the discharge line 24 (ie, the common electrode line) or the data line 23 can be discharged to the shorting bar 25 through the first transistor T1 or the second transistor T2, thereby realizing electrostatic protection.
  • the specific protection process of the electrostatic protection circuit in this embodiment is similar to the protection process in the foregoing embodiment, and will not be described in detail.
  • 5a to 5d are schematic diagrams of a method of manufacturing an array substrate.
  • An array substrate includes a plurality of wires and an electrostatic protection circuit. At least some of the wires are connected by the electrostatic protection circuit.
  • the two wires connected to each electrostatic protection circuit are a first wire 221 (for example, a data wire) and a second wire.
  • Wire 222 (for example, a data line).
  • Each electrostatic protection circuit includes a first transistor T1, a second transistor T2, a first capacitor C1, and optionally a second capacitor C2.
  • the gate 211d of the first transistor T1 and the gate 212d of the second transistor T2 are formed on the substrate 1.
  • One or more low-resistance metal material films are deposited on the substrate 1 by a physical vapor deposition method such as magnetron sputtering, and a photolithography process is used to form the gate 211d of the first transistor and the gate 212d of the second transistor.
  • the metal film forming the gate can be a single-layer metal film such as Al (aluminum), Cu (copper), Mo (molybdenum), Ti (titanium) or AlNd (aluminum neodymium), or it can be Mo/Al/Mo or Ti /Al/Ti and other multilayer metal films.
  • a gate insulating layer 2 is formed on the side of the gate 211d of the first transistor and the gate 212d of the second transistor away from the substrate 1.
  • the gate insulating layer 2 completely covers the gate 211d of the first transistor and the second transistor.
  • the gate of the transistor 212d is formed on the side of the gate 211d of the first transistor and the gate 212d of the second transistor away from the substrate 1.
  • the active layer 211c of the first transistor T1 and the active layer 212c of the second transistor T2 are formed on the gate insulating layer (the active layer 212c of the second transistor T2 is shown in FIG. 1e).
  • the transistor channel in the polysilicon active layer 4 is doped with low-concentration ions by the ion implantation process, and the conductive channel required by the thin film transistor is formed in the polysilicon active layer 4.
  • a first electrode 211a on the side of the active layer 211c of the first transistor T1 away from the substrate 1 is formed a first electrode 211a, a second electrode 211b of the first transistor T1, and a second electrode 211a integrally formed with the first electrode 211a.
  • the second wire 222 extends on the gate 211d of the first transistor T1, so that the first extension E1 of the second wire 222 and a part of the gate 211d of the first transistor T1 form a first capacitor C1, as shown in the box.
  • the first extension portion E1 of the second wire 222 serves as the first pole piece of the first capacitor C1, that is, the first extension portion E1 of the second wire 222 and the first pole piece of the first capacitor C1 form an integral structure.
  • a part of the gate 211d of the first transistor T1 serves as the second pole piece of the first capacitor C1, that is, a part of the gate 211d of the first transistor T1 and the second pole piece of the first capacitor C1 are formed as an integral structure.
  • the first electrode 212a and the second electrode 212b of the second transistor T2 are formed on the side of the active layer 212c of the second transistor T2 away from the substrate 1 (FIG. 1e shows the first electrode 212a and the second electrode of the second transistor T2. 212b), the first wire 221 and the second extension portion E2 of the first wire 221.
  • the second extension E2 of the first wire 221 extends on the gate 212d of the second transistor T2, so that the second extension E2 of the first wire 221 and a part of the gate 212d of the second transistor T2 form a second capacitor C2, As shown in the box.
  • the second extension portion E2 of the first wire 221 serves as the first pole piece of the second capacitor C2, that is, the second extension portion E2 of the first wire 221 and the first pole piece of the second capacitor C2 are formed as an integral structure.
  • a part of the gate 212d of the second transistor T2 serves as the second pole piece of the second capacitor C2, that is, a part of the gate 212d of the second transistor T2 and the second pole piece of the second capacitor C2 are formed as an integral structure.
  • the passivation layer 3 is formed.
  • a through hole penetrating the passivation layer 3 and a through hole penetrating the passivation layer 3, the data line 222 and the gate insulating layer 2 are formed.
  • These through holes are filled with conductive materials such as indium tin oxide (ITO) to form connecting electrodes 4-1 and 4-2, as shown in FIG. 1e.
  • ITO indium tin oxide
  • the second electrode 211b of the first transistor T1 of the electrostatic protection circuit is electrically connected to the gate 211d of the first transistor T1 through the connecting electrode 4-1.
  • the second wire 222 is connected to the gate 212d of the second transistor T2 of the electrostatic protection circuit through the connecting electrode 4-2.
  • the embodiment also discloses a display device, which includes the above-mentioned array substrate or the array substrate manufactured according to the above-mentioned method.
  • the display device can be a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators and other products or components with display functions.
  • OLED organic light-emitting diode

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Abstract

一种阵列基板及其制造方法以及显示装置。一种阵列基板，包括：基底（1）上的多条导线以及静电保护电路，至少部分导线间通过所述静电保护电路连接，与所述静电保护电路连接的两条导线分别为第一导线（221）和第二导线（222）；所述静电保护电路包括第一晶体管（T1）、第二晶体管（T2）和第一电容器（C1）；第一晶体管（T1）的第一极、第二晶体管（T2）的第一极和第二晶体管（T2）的栅极连接第二导线（222），第一晶体管（T1）的第二极、第二晶体管（T2）的第二极以及第一晶体管（T1）的栅极连接第一导线（221）；第一电容器（C1）连接在第一晶体管（T1）的栅极和第二导线（222）之间。

Description

阵列基板及其制造方法以及显示装置
相关申请的交叉引用
本公开要求2019年6月12日提交给中国专利局的第201920879076.4号专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本公开属于显示技术领域，具体涉及一种阵列基板及其制造方法以及显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor liquid crystal display，TFT-LCD)的结构设计中，为了防止阵列基板的导线中由于异常而电压突然增大对阵列基板上的器件造成损害，一般在阵列基板周边设置静电保护电路，以保证液晶显示的显示器性能。
发明内容
一方面，提供一种阵列基板，其包括：基底上的多条导线以及静电保护电路，至少部分导线间通过所述静电保护电路连接，与所述静电保护电路连接的两条导线分别为第一导线和第二导线。所述静电保护电路包括第一晶体管、第二晶体管和第一电容器。第一晶体管的第一极、第二晶体管的第一极和第二晶体管的栅极连接第二导线，第一晶体管的第二极、第二晶体管的第二极以及第一晶体管的栅极连接第一导线。第一电容器连接在第一晶体管的栅极和第二导线之间。
在一个实施例中，所述第一晶体管的栅极位于所述基板的一侧。所述栅极绝缘层位于所述第一晶体管的栅极远离所述基板的一侧。所述第一晶体管的有源层位于所述栅极绝缘层的远离所述基板的一侧。所述第二导线的第一延伸部分位于所述有源层的远 离所述基板的一侧，使得所述第二导线的第一延伸部分与所述第一晶体管的栅极的一部分构成所述第一电容器，其中所述第一导线的第一延伸部分作所述第一电容器的第一极片，并且所述第一晶体管的栅极的一部分用作所述第一电容器的第二极片。
在一个实施例中，所述静电保护电路还包括第二电容器，第二电容器连接在第二晶体管的栅极与第一导线之间。
在一个实施例中，所述第二晶体管的栅极位于所述基板的一侧。所述栅极绝缘层位于所述第二晶体管的栅极远离所述基板的一侧。所述第一导线的第二延伸部分位于所述栅极绝缘层的远离所述基板的一侧，使得所述第一导线的第二延伸部分与所述第二晶体管的栅极的一部分构成所述第二电容器，其中所述第一导线的第二延伸部分用作所述第二电容器的第一极片，并且所述第二晶体管的栅极的一部分用作所述第二电容器的第二极片。
在一个实施例中，所述第一导线的第三延伸部分用作所述第一晶体管的第二极，所述第一导线的第四延伸部分用作所述第二晶体管的第二极，所述第二导线的第五延伸部分用作所述第一晶体管的第一极，所述第二导线的第六延伸部分用作所述第二晶体管的第一极。
在一个实施例中，所述静电保护电路的第一晶体管的第一极包括多个间隔设置且一端电连接在一起的多个第一叉指，第一晶体管的第二极包括多个间隔设置且一端电连接在一起的多个第二叉指，每个第一叉指位于两个相邻的第二叉指间，每个第二叉指位于两个相邻的第一叉指间。
在一个实施例中，所述静电保护单元的第二晶体管的第一极包括多个间隔设置且一端电连接在一起的多个第三叉指，第二晶体管的第二极包括多个间隔设置且一端电连接在一起的多个第四叉指，每个第三叉指位于两个相邻的第四叉指间，每个第四叉指位于两个相邻的第三叉指间。
在一个实施例中，所述阵列基板包括多个静电保护电路。与每个静电保护电路电连接的所述第一导线均是第一数据线，与每 个静电保护电路电连接的所述第二导线是第二数据线的一个分支，第二数据线与所述第一数据线紧邻。在任意两相邻数据线之间连接所述多个静电保护电路中的一个静电保护电路。
在一个实施例中，与任意一个数据线相邻的两个静电保护电路以该数据线为对称轴对称地布置在该数据线的两侧。从任意一个数据线分支的两个第二导线以该数据线为对称轴对称地布置在该数据线的两侧。
在一个实施例中，所述阵列基板包括多个静电保护电路。所述多条导线还包括放电线。与每个静电保护电路电连接的第一导线均为数据线，每条数据线均通过所述静电保护电路与放电线连接。
在一个实施例中，所述第二导线位于两个相邻的数据线之间，各个第二晶体管的多个栅极和所述多个栅极的各个延伸部分在一条线延伸共同构成所述放电线，每个数据线的第二延伸部分在所述放电线上延伸，使得每个数据线的第二延伸部分与所述放电线的一部分构成所述静电保护电路的第二电容器，其中每个数据线的第二延伸部分用作所述第二电容器的第一极片，并且所述放电线的一部分用作所述第二电容器的第二极片。
在一个实施例中，所述阵列基板包括多个静电保护电路。所述多条导线还包括放电线和短路条。与每个静电保护电路电连接的第一导线是数据线或放电线。每条数据线和所述放电线分别通过所述静电保护电路与所述短路条连接。
在一个实施例中，多条第二导线中的一条第二导线位于放电线和与该放电线相邻的数据线之间。多条第二导线中的剩余第二导线中的每个位于任意两个相邻的数据线之间。各个第二晶体管的多个栅极和所述多个栅极的各个延伸部分在一条线上延伸共同构成所述短路条。所述数据线或放电线的第二延伸部分在所述短路条上延伸，使得所述数据线或放电线的第二延伸部分与所述短路条的一部分构成所述第二电容器，其中所述数据线或放电线的 第二延伸部分用作所述第二电容器的第一极片，并且所述短路条的一部分用作所述第二电容器的第二极片。
在一个实施例中，所述放电线为公共电极线。
一方面，提供一种显示装置，包括上述阵列基板。
一方面，提供一种制作阵列基板的方法，其中，所述阵列基板包括多条导线以及静电保护电路，所述静电保护电路包括第一晶体管、第二晶体管和第一电容器。所述方法包括：形成第一晶体管和第二晶体管，使得第一晶体管的第一极、第二晶体管的第一极和第二晶体管的栅极连接所述多条导线中的第二导线，并且第一晶体管的第二极、第二晶体管的第二极以及第一晶体管的栅极连接所述多条导线中的第一导线；形成第一电容器，使得第一电容器连接在第一晶体管的栅极和第二导线之间。
在一个实施例中，形成第一电容器，使得第一电容器连接在第一晶体管的栅极和第二导线之间包括：形成所述第二导线，使得所述第二导线的第一延伸部分在所述第一晶体管的栅极上延伸，从而所述第二导线的第一延伸部分与所述第一晶体管的栅极的一部分形成所述第一电容器，其中所述第二导线的第一延伸部分作所述第一电容器的第一极片，并且所述第一晶体管的栅极的一部分用作所述第一电容器的第二极片。
在一个实施例中，所述方法还包括形成所述静电保护电路的第二电容器，使得第二电容器连接在第二晶体管的栅极与第一导线之间。
在一个实施例中，形成第二电容器，使得第二电容器连接在第二晶体管的栅极与第一导线之间包括：形成第一导线，使得第一导线的第二延伸部分在所述第二晶体管的栅极上延伸，从而所述第一导线的第二延伸部分与所述第二晶体管的栅极的一部分形成所述第二电容器，其中第一导线的第二延伸部分用作所述第二电容器的第一极片，并且所述第二晶体管的栅极的一部分用作所述第二电容器的第二极片。
附图说明
图1a为根据本公开的实施例的阵列基板的电路图；
图1b为图1a所示的阵列基板的结构的俯视图；
图1c为根据本公开实施例的阵列基板的电路图；
图1d为图1c所示的阵列基板的结构的俯视图；
图1e为图1d所示的阵列基板的沿AA’线截取的剖视图；
图1f为图1d所示的阵列基板的沿BB’线截取的剖视图；
图2a为根据本公开的实施例的阵列基板的电路图；
图2b为图2a所示的阵列基板的结构的俯视图；
图2c为根据本公开的实施例的阵列基板的电路图；
图2d为图2c所示的阵列基板的结构的俯视图；
图3a为根据本公开的实施例的阵列基板的电路图；
图3b为图3a的阵列基板的结构的俯视图；
图4a为根据本公开的实施例的阵列基板的电路图；
图4b为图4a的阵列基板的结构的俯视图；
图5a至图5d为制作阵列基板的方法的示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
相关技术中的静电保护电路包括静电防护线以及至少一个晶体管。该晶体管的栅极和漏极都与液晶显示器中的一条信号线连接，源极与静电防护线连接。当信号线的静电电压过大时，该晶体管导通，使得信号线的电压释放至静电防护线上，从而保证该液晶显示器的性能。
然而，当信号线中产生瞬时较大的电压时，此时很有可能由于晶体管的源极和漏极之间的电压差过大而造成晶体管的损坏，从而导致静电保护电路的失效。
在本公开中，两结构“同层设置”是指二者是由同一个材料层形成的，故它们在层叠关系上处于相同层中，但并不代表它们 与基板间的距离相等，也不代表它们与基板间的其它层结构完全相同。在本公开中，“一体结构”或“整体结构”是指形成“一体结构”或“整体结构”的各个组成部分由同一种材料形成为一个整体或一个整块。可替换地，“一体结构”或“整体结构”的各个部分在层叠关系上处于相同层中。
需要说明的是，本公开的阵列基板的静电保护电路中采用的晶体管可以均为薄膜晶体管。所有晶体管的源极、漏极是对称的，所以源极和漏极是可以互换的。在本公开的实施例中，可以将源极称为第一极，漏极称为第二极；可替换地，将漏极称为第一极，源极称为第二极。在以下实施例的描述中第一晶体管的漏极作为第一极，第一晶体管的源极作为第二极；第二晶体管的源极作为第一极，第二晶体管的漏极作为第二极。
图1a为根据本公开的实施例的阵列基板的电路图。图1b为图1a所示的阵列基板的结构的俯视图。如图1a和图1b所示，一种阵列基板包括：多条导线以及静电保护电路，至少部分导线间通过静电保护电路连接，与每个静电保护电路连接的两条导线分别为第一导线221和第二导线222；
每个静电保护电路包括第一晶体管T1、第二晶体管T2和第一电容器C1；
第一晶体管T1的第一极、第二晶体管T2的第一极和第二晶体管T2的栅极连接第二导线222，第一晶体管T1的第二极、第二晶体管T2的第二极以及第一晶体管T1的栅极连接第一导线221；
第一电容器C1连接在第一晶体管T1的栅极和第二导线222之间。
在一个实施例中，阵列基板可以包括多个静电保护电路，每个静电保护电路中包括对置且并联的两个晶体管。与每个静电保护电路相连接的两条导线分别为与该静电保护电路连接的第一导线221和第二导线222。
该静电保护电路的静电保护过程为：对于一个静电保护电路， 若与该静电保护电路连接的第二导线222作为静电防护线，由于静电防护线一般接地，因此静电防护线的电压可为0V。当第一导线221的电压突然发生较大变化时，第一晶体管T1或者第二晶体管T2导通，第一导线221的电压通过第一晶体管T1或者第二晶体管T2释放至第二导线222，从而实现静电保护电路的对第一导线221的静电保护。
例如，在图1a所示的静电保护电路中，当信号线中产生瞬时较大的电压时(例如，当第一导线221的电压突然升高时)，通过设置在第一晶体管T1的栅极和第二导线222之间的第一电容器C1的耦合作用，可使第一晶体管T1的第一极的电压也相应升高(但是第一晶体管T1的第一极的电压达不到第二导线222升高后的电压)，从而降低第一晶体管T1的第一极和第二极间的电压差，避免第一晶体管T1的第一极和第二极之间的电压差过大而造成第一晶体管T1的损坏，从而延长静电保护电路的寿命。
例如，假设第一导线221的工作电压为5V，则通过第一电容器C1的耦合作用，第一晶体管T1的第一极的电压变为4V，第一晶体管T1的栅极和第一极间的电压差(为1V)小于第一晶体管T1的阈值电压(5V)，故第一晶体管T1不导通。
当第一导线221的电压突然增大至20V时，由于第一电容器C1的耦合作用，第一晶体管T1的第一极的电压为10V，而第一晶体管T1的第二极的电压和栅极的电压均为20V；此时第一晶体管T1的栅极的电压与第一电极的电压之间的电压差为10V，其大于第一晶体管T1的阈值电压(5V)，因此第一晶体管T1导通，实现静电保护；此外，第一晶体管T1的第一电极的电压和第二电极的电压之间的电压差为10V，与没有设置第一电容器C1的情况(这种情况下，第一电极的电压和第二电极的电压之间的电压差为20V)相比，第一晶体管T1的第一电极的电压和第二电极的电压之间的电压差减小很多，从而避免第一晶体管T1由于第一电极的电压和第二电极的电压之间的电压差过大而损坏。
又如，第一导线221工作电压突然减小至-20V，由于第一电 容器C1的耦合作用，第二晶体管T2的栅极的电压、第一极的电压均为-10V，而第二晶体管T2的第二极电压为-20V；此时第二晶体管T2的栅极与第二电极的电压差为10V，其大于第二晶体管T2的阈值电压(5V)，第二晶体管T2导通，实现静电保护；此时，第二晶体管T2的第一电极的电压和第二电极的电压之间的电压差为10V，与没有设置第一电容器C1的情况(这种情况下，第一电极和第二电极的电压差为20V)相比，第二晶体管T2的第一电极的电压和第二电极的电压之间电压差减小很多，从而避免第二晶体管T2由于第一电极和第二电极之间电压差过大而损坏。
图1b为图1a所示的阵列基板的结构的俯视图。图1b中的方框示出的第一晶体管T1和第二晶体管T2是图1a中的第一晶体管T1和第二晶体管T2的结构图，图1b中的方框示出的第一电容器C1是图1a中的第一电容器C1的结构图。
图1c为根据本公开实施例的阵列基板的电路图。如图1c所示，除了每个静电保护电路还包括第二电容器C2之外，图1c所示的阵列基板的电路图与图1a所示的阵列基板的电路图基本相同。第二电容器C2连接在第二晶体管T2的栅极与第一导线221之间。
每个静电保护电路包括两个晶体管T1、T2和两个电容器C1、C2。包括两个电容器C1、C2的静电保护电路的工作过程与以上静电保护电路的工作过程相似，故不再详细描述。
两个电容器比一个电容器的耦合作用更大，从而可以更好的减小第一晶体管T1的第一极和第二极之间的电压差、以及第二晶体管T2的第一极和第二极之间的电压差，更大程度上实现对第一晶体管T1和第二晶体管T2的保护，从而进一步保证静电保护电路的性能。
图1d为图1c所示的阵列基板的结构的俯视图。图1d示出了第二电容器C2的结构。除了静电保护电路还包括第二电容器C2之外，图1d所示的阵列基板的结构与图1b所示的阵列基板的结构基本相同。
图1e是沿图1d中的线AA’截取的剖视图。如图1d和图1e所示，本实施例的阵列基板的静电保护电路包括：基板1、形成在基板1上的第一晶体管T1和第二晶体管T2。
第一晶体管T1的第一栅极211d以及第二晶体管T2的第二栅极212d均位于基板1上。
栅极绝缘层2位于第一栅极211d和第二栅极212d远离基板1的一侧，且覆盖第一栅极211d和第二栅极212d；
第一晶体管T1的第一有源层211c位于栅极绝缘层2远离基板1的一侧，且第一有源层211c在基板1上的正投影与第一栅极211d在基板1上的正投影重叠(例如，完全重叠)。
第二晶体管T2的第二有源层212c位于栅极绝缘层2远离基板的一侧，且第二有源层212c在基板1上的正投影与第二栅极212d在基板1上的正投影重叠(例如，完全重叠)。
第一晶体管T1的第一电极211a、第二晶体管T2的第一电极212a连接至第二导线222并且与第二导线222形成为一体结构或一个整体。如图1d所示，第二导线222的一延伸部分(即，第五延伸部分)向左延伸出去形成第一晶体管T1的第一电极211a，并且第二导线222的另一延伸部分(即，第六延伸部分)向左延伸出去形成第二晶体管T2的第一电极212a。
第一晶体管T1的第一电极211a位于第一有源层211c远离基板的一侧。第二导线222通过栅极绝缘层2、数据线222和钝化层3中的通孔和钝化层3中的通孔与第二晶体管T2的第二栅极212d电连接。
第二晶体管T2的第一电极212a位于第二有源层212c远离基板的一侧，且通过栅极绝缘层2、数据线222和钝化层3中的通孔和钝化层3中的通孔与第二晶体管T2的第二栅极212d电连接。
第二晶体管T2的第二极212b位于第二有源层212c远离基底1的一侧。
第一晶体管T1的第二极211b位于第一有源层211c远离基底1的一侧，且通过栅极绝缘层2荷钝化层3中的通孔与第一晶体管 T1的第一栅极211d电连接。
第一晶体管T1的第二极211b、第二晶体管T2的第二极212b与第一导线221连接并且与第一导线221形成为一体结构或一个整体结构。如图1d所示，第一导线221的一延伸部分(即，第三延伸部分)向右延伸出去形成第一晶体管T1的第二电极211b，并且第一导线221的另一延伸部分(即，第四延伸部分)向右延伸出去形成第二晶体管T2的第二电极212b。
图1f是沿图1d中的线BB’截取的剖视图。
第一晶体管T1的第一电极211a位于第一有源层211c远离基板1的一侧。第二导线222和第一晶体管T1的第一电极211a是一体结构。第二导线222的延伸部分(即，第一延伸部分E1)在第一晶体管T1的栅极211d上延伸。所述第二导线222的第一延伸部分E1位于第一晶体管T1的第一有源层211c的远离所述基板1的一侧。.所述第二导线222的第一延伸部分E1与所述第一晶体管T1的栅极211d的一部分形成所述第一电容器C1，如方框所示。所述第二导线222的第一延伸部分E1作所述第一电容器C1的第一极片，并且所述第一晶体管T1的栅极211d的一部分用作所述第一电容器C1的第二极片。
第一晶体管T1的第二极211b位于第一晶体管T1的有源层211c远离基板1的一侧。第一晶体管T1的第二极211b通过栅极绝缘层2、数据线222和钝化层3中的通孔和钝化层3中的通孔与第一晶体管T1的栅极211d连接。
第一导线221的延伸部分(即，第二延伸部分E2)从第一导线221延伸出来、在第二晶体管T2的栅极212d上延伸。所述第一导线221的第二延伸部分E2位于所述栅极绝缘层2的远离所述基板1的一侧，使得所述第一导线221的第二延伸部分E2与所述第二晶体管T2的栅极212d的一部分形成所述第二电容器C2，如方框所示。所述第一导线221的第二延伸部分E2作所述第二电容器C2的第一极片，并且所述第二晶体管T2的栅极212d的一部分用作所述第二电容器C2的第二极片。
在一个实施例中，如图1b和图1d所示，第一晶体管的第一极211a包括间隔设置且相互电连接的多个第一叉指，第一晶体管的第二极211b包括间隔设置且相互电连接的多个第二叉指，至少部分第一叉指位于相邻的第二叉指间，至少部分第二叉指位于相邻的第一叉指间。多个第一叉指与多个第二叉指交错间隔排布。
在一个实施例中，每个第一叉指位于两个相邻的第二叉指间，每个第二叉指位于两个相邻的第一叉指间。
第二晶体管T2的第一极212a包括间隔设置且相互电连接的多个第三叉指，第二晶体管T2的第二极212b包括间隔设置且相互电连接的多个第四叉指，至少部分第三叉指位于相邻的第四叉指间，至少部分第四叉指位于相邻的第三叉指间。多个第三叉指与多个第四叉指交错间隔排布。
在一个实施例中，每个第三叉指位于相邻的第四叉指间，每个第四叉指位于相邻的第三叉指间。
第一晶体管的第一极211a和第二极211b为相互交叉排布且间隔开的叉指电极结构；第二晶体管T2的第一极212a和第二极212b为相互交叉排布且间隔开的叉指电极结构。
第一晶体管T1的叉指电极结构和第二晶体管T2的叉指电极结构使得第一晶体管T1的第一极211a和第二极211b的导电更加均匀，并且第二晶体管T2的第一极212a和第二极212b的导电更加均匀，从而更大程度的避免晶体管的损坏，进一步提高静电保护电路的性能以及使用寿命。
如图1d所示，第二导线222、第二导线222的第一延伸部分E1、第一晶体管T1的第一极211a、第二晶体管T2的第一极212a、第一电容器C1的第一极片为一体结构。第一晶体管T1的栅极211d与第一电容器C1的第二极片为一体结构。第一晶体管T1的第二极211b、第二晶体管T2的第二极212b、第一导线221、第一导线221的第一延伸部分E1、第二电容器C2的第一极片为一体结构。第二晶体管T2的栅极212d与第二电容器C2的第二极片为一体结构。
第二导线222、第二导线222的第一延伸部分E1、第一电容器C1的第一极片、第一晶体管T1的第一极211a、第二晶体管T2的第一极212a同层设置。第一电容器C1的第二极片与第一晶体管T1的栅极211d同层设置。第一导线221、第一导线221的第二延伸部分E2、第二电容器C2的第一极片、第一晶体管T1的第二极211b、第二晶体管T2的第二极212b同层设置。第二电容器C2的第二极片与第二晶体管T2的栅极212d同层设置。
第二导线222的第一延伸部分E1用作或形成为第一电容器C1的第一极片，第一晶体管T1的栅极211d的一部分用作或形成为第一电容器C1的第二极片。第一导线221的第二延伸部分E2用作或形成为第二电容器C2的第一极片，第二晶体管T2的栅极212d的一部分用作或形成为第二电容器C2的第二极片。
上述第一电容器C1与第二电容器C2的设置并没有使本实施例的阵列基板的制作步骤变复杂，而是使得本实施例的阵列基板在没有增加制作步骤的复杂程度的前提下，能够更好的保证静电保护电路的性能。
在上述实施例中，导线可以是数据线。
图2a为根据本公开的实施例的阵列基板的电路图；图2b为根据本公开的实施例的阵列基板的结构的俯视图。如图2a和图2b所示，本实施例提供一种阵列基板，包括：多条导线以及静电保护电路。多条导线中的每一个是数据线。至少部分导线间通过静电保护电路连接，与每个静电保护电路连接的两条导线分别为第一数据线23-1和第二数据线23-2。
如图2a所示，每个静电保护电路包括第一晶体管T1、第二晶体管T2和第一电容器C1；
对于第一数据线23-1与第二数据线23-2之间的静电保护电路，第一晶体管T1的第一极211a、第二晶体管T2的栅极212d以及第二晶体管T2的第一极212a连接第二数据线23-2。第一晶体管T1的第二极211b、第二晶体管T2的第二极212b以及第一晶体管T1的栅极211d连接第一数据线23-1。
第一电容器C1连接在第一晶体管T1的栅极211d和第二数据线23-2之间。
对于第二数据线23-2与第三数据线23-3之间的静电保护电路，第一晶体管T1的第一极211a、第一晶体管T1的栅极211d以及第二晶体管T2的第一极212a连接第三数据线23-3；第一晶体管T1的第二极211b、第二晶体管T2的第二极212b以及第二晶体管T2的栅极212d连接第二数据线23-2。
第一电容器C1连接在第一晶体管T1的栅极211d和第二数据线23-2之间。
对于第三数据线23-3与第四数据线23-4之间的静电保护电路的结构与第一数据线23-1与第二数据线23-2之间的静电保护电路的结构基本相同，因此不再赘述。
在本实施例中，与任意一数据线相连的两个静电保护电路以该数据线为轴，轴对称布置在该数据线的两侧。
图2c为根据本公开的实施例的阵列基板的电路图；图2d为图2c所示的阵列基板的结构的俯视图。如图2c所示，每个静电保护电路包括第一晶体管T1、第二晶体管T2、第一电容器C1和第二电容器C2。除了每个静电保护电路包括第二电容器C2之外，图2c所示的阵列基板中的静电保护电路与图2a所示的阵列基板的静电保护电路基本相同。
在如图2a至图2d所示的本实施例中，全部的导线23-1、23-2、23-3、23-4都是数据线，除此之外，图2a和图2c所示的阵列基板中的静电保护电路的结构与图1a和图1c所示的阵列基板中的静电保护电路的结构基本相同，因此不再赘述。
如图2c和图2d所示，阵列基板包括多个静电保护单元和多条数据线23-1、23-2、23-3、23-4等等。多条数据线按照编号依次排列，而任意相邻的两条数据线之间连接一个静电保护电路。
如图2d所示，奇数编号的数据线23-1、23-3没有分支，并且偶数编号的数据线23-2、23-4被分支为两个第二导线222。两个 相邻的第二导线222与数据线23-1之间电连接一个静电保护单元。第二导线222位于任意两个相邻的数据线23-1、23-2之间。
所述第二导线222的延伸部分(即，第一延伸部分E1)在所述第一晶体管T1的栅极211d上延伸，使得所述第二导线222的第一延伸部分E1与所述第一晶体管T1的栅极211d的一部分构成所述第一电容器C1，其中所述第二导线222的第一延伸部分E1用作所述第一电容器C1的第一极片，并且所述第一晶体管T1的栅极211d的一部分用作所述第一电容器C1的第二极片。
与所述静电保护电路连接的数据线23-1的延伸部分(即，第二延伸部分E2)在所述第二晶体管T2的栅极212d上延伸，使得所述数据线23-2的所述第二延伸部分E2与所述第二晶体管T2的栅极212d的一部分构成所述第二电容器C2，其中所述数据线23-2的第二延伸部分E2用作所述第二电容器C2的第一极片，并且所述第二晶体管T2的栅极212d的一部分用作所述第二电容器C2的第二极片。
所述数据线23-1的一延伸部分(即，第三延伸部分E3)用作所述第一晶体管T1的第二极211b，所述数据线23-1的另一延伸部分(即，第四延伸部分E4)用作所述第二晶体管T2的第二极212b。所述第二导线222的一延伸部分(即，第五延伸部分E5)用作所述第一晶体管T1的第一极211a，所述第二导线222的另一延伸部分(即，第六延伸部分E6)用作所述第二晶体管T2的第一极212a。
所述数据线23-1、数据线23-1的第二延伸部分E2、所述静电保护电路的第一晶体管T1的第二极211b、第二晶体管T2的第二极212b是一体结构。
与所述静电保护电路电连接的第二导线2、第二导线的第一延伸部分E1、所述第一晶体管T1的第一极211a、和所述第二晶体管T2的第一极212a是一体结构。
本实施例的阵列基板与前述实施例的阵列基板的主要区别在于：多条导线23-1、23-2、23-3、23-4均为数据线，任意两个相 邻的数据线间通过静电保护电路连接。
静电保护电路连接在与其相邻的两条数据线23之间。当其中一条数据线的电压突然升高，该电压会通过第一晶体管T1或者第二晶体管T2释放至该静电保护电路连接的另一条数据线上。
在不同情况下，每一条数据线都可以作为通过静电保护电路与其相连接的另一条数据线的静电防护线，这样本实施例的阵列基板不需要设置专门的静电防护线，也可以使得静电保护电路达到很好的静电保护效果。
本实施例的静电防护电路的走线排布更简单，制作更加简便。
图3a为根据本公开的实施例的阵列基板的电路图；图3b为图3a的阵列基板的结构的俯视图。如图3a至图3b所示，本实施例提供一种阵列基板，包括：多条数据线、放电线和静电保护电路。至少部分导线间通过静电保护电路连接，与每个静电保护电路连接的两条导线分别为数据线23和放电线24。
每个静电保护电路包括第一晶体管T1、第二晶体管T2、第一电容器C1、和可选地第二电容器C2。图3a至图3b示出了静电保护电路包括第一电容器C1和第二电容器C2的情况。当然，静电保护电路也可以仅包括第一电容器C1。
第一晶体管T1的第一极211a、第二晶体管T2的第一极212a和第二晶体管T2的栅极212d电连接放电线24，第一晶体管T1的第二极211b、第二晶体管T2的第二极212b以及第一晶体管T1的栅极211d电连接数据线23；
第一电容器C1连接在第一晶体管T1的栅极和放电线24之间。第二电容器C2连接在第二晶体管T2的栅极和数据线23之间。
本实施例的阵列基板与前述实施例的阵列基板的主要区别在于：多条导线包括数据线23和放电线24，至少部分数据线23(或每条数据线23)通过静电保护电路与放电线24连接。除此之外，本实施例的阵列基板与前述实施例中的阵列基板基本相同。
如图3b所示，每个静电保护电路连接在相邻的数据线23与第二导线222之间，第二导线222位于两个相邻的数据线23之间。
所述第二导线222的第一延伸部分E1在所述第一晶体管T1的栅极211d上延伸，使得所述第二导线222的第一延伸部分E1与所述第一晶体管T1的栅极211d的一部分形成所述静电保护电路的第一电容器C1，其中所述第二导线222的第一延伸部分E1用作所述第一电容器C1的第一极片，所述第一晶体管T1的栅极211d的一部分用作所述第一电容器C1的第二极片。
各个第二晶体管T2的多个栅极212d和所述多个栅极212d的各个延伸部分7在一条线上延伸共同构成所述放电线24。
各个第二晶体管T2的多个栅极212d、所述多个栅极的各个延伸部分7、放电线24是或形成为一体结构或整块结构。
每条数据线23的第二延伸部分E2在所述放电线24上延伸，使得所述数据线23的所述第二延伸部分E2与所述放电线24的一部分构成所述静电保护电路的第二电容器C2，其中所述数据线23的第二延伸部分E2用作所述第二电容器C2的第一极片，并且所述放电线24的一部分用作所述第二电容器C2的第二极片。
所述数据线23的第三延伸部分E3用作所述第一晶体管T1的第二极211b，所述数据线23的第四延伸部分E4用作所述第二晶体管T2的第二极211b。所述第二导线222的第五延伸部分E5用作所述第一晶体管T1的第一极211a，所述第二导线222的第六延伸部分E6用作所述第二晶体管T2的第一极212a。
所述静电保护电路的第一晶体管T1的第一极211a、第二晶体管T2的第一极212a、第二导线222、和第二导线222的第一延伸部分E1是一体结构。
所述静电保护电路的第一晶体管T1的第二极211b、第二晶体管T2的第二极212b、数据线23、和数据线23的第二延伸部分E2是一体结构。
在本实施例中，静电保护电路连接在数据线23与放电线24之间，从而形成数据线23与放电线24的连接。当任意一条数据 线23的电压瞬时增大，通过第一晶体管T1或者第二晶体管T2将该电压释放至放电线24，从而实现静电保护电路的静电保护。本实施例的静电保护电路的具体的保护过程与前述实施例中的保护过程相似，不再详细描述。
具体的，放电线24为公共电极线，且该公共电极线可接地。
图4a为根据本公开的实施例的阵列基板的电路图；图4b为图4a的阵列基板的结构的俯视图。如图4a至4b所示，本实施例提供一种阵列基板，包括：多条导线以及多个静电保护电路，至少部分导线间通过静电保护电路连接。多条导线包括多条数据线23、一个放电线24与一个短路条25。
所述多个静电保护电路是依次排列的，并且放电线24和多条数据线23依次排列。
第一个静电保护电路连接在放电线24与短路条25之间。剩余静电保护电路中的每个连接在一个数据线23与放电线25之间。
每个静电保护电路包括第一晶体管T1、第二晶体管T2和第一电容器C1和可选地第二电容器C2；
对于连接在放电线24与短路条25之间的第一静电保护电路，第一晶体管的第一极211a、第一晶体管T2的栅极212d以及第二晶体管T2的第一极212a连接短路条25。第一晶体管T1的第二极211b、第二晶体管T2的第二极212b以及第一晶体管T1的栅极211d连接放电线24。第一电容器C1连接在第一晶体管T1的栅极211d和短路条25之间。第二电容器C2连接在第二晶体管T2的栅极212d与放电线24之间。
对于除了第一静电保护电路之外的剩余静电保护电路中的每一个，第一晶体管T1的第一极211a、第二晶体管T2的栅极212d以及第二晶体管的第一极212a连接短路条25。第一晶体管T1的第二极211b、第二晶体管的第二极212b以及第一晶体管T1的栅极211d连接数据线23；第一电容器C1连接在第一晶体管T1的栅极211d和短路条25之间。第二电容器C2连接在第二晶体管 T2的栅极212d和数据线23之间。
如图4b所示，所述多个静电保护电路中的每个静电保护电路连接在相邻的数据线23与第二导线222之间，或者链接在放电线24与第二导线222之间。第二导线222位于放电线24和与该放电线24相邻的数据线23之间。其他第二导线222还位于两相邻的数据线23之间。
所述第二导线222的第一延伸部分E1在所述第一晶体管T1的栅极211d上延伸，使得所述第二导线222的第一延伸部分E1与所述第一晶体管T1的栅极211d的一部分形成所述第一电容器C1，其中所述第二导线222的第一延伸部分E1用作所述第一电容器C1的第一极片，并且所述第一晶体管T1的栅极211d的一部分用作所述第一电容器C1的第二极片。
各个第二晶体管T2的多个栅极212d和所述多个栅极的各个延伸部分7在一条线上延伸共同构成所述短路条25。
各个第二晶体管T2的多个栅极212d、所述多个栅极的各个延伸部分7、短路条25是一体结构或整块结构或形成为一体结构或整体结构。
每条数据线23或放电线24的第二延伸部分E2在所述短路条上25延伸，使得每条数据线23或放电线24的第二延伸部分E2与所述短路条25的一部分形成所述第二电容器C2，其中所述数据线23或放电线24的第二延伸部分E2用作所述第二电容器C2的第一极片，并且所述短路条25的一部分用作所述第二电容器C2的第二极片。
所述数据线23或放电线24的第三延伸部分E3用作所述第一晶体管T1的第二极211b，所述数据线23或放电线24的第四延伸部分E4用作所述第二晶体管T2的第二极212b，所述第二导线222的第五延伸部分E5用作所述第一晶体管T1的第一极211a，所述第二导线222的第六延伸部分E6用作所述第二晶体管T2的第一极212a。
所述静电保护电路的第一晶体管T1的第一极211a、第二晶 体管T2的第一极212a、所述第二导线222、所述第二导线222的第一延伸部分E1是一体结构。
所述静电保护电路的第一晶体管T1的第二极211b、第二晶体管T2的第二极212b、数据线23或放电线24、数据线23或放电线24的第二延伸部分E2是一体结构。
本实施例的阵列基板与前述实施例的阵列基板的主要区别在于：多条导线包括数据线23、放电线24和短路条25，一条短路条25通过多个静电保护电路分别连接多条数据线23，放电线24通过一个静电保护电路连接短路条25。除此之外，本实施例的阵列基板与前述实施例的阵列基板基本相同。
具体的，各个静电保护电路是依次排列的，第一个静电保护电路连接至放电线24，而剩余静电保护电路分别连接至多条数据线23，并且所有第二晶体管T2的栅极连接在一条短路条25上。放电线24为公共电极线。放电线24(即，公共电极线)或者数据线23的静电电压可通过第一晶体管T1或者第二晶体管T2释放至短路条25上，从而实现静电保护。本实施例的静电保护电路的具体的保护过程与前述实施例中的保护过程相似，不再详细描述。
图5a至图5d为制作阵列基板的方法的示意图。
一种阵列基板包括：多条导线以及静电保护电路，至少部分导线间通过静电保护电路连接，与每个静电保护电路连接的两条导线分别为第一导线221(例如，数据线)和第二导线222(例如，数据线)。每个静电保护电路包括第一晶体管T1、第二晶体管T2和第一电容器C1和可选地第二电容器C2。
参照图5a，在基底1上形成第一晶体管T1的栅极211d和第二晶体管T2的栅极212d。
通过磁控溅射等物理气相沉积方法在基底1上沉积一种或者多种低电阻的金属材料薄膜，利用光刻工艺形成第一晶体管的栅极211d和第二晶体管的栅极212d。形成该栅极的金属薄膜可以是Al(铝)、Cu(铜)、Mo(钼)、Ti(钛)或AlNd(铝钕)等 单层金属薄膜，也可以是Mo/Al/Mo或Ti/Al/Ti等多层金属薄膜。
然后，在第一晶体管的栅极211d和第二晶体管的栅极212d远离基板1的一侧形成栅极绝缘层2，所述栅极绝缘层2完全覆盖第一晶体管的栅极211d和第二晶体管的栅极212d。
参照图5b，在栅极绝缘层上形成第一晶体管T1的有源层211c和第二晶体管T2的有源层212c(图1e中示出了第二晶体管T2的有源层212c)。
利用离子注入工艺对多晶硅有源层4中的晶体管沟道进行低浓度离子掺杂，在多晶硅有源层4中形成薄膜晶体管要求的导电沟道。
参照图5c，在第一晶体管T1的有源层211c远离基板1的一侧形成第一晶体管T1的第一极211a、第二极211b、与所述第一极211a形成为一体结构的第二导线222和第二导线222的第一延伸部分E1。
第二导线222在第一晶体管T1的栅极211d上延伸，使得第二导线222的第一延伸部分E1和第一晶体管T1的栅极211d的一部分形成第一电容器C1，如方框所示。第二导线222的第一延伸部分E1用作第一电容器C1的第一极片，即，第二导线222的第一延伸部分E1与第一电容器C1的第一极片形成为一体结构。第一晶体管T1的栅极211d的一部分用作第一电容器C1的第二极片，即，第一晶体管T1的栅极211d的一部分和第一电容器C1的第二极片形成为一体结构。
在第二晶体管T2的有源层212c远离基板1的一侧形成第二晶体管T2的第一极212a、第二极212b(图1e示出了第二晶体管T2的第一极212a和第二极212b)、第一导线221和第一导线221的第二延伸部分E2。
第一导线221的第二延伸部分E2在第二晶体管T2的栅极212d上延伸，使得第一导线221的第二延伸部分E2和第二晶体管T2的栅极212d的一部分形成第二电容器C2，如方框所示。第一导线221的第二延伸部分E2用作第二电容器C2的第一极片， 即，第一导线221的第二延伸部分E2与第二电容器C2的第一极片形成为一体结构。第二晶体管T2的栅极212d的一部分用作第二电容器C2的第二极片，即，第二晶体管T2的栅极212d的一部分和第二电容器C2的第二极片形成为一体结构。
参照图5d，在第一晶体管T1的第一极211a和第二极211b、第二晶体管T2的第一极212a、第二极212b、第一导线221和第二导线222远离基板1的一侧形成钝化层3。
最后，在形成贯穿钝化层3的通孔和贯穿钝化层3、数据线222和栅极绝缘层2的通孔。在这些通孔中填充诸如氧化铟锡(ITO)等导电材料，形成连接电极4-1、4-2，如图1e所示。
如图1e所示，通过所述连接电极4-1，静电保护电路的第一晶体管T1的第二极211b电连接至第一晶体管T1的栅极211d。
如图1e所示，通过所述连接电极4-2，第二导线222连接至静电保护电路的第二晶体管T2的栅极212d。
本实施例还公开一种显示装置，其包括上述的阵列基板或包括根据上述方法制造的阵列基板。该显示装置可为液晶显示面板、有机发光二极管(OLED)显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (19)

  1. 一种阵列基板，包括：基底上的多条导线以及静电保护电路，至少部分导线间通过所述静电保护电路连接，与所述静电保护电路连接的两条导线分别为第一导线和第二导线，其中
    所述静电保护电路包括第一晶体管、第二晶体管和第一电容器；
    第一晶体管的第一极、第二晶体管的第一极和第二晶体管的栅极连接第二导线，第一晶体管的第二极、第二晶体管的第二极以及第一晶体管的栅极连接第一导线；
    第一电容器连接在第一晶体管的栅极和第二导线之间。
  2. 根据权利要求1所述的阵列基板，还包括栅极绝缘层，其中
    所述第一晶体管的栅极位于所述基板的一侧，
    所述栅极绝缘层位于所述第一晶体管的栅极远离所述基板的一侧，
    所述第一晶体管的有源层位于所述栅极绝缘层的远离所述基板的一侧，
    所述第二导线的第一延伸部分位于所述第一晶体管的有源层的远离所述基板的一侧，使得所述第二导线的第一延伸部分与所述第一晶体管的栅极的一部分构成所述第一电容器，其中所述第一导线的第一延伸部分作所述第一电容器的第一极片，并且所述第一晶体管的栅极的一部分用作所述第一电容器的第二极片。
  3. 根据权利要求2所述的阵列基板，其中，所述静电保护电路还包括第二电容器，第二电容器连接在第二晶体管的栅极与第一导线之间。
  4. 根据权利要求3所述的阵列基板，其中
    所述第二晶体管的栅极位于所述基板的一侧，
    所述栅极绝缘层位于所述第二晶体管的栅极远离所述基板的一侧，
    所述第一导线的第二延伸部分位于所述栅极绝缘层的远离所述基板的一侧，使得所述第一导线的第二延伸部分与所述第二晶体管的栅极的一部分构成所述第二电容器，其中所述第一导线的第二延伸部分用作所述第二电容器的第一极片，并且所述第二晶体管的栅极的一部分用作所述第二电容器的第二极片。
  5. 根据权利要求4所述的阵列基板，其中
    所述第一导线的第三延伸部分用作所述第一晶体管的第二极，
    所述第一导线的第四延伸部分用作所述第二晶体管的第二极，
    所述第二导线的第五延伸部分用作所述第一晶体管的第一极，
    所述第二导线的第六延伸部分用作所述第二晶体管的第一极。
  6. 根据权利要求5所述的阵列基板，其中，
    所述静电保护电路的第一晶体管的第一极包括多个间隔设置且一端电连接在一起的多个第一叉指，第一晶体管的第二极包括多个间隔设置且一端电连接在一起的多个第二叉指，每个第一叉指位于两个相邻的第二叉指间，每个第二叉指位于两个相邻的第一叉指间。
  7. 根据权利要求6述的阵列基板，其中
    所述静电保护单元的第二晶体管的第一极包括多个间隔设置且一端电连接在一起的多个第三叉指，第二晶体管的第二极包括多个间隔设置且一端电连接在一起的多个第四叉指，每个第三叉 指位于两个相邻的第四叉指间，每个第四叉指位于两个相邻的第三叉指间。
  8. 根据权利要求7所述的阵列基板，包括多个静电保护电路，其中
    与每个静电保护电路电连接的所述第一导线均是第一数据线，
    与每个静电保护电路电连接的所述第二导线是第二数据线的一个分支，第二数据线与所述第一数据线紧邻，
    在任意两相邻数据线之间连接所述多个静电保护电路中的一个静电保护电路。
  9. 根据权利要求8所述的阵列基板，其中
    与任意一个数据线相邻的两个静电保护电路以该数据线为对称轴对称地布置在该数据线的两侧，
    从任意一个数据线分支的两个第二导线以该数据线为对称轴对称地布置在该数据线的两侧。
  10. 根据权利要求7所述的阵列基板，包括多个静电保护电路，其中，
    所述多条导线还包括放电线，
    与每个静电保护电路电连接的第一导线均为数据线，
    每条数据线均通过所述静电保护电路与放电线连接。
  11. 根据权利要求10所述的阵列基板，其中
    所述第二导线位于两个相邻的数据线之间，
    各个第二晶体管的多个栅极和所述多个栅极的各个延伸部分在一条线上延伸共同构成所述放电线，
    每个数据线的第二延伸部分在所述放电线上延伸，使得每个数据线的第二延伸部分与所述放电线的一部分构成所述静电保护 电路的第二电容器，其中每个数据线的第二延伸部分用作所述第二电容器的第一极片，并且所述放电线的一部分用作所述第二电容器的第二极片。
  12. 根据权利要求7所述的阵列基板，包括多个静电保护电路，其中，
    所述多条导线还包括放电线和短路条，
    与每个静电保护电路电连接的第一导线是数据线或放电线，
    每条数据线和所述放电线分别通过所述静电保护电路与所述短路条连接。
  13. 根据权利要求12所述的阵列基板，其中
    多条第二导线中的一条第二导线位于放电线和与该放电线相邻的数据线之间，
    多条第二导线中的剩余第二导线中的每个位于任意两个相邻的数据线之间，
    各个第二晶体管的多个栅极和所述多个栅极的各个延伸部分在一条线上延伸共同构成所述短路条，
    所述数据线或放电线的第二延伸部分在所述短路条上延伸，使得所述数据线或放电线的第二延伸部分与所述短路条的一部分构成所述第二电容器，其中所述数据线或放电线的第二延伸部分用作所述第二电容器的第一极片，并且所述短路条的一部分用作所述第二电容器的第二极片。
  14. 根据权利要求10至13中任一项所述的阵列基板，其中，所述放电线为公共电极线。
  15. 一种显示装置，包括前述权利要求中任意一项所述的阵列基板。
  16. 一种制作阵列基板的方法，其中，所述阵列基板包括多条导线以及静电保护电路，所述静电保护电路包括第一晶体管、第二晶体管和第一电容器，所述方法包括：
    形成第一晶体管和第二晶体管，使得第一晶体管的第一极、第二晶体管的第一极和第二晶体管的栅极连接所述多条导线中的第二导线，并且第一晶体管的第二极、第二晶体管的第二极以及第一晶体管的栅极连接所述多条导线中的第一导线，
    形成第一电容器，使得第一电容器连接在第一晶体管的栅极和第二导线之间。
  17. 根据权利要求16所述的方法，其中
    形成第一电容器，使得第一电容器连接在第一晶体管的栅极和第二导线之间包括：
    形成所述第二导线，使得所述第二导线的第一延伸部分在所述第一晶体管的栅极上延伸，从而所述第二导线的第一延伸部分与所述第一晶体管的栅极的一部分形成所述第一电容器，其中所述第二导线的第一延伸部分作所述第一电容器的第一极片，并且所述第一晶体管的栅极的一部分用作所述第一电容器的第二极片。
  18. 根据权利要求16或17所述的方法，还包括形成所述静电保护电路的第二电容器，使得第二电容器连接在第二晶体管的栅极与第一导线之间。
  19. 根据权利要求18所述的方法，其中
    形成第二电容器，使得第二电容器连接在第二晶体管的栅极与第一导线之间包括：
    形成第一导线，使得第一导线的第二延伸部分在所述第二晶体管的栅极上延伸，从而所述第一导线的第二延伸部分与所述第二晶体管的栅极的一部分形成所述第二电容器，其中第一导线的 第二延伸部分用作所述第二电容器的第一极片，并且所述第二晶体管的栅极的一部分用作所述第二电容器的第二极片。
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CN209691755U (zh) * 2019-06-12 2019-11-26 京东方科技集团股份有限公司 阵列基板以及显示装置
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