WO2020248408A1 - 阵列基板、显示面板及阵列基板的制作方法 - Google Patents

阵列基板、显示面板及阵列基板的制作方法 Download PDF

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Publication number
WO2020248408A1
WO2020248408A1 PCT/CN2019/105085 CN2019105085W WO2020248408A1 WO 2020248408 A1 WO2020248408 A1 WO 2020248408A1 CN 2019105085 W CN2019105085 W CN 2019105085W WO 2020248408 A1 WO2020248408 A1 WO 2020248408A1
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Prior art keywords
layer
inorganic layer
inorganic
substrate
array substrate
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PCT/CN2019/105085
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English (en)
French (fr)
Inventor
丁文涛
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武汉华星光电技术有限公司
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Priority to US16/612,419 priority Critical patent/US20200395391A1/en
Publication of WO2020248408A1 publication Critical patent/WO2020248408A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • the present invention relates to the field of display, in particular to a manufacturing method of an array substrate, a display panel and an array substrate.
  • the flexible thin film transistor liquid crystal display (Thin Film Transistor Liquid Crystal Display, TFT-LCD) array substrate process has more polyimide (PI) material substrate layer, and the buffer on the substrate layer
  • PI polyimide
  • the layer is currently single-layer SiNx or single-layer SiO 2 , the edge of the single-layer SiNx will tilt away from the direction of the substrate layer and present tension, and the edge of the single-layer SiO 2 will bend toward the direction of the substrate layer and present pressure;
  • the buffer layer is made of SiNx or single layer SiO 2 , due to film stress, the SiNx or SiO 2 may be separated from the film layer connected above or below, causing the array substrate to fail.
  • the buffer layer is easily separated from the substrate layer during the manufacturing process of the array substrate, especially the alignment mark (Mark) provided on the buffer layer will also be lost with the separation of the buffer layer and the substrate layer, resulting in the subsequent exposure process.
  • the alignment mark can be recognized and terminated.
  • the purpose of the present invention is to provide a method for manufacturing an array substrate, a display panel, and an array substrate, which improves the structure of the existing buffer layer to increase the adhesion between the buffer layer and the substrate layer, thereby retaining the alignment mark (Mark ), which can solve the problems related to the loss of alignment marks due to the lack of adhesion between the buffer layer and the substrate layer during the manufacturing process of the array substrate.
  • one of the embodiments of the present invention provides an array substrate, which includes a substrate layer, a buffer layer, a marking layer, and a thin film transistor layer that are stacked.
  • the buffer layer is provided on one side of the substrate layer, and at least two inorganic layers whose stresses cancel each other are laminated in the buffer layer;
  • the marking layer is provided on the buffer layer away from the substrate layer.
  • One side; the thin film transistor layer is provided on the side of the buffer layer with the marking layer.
  • the number of layers of the inorganic layer is an odd number of layers.
  • the number of layers of the inorganic layer is three, including a first inorganic layer, a second inorganic layer, and a third inorganic layer.
  • the first inorganic layer is provided on the substrate layer, and its material is silicon nitride;
  • the second inorganic layer is provided on the side of the first inorganic layer away from the substrate layer, and the material is Is silicon oxide;
  • the third inorganic layer is provided on the side of the second inorganic layer away from the first inorganic layer, and the material is silicon nitride.
  • the number of layers of the inorganic layer is five, and the inorganic layer includes a first inorganic layer, a second inorganic layer, a third inorganic layer, a fourth inorganic layer, and a fifth inorganic layer.
  • the first inorganic layer is provided on the substrate layer, and its material is silicon nitride
  • the second inorganic layer is provided on the side of the first inorganic layer away from the substrate layer, and the material is Is silicon oxide
  • the third inorganic layer is provided on the side of the second inorganic layer away from the first inorganic layer, and its material is silicon nitride
  • the fourth inorganic layer is provided on the third inorganic layer
  • the material of the side facing away from the substrate layer is silicon oxide
  • the fifth inorganic layer is arranged on the side of the fourth inorganic layer facing away from the third inorganic layer, and the material is silicon nitride.
  • the film thicknesses of the first inorganic layer, the second inorganic layer, the third inorganic layer, the fourth inorganic layer and the fifth inorganic layer are equal.
  • the marking layer includes a plurality of alignment marks, and the alignment marks are arranged around the periphery of the marking layer.
  • Another embodiment of the present invention provides a manufacturing method of an array substrate, which includes the following steps:
  • the thin film transistor layer is fabricated on the side of the buffer layer with the marking layer.
  • the manufacturing steps of the buffer layer include:
  • a silicon nitride material is deposited on the second inorganic layer to form a third inorganic layer.
  • the manufacturing steps of the buffer layer include:
  • a silicon nitride material is deposited on the fourth inorganic layer to form a fifth inorganic layer.
  • a display panel which includes the above-mentioned array substrate.
  • the beneficial effect of the present invention is to provide a manufacturing method of an array substrate, a display panel and an array substrate, which improves the structure of the existing buffer layer to increase the adhesion between the buffer layer and the substrate layer, thereby retaining the alignment mark ( Mark), which can solve the problems related to the loss of alignment marks due to the lack of adhesion between the buffer layer and the substrate layer during the manufacturing process of the array substrate.
  • FIG. 1 is a schematic diagram of the structure of an array substrate in the first embodiment of the present invention
  • FIG. 2 is a top view of the buffer layer in the first embodiment of the present invention, which mainly shows the distribution positions of the alignment marks;
  • FIG. 3 is a schematic diagram of the structure of the thin film transistor layer in the first embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the structure of an array substrate in the second embodiment of the present invention.
  • FIG. 5 is a flowchart of a manufacturing method of an array substrate in an embodiment of the present invention.
  • Fig. 6 is a flow chart of manufacturing the buffer layer in the first embodiment of the present invention.
  • Fig. 7 is a production flow chart of the buffer layer in the second embodiment of the present invention.
  • Substrate layer 2. Buffer layer, 3. Marking layer, 4. Thin film transistor layer, 5. Cathode layer,
  • Source and drain layer 100.
  • Array substrate 100.
  • the component can be directly placed on the other component; there may also be an intermediate component on which the component is placed , And the intermediate component is placed on another component.
  • a component is described as “installed to” or “connected to” another component, both can be understood as directly “installed” or “connected”, or a component is “installed to” or “connected to” through an intermediate component Another component.
  • an array substrate 100 which includes a substrate layer 1, a buffer layer 2, a marking layer 3, and a thin film transistor layer 4 that are stacked.
  • the buffer layer 2 is provided on one side of the substrate layer 1, and the buffer layer 2 is laminated with at least two inorganic layers whose stresses cancel each other; the marking layer 3 is provided on the buffer layer 2 away from each other.
  • One side of the substrate layer 1; the thin film transistor layer 4 is provided on the side of the buffer layer 2 with the marking layer 3.
  • the material of the substrate layer 1 is polyimide (PI) or other buffer materials, which play a role of buffer protection.
  • the number of layers of the inorganic layer of the buffer layer 2 is set to an odd number. In this embodiment, it is set to three layers, including a first inorganic layer 21a, a second inorganic layer 22a, and a third inorganic layer. ⁇ 23a.
  • the first inorganic layer 21a is provided on the substrate layer 1, and its material is silicon nitride
  • the second inorganic layer 22a is provided on the first inorganic layer 21a away from the substrate layer 1.
  • the material is silicon oxide
  • the third inorganic layer 23a is provided on the side of the second inorganic layer 22a away from the first inorganic layer 21a, and the material is silicon nitride.
  • a silicon nitride material is used as the first inorganic layer 21a, which can be closely combined with the substrate layer 1, because the bonding force between silicon nitride and polyimide is greater than the bonding force between silicon oxide and polyimide , Thereby increasing the adhesion between the buffer layer 2 and the substrate layer 1.
  • a single-layer SiNx film for example, the first inorganic layer 21a
  • the edge of the single-layer SiNx film will tilt away from the substrate layer 1 and present tension
  • the SiO 2 film for example, the second inorganic layer 22a
  • the edges of the single-layer SiO 2 film will bend toward the substrate layer 1 and present pressure
  • the SiNx is arranged by overlapping
  • the film and the SiO 2 film can offset the tension generated by the SiNx film and the pressure generated by the SiO 2 film, that is, the stresses of the first inorganic layer 21a and the second inorganic layer 22a offset each other, and the second inorganic layer 22a
  • the stresses of the third inorganic layer 23a and the third inorganic layer 23a offset each other, thereby reducing the stress generated in the buffer layer 2 and avoiding the separation of the buffer layer 2 and the substrate layer 1.
  • the buffer layer design the buffer layer
  • the film thicknesses of the first inorganic layer 21a, the second inorganic layer 22a, and the third inorganic layer 23a are equal.
  • the equal thickness of the film layer can effectively offset the tension and pressure, thereby reducing the stress generated in the buffer layer 2 and avoiding the separation of the buffer layer 2 and the substrate layer 1.
  • the second inorganic layer 22a and the third inorganic layer 23a are repeatedly attached multiple times to form a thin film stack structure in which silicon nitride thin films and silicon oxide thin films are interlaced, that is, the buffer layer 2 is formed It is an odd-numbered film stack structure of 3, 5, 7...
  • the marking layer 3 includes a plurality of alignment marks 10, the alignment marks 10 are arranged around the periphery of the marking layer 3, and the alignment marks 10 can be distributed on all The four corners of the marking layer 3 may also be distributed on the edge of the marking layer 3, so that the requirement for setting the alignment mark 10 can be satisfied without affecting other functions.
  • the alignment mark 10 has a cross shape to facilitate alignment. Because the buffer layer 2 and the substrate layer 1 will not be separated, the alignment mark 10 will remain intact, which facilitates the subsequent exposure process to perform identification and alignment based on the alignment mark 10 smoothly.
  • the thin film transistor layer 4 includes a gate layer 41, a gate insulating layer 42, an active layer 43 and a source-drain layer 44 that are stacked.
  • the gate layer 41 is provided on a side of the buffer layer 2 away from the substrate layer 1; the gate insulating layer 42 is provided on a side of the gate layer 41 away from the buffer layer 2
  • the active layer 43 is provided on the side of the gate insulating layer 42 away from the gate layer 41; the source and drain layer 44 is provided on the active layer 43 away from the gate insulating layer 42 side.
  • the structure of the thin film transistor layer 4 shown in FIG. 3 is only an example, not a limitation of the protection scope of the present invention. All the thin film transistor layer 4 structures in the prior art belong to the protection scope of the present invention.
  • the array substrate 100 further includes a cathode layer 5 and a protective layer 6.
  • the cathode layer 5 is disposed on the side of the thin film transistor layer 4 away from the buffer layer 2; the protective layer 6 is completely covered on a side of the cathode layer 5 away from the thin film transistor layer 4 side.
  • the protective layer 6 completely covers the upper surface of the cathode layer 5 to protect the thin film transistor layer 4, reduce the possibility of water and oxygen intrusion, and improve the performance of the display panel.
  • one embodiment of the present invention provides a manufacturing method of the array substrate 100, which includes steps S1-S3.
  • Step S1 Fabricate a substrate layer 1.
  • the material of the substrate layer 1 is polyimide (PI) or other buffer materials, which play a role of buffer protection.
  • Step S2 fabricating at least two stacked inorganic layers whose stresses cancel each other out on the substrate layer 1 to form a buffer layer 2.
  • This arrangement on the one hand, can effectively eliminate the stress generated inside the buffer layer 2, so that the tension and pressure can cancel each other out.
  • Step S3 Fabricate a marking layer 3 on the side of the buffer layer 2 away from the substrate layer 1.
  • Step S4 fabricating a thin film transistor layer 4 on the side of the buffer layer 2 with the marking layer 3.
  • the manufacturing steps of the buffer layer 2 include S21-S23.
  • Step S21 Depositing a silicon nitride material on the substrate layer 1 to form a first inorganic layer 21a; using silicon nitride material as the first inorganic layer 21a, it can be closely combined with the substrate layer 1, because silicon nitride The bonding force with polyimide is greater than the bonding force between silicon oxide and polyimide, thereby increasing the adhesion between the buffer layer 2 and the substrate layer 1.
  • Step S22 deposit a silicon oxide material on the first inorganic layer 21a to form a second inorganic layer 22a.
  • Step S23 depositing a silicon nitride material on the second inorganic layer 22a to form a third inorganic layer 23a.
  • a single-layer SiNx film for example, the first inorganic layer 21a
  • the edge of the single-layer SiNx film will tilt away from the substrate layer 1 Tension
  • a single-layer SiO 2 film for example, the second inorganic layer 22a
  • the edges of the single-layer SiO 2 film will bend toward the substrate layer 1 and present pressure
  • the tension generated by the SiNx film and the pressure generated by the SiO 2 film can cancel each other, that is, the stresses of the first inorganic layer 21a and the second inorganic layer 22a cancel each other.
  • the buffer layer 2 cleverly utilizes the SiNx film and the SiO 2 film to offset each other in opposite stress directions, effectively avoiding the film stress. Impact.
  • the second embodiment of the present invention includes all the technical features of the first embodiment. The difference is that in the second embodiment of the present invention, the number of layers of the inorganic layer of the buffer layer 2 is Five layers.
  • the buffer layer 2 includes the first inorganic layer 21 b, the second inorganic layer 22 b, the third inorganic layer 23 b, the fourth inorganic layer 24 and the fifth inorganic layer 25.
  • the first inorganic layer 21b is provided on the substrate layer 1, and its material is silicon nitride; the second inorganic layer 22b is provided on the side of the first inorganic layer 21b away from the substrate layer 1 , The material is silicon oxide; the third inorganic layer 23b is provided on the side of the second inorganic layer 22b away from the first inorganic layer 21b, and the material is silicon nitride; the fourth inorganic layer 24 is provided On the side of the third inorganic layer 23b facing away from the substrate layer, the material is silicon oxide; the fifth inorganic layer 25 is provided on the side of the fourth inorganic layer 24 facing away from the third inorganic layer 23b , Its material is silicon nitride.
  • silicon nitride material as the first inorganic layer 21b can make it tightly combined with the substrate layer 1, because the bonding force of silicon nitride and polyimide is greater than the bonding force of silicon oxide and polyimide, thereby increasing the buffer Adhesion of layer 2 to substrate layer 1.
  • the stresses of the fourth inorganic layer 24 and the fifth inorganic layer 25 cancel each other out, thereby reducing the stress generated inside the buffer layer 2 and avoiding the separation of the buffer layer 2 and the substrate layer 1.
  • the buffer layer 2 is preferably arranged as five layers. On the one hand, it can effectively eliminate the stress generated inside the buffer layer 2, so that the tension and pressure can cancel each other out. The manufacturing cost is reduced and the thinness of the array substrate 100 is ensured to the greatest extent.
  • the film thicknesses of the first inorganic layer 21b, the second inorganic layer 22b, and the third inorganic layer 23b are equal.
  • the equal thickness of the film layer can effectively offset the tension and pressure, thereby reducing the stress generated in the buffer layer 2 and avoiding the separation of the buffer layer 2 and the substrate layer 1.
  • one embodiment of the present invention provides a manufacturing method of the array substrate 100, which includes steps S1-S3.
  • Step S1 Fabricate a substrate layer 1.
  • the material of the substrate layer 1 is polyimide (PI) or other buffer materials, which play a role of buffer protection.
  • Step S2 fabricating at least two stacked inorganic layers whose stresses cancel each other out on the substrate layer 1 to form a buffer layer 2.
  • This arrangement on the one hand, can effectively eliminate the stress generated inside the buffer layer 2, so that the tension and pressure can cancel each other out.
  • Step S3 Fabricate a marking layer 3 on the side of the buffer layer 2 away from the substrate layer 1.
  • Step S4 fabricating a thin film transistor layer 4 on the side of the buffer layer 2 with the marking layer 3.
  • the manufacturing steps of the buffer layer 2 include S21-S25.
  • Step S21 depositing a silicon nitride material on the substrate layer 1 to form a first inorganic layer 21b; using silicon nitride material as the first inorganic layer 21b, it can be closely combined with the substrate layer 1, because the silicon nitride The bonding force with polyimide is greater than the bonding force between silicon oxide and polyimide, thereby increasing the adhesion between the buffer layer 2 and the substrate layer 1.
  • Step S22 depositing a silicon oxide material on the first inorganic layer 21b to form a second inorganic layer 22b.
  • Step S23 depositing a silicon nitride material on the second inorganic layer 22b to form a third inorganic layer 23b.
  • Step S24 deposit a silicon oxide material on the third inorganic layer 23b to form a fourth inorganic layer 24.
  • Step S25 depositing a silicon nitride material on the fourth inorganic layer 24 to form a fifth inorganic layer 25.
  • a single-layer SiNx film for example, the first inorganic layer 21b
  • the edge of the single-layer SiNx film will tilt away from the substrate layer 1 Tension
  • a single-layer SiO 2 film for example, the second inorganic layer 22b
  • the edges of the single-layer SiO 2 film will bend toward the substrate layer 1 and present pressure
  • the tension generated by the SiNx film and the pressure generated by the SiO 2 film can cancel each other, that is, the stresses of the first inorganic layer 21b and the second inorganic layer 22b cancel each other.
  • the buffer layer 2 cleverly utilizes the SiNx film and the SiO 2 film to offset each other in opposite stress directions, effectively avoiding the film stress. Impact.
  • the buffer layer 2 is preferably arranged in five layers. On the one hand, it can effectively eliminate the stress generated in the buffer layer 2, so that the tension and pressure can cancel each other, and on the other hand, it can reduce the production cost and maximize the guarantee
  • the array substrate 100 is light and thin.
  • the film thickness of the deposited silicon nitride material is equal to the film thickness of the deposited silicon oxide material, and all of them are vapor deposition, atomic deposition, pulsed laser deposition, or sputtering. Made in at least one way.
  • the film thicknesses of the first inorganic layer 21b, the second inorganic layer 22b and the third inorganic layer 23b, the fourth inorganic layer 24 and the fifth inorganic layer 25 are equal, which can effectively reduce tension and pressure. They cancel each other out, thereby reducing the stress generated inside the buffer layer 2 and avoiding the separation of the buffer layer 2 and the substrate layer 1.
  • one embodiment of the present invention provides a display panel, including the array substrate 100 described in Embodiment 1 or Embodiment 2.
  • the main content of the present invention is that the buffer layer 2 of the array substrate 100 is laminated with at least two inorganic layers whose stresses cancel each other.
  • the material of the inorganic layer is SiNx and SiO 2 , and the SiNx film is arranged by overlapping And the SiO 2 film can offset the tension generated by the SiNx film and the pressure generated by the SiO 2 film, thereby reducing the stress generated inside the buffer layer 2 and avoiding the separation of the buffer layer 2 and the substrate layer 1.
  • the buffer layer 2 cleverly utilizes the SiNx film and the SiO 2 film to offset each other in opposite stress directions, effectively avoiding the film stress. Impact.
  • the present invention improves the structure of the existing buffer layer to increase the adhesion between the buffer layer 2 and the substrate layer 1, thereby retaining the alignment mark 10, and can solve the problem caused by the buffer layer 2 falling off. The related problems of the loss of the alignment mark 10 are described.
  • the buffer layer 2 can be arranged in an odd-numbered film stack structure, preferably five layers. On the one hand, it can effectively eliminate the stress generated in the buffer layer 2, so that the tension and pressure can offset each other, and on the other hand, it can reduce the production The cost also guarantees the lightness and thinness of the array substrate 100 to the greatest extent.
  • the display panel in this embodiment may be any product or component with display function, such as wearable devices, mobile phones, tablet computers, televisions, displays, notebook computers, e-books, e-newspapers, digital photo frames, navigators, etc.
  • wearable devices include smart bracelets, smart watches, VR (Virtual Reality) and other devices.
  • the beneficial effect of the present invention is to provide a manufacturing method of an array substrate, a display panel and an array substrate, which improves the structure of the existing buffer layer to increase the adhesion between the buffer layer and the substrate layer, thereby retaining the alignment mark ( Mark), which can solve the problems related to the loss of alignment marks due to the lack of adhesion between the buffer layer and the substrate layer during the manufacturing process of the array substrate.
  • the buffer layer of the present invention cleverly utilizes the opposite stress directions of the SiNx film and the SiO 2 film to cancel each other out, and effectively avoids the influence of the film stress.

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Abstract

本发明提供一种阵列基板、显示面板及阵列基板的制作方法。阵列基板包括层叠设置的衬底层、缓冲层、标记层和薄膜晶体管层；所述缓冲层设于所述衬底层的一面，所述缓冲层中层叠有应力相互抵消的至少两层无机层；所述标记层设于所述缓冲层背离所述衬底层的一面；所述薄膜晶体管层设于所述缓冲层具有标记层的一侧。显示面板包括所述的阵列基板。阵列基板的制作方法包括步骤：基板提供、衬底层制作、缓冲层制作和薄膜晶体管层制作。

Description

阵列基板、显示面板及阵列基板的制作方法 技术领域
本发明涉及显示领域，尤其涉及一种阵列基板、显示面板及阵列基板的制作方法。
 背景技术
随着科技的进步和时代的发展，人们对手机显示屏的要求也越来越高。当前主流的硬屏显示已不能满足市场的需求，对柔性显示屏的开发就显得尤为重要。相比于硬屏制程，柔性薄膜晶体管液晶显示屏（Thin Film Transistor Liquid Crystal Display，TFT-LCD）的阵列基板制程多了聚酰亚胺（PI）材料的衬底层，而在衬底层上的缓冲层目前为单层SiNx或者单层SiO 2，单层SiNx的边缘会相背离衬底层方向翘起呈现张力，单层SiO 2的边缘会相朝向衬底层方向弯折呈现压力；当只做单层SiNx或者单层SiO 2制作缓冲层时，由于薄膜应力导致SiNx或者SiO 2可能与其上方或下方连接的膜层分离导致阵列基板失效。由于在阵列基板制程中缓冲层很容易与衬底层分离，尤其是设置在缓冲层上的对位标记（Mark）也会随着缓冲层与衬底层的分离而丢失，从而造成后续曝光制程因无对位标记可识别而终止。
因此，有必要提供一种新的阵列基板、显示面板及阵列基板的制作方法，以克服现有技术中存在的问题。
 技术问题
本发明的目的在于，提供一种阵列基板、显示面板及阵列基板的制作方法，通过改善现有的缓冲层的结构来增加缓冲层与衬底层的粘附力，从而保留了对位标记（Mark），可解决阵列基板制程中因缓冲层很容易与衬底层粘附力不够引起分离造成对位标记丢失的相关问题。
 技术解决方案
为了解决上述问题，本发明其中一实施例中提供一种阵列基板，包括层叠设置的衬底层、缓冲层、标记层和薄膜晶体管层。具体地讲，所述缓冲层设于所述衬底层的一面，所述缓冲层中层叠有应力相互抵消的至少两层无机层；所述标记层设于所述缓冲层背离所述衬底层的一面；所述薄膜晶体管层设于所述缓冲层具有标记层的一侧。
进一步地，在所述缓冲层中，所述无机层的层数为奇数层。
进一步地，所述无机层的层数为三层，包括第一无机层、第二无机层和第三无机层。具体地讲，所述第一无机层设于所述衬底层上，其材料为氮化硅；所述第二无机层设于所述第一无机层背离所述衬底层的一面上，其材料为氧化硅；所述第三无机层设于所述第二无机层背离所述第一无机层的一面上，其材料为氮化硅。
进一步地，所述无机层的层数为五层，所述无机层包括第一无机层、第二无机层、第三无机层、第四无机层和第五无机层。具体地讲，所述第一无机层设于所述衬底层上，其材料为氮化硅；所述第二无机层设于所述第一无机层背离所述衬底层的一面上，其材料为氧化硅；所述第三无机层设于所述第二无机层背离所述第一无机层的一面上，其材料为氮化硅；所述第四无机层设于所述第三无机层背离所述衬底层的一面上，其材料为氧化硅；所述第五无机层设于所述第四无机层背离所述第三无机层的一面上，其材料为氮化硅。
进一步地，所述第一无机层、所述第二无机层、所述第三无机层、所述第四无机层和所述第五无机层的膜层厚度相等。
进一步地，所述标记层包括若干对位标记，所述对位标记环绕所述标记层的周边设置。
本发明又一实施例中提供一种阵列基板的制作方法，包括以下步骤：
制作一衬底层；
制作应力相互抵消的至少两层层叠的无机层于所述衬底层上，形成缓冲层；
制作标记层于所述缓冲层背离所述衬底层的一面；以及
制作薄膜晶体管层于所述缓冲层具有标记层的一侧。
进一步地，所述缓冲层的制作步骤包括：
沉积氮化硅材料于所述衬底层上，形成第一无机层；
沉积氧化硅材料于所述第一无机层上，形成第二无机层；以及
沉积氮化硅材料于所述第二无机层上，形成第三无机层。
进一步地，所述缓冲层的制作步骤包括：
沉积氮化硅材料于所述衬底层上，形成第一无机层；
沉积氧化硅材料于所述第一无机层上，形成第二无机层；
沉积氮化硅材料于所述第二无机层上，形成第三无机层；
沉积氧化硅材料于所述第三无机层上，形成第四无机层；以及
沉积氮化硅材料于所述第四无机层上，形成第五无机层。
本发明再一实施例中提供一种显示面板，包括以上所述的阵列基板。
 有益效果
本发明的有益效果在于，提供一种阵列基板、显示面板及阵列基板的制作方法，通过改善现有的缓冲层的结构来增加缓冲层与衬底层的粘附力，从而保留了对位标记（Mark），可解决阵列基板制程中因缓冲层很容易与衬底层粘附力不够引起分离造成对位标记丢失的相关问题。
 附图说明
图1为本发明第一实施例中一种阵列基板的结构示意图；
图2为本发明第一实施例中所述缓冲层的俯视图，主要表现所述对位标记的分布位置；
图3为本发明第一实施例中所述薄膜晶体管层的结构示意图；
图4为本发明第二实施例中一种阵列基板的结构示意图；
图5为本发明实施例中一种阵列基板的制作方法的流程图；
图6为本发明第一实施例中所述缓冲层的制作流程图；
图7为本发明第二实施例中所述缓冲层的制作流程图。
图中部件标识如下：
1、衬底层，2、缓冲层，3、标记层，4、薄膜晶体管层，5、阴极层，
6、保护层，10、对位标记，20、玻璃基板，21a、21b、第一无机层，
22a、21b、第二无机层，23a、23b、所述第三无机层，24、第四无机层，
25、第五无机层，41、栅极层，42、栅极绝缘层，43、有源层，
44、源漏极层，100、阵列基板。
 本发明的实施方式
以下结合说明书附图详细说明本发明的优选实施例，以向本领域中的技术人员完整介绍本发明的技术内容，以举例证明本发明可以实施，使得本发明公开的技术内容更加清楚，使得本领域的技术人员更容易理解如何实施本发明。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例，下文实施例的说明并非用来限制本发明的范围。
本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是附图中的方向，本文所使用的方向用语是用来解释和说明本发明，而不是用来限定本发明的保护范围。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。此外，为了便于理解和描述，附图所示的每一组件的尺寸和厚度是任意示出的，本发明并没有限定每个组件的尺寸和厚度。
当某些组件，被描述为“在”另一组件“上”时，所述组件可以直接置于所述另一组件上；也可以存在一中间组件，所述组件置于所述中间组件上，且所述中间组件置于另一组件上。当一个组件被描述为“安装至”或“连接至”另一组件时，二者可以理解为直接“安装”或“连接”，或者一个组件通过一中间组件“安装至”或“连接至”另一个组件。
实施例1
请参阅图1所示，本发明第一实施例中提供一种阵列基板100，包括层叠设置的衬底层1、缓冲层2、标记层3和薄膜晶体管层4。具体地讲，所述缓冲层2设于所述衬底层1的一面，所述缓冲层2中层叠有应力相互抵消的至少两层无机层；所述标记层3设于所述缓冲层2背离所述衬底层1的一面；所述薄膜晶体管层4设于所述缓冲层2具有标记层3的一侧。所述衬底层1的材质为聚酰亚胺（PI）或其他缓冲材质，起到缓冲保护的作用。
为了便于应力相互抵消，所述缓冲层2的所述无机层的层数设置为奇数层，本实施例中，设置为三层，包括第一无机层21a、第二无机层22a和第三无机层23a。具体地讲，所述第一无机层21a设于所述衬底层1上，其材料为氮化硅；所述第二无机层22a设于所述第一无机层21a背离所述衬底层1的一面上，其材料为氧化硅；所述第三无机层23a设于所述第二无机层22a背离所述第一无机层21a的一面上，其材料为氮化硅。本实施例中采用氮化硅材料作为第一无机层21a，可使其与衬底层1紧密结合，是因为氮化硅与聚酰亚胺的结合力大于氧化硅与聚酰亚胺的结合力，从而增加缓冲层2与衬底层1的粘附力。若单层SiNx薄膜贴（例如所述第一无机层21a）附于所述衬底层1上时，在单层SiNx薄膜的边缘会相背离所述衬底层1方向翘起呈现张力；若单层SiO 2薄膜（例如所述第二无机层22a）设于所述衬底层1上时，在单层SiO 2薄膜的边缘会相朝向所述衬底层1方向弯折呈现压力；通过交叠设置SiNx薄膜和SiO 2薄膜可将SiNx薄膜产生的张力和SiO 2薄膜产生的压力相互抵消，即所述第一无机层21a和所述第二无机层22a的应力相互抵消，所述第二无机层22a和所述第三无机层23a的应力相互抵消，从而减小所述缓冲层2内部产生的应力，避免所述缓冲层2与所述衬底层1的分离。相比于现有的单层SiNx薄膜或者单层SiO 2薄膜的缓冲层设计，所述缓冲层2巧妙的利用了SiNx薄膜和SiO 2薄膜应力方向相反互相抵消，有效的规避了膜应力带来的影响。
本实施例中，所述第一无机层21a、所述第二无机层22a和所述第三无机层23a的膜层厚度相等。膜层厚度相等可有效将张力和压力相互抵消，从而减小所述缓冲层2内部产生的应力，避免所述缓冲层2与所述衬底层1的分离。
可选地，所述第二无机层22a和所述第三无机层23a重复贴附多次，形成氮化硅薄膜与氧化硅薄膜相互交错的薄膜堆叠结构，亦即形成的所述缓冲层2为3层、5层、7层……的奇数层薄膜堆叠结构。
请参阅图2所示，本实施例中，所述标记层3包括若干对位标记10，所述对位标记10环绕所述标记层3的周边设置，所述对位标记10可分布于所述标记层3的四个边角处，也可分布于所述标记层3的边缘，这样既可满足设置所述对位标记10的要求又可不影响其他功能。一般的，所述对位标记10呈十字形，方便对位对准。因所述缓冲层2与衬底层1不会分离，对位标记10会完整保留，从而利于后续曝光制程依据对位标记10进行识别对位后顺利进行。
请参阅图3所示，本实施例中，所述薄膜晶体管层4包括层叠设置的栅极层41、栅极绝缘层42、有源层43和源漏极层44。具体地讲，所述栅极层41设于所述缓冲层2背离所述衬底层1的一侧；所述栅极绝缘层42设于所述栅极层41背离所述缓冲层2的一侧；所述有源层43设于所述栅极绝缘层42背离所述栅极层41的一侧；所述源漏极层44设于所述有源层43背离所述栅极绝缘层42的一侧。值得说明的是，图3所示的所述薄膜晶体管层4结构仅为举例说明，而不是对本发明保护范围的限定，现有技术所有的所述薄膜晶体管层4结构均属于本发明保护范围。
请参阅图1所示，本实施例中，所述阵列基板100还包括阴极层5和保护层6。具体地讲，所述阴极层5设置于所述薄膜晶体管层4背离所述缓冲层2的一侧；所述保护层6完全包覆于所述阴极层5背离所述薄膜晶体管层4的一侧。保护层6完全包覆于阴极层5的上表面，起到保护薄膜晶体管层4的作用，减少水氧入侵的可能性，提高显示面板的性能。
请参阅图5所示，本发明其中一实施例提供一种阵列基板100的制作方法，其包括步骤S1-S3。
步骤S1：制作一衬底层1。所述衬底层1的材质为聚酰亚胺（PI）或其他缓冲材质，起到缓冲保护的作用。
步骤S2：制作应力相互抵消的至少两层层叠的无机层于所述衬底层1上，形成缓冲层2。这样设置，一方面可有效消除所述缓冲层2内部产生的应力，使张力和压力相互抵消。
步骤S3：制作标记层3于所述缓冲层2背离所述衬底层1的一面。
步骤S4：制作薄膜晶体管层4于所述缓冲层2具有标记层3的一侧。
请参阅图6所示，本实施例中，所述缓冲层2的制作步骤包括S21-S23。
步骤S21：沉积氮化硅材料于所述衬底层1上，形成第一无机层21a；采用氮化硅材料作为第一无机层21a，可使其与衬底层1紧密结合，是因为氮化硅与聚酰亚胺的结合力大于氧化硅与聚酰亚胺的结合力，从而增加缓冲层2与衬底层1的粘附力。
步骤S22：沉积氧化硅材料于所述第一无机层21a上，形成第二无机层22a。
步骤S23：沉积氮化硅材料于所述第二无机层22a上，形成第三无机层23a。
值得说明的是，若单层SiNx薄膜贴（例如所述第一无机层21a）附于所述衬底层1上时，在单层SiNx薄膜的边缘会相背离所述衬底层1方向翘起呈现张力；若单层SiO 2薄膜（例如所述第二无机层22a）设于所述衬底层1上时，在单层SiO 2薄膜的边缘会相朝向所述衬底层1方向弯折呈现压力；通过交叠设置SiNx薄膜和SiO 2薄膜可将SiNx薄膜产生的张力和SiO 2薄膜产生的压力相互抵消，即所述第一无机层21a和所述第二无机层22a的应力相互抵消，所述第二无机层22a和所述第三无机层23a的应力相互抵消，从而减小所述缓冲层2内部产生的应力，避免所述缓冲层2与所述衬底层1的分离。相比于现有的单层SiNx薄膜或者单层SiO 2薄膜的缓冲层设计，所述缓冲层2巧妙的利用了SiNx薄膜和SiO 2薄膜应力方向相反互相抵消，有效的规避了膜应力带来的影响。
实施例2
请参阅图4所示，本发明第二实施例中包括第一实施例的所有技术特征，其区别在于，在本发明第二实施例中所述缓冲层2的所述无机层的层数为五层，具体的，所述缓冲层2包括所述第一无机层21b、所述第二无机层22b、所述第三无机层23b、第四无机层24和第五无机层25。其中，所述第一无机层21b设于所述衬底层1上，其材料为氮化硅；所述第二无机层22b设于所述第一无机层21b背离所述衬底层1的一面上，其材料为氧化硅；所述第三无机层23b设于所述第二无机层22b背离所述第一无机层21b的一面上，其材料为氮化硅；所述第四无机层24设于所述第三无机层23b背离所述衬底层的一面上，其材料为氧化硅；所述第五无机层25设于所述第四无机层24背离所述第三无机层23b的一面上，其材料为氮化硅。采用氮化硅材料作为第一无机层21b，可使其与衬底层1紧密结合，是因为氮化硅与聚酰亚胺的结合力大于氧化硅与聚酰亚胺的结合力，从而增加缓冲层2与衬底层1的粘附力。所述第四无机层24和所述第五无机层25的应力相互抵消，从而减小所述缓冲层2内部产生的应力，避免所述缓冲层2与所述衬底层1的分离。
请参阅图4所示，本实施例中，所述缓冲层2优选设置为五层，其一方面可有效消除所述缓冲层2内部产生的应力，使张力和压力相互抵消，另一方面可减少制作成本并最大程度保证所述阵列基板100的轻薄化。
本实施例中，所述第一无机层21b、所述第二无机层22b和所述第三无机层23b的膜层厚度相等。膜层厚度相等可有效将张力和压力相互抵消，从而减小所述缓冲层2内部产生的应力，避免所述缓冲层2与所述衬底层1的分离。
请参阅图5所示，本发明其中一实施例提供一种阵列基板100的制作方法，其包括步骤S1-S3。
步骤S1：制作一衬底层1。所述衬底层1的材质为聚酰亚胺（PI）或其他缓冲材质，起到缓冲保护的作用。
步骤S2：制作应力相互抵消的至少两层层叠的无机层于所述衬底层1上，形成缓冲层2。这样设置，一方面可有效消除所述缓冲层2内部产生的应力，使张力和压力相互抵消。
步骤S3：制作标记层3于所述缓冲层2背离所述衬底层1的一面。
步骤S4：制作薄膜晶体管层4于所述缓冲层2具有标记层3的一侧。
请参阅图7所示，本实施例中，所述缓冲层2的制作步骤包括S21-S25。
步骤S21：沉积氮化硅材料于所述衬底层1上，形成第一无机层21b；采用氮化硅材料作为第一无机层21b，可使其与衬底层1紧密结合，是因为氮化硅与聚酰亚胺的结合力大于氧化硅与聚酰亚胺的结合力，从而增加缓冲层2与衬底层1的粘附力。
步骤S22：沉积氧化硅材料于所述第一无机层21b上，形成第二无机层22b。
步骤S23：沉积氮化硅材料于所述第二无机层22b上，形成第三无机层23b。
步骤S24：沉积氧化硅材料于所述第三无机层23b上，形成第四无机层24。
步骤S25：沉积氮化硅材料于所述第四无机层24上，形成第五无机层25。
值得说明的是，若单层SiNx薄膜贴（例如所述第一无机层21b）附于所述衬底层1上时，在单层SiNx薄膜的边缘会相背离所述衬底层1方向翘起呈现张力；若单层SiO 2薄膜（例如所述第二无机层22b）设于所述衬底层1上时，在单层SiO 2薄膜的边缘会相朝向所述衬底层1方向弯折呈现压力；通过交叠设置SiNx薄膜和SiO 2薄膜可将SiNx薄膜产生的张力和SiO 2薄膜产生的压力相互抵消，即所述第一无机层21b和所述第二无机层22b的应力相互抵消，所述第二无机层22b和所述第三无机层23b的应力相互抵消，述第四无机层24和所述第五无机层25的应力相互抵消，从而减小所述缓冲层2内部产生的应力，避免所述缓冲层2与所述衬底层1的分离。相比于现有的单层SiNx薄膜或者单层SiO 2薄膜的缓冲层设计，所述缓冲层2巧妙的利用了SiNx薄膜和SiO 2薄膜应力方向相反互相抵消，有效的规避了膜应力带来的影响。
本实施例中，所述缓冲层2优选设置为五层，其一方面可有效消除所述缓冲层2内部产生的应力，使张力和压力相互抵消，另一方面可减少制作成本并最大程度保证所述阵列基板100的轻薄化。
本实施例中，所述沉积氮化硅材料的膜层厚度和所述沉积氧化硅材料的膜层厚度相等，其均采用气相沉积法、原子沉积法、脉冲激光沉积法或溅镀法中的至少一种方式制作。所述第一无机层21b、所述第二无机层22b和所述第三无机层23b、所述第四无机层24和所述第五无机层25的膜层厚度相等可有效将张力和压力相互抵消，从而减小所述缓冲层2内部产生的应力，避免所述缓冲层2与所述衬底层1的分离。
基于同样的发明构思，本发明其中一实施例中提供一种显示面板，包括实施例1或实施例2所述的阵列基板100。本发明主要发明内容在于，在所述阵列基板100的所述缓冲层2中层叠有应力相互抵消的至少两层无机层，所述无机层的材料采用SiNx和SiO 2，通过交叠设置SiNx薄膜和SiO 2薄膜可将SiNx薄膜产生的张力和SiO 2薄膜产生的压力相互抵消，从而减小所述缓冲层2内部产生的应力，避免所述缓冲层2与所述衬底层1的分离。相比于现有的单层SiNx薄膜或者单层SiO 2薄膜的缓冲层设计，所述缓冲层2巧妙的利用了SiNx薄膜和SiO 2薄膜应力方向相反互相抵消，有效的规避了膜应力带来的影响。本发明通过改善现有的缓冲层的结构来增加所述缓冲层2与所述衬底层1的粘附力，从而保留了所述对位标记10，可解决因所述缓冲层2脱落造成所述对位标记10丢失的相关问题。
其中所述缓冲层2可设置成奇数层薄膜堆叠结构，优选设置为五层，其一方面可有效消除所述缓冲层2内部产生的应力，使张力和压力相互抵消，另一方面可减少制作成本并最大程度保证所述阵列基板100的轻薄化。
本实施例中的显示面板可以为：可穿戴设备、手机、平板电脑、电视机、显示器、笔记本电脑、电子书、电子报纸、数码相框、导航仪等任何具有显示功能的产品或部件。其中可穿戴设备包括智能手环、智能手表、VR（Virtual Reality，即虚拟现实）等设备。
本发明的有益效果在于，提供一种阵列基板、显示面板及阵列基板的制作方法，通过改善现有的缓冲层的结构来增加缓冲层与衬底层的粘附力，从而保留了对位标记（Mark），可解决阵列基板制程中因缓冲层很容易与衬底层粘附力不够引起分离造成对位标记丢失的相关问题。本发明所述缓冲层巧妙的利用了SiNx薄膜和SiO 2薄膜应力方向相反互相抵消，有效的规避了膜应力带来的影响。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种阵列基板，其包括
    衬底层；
    缓冲层，设于所述衬底层的一面，所述缓冲层中层叠有应力相互抵消的至少两层无机层；
    标记层，设于所述缓冲层背离所述衬底层的一面；以及
    薄膜晶体管层，设于所述缓冲层具有标记层的一侧。
  2. 根据权利要求1所述的阵列基板，其中，在所述缓冲层中，所述无机层的层数为奇数层。
  3. 根据权利要求1所述的阵列基板，其中，所述无机层的层数为三层，包括
    第一无机层，设于所述衬底层上，其材料为氮化硅；
    第二无机层，设于所述第一无机层背离所述衬底层的一面上，其材料为氧化硅；以及
    第三无机层，设于所述第二无机层背离所述第一无机层的一面上，其材料为氮化硅。
  4. 根据权利要求1所述的阵列基板，其中，所述无机层的层数为五层，还包括
    第一无机层，设于所述衬底层上，其材料为氮化硅；
    第二无机层，设于所述第一无机层背离所述衬底层的一面上，其材料为氧化硅；
    第三无机层，设于所述第二无机层背离所述第一无机层的一面上，其材料为氮化硅；
    第四无机层，设于所述第三无机层背离所述衬底层的一面上，其材料为氧化硅；以及
    第五无机层，设于所述第四无机层背离所述第三无机层的一面上，其材料为氮化硅。
  5. 根据权利要求1所述的阵列基板，其中，所述标记层包括若干对位标记，所述对位标记环绕所述标记层的周边设置。
  6. 根据权利要求4所述的阵列基板，其中，所述第一无机层、所述第二无机层、所述第三无机层、所述第四无机层和所述第五无机层的膜层厚度相等。
  7. 一种阵列基板的制作方法，其包括以下步骤：
    制作一衬底层；
    制作应力相互抵消的至少两层层叠的无机层于所述衬底层上，形成缓冲层；
    制作标记层于所述缓冲层背离所述衬底层的一面；以及
    制作薄膜晶体管层于所述缓冲层具有标记层的一侧。
  8. 根据权利要求7所述的阵列基板的制作方法，其中，所述缓冲层的制作步骤包括：
    沉积氮化硅材料于所述衬底层上，形成第一无机层；
    沉积氧化硅材料于所述第一无机层上，形成第二无机层；以及
    沉积氮化硅材料于所述第二无机层上，形成第三无机层。
  9. 根据权利要求7所述的阵列基板的制作方法，其中，所述缓冲层的制作步骤还包括：
    沉积氮化硅材料于所述衬底层上，形成第一无机层；
    沉积氧化硅材料于所述第一无机层上，形成第二无机层；
    沉积氮化硅材料于所述第二无机层上，形成第三无机层；
    沉积氧化硅材料于所述第三无机层上，形成第四无机层；以及
    沉积氮化硅材料于所述第四无机层上，形成第五无机层。
  10. 一种显示面板，其包括根据权利要求1所述的阵列基板。
PCT/CN2019/105085 2019-06-12 2019-09-10 阵列基板、显示面板及阵列基板的制作方法 WO2020248408A1 (zh)

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