WO2020244042A1 - 存储芯片、固态硬盘及其温度控制方法 - Google Patents

存储芯片、固态硬盘及其温度控制方法 Download PDF

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Publication number
WO2020244042A1
WO2020244042A1 PCT/CN2019/098030 CN2019098030W WO2020244042A1 WO 2020244042 A1 WO2020244042 A1 WO 2020244042A1 CN 2019098030 W CN2019098030 W CN 2019098030W WO 2020244042 A1 WO2020244042 A1 WO 2020244042A1
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flash memory
temperature sensor
memory chip
wafer
temperature
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PCT/CN2019/098030
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English (en)
French (fr)
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孙成思
孙日欣
李振华
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深圳佰维存储科技股份有限公司
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Publication of WO2020244042A1 publication Critical patent/WO2020244042A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
    • G05D23/00—Control of temperature
    • G05D23/19—Control of temperature characterised by the use of electric means
    • G05D23/20—Control of temperature characterised by the use of electric means with sensing elements having variation of electric or magnetic properties with change of temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • This application relates to the field of solid state drives, and in particular to a storage chip, a solid state drive and a temperature control method thereof.
  • Solid state drives are widely used in various fields due to their advantages of fast read and write speed, low power consumption and lightness.
  • solid state drives used in industrial applications have high temperature in the application environment, and at the same time, the product heats up greatly, which will cause The radiation and movement of electric charges can easily cause storage errors when the temperature reaches a certain level. In severe cases, it may cause damage to the hard disk and cause incalculable losses. Therefore, improving the stability and integrity of hard disk data writing is the current chip industry One of the important quality assessment standards.
  • a temperature sensor is usually installed next to the memory chip to collect temperature data.
  • the temperature sensor is used to detect the temperature of the chip and collect the data to the main controller.
  • the main controller then adjusts the solid-state hard drive according to the temperature.
  • Working conditions to protect products and internal data.
  • the internal temperature of the memory chip causes a temperature difference between the inside and the outside, and the temperature of multiple memory chips in the solid state drive affects each other, it is difficult for the temperature sensor to obtain the accurate temperature data of each storage chip, making the solid state drive still prone to storage Problems with errors or even damage.
  • the main purpose of this application is to propose a memory chip, which aims to solve the problem in the prior art that it is difficult for the temperature sensor to detect the temperature inside the memory chip, which affects the accurate control of the temperature of the memory chip.
  • a storage chip includes a packaging substrate, a temperature sensor, and a flash memory wafer arranged on the packaging substrate, and the temperature sensor and the flash memory wafer are packaged in the same space.
  • the flash memory wafer has a single-layer structure, and the temperature sensor is arranged on the upper surface of the flash memory wafer.
  • the flash memory wafer has a multi-layer structure
  • the temperature sensor is disposed on the packaging substrate and is located on one side of the flash memory wafer, and the temperature sensor and the flash memory wafer conduct heat through the packaging substrate.
  • the memory chip further includes a thermally conductive metal for connecting the flash memory wafer and the temperature sensor.
  • the thermally conductive metal is a copper sheet located at the bottom of the flash memory wafer and the temperature sensor; or, the thermally conductive metal is a copper wire, and one end of the copper wire is connected to the flash memory interface of the flash memory wafer Connected, the other end is connected with the temperature sensor.
  • the flash memory wafer with a multi-layer structure is arranged in a stepwise staggered arrangement on the packaging substrate.
  • the packaging substrate has a first surface on which the flash memory wafer is mounted and a second surface opposite to the first surface, and the first surface is provided with a temperature sensor and a flash memory wafer.
  • the second surface is provided with a solder ball layer.
  • the present application also proposes a solid-state hard disk, including a controller and a number of storage chips, the storage chip being the storage chip as described in any one of the above, and the plurality of storage chips are serially connected in series and then electrically connected to the controller.
  • This application also proposes a temperature control method for a solid-state hard disk, and the temperature control method includes:
  • any memory chip reaches the second threshold, stop the operation of the memory chip whose temperature reaches the second threshold, and the second threshold is greater than the first threshold.
  • the temperature sensor and the flash memory wafer are packaged in the same space, so the controller outside the memory chip can directly obtain the internal temperature of the memory chip, thereby accurately monitoring the internal temperature of each memory chip, and reducing the temperature difference between the inside and outside of the memory chip. Problems such as inaccurate temperature detection caused by the mutual influence of the temperature between the memory chips. Therefore, the controller can adjust the temperature of each memory chip according to the internal temperature of each memory chip in time by adjusting the operating frequency of the memory chip to prevent damage caused by excessive temperature, increase the working life of the memory chip and solid state drive, and reduce storage Error rate.
  • FIG. 1 is a schematic structural diagram of an embodiment of a memory chip of this application
  • FIG. 2 is a schematic structural diagram of another embodiment of the memory chip of the application.
  • FIG. 3 is a schematic structural diagram of an embodiment of the solid-state hard disk of this application.
  • FIG. 4 is a schematic flowchart of the temperature control method of the solid-state hard disk of this application.
  • the present application proposes a memory chip 10.
  • the memory chip 10 includes a packaging substrate 1, a temperature sensor 3, and a flash memory wafer 2 arranged on the packaging substrate 1.
  • the temperature sensor 3 and the flash memory wafer 2 are packaged in the same space.
  • the solid-state hard disk includes a memory chip 10 and a controller 20, both of which are fixed on the PCB circuit board 30 of the hard disk through glue.
  • the packaging substrate 1 is a PCB board with a circuit structure and a data interface on its surface.
  • the flash memory wafer 2 and the temperature sensor 3 in the memory chip 10 are both fixed to the corresponding positions on the packaging substrate 1 by insulating glue, and then packaged into particles, and the flash memory The wafer 2 and the temperature sensor 3 are packaged in the same space.
  • the flash memory interface and the temperature sensor 3 of the flash memory wafer 2 after packaging are respectively connected to the data interface of the packaging substrate 1, and communicate with the controller 20 outside the memory chip 10 through the data interface.
  • the controller 20 can directly obtain the internal temperature of the memory chip 10, so as to accurately monitor the internal temperature of each memory chip 10, and reduce the temperature difference between the internal and the external of the memory chip 10. Inaccurate temperature detection caused by the mutual influence of the temperature between two memory chips 10, the controller 20 can therefore adjust the operating frequency of each memory chip 10 in time according to the internal temperature of each memory chip 10 by controlling the operating frequency of the memory chip 10 The temperature prevents damage caused by excessively high temperature, improves the working life of the storage chip 10 and the solid state hard disk, and reduces the storage error rate.
  • the flash memory wafer 2 has a single-layer structure, and the temperature sensor 3 is disposed on the upper surface of the flash memory wafer 2.
  • the flash memory wafer 2 is a single-layer structure, which means that only one flash memory wafer 2 is fixed on the package substrate 1. As the number of flash memory wafers 2 is small, the height after stacking is correspondingly small, and the temperature sensor 3 is directly arranged on the flash memory wafer. The circle 2 does not affect the overall height of the memory chip 10, and the direct contact between the temperature sensor 3 and the flash memory wafer 2 is more conducive to directly collecting the temperature of the flash memory wafer 2.
  • the flash memory wafer 2 has a multi-layer structure
  • the temperature sensor 3 is disposed on the packaging substrate 1 and is located on one side of the flash memory wafer 2
  • the temperature sensor 3 and the flash memory wafer 2 Heat conduction through the package substrate 1.
  • the flash memory wafer 2 with a multi-layer structure refers to a stack of multiple flash memory wafers 2, and the stacking direction is perpendicular to the surface of the package substrate 1.
  • the flash memory interfaces of two adjacent flash memory wafers 2 are connected, and the most The flash memory interface of the flash memory wafer 2 close to the package substrate 1 is connected to the data interface of the package substrate 1 to form a series structure as a whole.
  • the stacked flash memory wafers 2 have a small distance between each other, so connecting the connecting lines of two adjacent flash memory interfaces Very short, so the parasitic capacitance is very small.
  • the stacked form of a plurality of flash memory wafers 2 enables the memory chip 10 to have a certain height of packaging space.
  • the temperature sensor 3 is located in the packaging space and is arranged on either side of the flash memory wafer 2 on the front, back, left or right. Therefore, the original height of the memory chip 10 (that is, the height when only the flash memory wafer is packaged) is no longer increased, and the packaged height of the memory chip 10 is maintained within a certain range. While the temperature sensor 3 is used, it is reduced as much as possible The volume of the memory chip 10.
  • the flash memory wafer 2 and the temperature sensor 3 can conduct heat through the circuit structure (or other heat conducting components) on the packaging substrate 1.
  • the memory chip 10 further includes a thermally conductive metal for connecting the flash memory wafer 2 and the temperature sensor 3.
  • the function of the thermally conductive metal is to directly transmit the temperature of the flash memory wafer 2 to the temperature sensor 3 so that the temperature sensor 3 can obtain the temperature of the flash memory wafer 2 more accurately.
  • the heat-conducting metal can be made of copper, silver, aluminum and other materials.
  • the thermally conductive metal is a copper sheet, which is located at the bottom of the flash memory wafer 2 and the temperature sensor 3; or, the thermally conductive metal is a copper wire, and one end of the copper wire is connected to the flash memory interface of the flash memory wafer 2. The other end is connected to the temperature sensor 3.
  • the thermally conductive metal can be copper sheet or copper wire.
  • the copper sheet can be placed on the bottom of flash memory wafer 2 and temperature sensor 3 to reduce the space occupied; when copper wire is used, copper wire can be used.
  • the two ends of the are respectively connected to the flash memory interface of the flash memory wafer 2 and the temperature probe of the temperature sensor 3.
  • the heat-conducting metal using copper sheet or copper wire can be selected according to actual production requirements.
  • the flash memory wafer 2 with a multi-layer structure is arranged in a stepped staggered arrangement on the packaging substrate 1.
  • the stacking direction of the flash memory wafer 2 of the multi-layer structure is perpendicular to the surface of the packaging substrate 1.
  • the flash memory wafer 2 of the multi-layer structure is arranged in a staggered manner, thus forming a stepped top. Between the bottom and the bottom, a concave space is formed, and the temperature sensor 3 is located in the concave space.
  • the package substrate 1 has a first surface on which the flash memory wafer 2 is mounted and a second surface opposite to the first surface.
  • the first surface is provided with a circuit structure, and the flash memory wafer 2 and the temperature sensor 3 are correspondingly fixed at designated positions in the circuit structure
  • the edge of the packaging substrate 1 is provided with a data interface connected to the circuit structure. After the memory chip 10 is packaged, the circuit structure is located inside the packaging particles, and the data interface is located outside the packaging particles to connect to the controller 20.
  • the second surface of the packaging substrate 1 is provided with a solder ball layer, which is used to electrically connect with the PCB circuit board 30 of the solid state hard disk to realize communication with the controller 20.
  • the present application also proposes a solid-state hard disk, including a PCB circuit board 30, a controller 20 arranged on the circuit board 30, and a plurality of memory chips 10, the memory chip 10 being as described in any of the above embodiments
  • the memory chip 10 is connected in series with a plurality of memory chips 10 and then electrically connected to the controller 20.
  • a number of memory chips 10 on the PCB circuit board 30 are serially connected in series (that is, the data interfaces of the packaging substrates 1 of two adjacent memory chips 10 are connected) and then connected to the controller 20, and the controller 20 responds to the memory chip 10 accordingly.
  • the controller 20 can control the operating frequency of each memory chip 10 after obtaining the internal temperature sensor 3 of each memory chip 10 to adjust its temperature and reduce the thermal damage of the memory chip 10.
  • the present application also proposes a temperature control method for a solid state hard disk, and the temperature control method includes:
  • Step S10 Acquire the temperature inside each storage chip 10 in real time, that is, the controller 20 obtains the temperature data collected by the temperature sensor 3 in the storage chip 10.
  • Step S20 If the temperature of any memory chip 10 reaches the first threshold, the operating frequency of the memory chip 10 whose temperature reaches the first threshold is reduced.
  • the first threshold can be selected according to actual needs. Generally, its range does not exceed 70°C-95°C.
  • the first threshold When the temperature in the memory chip 10 is greater than the first threshold, it indicates that the memory chip 10 has performance degradation and storage errors. Therefore, it is necessary to reduce its operating frequency to reduce the power consumption of the flash memory wafer 2, thereby reducing its temperature output, reducing the temperature accumulation in the memory chip 10, and allowing the memory chip 10 to naturally cool down.
  • the temperature of the memory chip 10 is lower than the first threshold, the operating frequency can be restored.
  • Step S30 If the temperature of any memory chip 10 reaches the second threshold, stop the operation of the memory chip 10 whose temperature reaches the second threshold, and the second threshold is greater than the first threshold.
  • the second threshold can be selected according to actual needs. Generally, its range does not exceed 95°C-100°C.
  • the working process of the memory chip 10 should be stopped immediately, restarted when its temperature drops to the second threshold, and work at the first operating frequency; when its temperature drops to the first threshold, it will work at the second operating frequency.
  • a working frequency is less than the second working frequency.
  • the working frequency of the storage chip 10 needs to be set according to actual applications. Different environments and solid-state hard disks for different purposes have different parameters.

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Abstract

一种存储芯片、固态硬盘及其温度控制方法，其中存储芯片（10）包括封装基板（1）、温度传感器（3）和设置于封装基板（1）上的闪存晶圆（2），温度传感器（3）与闪存晶圆（2）封装于同一空间内。将温度传感器（3）与闪存晶圆（2）封装于同一空间内，因此存储芯片（10）外部的控制器（20）能够直接获得存储芯片（10）的内部温度，从而准确监控每个存储芯片（10）的内部温度，降低因存储芯片（10）内外温差等造成的温度检测不准问题。

Description

存储芯片、固态硬盘及其温度控制方法 技术领域
本申请涉及固态硬盘领域，具体涉及一种存储芯片、固态硬盘及其温度控制方法。
背景技术
固态硬盘以其读写速度快、功耗低和轻便的优势广泛应用于各个领域，其中应用于工业场合的固态硬盘产品，因为应用环境温度较高，而同时产品自身发热较大，温度会导致电荷的放射和移动，当温度高达一定程度时却容易造成存储出错，严重的还可能引起硬盘的损毁，造成难以估摸的损失，因此，提高硬盘数据写入的稳定性和完整性是当前芯片行业重要的质量评估标准之一。
在现有技术中，通常是在存储芯片的旁边安装温度传感器以采集温度数据，以温度传感器来对芯片温度进行侦测并把数据采集到主控制器，主控制器再根据温度调节固态硬盘的工作状况，从而对产品和内部数据进行保护。但是因为存储芯片内部有温升使其内外产生温差，且固态硬盘中多个存储芯片之间的温度相互影响，令温度传感器难以得到每个存储芯片的准确温度数据，使得固态硬盘仍旧容易出现存储出错甚至损坏的问题。
技术问题
本申请的主要目的是提出一种存储芯片，旨在解决现有技术中温度传感器难以检测到存储芯片内部的温度而影响对存储芯片温度的准确控制的问题。
技术解决方案
本申请解决上述技术问题所采用的技术方案如下：
一种存储芯片，所述存储芯片包括封装基板、温度传感器和设置于封装基板上的闪存晶圆，所述温度传感器与所述闪存晶圆封装于同一空间内。
优选地，所述闪存晶圆为单层结构，所述温度传感器设置在所述闪存晶圆的上表面。
优选地，所述闪存晶圆为多层结构，所述温度传感器设置在所述封装基板上且位于所述闪存晶圆的一侧，所述温度传感器与闪存晶圆通过所述封装基板导热。
优选地，存储芯片还包括用于连接所述闪存晶圆与所述温度传感器的导热金属。
优选地，所述导热金属为铜片，所述铜片位于所述闪存晶圆和温度传感器的底部；或者，所述导热金属为铜丝，所述铜丝的一端与闪存晶圆的闪存接口连接，另一端与所述温度传感器连接。
优选地，多层结构的所述闪存晶圆在所述封装基板上呈阶梯状错位布置。
优选地，所述封装基板具有安装所述闪存晶圆的第一表面和与所述第一表面相对的第二表面，所述第一表面上设有用于与所述温度传感器和闪存晶圆连接的数据接口，所述第二表面设有锡球层。
本申请还提出一种固态硬盘，包括控制器和若干存储芯片，所述存储芯片为如上任一项所述的存储芯片，若干所述存储芯片依次串联后与所述控制器电连接。
本申请还提出一种固态硬盘的温度控制方法，该温度控制方法包括：
实时获取每个存储芯片内部的温度；
若任一存储芯片的温度达到第一阈值，则降低温度达到第一阈值的存储芯片的工作频率；
若任一存储芯片的温度达到第二阈值，则停止温度达到第二阈值的存储芯片的工作，所述第二阈值大于所述第一阈值。
有益效果
本申请将温度传感器与闪存晶圆封装于同一空间内，因此存储芯片外部的控制器能够直接获得存储芯片的内部温度，从而准确监控每个存储芯片的内部温度，降低因存储芯片内外温差、多个存储芯片间温度互相影响等造成 的温度检测不准等问题。控制器因此能够根据每个存储芯片的内部温度及时通过调节存储芯片的工作频率而相应调节每个存储芯片的温度，防止其温度过高造成损害，提高存储芯片以及固态硬盘的工作寿命，降低存储出错率。
附图说明
图1为本申请的存储芯片一实施例的结构示意图；
图2为本申请的存储芯片又一实施例的结构示意图；
图3为本申请的固态硬盘一实施例的结构示意图；
图4为本申请的固态硬盘的温度控制方法的流程示意图。
本申请的实施方式
下面将详细描述本申请的实施例，实施例的示例在附图中示出，其中自始至终相同标号表示相同的元件或具有相同功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本申请，而不能理解为对本申请的限制，基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
为解决上述技术问题，如图1和图2所示，本申请提出一种存储芯片10，存储芯片10包括封装基板1、温度传感器3和设置于封装基板1上的闪存晶圆2，温度传感器3与闪存晶圆2封装于同一空间内。
本实施例中，如图3所示，固态硬盘包括有存储芯片10和控制器20，两者均通过贴溶胶固定在硬盘的PCB电路板30上。封装基板1为PCB板，其表面具有电路结构及数据接口，存储芯片10中闪存晶圆2和温度传感器3均通过绝缘胶固定在封装基板1上的相应位置，再封装为颗粒，并且将闪存晶圆2与温度传感器3封装于同一空间内。封装后闪存晶圆2的闪存接口和温度传感器3分别与封装基板1的数据接口连接，通过该数据接口与存储芯片10外部的控制器20连接通信。
由于温度传感器3与闪存晶圆2封装于同一空间内，因此控制器20能够直接获得存储芯片10的内部温度，从而准确监控每个存储芯片10的内部温度，降低因存储芯片10内外温差、多个存储芯片10间温度互相影响等造成的温度检测不准等问题，控制器20因此能够根据每个存储芯片10的内部温 度及时通过控制存储芯片10的工作频率而相应调节每个存储芯片10的温度，防止其温度过高造成损害，提高存储芯片10以及固态硬盘的工作寿命，降低存储出错率。
在一较佳实施例中，如图2所示，闪存晶圆2为单层结构，温度传感器3设置在闪存晶圆2的上表面。
闪存晶圆2为单层机构，意为封装基板1上只固定有一片闪存晶圆2，由于闪存晶圆2数量少，其堆叠之后的高度相应较小，将温度传感器3直接设置在闪存晶圆2上，并不影响存储芯片10的整体高度，并且温度传感器3与闪存晶圆2的直接接触，更有利于直接采集闪存晶圆2的温度。
在一较佳实施例中，如图1所示，闪存晶圆2为多层结构，温度传感器3设置在封装基板1上且位于闪存晶圆2的一侧，温度传感器3与闪存晶圆2通过封装基板1导热。
多层结构的闪存晶圆2指的是多片闪存晶圆2叠合而成，且其叠合方向垂直于封装基板1的表面，相邻两片闪存晶圆2的闪存接口相连接，最靠近封装基板1的闪存晶圆2的闪存接口与封装基板1的数据接口连接，使整体形成串联结构，堆叠的闪存晶圆2相互之间间距很小，因此连接相邻两闪存接口的连接线非常短，寄生电容因此很小。
多个闪存晶圆2叠合的形态，使存储芯片10具有一定高度的封装空间，温度传感器3位于该封装空间内，并设置于闪存晶圆2的前、后、左、右任意一侧，因此不再增加存储芯片10的原始高度(即仅封装有闪存晶圆的情况下的高度)而将存储芯片10封装后的高度维持在一定范围内，在使用温度传感器3的同时，尽可能缩减存储芯片10的体积。闪存晶圆2与温度传感器3可通过封装基板1上的电路结构(或其他导热件)导热。
为进一步将温度传感器3所检测的温度与闪存晶圆2的实际温度之间的误差缩小，存储芯片10还包括用于连接闪存晶圆2与温度传感器3的导热金属。该导热金属的作用是将闪存晶圆2的温度直接传导给温度传感器3，使温度传感器3能够更准确地获得闪存晶圆2的温度。本实施例中，导热金属可采用铜、银、铝等材质。
在一较佳实施例中，导热金属为铜片，铜片位于闪存晶圆2和温度传感器3的底部；或者，导热金属为铜丝，铜丝的一端与闪存晶圆2的闪存接口 连接，另一端与温度传感器3连接。
综合导热性能和材料成本，铜材料兼具高导热和低成本的优点。导热金属可以为铜片或铜丝，当其采用铜片时，可将该铜片设置在闪存晶圆2和温度传感器3的底部，减少占用空间；当其采用铜丝时，可令铜丝的两端分别与闪存晶圆2的闪存接口和温度传感器3的温度探头连接。导热金属采用铜片或铜丝可根据实际生产需求而选择。
进一步的，如图1所示，多层结构的闪存晶圆2在封装基板1上呈阶梯状错位布置。多层结构的闪存晶圆2的叠加方向垂直于封装基板1的表面，在平行于封装基板1表面的方向上，多层结构的闪存晶圆2错位布置，因此形成阶梯状，阶梯状的顶部和底部之间，构成了内凹空间，温度传感器3位于该内凹空间内。
封装基板1具有安装闪存晶圆2的第一表面和与第一表面相对的第二表面，第一表面上设有电路结构，闪存晶圆2和温度传感器3对应固定在电路结构中的指定位置，封装基板1边缘设置有与该电路结构连接的数据接口，存储芯片10封装后，电路结构位于封装颗粒内，数据接口位于封装颗粒外，以连接控制器20。封装基板1的第二表面设有锡球层，用于与固态硬盘的PCB电路板30电连接，实现与控制器20的通信。
如图3所示，本申请还提出一种固态硬盘，包括PCB电路板30和设置于电路板30上的控制器20与若干存储芯片10，存储芯片10为如上任意一项实施例所述的存储芯片10，若干存储芯片10依次串联后与控制器20电连接。
本实施例中，PCB电路板30上若干存储芯片10依次串联(即相邻两存储芯片10的封装基板1的数据接口相连接)后与控制器20连接，控制器20则相应对存储芯片10进行指令控制和数据传输，控制器20获得每个存储芯片10的内部温度传感器3后可相应控制每个存储芯片10的工作频率以调节其温度，减少存储芯片10热损坏等问题。
如图4所示，本申请还提出一种固态硬盘的温度控制方法，该温度控制方法包括：
步骤S10：实时获取每个存储芯片10内部的温度，即控制器20获取存储芯片10中的温度传感器3所采集的温度数据。
步骤S20：若任一存储芯片10的温度达到第一阈值，则降低温度达到第 一阈值的存储芯片10的工作频率。
本步骤中，第一阈值可根据实际所需选取，一般其范围不超过70℃-95℃，当存储芯片10内的温度大于第一阈值，则表明该存储芯片10存在性能降低、存储出错的风险，因此需要减小其工作频率来减少闪存晶圆2的功耗，从而令其温度输出降低，减小存储芯片10内的温度累积，令存储芯片10自然降温。当存储芯片10的温度低于第一阈值后，可恢复工作频率。
步骤S30：若任一存储芯片10的温度达到第二阈值，则停止温度达到第二阀值的存储芯片10的工作，第二阈值大于第一阈值。
本步骤中，第二阈值可根据实际所需选取，一般其范围不超过95℃-100℃，当存储芯片10内的温度达到更高的第二阈值，则表明该存储芯片10存在损毁风险，应立刻停止该存储芯片10的工作进程，当其温度降低至第二阈值时重新启动，并以第一工作频率工作；当其温度降低至第一阈值后，则以第二工作频率工作，第一工作频率小于第二工作频率，该存储芯片10的工作频率的选取需根据实际应用时设定，不同的环境以及不同用途的固态硬盘，其各项参数存在差别。
以上的仅为本申请的部分或优选实施例，无论是文字还是附图都不能因此限制本申请保护的范围，凡是在与本申请一个整体的构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请保护的范围内。

Claims (15)

  1. 一种存储芯片，其特征在于，包括封装基板、温度传感器和设置于封装基板上的闪存晶圆，所述温度传感器与所述闪存晶圆封装于同一空间内。
  2. 根据权利要求1所述的存储芯片，其特征在于，所述闪存晶圆为单层结构，所述温度传感器设置在所述闪存晶圆的上表面。
  3. 根据权利要求1所述的存储芯片，其特征在于，所述闪存晶圆为多层结构，所述温度传感器设置在所述封装基板上且位于所述闪存晶圆的一侧，所述温度传感器与闪存晶圆通过所述封装基板导热。
  4. 根据权利要求3所述的存储芯片，其特征在于，还包括用于连接所述闪存晶圆与所述温度传感器的导热金属。
  5. 根据权利要求4所述的存储芯片，其特征在于，所述导热金属为铜片，所述铜片位于所述闪存晶圆和温度传感器的底部；或者，所述导热金属为铜丝，所述铜丝的一端与闪存晶圆的闪存接口连接，另一端与所述温度传感器连接。
  6. 根据权利要求4所述的存储芯片，其特征在于，多层结构的所述闪存晶圆在所述封装基板上呈阶梯状错位布置。
  7. 根据权利要求1所述的存储芯片，其特征在于，所述封装基板具有安装所述闪存晶圆的第一表面和与所述第一表面相对的第二表面，所述第一表面上设有用于与所述温度传感器和闪存晶圆连接的数据接口，所述第二表面设有锡球层。
  8. 一种固态硬盘，包括控制器和若干存储芯片，其特征在于，所述存储芯片包括封装基板、温度传感器和设置于封装基板上的闪存晶圆，所述温度传感器与所述闪存晶圆封装于同一空间内，若干所述存储芯片依次串联后与 所述控制器电连接。
  9. 根据权利要求8所述的存储芯片，其特征在于，所述闪存晶圆为单层结构，所述温度传感器设置在所述闪存晶圆的上表面。
  10. 根据权利要求8所述的存储芯片，其特征在于，所述闪存晶圆为多层结构，所述温度传感器设置在所述封装基板上且位于所述闪存晶圆的一侧，所述温度传感器与闪存晶圆通过所述封装基板导热。
  11. 根据权利要求10所述的存储芯片，其特征在于，还包括用于连接所述闪存晶圆与所述温度传感器的导热金属。
  12. 根据权利要求11所述的存储芯片，其特征在于，所述导热金属为铜片，所述铜片位于所述闪存晶圆和温度传感器的底部；或者，所述导热金属为铜丝，所述铜丝的一端与闪存晶圆的闪存接口连接，另一端与所述温度传感器连接。
  13. 根据权利要求11所述的存储芯片，其特征在于，多层结构的所述闪存晶圆在所述封装基板上呈阶梯状错位布置。
  14. 根据权利要求8所述的存储芯片，其特征在于，所述封装基板具有安装所述闪存晶圆的第一表面和与所述第一表面相对的第二表面，所述第一表面上设有用于与所述温度传感器和闪存晶圆连接的数据接口，所述第二表面设有锡球层。
  15. 一种固态硬盘的温度控制方法，其特征在于，包括：
    实时获取每个存储芯片内部的温度；
    若任一存储芯片的温度达到第一阈值，则降低温度达到第一阈值的存储芯片的工作频率；
    若任一存储芯片的温度达到第二阈值，则停止温度达到第二阈值的存储芯片的工作，所述第二阈值大于所述第一阈值。
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