WO2020238430A1 - Dispositif de photodiode, substrat matriciel et son procédé de fabrication, panneau d'affichage et appareil d'affichage - Google Patents

Dispositif de photodiode, substrat matriciel et son procédé de fabrication, panneau d'affichage et appareil d'affichage Download PDF

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WO2020238430A1
WO2020238430A1 PCT/CN2020/083891 CN2020083891W WO2020238430A1 WO 2020238430 A1 WO2020238430 A1 WO 2020238430A1 CN 2020083891 W CN2020083891 W CN 2020083891W WO 2020238430 A1 WO2020238430 A1 WO 2020238430A1
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electrode
photodiode
layer
base substrate
sharp corner
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PCT/CN2020/083891
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English (en)
Chinese (zh)
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刘清召
王国强
王久石
董水浪
梁志伟
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京东方科技集团股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the embodiments of the present disclosure relate to a photodiode device and a manufacturing method thereof, an array substrate and a manufacturing method thereof, a display panel, and a display device.
  • the photodiode PIN
  • it can be divided into the bulk dark current inside the PIN and the edge dark current on the sidewall of the PIN.
  • the bulk dark current is mainly reduced by adjusting the PIN deposition parameters and the band gap adjustment.
  • the edge dark current is caused during the PIN patterning (etching process). Since etching itself is a destructive process, sidewall defects cannot be avoided, and the contribution of defects to the edge dark current can only be appropriately reduced or weakened.
  • At least one embodiment of the present disclosure provides a photodiode device.
  • the photodiode device includes a first electrode, a photodiode, and a second electrode that are sequentially stacked, wherein the outer contour of the photodiode has at least one sharp corner, so At least one of the first electrode and the second electrode is chamfered at a position corresponding to the position of the at least one sharp corner to expose the at least one sharp corner.
  • the at least one sharp corner includes a plurality of sharp corners, and at least one of the first electrode and the second electrode is in contact with the plurality of sharp corners.
  • the chamfering is set at the corresponding position of each position.
  • the photodiode device provided by at least one embodiment of the present disclosure further includes a base substrate, wherein the first electrode, the photodiode, and the second electrode are sequentially stacked on the base substrate, and the second electrode Are chamfered at positions corresponding to the position of each of the plurality of sharp corners; at the position of each of the plurality of sharp corners, the second electrode is the smallest relative to the photodiode
  • the amount of indentation is equal, and the amount of indentation is the distance from the apex of the sharp corner to the edge position of the second electrode at the corresponding position of the sharp corner on the surface where the second electrode and the photodiode are in contact. The distance between points.
  • the shape of at least one of the first electrode and the second electrode is a circular arc shape.
  • the shape of the second electrode is an arc shape.
  • the preset minimum shrinkage is greater than or equal to 1 micrometer.
  • the orthographic projection of the second electrode on the base substrate is within the orthographic projection of the photodiode on the base substrate, and except for Outside the position where the at least one sharp corner is located, the edge of the orthographic projection of the second electrode on the base substrate coincides with the edge of the orthographic projection of the photodiode on the base substrate.
  • the photodiode includes a P-type semiconductor layer, an intrinsic semiconductor layer, and an N-type semiconductor layer stacked in sequence.
  • At least one embodiment of the present disclosure provides an array substrate, which includes: a base substrate, and at least one photodiode device according to an embodiment of the present disclosure, wherein the photodiode device is disposed on the base substrate , And a thin film transistor electrically connected to the at least one photodiode device, wherein the thin film transistor is between the base substrate and the photodiode device, and the thin film transistor is electrically connected to the first photodiode device.
  • the thin film transistor includes a gate, a gate insulating layer, an active layer, and a source and drain that are sequentially disposed on the base substrate; the thin film transistor is also It includes a passivation layer disposed on the side of the source and drain away from the base substrate, the passivation layer has a first via hole exposing the source and drain, and the first electrode passes through the first The via hole is electrically connected to the source and drain.
  • the array substrate provided by at least one embodiment of the present disclosure further includes: a first protective layer, a flat layer, an insulating layer, a metal layer, and a second protective layer, a flat layer, an insulating layer, and a second electrode on a side of the second electrode away from the base substrate.
  • Protective layer; the first protective layer, the flat layer, and the insulating layer have a second via hole exposing the second electrode, and the metal layer passes through the second via hole and the second electrode Electric connection.
  • At least one embodiment of the present disclosure provides a display panel including the array substrate provided in the embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a display device including the display panel provided by the embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a method for manufacturing a photodiode device, including: sequentially forming a first electrode and a photodiode on a base substrate, the outer contour of the photodiode has at least one sharp corner; A second electrode is formed on the side away from the base substrate, wherein at least one of the first electrode and the second electrode is chamfered at a position corresponding to the position of the at least one sharp corner.
  • the second electrode is formed on a side of the photodiode away from the base substrate through a patterning process, and the second electrode is A chamfer is provided at a position corresponding to the position of the at least one sharp corner.
  • forming the second electrode includes: forming an initial second electrode on a side of the photodiode away from the base substrate, and the initial The planar shape of the second electrode is the same as the planar shape of the photodiode, and the initial second electrode is etched to form the second electrode.
  • the patterning process includes: depositing a transparent conductive layer on a side of the photodiode away from the base substrate, and The side of the transparent conductive layer away from the base substrate is coated with photoresist; the photoresist is exposed by using a gray-scale or half-level mask, and the gray-scale or half-level mask is completely shielded from light
  • the area and the partial light-shielding area correspond to the area of the photodiode, wherein the partial light-shielding area corresponds to the area that needs to be chamfered; the transparent conductive layer at the position corresponding to the partial light-shielding area is removed by etching, so that the The transparent conductive layer is chamfered at a position corresponding to the position of the sharp corner; the remaining photoresist is removed to form the second electrode.
  • At least one embodiment of the present disclosure provides a method for manufacturing an array substrate, including: forming a thin film transistor on a base substrate through a patterning process, the transistor including a gate and a gate insulating gate formed on the base substrate in sequence Layer, active layer, source and drain; forming a passivation layer on the side of the source and drain away from the base substrate, and the passivation layer has a first via hole exposing the source and drain;
  • the photodiode device is formed on the side of the passivation layer away from the base substrate by the manufacturing method provided by the embodiment of the present disclosure, wherein the first electrode of the photodiode device passes through the first via hole and the The source and drain are electrically connected.
  • the method further includes: performing a patterning process on the side of the second electrode far from the base substrate A first protective layer, a flat layer, an insulating layer, a metal layer, and a second protective layer are sequentially formed; wherein the first protective layer, the flat layer, and the insulating layer have a second protective layer exposing the second electrode.
  • the metal layer is electrically connected to the second electrode of the photodiode device through the second via hole.
  • Figure 1 is a schematic diagram of a cross-sectional structure of a photodiode
  • FIG. 2 is a schematic top view of the structure of an array substrate with photodiodes
  • Fig. 3 is a schematic cross-sectional structure view of Fig. 2 along the BB1 direction;
  • Figure 4 is a diagram showing the relationship between the number of sharp corners of the photodiode and the dark current
  • 5A is a top view of a photodiode device provided by at least one embodiment of the present disclosure.
  • 5B is a top view of another photodiode device provided by at least one embodiment of the present disclosure.
  • 5C is a top view of an array substrate provided by at least one embodiment of the present disclosure.
  • Fig. 6 is a schematic diagram of calculating the radius of the arc in part A of Fig. 5C;
  • FIG. 7 is a schematic cross-sectional structure diagram of an array substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a manufacturing method of an array substrate provided by at least one embodiment of the present disclosure
  • FIG. 9 is a schematic cross-sectional structure diagram of the array substrate after the second electrode is fabricated in at least one embodiment of the disclosure.
  • 21-Intrinsic silicon 22-P-type silicon; 23-N-type silicon.
  • Figure 1 shows a schematic diagram of a photodiode.
  • a first electrode 2 is provided at the bottom of the photodiode 1
  • a second electrode 3 is provided on the top of the photodiode 1, wherein the photodiode 1 is provided between the first electrode 2 and the second electrode 3.
  • It includes N-type silicon 23, intrinsic silicon 21, and P-type silicon 22 arranged on the second electrode 3 in sequence.
  • the dark current includes the bulk dark current inside the photodiode 1 and the edge dark current on the sidewall of the photodiode.
  • the bulk dark current includes composite bulk dark current, diffusion bulk dark current and tunneling bulk dark current.
  • the generation mechanism of the dark current of the composite body is the generation and recombination of electron-hole pairs in the depletion area.
  • the dark current of the composite body is not only affected by the material of the photodiode, but also by the temperature, applied bias and photosensitive area during manufacture. Impact. In order to overcome the dark current of the composite body, the band gap of the intrinsic silicon layer can be increased and the carrier concentration can be reduced, but the photocurrent will also be reduced.
  • the generation mechanism of the dark current of the diffused body is the diffusion of the minority carriers thermally excited outside the depletion region to the depletion region, and the influence conditions are the same as those of the dark current of the composite body.
  • the mechanism of the tunneling body dark current is that when the reverse bias voltage is high, electrons in the valence band of the P zone pass through the forbidden band to reach the conduction band of the N zone through the tunnel effect.
  • the generation mechanism of the edge dark current of the sidewall of the photodiode is that defects are generated during the etching process, and the defects act as recombination centers to cause dark current. Since etching itself is a destructive process, sidewall defects cannot be avoided, and the contribution of defects to the edge dark current can only be appropriately reduced or weakened.
  • the second electrode 3 can be etched a second time so that the second electrode 3 shrinks to reduce the electric field experienced by the sidewall of the photodiode, thereby weakening the contribution of sidewall defects to the edge dark current.
  • FIG. 2 is a top view of an array substrate on which the photodiode 1 is fabricated.
  • the array substrate includes a thin film transistor 4 electrically connected to the photodiode.
  • the thin film transistor 4 is used to control the photodiode 1.
  • Fig. 3 is a cross-sectional view of Fig. 2 along the BB1 direction.
  • the second electrode 3 shown in FIG. 1 is etched twice, so that the second electrode 3 is retracted, and the retracted distance is D.
  • the specific value of D can be determined by experiments, as shown in FIGS. 2 and 3 , So the edge of the photodiode 1 is exposed.
  • the following introduces the principle of reducing the electric field experienced by the sidewall of the photodiode by the way the second electrode 3 is retracted, thereby weakening the contribution of the sidewall defects to the edge dark current.
  • the outer contour of the photodiode has multiple sharp corners.
  • the inventor found through research that the position of the sharp corner is the defect concentration area on the sidewall of the photodiode. There are more defects at the sharp corner.
  • the photodiode is in the same area and same circumference.
  • the edge dark current has a significant rise. Specifically, as shown in FIG. 4, the abscissa in the figure shows the number of sharp corners, and the ordinate shows the value of the edge dark current.
  • At least one embodiment of the present disclosure provides a photodiode device and a manufacturing method thereof, an array substrate and a manufacturing method thereof, a display panel and a display device.
  • the photodiode device includes a first electrode, a photodiode, and a second electrode that are sequentially stacked.
  • the outer contour of the photodiode has at least one sharp corner.
  • At least one of the first electrode and the second electrode is in contact with the at least one sharp corner.
  • a chamfer is set at a position corresponding to the position to expose at least one sharp corner. While ensuring that the photodiode still has a larger effective area, the photodiode device can weaken the edge dark current caused by the sidewall defect of the photodiode.
  • the photodiode device includes a first electrode 2 (because it is shielded, not shown in FIG. 5A), a photodiode 1 and And the second electrode 3, the outer contour of the photodiode 1 has at least one sharp corner, for example, a plurality of sharp corners, and at least one of the first electrode 2 and the second electrode 3 is inverted at a position corresponding to the position of the at least one sharp corner.
  • the corner arrangement that is, at least one of the first electrode 2 and the second electrode 3 is retracted and arranged at a position corresponding to the position of the at least one sharp corner, thereby exposing the at least one sharp corner, for example, exposing a plurality of sharp corners.
  • only the first electrode 2 is chamfered at a position corresponding to the position of the at least one sharp corner, that is, only the first electrode 2 is set inwardly at a position corresponding to the position of the at least one sharp corner, Thus exposing the at least one sharp corner; in other embodiments, only the second electrode 3 is chamfered at a position corresponding to the position of the at least one sharp corner, that is, only the second electrode 3 is chamfered at the position corresponding to the at least one sharp corner. The position corresponding to the position is retracted to expose the at least one sharp corner (the example shown in FIG.
  • both the first electrode 2 and the second electrode 3 The position corresponding to the position of is chamfered, that is, the first electrode 2 and the second electrode 3 are both retracted and arranged at the position corresponding to the position of the at least one sharp corner, thereby exposing the at least one sharp corner.
  • the sharp corner of the photodiode 1 can be exposed,
  • the sharp corner position is the defect concentration area on the sidewall of the photodiode.
  • the photodiode 1 an area not covered by the first electrode 2 or the second electrode 3 is formed at the sharp corner, and the electric field in this area will be significantly weakened or even disappear, so
  • the design of the electrode of the photodiode device can weaken the contribution of sidewall defects to the edge dark current and improve the signal-to-noise ratio of the photodiode; in addition, since the electrode of the photodiode device is only chamfered at the position corresponding to the position of the sharp corner Compared with the way that the entire first electrode 2 or the second electrode 3 is retracted, the effective area is not significantly reduced, that is, it still has a higher effective area, and therefore has less impact on the photocurrent.
  • the photodiode 1 has a cutout for use in fabricating an array substrate (detailed later).
  • the photodiode 1 may not have a notch, so that its planar shape is substantially rectangular as a whole.
  • the embodiment of the present disclosure does not limit the specific shape of the photodiode 1.
  • the partial shape of the first electrode 2 and/or the second electrode 3 provided with a chamfer is a circular arc shape.
  • the radius of each arc is the same.
  • the preset minimum indentation d is greater than or equal to 1 micron.
  • the photodiode device may further include a base substrate 10, and the first electrode 2, the photodiode 1, and the second electrode 3 are sequentially arranged on the base substrate.
  • the second electrode 3 farther from the base substrate is chamfered at a position corresponding to the position of at least one sharp corner, that is, the second electrode 3 is set inwardly at a position corresponding to the position of at least one sharp corner.
  • the at least one sharp corner is exposed.
  • the first electrode 2 closer to the base substrate may have the same planar shape as the photodiode 1 and be completely overlapped with the photodiode 1.
  • the photodiode 1 can be conveniently formed on the first electrode 2 and the second electrode 3 with chamfered corners can be formed on the photodiode 1, thereby simplifying the manufacturing process of the photodiode device.
  • the orthographic projection of the second electrode 3 on the base substrate 10 is within the orthographic projection of the photodiode 1 on the base substrate.
  • the edge of the orthographic projection of the second electrode 3 on the base substrate 10 coincides with the edge of the orthographic projection of the photodiode 1 on the base substrate 10, that is, the second electrode 3 is only It is retracted at a position corresponding to the position of at least one sharp corner, thereby maximizing the effective area of the photodiode 1.
  • the photodiode 1 includes a P-type semiconductor layer, an intrinsic semiconductor layer, and an N-type semiconductor layer stacked sequentially, such as an N-type silicon layer, an intrinsic silicon layer, and a P-type silicon layer stacked sequentially on the first electrode 2.
  • a P-type semiconductor layer such as an N-type silicon layer, an intrinsic silicon layer, and a P-type silicon layer stacked sequentially on the first electrode 2.
  • At least one embodiment of the present disclosure further provides an array substrate.
  • the array substrate has any photodiode device described above, and further includes a thin film transistor 4, which is electrically connected to the photodiode device, for example, The first electrode or the second electrode of the diode device is electrically connected for controlling the photodiode device.
  • the planar shape of the photodiode device has a gap, and the thin film transistor 4 is disposed at the gap position.
  • the embodiment of the present disclosure does not limit the specific arrangement of the thin film transistor 4, and can refer to the related technology, which will not be repeated here.
  • At least one of the first electrode and the second electrode is provided with a chamfer at a position corresponding to the position of the sharp corner, so that the sharp corner of the photodiode 1 can be exposed.
  • the corner position is the defect concentrated area on the sidewall of the photodiode.
  • an area not covered by the first electrode 2 or the second electrode 3 is formed at the sharp corner. The electric field in this area will be significantly weakened or even disappear.
  • the The design of the electrodes of the photodiode device can weaken the contribution of sidewall defects to the edge dark current and improve the signal-to-noise ratio of the photodiode; in addition, since at least one of the first electrode and the second electrode 3 only corresponds to the sharp corner position The chamfered setting at the position of, compared with the way that the entire first electrode 2 or the second electrode 3 is retracted, the effective area is not significantly reduced, and the impact on the photocurrent is small.
  • At least one of the first electrode 2 and the second electrode 3 is chamfered at a position corresponding to the position of each sharp corner.
  • the arrangement of the first electrode 2 and the second electrode 3 can be the same or similar, and the second electrode 3 is chamfered at a position corresponding to the position of each sharp corner as an example for introduction.
  • the minimum indentation of the second electrode 3 relative to the photodiode 1 is equal.
  • the indentation is the distance between the apex of the sharp corner and the edge position of the second electrode 3 at the corresponding position of the sharp corner on the surface where the second electrode 3 contacts the photodiode 1. Distance; Since the minimum retraction of the second electrode 3 at the position corresponding to the position of each sharp corner is equal, the design difficulty can be greatly reduced and the manufacturing cost can be reduced.
  • the shape of the second electrode 3 is an arc shape at a position corresponding to the position of the sharp corner, and the arc shape design can make the electric field distribution more uniform and avoid A concentrated electric field appears.
  • the shape of the second electrode 3 is an arc shape, and the radii of the arcs are all equal, thereby reducing manufacturing difficulty, reducing manufacturing costs, and enhancing market competitiveness.
  • the radius of the arc in the embodiment of the present disclosure is calculated according to the following formula:
  • r is the radius of the arc
  • d is the preset minimum indentation
  • the minimum shrinkage may be different, which can be confirmed by experiments.
  • the shrinkage mark it as d, and calculate the radius of the circle of the second electrode 3 arc according to the above formula.
  • the arc structure can avoid the electric field concentration phenomenon caused by the right angle and make the electric field distribution more uniform.
  • the preset minimum indentation is greater than or equal to 1 micron. Because, according to experimental data, the minimum indentation of the second electrode 3 of about 1 micron can effectively reduce the dark current. Of course, the greater the value of the minimum indentation, the more conducive to reducing the dark current, but the smallest indentation The value of the amount should not be designed to be too large. If the design is too large, it will have a greater impact on the photocurrent.
  • the preset minimum indentation in the embodiment of the present disclosure is equal to 1 micron as an example.
  • FIG. 7 shows a schematic cross-sectional structure diagram of an array substrate provided by at least one embodiment of the present disclosure.
  • the thin film transistor 4 is disposed between the base substrate 10 and the photodiode device. For example, it is provided between the base substrate 10 and the first electrode 2.
  • the thin film transistor 4 is electrically connected to the first electrode 2 (the case shown in FIG. 7) or the second electrode 3.
  • the thin film transistor 4 includes a gate 11, a gate insulating layer 12, an active layer 13, and a source and drain 14 which are sequentially arranged on a base substrate 10.
  • a passivation layer 15 is provided on the side of the source drain 14 away from the base substrate.
  • the first electrode 2 is disposed on the side of the passivation layer 15 away from the base substrate.
  • the passivation layer 15 has a first via hole, and the first electrode 2 passes through the first via hole in the passivation layer 15 and the source and drain electrodes 14 Electrically connected, so that the thin film transistor 4 can control the working state of the photodiode 1.
  • the specific arrangement of the gate 11, the gate insulating layer 12, the active layer 13, the source and drain electrodes 14 and the passivation layer 15 can be referred to related technologies, which will not be repeated here.
  • a first protective layer 16, a flat layer 17, an insulating layer 18, a metal layer 19, and a second electrode 3 are sequentially disposed on the side of the second electrode 3 away from the base substrate.
  • the first protective layer 16, the flat layer 17, and the insulating layer 18 have second via holes, and the metal layer 19 is electrically connected to the second electrode 3 through the second via holes, so that the metal layer 19 can be used to apply electrical signals to the second electrode 3 .
  • the metal layer 19 may be, for example, a common electrode layer, including metal traces.
  • the photodiode 1 and the thin film transistor 4 shown in FIG. 5C may constitute a pixel unit.
  • the array substrate may have a plurality of pixel units arranged in an array for display.
  • At least one embodiment of the present disclosure also provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure.
  • the display panel has the same beneficial effects as the above-mentioned array substrate, which will not be repeated here.
  • At least one embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure.
  • the display device has the same beneficial effects as the above-mentioned display panel, which will not be repeated here.
  • At least one embodiment of the present disclosure also provides a method for manufacturing a photodiode device. As shown in FIG. 8, the method includes step S101 and step S102.
  • Step S101 sequentially forming a first electrode and a photodiode on a base substrate, and the outer contour of the photodiode has at least one sharp corner.
  • the first electrode and the photodiode may be sequentially formed on the base substrate through a patterning process, and the outer contour of the photodiode has a plurality of sharp corners, for example.
  • the patterning process may form a patterned functional layer.
  • a patterning process may include processes such as photoresist formation, exposure, development, and etching, or processes including other patternable material layers.
  • Step S102 A second electrode is formed on the side of the photodiode far away from the base substrate, and at least one of the first electrode and the second electrode is chamfered at a position corresponding to the position of the at least one sharp corner.
  • step S101 may be performed sequentially with step S102, or partially performed simultaneously, such as the photodiode and the second electrode. Part of the preparation process can be carried out at the same time.
  • the sharp corner is exposed, so that the photodiode is formed at the sharp corner without the first electrode or/and
  • the area covered by the second electrode reduces the electric field in the sharp corner area and weakens the dark current at the edge of the photodiode, while the effective area of the photodiode does not decrease significantly.
  • the second electrode in step S102, may be fabricated on the photodiode through a patterning process, and the second electrode in step S102 is chamfered at a position corresponding to the position of the sharp corner.
  • step S102 may include step S1021 to step S1024.
  • Step S1021 Deposit a transparent conductive layer on the side of the photodiode far away from the base substrate, and coat photoresist on the side of the transparent conductive layer far away from the base substrate.
  • Step S1022 Expose the transparent conductive layer by using a gray-scale or half-level mask.
  • the completely shading area and part of the shading area of the gray-scale or half-level mask correspond to the area of the photodiode, and the partial shading area needs to be correspondingly performed The area where the chamfer is set.
  • Step S1023 etching and removing the transparent conductive layer at the position corresponding to the part of the shading area, so that the transparent conductive layer is chamfered at the position corresponding to the position of the sharp corner.
  • Step S1024 removing the remaining photoresist to form a second electrode.
  • the shape of the junction between the partially shielded area and the fully shielded area is an arc shape.
  • This design method can make the shape of the second electrode at the position corresponding to the sharp corner be an arc shape.
  • the design method can make the electric field distribution more uniform and avoid the electric field concentration area.
  • it can also be designed into other suitable shapes according to actual conditions.
  • At least one embodiment of the present disclosure also provides a method for manufacturing an array substrate, which includes forming a photodiode device using the above manufacturing method, and before forming the photodiode device on a base substrate, the method for manufacturing the array substrate includes: A thin film transistor is formed on the base substrate.
  • forming a thin film transistor includes sequentially forming a gate, a gate insulating layer, an active layer, and a source and drain.
  • the manufacturing method of the array substrate further includes: forming a passivation layer on the side of the source and drain electrodes away from the base substrate.
  • the passivation layer has a first via hole exposing the source and drain, and the first electrode of the photodiode device is electrically connected to the source and drain through the first via.
  • the manufacturing method of the array substrate further includes: sequentially forming a first protective layer, a flat layer, an insulating layer, a metal layer, and a second electrode on the second electrode through a patterning process.
  • the protective layer For example, the first protective layer, the flat layer and the insulating layer have second via holes exposing the second electrode, and the metal layer is electrically connected to the second electrode through the second via hole.
  • the metal layer is, for example, a common electrode layer, including metal traces, for providing electrical signals for the second electrode.
  • a metal layer is deposited on the base substrate 10 and patterned to form the gate 11.
  • the metal layer may be a single metal layer or a multi-layer metal layer formed of molybdenum, aluminum, copper, or titanium, with a thickness of 200 nm to 400 nm.
  • a gate insulating layer 12 is formed on the gate electrode 11 using plasma enhanced chemical vapor deposition.
  • the gate insulating layer 12 includes, for example, a stack of SiN and SiO 2 , where the thickness of SiN is 50 nm to 150 nm. , The thickness of SiO 2 is 100 nanometers to 400 nanometers.
  • the specific manufacturing method of the gate 11 and the gate insulating layer 12 can be referred to related technologies, and will not be repeated here.
  • an active layer 13 is fabricated on the gate insulating layer 12 using a patterning process.
  • the active layer 13 can be an amorphous silicon (aSi) layer, or a polysilicon (pSi) layer, or It is a metal oxide active layer, such as indium gallium zinc oxide (IGZO).
  • aSi amorphous silicon
  • pSi polysilicon
  • IGZO indium gallium zinc oxide
  • the source and drain electrodes 14 are formed through a patterning process.
  • the source and drain electrodes 14 may be a single-layer metal layer formed of molybdenum, aluminum, copper, or titanium. Or multiple metal layers with a thickness of 200 nanometers to 400 nanometers.
  • the specific manufacturing method of the source and drain electrodes 14 can be referred to related technologies, which will not be repeated here.
  • a passivation layer 15 is fabricated by a patterning process.
  • the passivation layer 15 includes, for example, a stack of SiN and SiO 2 where the thickness of SiN is 50 nm to 150 nm, and the thickness of SiO 2 is 100 nm to 400 nm.
  • a first via hole exposing the source and drain electrodes 14 is formed in the passivation layer 15 through a patterning process.
  • the specific manufacturing method of the passivation layer 15 can be referred to related technologies, which will not be repeated here.
  • the first electrode 2 is fabricated through a patterning process.
  • the material of the first electrode 2 may be Mo, aluminum, copper or titanium, and the thickness is 200 nm to 400 nm.
  • the first electrode 2 is electrically connected to the source and drain 14 through a first via hole.
  • the specific manufacturing method of the first electrode 2 can refer to the related technology, which will not be repeated here.
  • an N-type silicon material layer, an intrinsic silicon material layer, and a P-type silicon material layer are sequentially deposited on the first electrode 2 using a plasma-enhanced chemical vapor deposition method, and the N-type silicon material is processed through a patterning process.
  • Material layer, intrinsic silicon material layer, and P-type silicon material layer to form a photodiode 1.
  • the photodiode 1 includes N-type silicon 23 (as shown in FIG. 1), intrinsic silicon 21 (as shown in FIG. 1), and P Type silicon 22 (shown in Figure 1).
  • the thickness of the N-type silicon 23 is 20 nm-50 nm
  • the thickness of the intrinsic silicon 21 is 500 nm-900 nm
  • the thickness of the P-type silicon 22 is 5 nm-50 nm.
  • the specific manufacturing method of the photodiode 1 can be referred to related technologies, which will not be repeated here.
  • a transparent conductive layer is deposited on the photodiode 1, the thickness of the transparent conductive layer is 40 nanometers ⁇ 70 nanometers, and photoresist is coated on the transparent conductive layer; after that, grayscale or The half-level mask is exposed, and the completely shading area and part of the shading area of the gray-scale or half-level mask correspond to the area of the photodiode.
  • the part of the shading area corresponds to the area that needs to be chamfered;
  • the transparent conductive layer at the corresponding position of the light-shielding area makes the transparent conductive layer form a chamfer at the position corresponding to the position of the sharp corner; the remaining photoresist is removed to form the second electrode 3, specifically, the partial light-shielding area and the completely light-shielding area
  • the shape of the junction is an arc shape, and the top view of the formed second electrode 3 can be referred to as shown in FIG. 5C.
  • the photoresist after coating photoresist on the transparent conductive layer, the photoresist is exposed by using a gray-scale or half-level mask.
  • the gray-scale or half-level mask has a completely shading area, Partial shading area and light-transmitting area, full shading area and partial light-shielding area of gray-scale or half-level mask correspond to the area of photodiode, partial shading area corresponds to the area that needs to be chamfered, and light-transmitting area corresponds to the photodiode
  • the photoresist corresponding to the light-transmitting area is completely removed, the photoresist corresponding to the partial light-shielding area is partially removed, and the photoresist corresponding to the completely light-shielding area is not removed; pass once
  • the transparent conductive layer corresponding to the light-transmitting area is etched away to form an initial second electrode; for example, the initial second electrode has substantially the same plane pattern as the N-type silicon 23, the intrinsic
  • the photoresist corresponding to the part of the shading area is removed, and the transparent conductive layer at the position corresponding to the part of the shading area is removed by etching, so that the transparent conductive layer is chamfered at the position corresponding to the position of the sharp corner; finally, the remaining light is removed Resist, that is, the photoresist corresponding to the completely shading area is removed to form the second electrode 3.
  • the N-type silicon material layer and the intrinsic silicon material layer Pattern with the P-type silicon material layer, but deposit a transparent conductive layer on the P-type silicon material layer, and then use the first patterning process to simultaneously pattern the N-type silicon material layer, the intrinsic silicon material layer, and the P-type silicon layer Material layer and transparent conductive layer to form N-type silicon 23, intrinsic silicon 21, P-type silicon 22 and the initial second electrode.
  • the initial second electrode has the same characteristics as the N-type silicon 23, intrinsic silicon 21, and P-type silicon.
  • the silicon 22 has substantially the same planar pattern; then, the second electrode 3 is formed by performing a second patterning process on the initial second electrode. Therefore, the preparation process of the photodiode and the second electrode is partially performed simultaneously, which can simplify the preparation process of the array substrate.
  • the N-type silicon material layer, the intrinsic silicon material layer, and the The P-type silicon material layer is patterned, but an initial second electrode is formed on the P-type silicon material layer.
  • a transparent conductive layer is directly deposited through a mask to form the initial second electrode, or it is formed by a patterning process Initialize the second electrode, and then use the initial second electrode as a mask to simultaneously pattern the N-type silicon material layer, the intrinsic silicon material layer, and the P-type silicon material layer to form the N-type silicon 23, the intrinsic silicon 21, and the P-type silicon material layer. Silicon 22.
  • the initial second electrode has basically the same plane pattern as the N-type silicon 23, intrinsic silicon 21, and P-type silicon 22; then the second patterning process is performed on the initial second electrode to form the second electrode 3.
  • the embodiment of the present disclosure does not limit the specific forming method of the photodiode 1 and the second electrode.
  • a first protective layer 16, a flat layer 17, and an insulating layer 18 are sequentially formed on the second electrode 3.
  • the material of the first protective layer 16 may be an inorganic insulating material such as SiN with a thickness of 50 nm to 150 nm.
  • the material of the flat layer 17 is an organic insulating material such as resin with a thickness of 1.2 ⁇ m to 2.5 ⁇ m.
  • the material of the insulating layer 18 It is an inorganic insulating material such as SiO 2 with a thickness of 100 nanometers to 150 nanometers.
  • a second via hole exposing the second electrode 3 is formed in the first protective layer 16, the planarization layer 17, and the insulating layer 18 through a patterning process.
  • the specific manufacturing methods of the first protective layer 16, the flat layer 17, and the insulating layer 18 can be referred to related technologies, and will not be repeated here.
  • the metal lead 19 is made by a patterning process.
  • the material of the metal lead 19 is molybdenum, aluminum, copper, or titanium, and the thickness is 200 nm to 400 nm.
  • the metal lead 19 serves as the electrode of the second electrode 3.
  • the metal lead 19 is electrically connected to the second electrode through the second via hole.
  • the specific manufacturing method of the metal lead 19 can be referred to the related technology, which will not be repeated here.
  • the second protective layer 20 is fabricated through a patterning process.
  • the material of the second protective layer 20 is an inorganic insulating material such as SiO 2 with a thickness of 50 nm to 150 nm.
  • the specific manufacturing method of the second protection layer 20 can be referred to related technologies, which will not be repeated here.
  • the second electrode included in the array substrate provided by the embodiment of the present invention is provided with a chamfer at a position corresponding to the position of the sharp corner, the sharp corner can be exposed, and the sharp corner position is the defect concentrated area on the sidewall of the photodiode.
  • the sharp corners of the area not covered by the second electrode will significantly weaken or even disappear the electric field. Therefore, the design of the second electrode can weaken the contribution of sidewall defects to the edge dark current and improve the photoelectricity. Diode signal-to-noise ratio.
  • the second electrode is only chamfered at the position corresponding to the position of the sharp corner, compared to the way that the entire second electrode is retracted, the effective area is not significantly reduced, and the impact on the photocurrent is small.
  • the shape of the second electrode is designed to be an arc shape, and the arc shape design method can make the electric field distribution more uniform and avoid the electric field concentration area.

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Abstract

L'invention concerne un dispositif de photodiode et son procédé de fabrication, un substrat matriciel et son procédé de fabrication, un panneau d'affichage et un appareil d'affichage, le substrat matriciel comprenant une première électrode (2), une photodiode (1) et une seconde électrode (3) qui sont empilées de manière séquentielle. Le contour externe de la photodiode (1) a au moins un coin aigu, et la première électrode (2) et/ou la seconde électrode (3) est chanfreinée à une position correspondant à la position de l'au moins un coins aigu, de façon à exposer l'au moins un coin aigu. La première électrode (2) et/ou la seconde électrode (3) est chanfreinée à une position correspondant à la position du coin aigu, de façon à exposer le coin aigu, ce qui affaiblit le courant d'obscurité au bord de la photodiode (1).
PCT/CN2020/083891 2019-05-30 2020-04-09 Dispositif de photodiode, substrat matriciel et son procédé de fabrication, panneau d'affichage et appareil d'affichage WO2020238430A1 (fr)

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