WO2020238343A1 - 显示基板、显示面板及显示装置 - Google Patents

显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2020238343A1
WO2020238343A1 PCT/CN2020/079636 CN2020079636W WO2020238343A1 WO 2020238343 A1 WO2020238343 A1 WO 2020238343A1 CN 2020079636 W CN2020079636 W CN 2020079636W WO 2020238343 A1 WO2020238343 A1 WO 2020238343A1
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WIPO (PCT)
Prior art keywords
sub
display area
type
segment
pixels
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PCT/CN2020/079636
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English (en)
French (fr)
Inventor
许传志
谢正芳
张露
楼均辉
Original Assignee
昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Publication of WO2020238343A1 publication Critical patent/WO2020238343A1/zh
Priority to US17/353,277 priority Critical patent/US11882749B2/en
Priority to US18/176,071 priority patent/US20230209957A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • This application relates to the field of display technology, and in particular to a display substrate, a display panel and a display device.
  • a display substrate includes a display area, the display area includes a first display area and a second display area, the light transmittance of the first display area is greater than the light transmittance of the second display area;
  • the display area includes a plurality of sub-pixels, the plurality of sub-pixels are divided into a plurality of pixel groups arranged in a second direction, and the plurality of pixel groups arranged in the second direction includes a plurality of first-type pixel groups And multiple second-type pixel groups;
  • the plurality of sub-pixels include a plurality of first sub-pixels arranged in the first display area and a plurality of second sub-pixels arranged in the second display area, and the distribution of the plurality of first sub-pixels The density is less than the distribution density of the plurality of second sub-pixels;
  • Each first-type pixel group includes some of the plurality of first sub-pixels and some of the plurality of second sub-pixels arranged along the first direction, and each second-type pixel group only includes The other ones of the plurality of second sub-pixels arranged in the first direction, the first one or both of each first-type pixel group and each second-type pixel group
  • the two sub-pixels are arranged in areas located on both sides of the first display area along the first direction;
  • the display area includes a plurality of first-type data lines, a plurality of second-type data lines, a power supply line, and a plurality of pixel circuits corresponding to the plurality of sub-pixels.
  • Each first sub-pixel in the same first-type pixel group The pixel circuit of the pixel and each second sub-pixel is connected to the same first-type data line, and the pixel circuit of each second sub-pixel in the same second-type pixel group is connected to the same second-type data line;
  • the portion of the power line located in the first display area is disposed below the portion of the at least one first type data line located in the first display area along the thickness direction of the display substrate.
  • each first sub-pixel includes a first electrode, a first light-emitting structure on the first electrode, and a second electrode on the first light-emitting structure, and each of the plurality of first type The part of the data line located in the first display area and the first electrode are arranged on the same layer.
  • the portion of the at least one first type data line located in the first display area and the portion of the at least one first type data line located in the second display area are located on different layers; the display substrate is further Including an insulating layer; the portion of the at least one first type data line located in the first display area and the portion of the at least one first type data line located in the second display area are located on opposite sides of the insulating layer The surfaces are connected through the first through holes provided on the insulating layer.
  • the plurality of first-type data lines and the plurality of second-type data lines are alternately arranged; or, the plurality of second-type data lines are distributed throughout the plurality of first-type data lines On both sides.
  • the pixel circuit of each of the plurality of first sub-pixels includes a first capacitor, and the first capacitor includes a lower electrode plate and an upper electrode plate disposed oppositely, and the upper electrode plate is located on the power line The portion of the first display area.
  • the plurality of pixel groups arranged along the second direction further includes a fifth type of pixel group, and the fifth type of pixel group only includes still some of the plurality of second sub-pixels.
  • the second sub-pixels in the class pixel group are all located on the same side of the first display area along the second direction;
  • the display area further includes a plurality of third-type data lines, and the pixel circuits of each second sub-pixel in the same fifth-type pixel group are connected to the same third-type data line.
  • the second sub-pixels of each second-type pixel group are arranged in areas located on both sides of the first display area along the first direction, and the second-type data line includes a first A section, a second section and a third section, the first section and the second section are respectively located on both sides of the first display area in the first direction, and the third section is connected to the Between the first segment and the second segment, the third segment is located in the first display area.
  • the light transmittance of the third section is greater than or equal to 70%.
  • the material of the third stage includes at least one of indium tin oxide, indium zinc oxide, silver-doped indium tin oxide, and silver-doped indium zinc oxide.
  • the first section and the second section are arranged on the same layer, the first section and the third section are on different layers, and the display substrate further includes the arrangement along the thickness direction of the display substrate.
  • a second through hole is provided on the insulating layer, and the first section and the second section respectively pass through the second through hole and The third segment is connected.
  • each first sub-pixel includes a first electrode, a first light-emitting structure on the first electrode, and a second electrode on the first light-emitting structure; the third segment and the first light-emitting structure An electrode is arranged on the same layer, and the first section and the second section are respectively arranged on the same layer as the power line.
  • the display substrate further includes a substrate, and the first electrode, the plurality of first-type data lines, the plurality of second-type data lines, and the power supply line are located above the substrate, The projection of the first electrode on the substrate falls within the projection of the part of the power line located in the first display area on the substrate.
  • the display area further includes a third display area located between the first display area and the second display area, and no sub-pixels are provided in the third display area;
  • the second sub-pixels of the second-type pixel group are arranged in areas located on both sides of the first display area along the first direction, and the second-type data line includes a first segment and a second segment And the third section, the first section and the second section are respectively located on both sides of the first display area in the first direction, and the third section is connected between the first section and the Between the second segment, the third segment is arranged in the third display area; the third segment includes a fourth sub-segment, a fifth sub-segment, and a sixth sub-segment that are sequentially connected.
  • the subsection and the sixth subsection extend in the second direction, the fifth subsection extends in the first direction, the fourth subsection is connected to the first section, and the sixth subsection is The section is connected with the third section.
  • the plurality of sub-pixels are further divided into a plurality of pixel groups arranged along a first direction, and the plurality of pixel groups arranged along the first direction include a plurality of third-type pixel groups and a plurality of second pixel groups.
  • Each third-type pixel group includes some of the plurality of first sub-pixels and some of the plurality of second sub-pixels arranged along the second direction, and each fourth-type pixel group only includes Other ones of the plurality of second sub-pixels arranged along the second direction, one or both of each of the third-type pixel groups and each of the fourth-type pixel groups
  • the second sub-pixels are arranged in areas located on both sides of the first display area along the second direction;
  • the display area also includes a plurality of first-type light-emitting control lines and a plurality of second-type light-emitting control lines, and the pixel circuits of each first sub-pixel and each second sub-pixel in the same third-type pixel group are connected to the same first sub-pixel.
  • Type light emission control line, the pixel circuit of each second sub-pixel in the same fourth type pixel group is connected to the same second type light emission control line; the first type light emission control line and the second type light emission control line are used for The plurality of sub-pixels provide emission control signals.
  • the second sub-pixels in each fourth-type pixel group are arranged in regions located on both sides of the first display area along the second direction, and the second-type light-emitting control line Including the tenth segment, the eleventh segment and the twelfth segment, the tenth segment and the eleventh segment are located in the second display area and respectively located in the first display On both sides of the area, the twelfth segment is connected between the tenth segment and the eleventh segment, and the twelfth segment is located in the first display area.
  • the plurality of sub-pixels are further divided into a plurality of pixel groups arranged along a first direction, and the plurality of pixel groups arranged along the first direction include a plurality of third-type pixel groups and a plurality of second pixel groups.
  • Each of the third-type pixel groups includes some of the plurality of first sub-pixels and some of the plurality of second sub-pixels arranged along the second direction, and each fourth-type pixel group Only the other ones of the plurality of second sub-pixels arranged along the second direction, one or both of each of the third-type pixel groups and each of the fourth-type pixel groups are included
  • the second sub-pixels are arranged in areas located on both sides of the first display area along the second direction;
  • the display area further includes a plurality of scan lines of the first type and a plurality of scan lines of the second type, and the pixel circuits of each first sub-pixel and each second sub-pixel in the same third-type pixel group are connected to the same first-type scan Line, the pixel circuit of each second sub-pixel in the same fourth-type pixel group is connected to the same second-type scan line; the first-type scan line and the second-type scan line are used to provide scan signals for the sub-pixels.
  • the second sub-pixels in each fourth-type pixel group are arranged in areas located on both sides of the first display area along the second direction
  • the second-type scan lines include The seventh segment, the eighth segment and the ninth segment, the seventh segment and the eighth segment are located in the second display area and are located on both sides of the first display area in the second direction,
  • the ninth segment is connected between the seventh segment and the eighth segment, and the ninth segment is located in the first display area.
  • each first sub-pixel includes a first electrode, a light-emitting structure located on the first electrode, and a second electrode located on the light-emitting structure, and the first electrode includes a mutual relationship along the first direction.
  • a plurality of first electrode blocks arranged at intervals and a connection part provided between two adjacent first electrode blocks, and the plurality of first electrode blocks are arranged staggered in the second direction.
  • a display panel wherein the display panel comprises the display substrate of claim 1 and a packaging structure for packaging the display substrate.
  • a display device including:
  • the device body has a device area
  • the display panel is covered on the device body;
  • the device area is located below the first display area, and a photosensitive device that emits or collects light through the first display area is provided in the device area.
  • FIG. 1 is a top view of an embodiment of a display substrate provided by the present application.
  • FIG. 2A is a top view of another embodiment of the display substrate provided by the present application.
  • FIG. 2B is a top view of another embodiment of the display substrate provided by the present application, and the position of the first display area is different from that in FIG. 2A.
  • FIG. 2C is a top view of another embodiment of the display substrate provided by the present application, and the position of the first display area is different from that in FIG. 2A.
  • FIG. 3 is a partial schematic diagram of the arrangement of sub-pixels in the embodiment of the display substrate shown in FIG. 1.
  • FIG. 4 is a schematic diagram of the arrangement of data lines in an embodiment of the display substrate corresponding to FIG. 3.
  • FIG. 5 is a partial schematic diagram of another sub-pixel arrangement of the display substrate shown in FIG. 1.
  • FIG. 6 is a schematic diagram of the arrangement of data lines of the display substrate corresponding to FIG. 5.
  • FIG. 7A is a cross-sectional view along the first direction of the embodiment of the display substrate shown in FIG. 1.
  • FIG. 7B is a cross-sectional view along the second direction of the embodiment of the display substrate shown in FIG. 1 showing only the insulating layer and the first type data line.
  • FIG. 8 is a partial structural diagram of the embodiment of the display substrate shown in FIG. 1.
  • FIG. 9 is a schematic diagram of the arrangement of light-emitting control lines in the embodiment of the display substrate shown in FIG. 1.
  • FIG. 10 is a schematic diagram of the arrangement of scan lines in the embodiment of the display substrate shown in FIG. 1.
  • FIG. 11 is a schematic diagram of the projection on the substrate of an embodiment of the first electrode provided by the present application.
  • FIG. 12 is a schematic diagram of the projection on the substrate of another embodiment of the first electrode provided by the present application, and the shape of the first electrode is different from that of FIG. 11.
  • FIG. 13 is a schematic diagram of projection on the substrate of another embodiment of the first electrode provided by the present application, and the shape of the first electrode is different from that of FIG. 11.
  • FIG. 14 is a schematic structural diagram of an embodiment of the first display area provided by the present application.
  • the driving mode of the non-transparent display is active driving, and the driving mode of the transparent display is passive driving.
  • the driving modes of the transparent display is passive driving.
  • two driving schemes are required on the screen body, which will greatly increase the complexity of the full screen driving.
  • the embodiments of the present application provide a display substrate, a display panel and a display device, which can well solve the above-mentioned problems.
  • the embodiment of the present application provides a display substrate. 1 and 2A to 2C, the display area of the display substrate 100 includes a first display area 10 and a second display area 20, and the light transmittance of the first display area 10 is greater than that of the second display area 20 .
  • the display area of the display substrate 100 includes a plurality of sub-pixels, which are arranged in an array manner and can be divided into a plurality of pixel groups.
  • the plurality of sub-pixels are divided into a plurality of pixel groups arranged in the second direction along the second direction, and each pixel group includes a plurality of sub-pixels arranged in the first direction.
  • the plurality of pixel groups includes a first type pixel group 101 and a second type pixel group 102.
  • a plurality of first sub-pixels 11 are provided in the first display area 10
  • a plurality of second sub-pixels 21 are provided in the second display area 20.
  • the distribution density of the first sub-pixel 11 is smaller than the distribution density of the second sub-pixel 21, where the distribution density refers to the number of sub-pixels per unit area of the display area.
  • the first-type pixel group 101 includes a first sub-pixel 11 and a second sub-pixel 21.
  • the second-type pixel group 102 only includes the second sub-pixel 21.
  • the second sub-pixels 21 in the first-type pixel group 101 are arranged in areas on both sides of the first display area 10 along the first direction, and/or the second sub-pixels 21 in the second-type pixel group 102 are arranged in rows The area is located on both sides of the first display area 10 along the first direction.
  • the display substrate 100 is provided with a first-type data line 31, a second-type data line 32, a pixel circuit 12 corresponding to the first sub-pixel 11, and a second sub-pixel 21.
  • the power line is a lead connected to ELVDD.
  • the pixel circuit 12 of each first sub-pixel 11 and the pixel circuit 22 of each second sub-pixel 21 in the same first-type pixel group 101 are connected to the same first-type data line 31.
  • the pixel circuit 22 of each second sub-pixel 21 in the same second-type pixel group 102 is connected to the same second-type data line 32.
  • the pixel circuit 12 of the first sub-pixel 11 may be disposed in the first display area 10, and the pixel circuit 22 of the second sub-pixel 21 may be disposed in the second display area 20.
  • the positions of the pixel circuits corresponding to the sub-pixels are arranged under the sub-pixels in a one-to-one correspondence along the thickness direction of the display substrate 100.
  • the portion 16 of the power line located in the first display area 10 is arranged under the portion of the first type data line 31 located in the first display area 10 along the thickness direction of the display substrate 100.
  • the part of the first type data line 31 located in the first display area 10 is the fifth segment 312 of the first type data line 31.
  • the photosensitive device can be arranged under the first display area 10 to ensure that the photosensitive device is normal. Under the premise of work, a full-screen display of the display substrate 100 is realized.
  • the first-type pixel group 101 Since the pixel circuit 12 of the first sub-pixel 11 and the pixel circuit 22 of the second sub-pixel 21 in the same first-type pixel group 101 are connected to the same first-type data line 31, the first-type pixel group 101 The sub-pixel 11 and the second sub-pixel 21 can be driven by the same first-type data line 31, thereby reducing the wiring complexity in the display area of the display substrate 100, and simultaneously enabling the display of the first display area 10 and the second display area 20 The effect is more consistent, which is conducive to improving the user experience.
  • the portion 16 of the power line located in the first display area 10 is disposed under the portion of the first type data line 31 located in the first display area 10, the portion 16 of the power line located in the first display area 10 can be Reduce the signal interference between the part of the first type data line 31 located in the first display area 10 and other signal lines (such as gate lines) in the first display area 10 under the power line, and improve the first type data line 31 and the The stability of signals received by other signal lines located under the power lines in a display area 10 can further improve the display effect of the display substrate.
  • the display substrate 100 provided by the embodiment of the present application may be as shown in FIG. 1, the first display area 10 is completely surrounded by the second display area 20, or the first display area 10 may be partially surrounded by the second display area 20.
  • an edge of the first display area 10 coincides with an edge of the display area, and the edge of the display area extends along the first direction.
  • the two opposite edges of the first display area 10 coincide with the two opposite edges of the display area, and the two edges of the display area both extend along the first direction.
  • the second sub-pixels 21 in the first-type pixel group 101 and the second-type pixel group 102 are both arranged in areas located on both sides of the first display area 10 along the first direction.
  • the first-type pixel group 101 and the second-type pixel group 102 include multiple sub-pixels arranged along a first direction, which means that multiple sub-pixels in the same pixel group are roughly arranged along the first direction. cloth.
  • the axes of the multiple sub-pixels in the same pixel group along the first direction may or may not overlap.
  • the multiple sub-pixels of the same pixel group are arranged in a staggered arrangement in the first direction, and the multiple sub-pixels of the pixel group are also considered to be arranged at intervals along the first direction.
  • the pixel circuit 12 corresponding to the first sub-pixel 11 and the pixel circuit 22 corresponding to the second sub-pixel 21 may be 2T1C circuits, 3T1C circuits, or 3T2C circuits, or 7T1C circuits, or 7T2C circuits.
  • T represents a transistor
  • C represents a storage capacitor.
  • the type of the pixel circuit of the first sub-pixel 11 and the pixel circuit of the second sub-pixel 21 may be the same or different.
  • the first sub-pixel 11 includes a first electrode 111, a first light-emitting structure 112 on the first electrode 111, and a second electrode 113 on the first light-emitting structure 112.
  • the two sub-pixels 21 include a third electrode 211, a second light-emitting structure 212 on the third electrode 211, and a fourth electrode 213 on the second light-emitting structure 212.
  • the display substrate 100 may further include a substrate 410, a buffer layer 420 on the substrate 410, a semiconductor layer 26 and a semiconductor layer 14 formed on the buffer layer 420, and a gate insulating layer formed on the semiconductor layer 26 and the semiconductor layer 14. 430.
  • the pixel circuit 22 of the second sub-pixel 21 includes a second transistor 25 and a second capacitor.
  • the second transistor 25 includes a source 251, a drain 252, and a gate 253.
  • the gate 253 is located between the gate insulating layer 430 and the capacitor insulating layer 44.
  • the source electrode 251 and the drain electrode 252 are located on the interlayer dielectric layer 45 and contact the semiconductor layer 26 through the gate insulating layer 430, the capacitor insulating layer 44 and the through holes on the interlayer dielectric layer 45.
  • the second capacitor includes an upper electrode plate 271 and a lower electrode plate 272, and the upper electrode plate 271 is located between the capacitor insulating layer 44 and the interlayer dielectric layer 45.
  • the bottom plate 272 is located between the gate insulating layer 430 and the capacitor insulating layer 44.
  • the third electrode 211 is located between the planarization layer 46 and the pixel defining layer 47.
  • the pixel circuit 12 of the first sub-pixel 11 includes a first transistor 13 and a first capacitor.
  • the first transistor 13 includes a source 131, a drain 132, and a gate 133.
  • the gate 133 is located between the gate insulating layer 430 and the capacitor insulating layer 44.
  • the source electrode 131 and the drain electrode 132 are located on the interlayer dielectric layer 45 and contact the semiconductor layer 14 through the gate insulating layer 430, the capacitor insulating layer 44 and the through holes on the interlayer dielectric layer 45.
  • the first capacitor includes an upper electrode plate 152 and a lower electrode plate 151.
  • the upper electrode plate 152 is located between the capacitor insulating layer 44 and the interlayer dielectric layer 45.
  • the bottom plate 151 is located between the gate insulating layer 430 and the capacitor insulating layer 44.
  • the first electrode 111 is located between the planarization layer 46 and the pixel defining layer 47.
  • a first conductive layer 17 may be provided in the first display area 10.
  • a part of the first conductive layer 17 can be used as the upper plate 152 of the first capacitor, and the other part can be used as the part 16 of the power line located in the first display area 10.
  • the portion 16 of the power line located in the first display area 10 and the upper plate 152 of the first capacitor can be formed in the same step, and it is not necessary to prepare either of the two after the power line and the upper plate 152 of the first capacitor are formed.
  • the inter-connection structure can simplify the manufacturing process of the display substrate 100.
  • the portion of the first type data line 31 located in the first display area 10 may be provided on the same layer.
  • the portion of the first-type data line 31 in the first display area 10 and the first electrode 111 can be formed in the same process step, thereby reducing the complexity of the manufacturing process.
  • the part of the first type data line 31 located in the second display area 20 and the part of the first type data line 31 located in the first display area 10 may be arranged on different layers.
  • An insulating layer is provided between the portion of the first type data line 31 located in the first display area 10 and the portion of the first type data line 31 located in the second display area 20. Referring to FIG.
  • the portion 31' of the first type data line 31 located in the first display area 10 and the portion 31" of the first type data line 31 located in the second display area 20 are provided on two opposite surfaces of the insulating layer.
  • the insulation The layer is provided with a first through hole 461.
  • the first type of data line 31 is located in the first display area 10 and the second type of data line 31 is located in the second display area 20 through the insulating layer
  • the first through hole 461 is connected.
  • the insulating layer is a planarization layer 46.
  • the first type data line 31 may include a fourth segment 311, a fifth segment 312, and a sixth segment 313 that are connected in sequence.
  • the fourth segment 311 and the sixth segment 313 are located in the second display area 20.
  • the fifth segment 312 is a portion of the first type data line 31 located in the first display area 10.
  • the portion of the fifth segment 312 in the first display area 10 and the first electrode 111 may be in the same layer.
  • the fourth segment 311, the sixth segment 313, and the source 251 and the drain 252 of the second transistor 25 can be formed in the same process step.
  • the insulating layer between the fourth segment 311 and the sixth segment 313 and the fifth segment 312 includes a planarization layer 46.
  • the second The class data line 32 may include a first section 321, a second section 322, and a third section 323.
  • the first segment 321 and the third segment 323 are located in the second display area 20 and are respectively located on both sides of the first display area 10 in the first direction.
  • the third section 323 connects the first section 321 and the second section 322.
  • the third section 323 can be set in the following two ways.
  • the third segment 323 is located in the first display area 10.
  • the light transmittance of the third section 323 may be greater than or equal to 70%.
  • the light transmittance of the third section 323 may be greater than or equal to 90%, for example, the light transmittance of the third section 323 may be 90%, 95%, or the like.
  • Such an arrangement can make the light transmittance of the first display area 10 larger, so that the light transmittance of the first display area 10 meets the lighting requirements of the photosensitive device disposed below it.
  • the material of the third segment 323 may include at least one of indium tin oxide, indium zinc oxide, silver-doped indium tin oxide, and silver-doped indium zinc oxide.
  • the material for preparing the third section 323 uses silver-doped indium tin oxide or silver-doped indium zinc oxide, so as to reduce the third section on the basis of ensuring the high light transmittance of the first display region 10 323 resistance.
  • the first section 321 and the second section 322 may be provided on the same layer, that is, the first section 321 and the second section 322 are formed in the same process step, and the first section 321 It is located on a different layer from the third section 323.
  • An insulating layer is provided between the third section 323 and the first section 321.
  • a plurality of second through holes are provided on the insulating layer, and the first section 321 and the second section 322 are respectively connected to the third section 323 through corresponding second through holes.
  • the third section 323 and the first electrode 111 may be arranged on the same layer.
  • the first section 321 and the second section 322 may be respectively located on the same layer as the power cord.
  • the third segment 323 and the first electrode 111 are formed in the same process step, and the first segment 321, the second segment 322 and the portion of the power line located in the second display area 20 can be formed in the same process step. Therefore, the complexity of the preparation process of the display substrate can be reduced, and the preparation process can be simplified.
  • the insulating layer between the first section 321 and the third section 323 is the planarization layer 46.
  • the third section 323 may be provided around a part of the first electrode 111.
  • the third section 323 includes a first subsection 3234, a second subsection 3235, and a third subsection 3236 that are sequentially connected.
  • the second sub-segment 3235 extends along the first direction.
  • the first sub-segment 3234 and the third sub-segment 3236 extend along the second direction.
  • the first sub-segment 3234 is connected to the first segment 321.
  • the third sub-segment 3236 is connected to the second segment 322.
  • the first type data line 31, the second type data line 32 and the power line may all be located above the substrate 410. At least a part of the projection of the first electrode 111 on the substrate 410 falls within the projection of the portion 16 of the power line located in the first display area 10 on the substrate 410.
  • the portion 16 of the power line located in the first display area 10 can shield the electric field between the first electrode 111 and the signal line (eg scan line) located below the power line along the thickness direction of the display substrate 100, so as to prevent the signal line from receiving
  • the received signal is unstable, which improves the stability of the signal received by the first sub-pixel 11, thereby improving the display effect of the first display area 10.
  • the drain 252 of the second transistor 25 in the pixel circuit 22 and the first segment 321 and the second segment 322 can be formed in the same process step. This arrangement can simplify the manufacturing process of the display substrate and reduce the complexity of the manufacturing process.
  • the first electrode 111 and the fifth segment 312 of the first type data line 31 are located on the same layer.
  • the power line is located in the portion 16 of the first display area 10
  • the third section 323 of the second type data line 31 and the upper electrode plate 152 of the capacitor are located on the same layer, and are located on the same layer as the first electrode 111 and the fifth section 312 Different layers.
  • the third section 323 of the second type data line 31 may be located between the portion 16 of the power line located in the first display area 10 and the upper plate 152 of the capacitor.
  • the area of the portion 16 of the power line located in the first display area 10 may be greater than the area of the upper electrode plate 152, and the area of the upper electrode plate 152 may be greater than the area of the third section 323 of the second type data line 31.
  • the distance between the portion 16 of the power line located in the first display area 10 and the third section 323 can be changed continuously or intermittently.
  • the third section 323 is connected to the upper plate 152.
  • the distance between can change continuously or intermittently.
  • the shape of the third section 323, the third section 323 and the upper electrode plate 152 of the second type data line 31 may be elongated, wavy, gourd, dumbbell, etc.
  • first section 321, the second section 322, and the third section 323 are located on the same layer, and the first section 321 and the second section 322 are respectively connected to the third section Segment 323 overlaps.
  • the third segment 323 and the portion 16 of the power line located in the first display area 10 may be disposed on the same layer, that is, the third segment 323 and the portion of the power line located in the first display area 10 are formed in the same process step.
  • the drain 251 of the second transistor 25 in the pixel circuit 22 of the second sub-pixel 21 can be formed in the same process step as the first segment 321 and the second segment 322. This configuration can further simplify the manufacturing process of the display substrate 100.
  • the third segment 323 of the second type data line 32 surrounds a part of the first display area 10.
  • the third segment 323 is arranged around the first display area 10. Compared with arranging the third segment 323 in the first display area 10, the structural complexity of the first display area 10 can be reduced, and the structure of the first display area 10 can be improved.
  • the light transmittance can reduce the diffraction caused when external light enters the first display area 10 due to the complicated structure of the first display area 10.
  • the third segment 323 may include a fourth sub-segment 3231, a fifth sub-segment 3232, and a sixth sub-segment 3233 that are sequentially connected.
  • the fourth sub-segment 3231 and the sixth sub-segment 3233 extend along the second direction.
  • the fifth sub-section 3232 extends along the first direction.
  • the fourth sub-segment 3231 is connected to the first segment 321.
  • the sixth sub-segment 3233 is connected to the third segment 323.
  • the first section 321, the second section 322 and the third section 323 may be located on the same layer. With this arrangement, the first section 321, the second section 322, and the third section 323 can be formed in the same process step, which can simplify the manufacturing process of the display substrate 100.
  • the drain 252 and the source 251 of the second transistor 25 of the pixel circuit 22 of the second sub-pixel 21 and the first section 321, the second section 322 and the third section 323 can be in the same process step.
  • the drain 252, the source 251, the first section 321, the second section 322 and the third section 323 of the second transistor 25 can be prepared through the same process step, which can further simplify the manufacturing process of the display substrate 100.
  • the first type data line 31, the second type data line 32 and the power line may be located above the substrate 410.
  • the projection of the first electrode 111 on the substrate 410 at least partially falls within the projection of the portion 16 of the power line located in the first display area 10 on the substrate 410.
  • the portion 16 of the power line located in the first display area 10 can shield the electric field between the first electrode 111 and the signal line (eg scan line) located below the power line along the thickness direction of the display substrate 100, so as to prevent the signal line from receiving
  • the received signal is unstable, which improves the stability of the signal received by the first sub-pixel, thereby improving the display effect of the first display area 10.
  • the display area of the display substrate 100 may further include a third display area 30 located between the first display area 10 and the second display area 20.
  • the third segment 323 of the second type data line 32 may be arranged in the third display area 30.
  • the third display area 30 may not be provided with sub-pixels.
  • the third display area 30 displays a black image, that is, the third display area 30 is in a black ring shape.
  • sub-pixels may also be arranged in the third display area 30.
  • the pixel circuit 12 of the first sub-pixel 11 close to the third display area 30 may be disposed in the third display area 30.
  • This configuration can further reduce the structural complexity of the first display area 10, reduce diffraction, and increase the light transmittance of the first display area 10.
  • the first type data lines 31 and the second type data lines 32 are alternately arranged.
  • only one second-type data line 32 is provided between two adjacent first-type data lines 31 for illustration.
  • two or more second-type data lines 32 may also be provided between two adjacent first-type data lines 31; or, two or more second-type data lines 32 may be provided between two adjacent second-type data lines 32.
  • the second-type data lines 32 are distributed on both sides of the entire first-type data lines 31. And when the number of the first type data lines 31 is more than two, more than two first type data lines 31 are arranged adjacently. When the number of the second type data lines 32 located on the same side of the first type data line 32 is more than two, two or more second type data lines 32 located on the same side of the first type data line 32 are arranged adjacently. This makes it easier to arrange the third segment 323 of the second type data line 32 in the second display area 20, and the process is easier to implement.
  • the plurality of pixel groups in the display area of the display substrate 100 may further include a fifth type of pixel group 103.
  • the fifth type pixel group 103 includes a plurality of second sub-pixels 21.
  • the multiple second sub-pixels 21 of the same fifth pixel group 103 are located on the same side of the first display area 10 in the second direction, and the multiple second sub-pixels 21 of the multiple second sub-pixels 21 are spaced along the first direction.
  • a third-type data line 33 may be further provided in the display substrate 100, and the pixel circuits 22 corresponding to a plurality of second sub-pixels 21 in the same fifth-type pixel group 103 are connected to the same third-type data line 33.
  • the sub-pixels in the display area of the display substrate 100 may also be divided into a third-type pixel group 201, a fourth-type pixel group 202, and a sixth-type pixel group 203.
  • the third-type pixel group 201, the fourth-type pixel group 202, and the sixth-type pixel group 203 are arranged along the first direction.
  • the third-type pixel group 201 includes a plurality of first sub-pixels 11 and a plurality of second sub-pixels 21.
  • the fourth-type pixel group 202 only includes a plurality of the second sub-pixels 21.
  • the plurality of sub-pixels in the third-type pixel group 201 and the fourth-type pixel group 202 are all arranged at intervals along the second direction.
  • the first-type pixel group 101, the second-type pixel group 102, and the fifth-type pixel group 103 are divided into a plurality of sub-pixels in a second direction, for example.
  • the third-type pixel group 201, the fourth-type pixel group 202, and the sixth-type pixel group 203 are divided into these sub-pixels again in another way, for example, in the first direction. Therefore, the same sub-pixel can belong to one of the first-type pixel group 101, the second-type pixel group 102, and the fifth-type pixel group 103, as well as the third-type pixel group 201, the fourth-type pixel group 202, and the third-type pixel group.
  • the same sub-pixel cannot belong to multiple groups of the first type pixel group 101, the second type pixel group 102, and the fifth type pixel group 103 at the same time, nor can it belong to the third type pixel group 201 and the fourth type pixel group at the same time.
  • 202 and a plurality of groups in the sixth type pixel group 203 are a plurality of groups in the sixth type pixel group 203.
  • the display area of the display substrate 100 is also provided with a first type of light-emitting control line 41 and a second type of light-emitting control line 42.
  • the pixel circuit 21 of each first sub-pixel 11 and the pixel circuit 22 of each second sub-pixel 21 in each of the third-type pixel groups 201 are connected to the same first-type light-emitting control line 41.
  • the pixel circuit 22 of each second sub-pixel 21 in each of the fourth-type pixel groups 202 is connected to the same second-type light-emitting control line 42.
  • the first type of light emitting control line 41 and the second type of light emitting control line 42 are used to provide light emitting control signals for the sub-pixels.
  • the third-type pixel group 201 One sub-pixel 11 and second sub-pixel 21 can be driven by the same first-type light-emitting control line 41, thereby reducing the complexity of wiring in the display area of the display substrate 100, and simultaneously enabling the first display area 10 and the second display area 20 The display effect is more consistent, which is conducive to improving the user experience.
  • the second sub-pixels 21 in each of the third-type pixel groups 201 are arranged in areas located on both sides of the first display area 10 along the second direction, and/ Or, the second sub-pixels 21 in the fourth-type pixel group 202 are arranged in areas located on both sides of the first display area 10 along the second direction.
  • the second-type light-emitting control line 42 may include a first Ten paragraph 421, eleventh paragraph 422 and twelfth paragraph 423.
  • the tenth segment 421 and the eleventh segment 422 are located in the second display area 20 and located on both sides of the first display area 10.
  • the twelfth segment 423 connects the tenth segment 421 and the eleventh segment 422.
  • the tenth segment 421, the eleventh segment 422, and the twelfth segment 423 can be located on the same layer, and the twelfth segment 423 can be located at the same level as the tenth segment 421 and the eleventh segment. 422 overlap. With this arrangement, there is no need to provide through holes on the insulating layer to realize the connection of the tenth segment 421 and the twelfth segment 423, and the eleventh segment 422 and the twelfth segment 423, which simplifies the preparation of the second type of light-emitting control line 42 Craft.
  • the twelfth segment 423 may be located in the first display area 10, and the light transmittance of the twelfth segment 423 is greater than or equal to 70%.
  • the light transmittance of the twelfth segment 423 may be greater than or equal to 90%, for example, the light transmittance of the twelfth segment 423 may be 90%, 95%, or the like.
  • Such an arrangement can make the light transmittance of the first display area 10 larger, so that the light transmittance of the first display area 10 meets the lighting requirements of the photosensitive device disposed below it.
  • the material of the twelfth segment 423 may include at least one of indium tin oxide, indium zinc oxide, silver-doped indium tin oxide, and silver-doped indium zinc oxide.
  • the material for preparing the twelfth segment 423 is made of silver-doped indium tin oxide or silver-doped indium zinc oxide, so as to ensure the high light transmittance of the first display region 10 and reduce the tenth Two-stage 423 resistance.
  • the twelfth segment 423 may surround a part of the first display area 10. Arranging the twelfth segment 423 around the first display area 10, compared to placing the twelfth segment 423 in the first display area 10, can reduce the structural complexity of the first display area 10 and help improve the first display area. The light transmittance of the area 10 can reduce the diffraction generated when external light enters the first display area 10 due to the complex structure of the first display area 10.
  • the twelfth segment 423 may be provided in the third display area 30.
  • the sixth type pixel group 203 may include a plurality of second sub-pixels 21.
  • the plurality of second sub-pixels 21 of the sixth type pixel group 203 are distributed in an area located on the side of the first display area 10 along the first direction, and the plurality of second sub-pixels 21 of the plurality of second sub-pixels 21 are along the first Arranged at intervals in two directions.
  • the display substrate 100 may further be provided with a third-type light-emitting control line 43, and the pixel circuits 22 corresponding to a plurality of second sub-pixels 21 in the same sixth-type pixel group 203 are connected to the same third-type light-emitting control line 43.
  • the first type scan lines 51 and the second type scan lines 52 may also be provided in the display area.
  • the pixel circuit 12 of each first sub-pixel 11 and the pixel circuit 22 of each second sub-pixel 21 in each third-type pixel group 201 are connected to the same first-type scan line 51.
  • the pixel circuit 22 of each second sub-pixel 21 in each fourth-type pixel group 202 is connected to the same second-type scan line 52.
  • the first type scan line 51 and the second type scan line 52 are used to provide scan signals for sub-pixels.
  • the first-type pixel group 201 Since the pixel circuit 12 of the first sub-pixel 11 and the pixel circuit 22 of the second sub-pixel 21 in the same third-type pixel group 201 are connected to the same first-type scan line 51, the first-type pixel group 201 The sub-pixels 11 and the second sub-pixels 21 can be driven by the same first-type scan line 51, thereby reducing the wiring complexity in the display area of the display substrate 100, and at the same time enabling the display of the first display area 10 and the second display area 20 The effect is more consistent, which is conducive to improving the user experience.
  • the second sub-pixels 21 in each of the third-type pixel groups 201 are arranged in areas located on both sides of the first display area 10 along the second direction, and/ Or, the second sub-pixels 21 in the fourth-type pixel group 202 are arranged in areas located on both sides of the first display area 10 along the second direction.
  • the second-type scan lines 52 The seventh segment 521, the eighth segment 522, and the ninth segment 523 can be included.
  • the seventh segment 521 and the eighth segment 522 are located in the second display area 20 and located on both sides of the first display area 10.
  • the ninth segment 523 connects the seventh segment 521 and the eighth segment 522.
  • the seventh section 521, the eighth section 522, and the ninth section 523 may be located on the same layer, and the ninth section 523 may overlap with the seventh section 521 and the eighth section 522, respectively. With this arrangement, there is no need to provide through holes on the insulating layer to realize the connection between the seventh segment 521 and the ninth segment 523, and the eighth segment 522 and the ninth segment 523, which simplifies the manufacturing process of the second type scan line 52.
  • the ninth segment 523 may be located in the first display area 10, and the light transmittance of the ninth segment 523 is greater than or equal to 70%.
  • the light transmittance of the ninth section 523 may be greater than or equal to 90%, for example, the light transmittance of the ninth section 523 may be 90%, 95%, or the like.
  • Such an arrangement can make the light transmittance of the first display area 10 larger, so that the light transmittance of the first display area 10 meets the lighting requirements of the photosensitive device disposed below it.
  • the material of the ninth segment 523 may include at least one of indium tin oxide, indium zinc oxide, silver-doped indium tin oxide, and silver-doped indium zinc oxide.
  • the material for preparing the ninth segment 523 uses silver-doped indium tin oxide or silver-doped indium zinc oxide to reduce the ninth segment while ensuring the high light transmittance of the first display region 10 523 resistance.
  • the ninth segment 523 may surround a part of the first display area 10. Arranging the ninth segment 523 around the first display area 10, compared to arranging the ninth segment 523 in the first display area 10, can reduce the structural complexity of the first display area 10 and help improve the first display area 10. The light transmittance of the first display area 10 is complicated, and the diffraction caused when external light enters the first display area 10 due to the complicated structure of the first display area 10 can be reduced.
  • the ninth segment 523 may be provided in the third display area 30.
  • the sixth type of pixel group 203 includes a plurality of second sub-pixels 21.
  • the plurality of second sub-pixels 21 of the sixth type pixel group 203 are distributed on one side of the first display area 10 along the first direction, and the plurality of second sub-pixels 21 of the plurality of second sub-pixels 21 are along the second direction. Arranged at intervals.
  • the display substrate 100 may further be provided with a third-type scan line 53, and the pixel circuits 22 corresponding to the plurality of second sub-pixels 21 in the same sixth-type pixel group 203 are connected to the same third-type scan line 53.
  • the first electrode 111 of each of the first sub-pixels 11 may include at least one first electrode block, and the light emitting structure includes a light emitting structure block correspondingly disposed on each first electrode block.
  • the first electrode 111 includes two or more first electrode blocks 1111, and the two or more first electrode blocks 1111 are arranged at intervals along the first direction. cloth.
  • the first electrode 111 further includes a connecting portion 1112 arranged between two adjacent first electrode blocks 1111, and the two adjacent first electrode blocks 1111 are electrically connected through corresponding connecting portions 1112.
  • the first electrode block 1111 in the first electrode 111 can be provided with a signal by one data line or scan line, which can reduce the complexity of the wiring in the first display area, and can effectively improve the light transmission of the first display area.
  • the diffractive superimposition phenomenon caused by the complicated wiring further improves the image quality of the camera set on the backlight surface of the first display area, and avoids the defect of image distortion.
  • the multiple first electrode blocks 1111 in the same first electrode 111 are electrically connected, so that the corresponding light-emitting structure blocks on the multiple first electrode blocks 1111 of the same first electrode 111 can be controlled to emit light or be turned off at the same time.
  • the control of the first display area 10 is simplified.
  • the first electrode block 1111 and the connecting portion 1112 of the same first electrode 111 are arranged on the same layer.
  • the first electrode block 1111 and the connecting portion 1112 of the same first electrode 111 can be formed in the same process step, reducing the complexity of the manufacturing process.
  • the size of the connecting portion 1112 perpendicular to the extending direction thereof is greater than 3 ⁇ m and smaller than one half of the maximum size of the first electrode block 1111.
  • the resistance of the connecting portion 1112 can be made smaller;
  • the arrangement of the connecting portion 1112 has a small effect on the size of the first electrode block 1111, avoiding that the size of the connecting portion 1112 is large and the size of the first electrode block 1111 is reduced, and the effective light-emitting area of the first display area 10 is reduced.
  • the projection of the first electrode block 1111 of the first electrode 111 on the substrate 410 of the display substrate 100 is composed of one first graphic unit or multiple first graphic units.
  • the first graphic unit may include a circle, an oval, a dumbbell, a gourd or a rectangle.
  • the first electrode 111 of the first display area 10 shown in FIG. 11 includes six first electrode blocks 1111, and the projection of each first electrode block 1111 on the substrate is composed of a first pattern unit.
  • the unit is rectangular.
  • the first electrode 111 in the first display area 10 shown in FIG. 12 includes five first electrode blocks 1111, and the projection of each first electrode block 1111 on the substrate is composed of a first pattern unit.
  • the graphic unit is circular.
  • the first electrode 111 in the first display area 10 shown in FIG. 13 includes two first electrode blocks 1111, and the projection of the first electrode block 1111 on the substrate is composed of a first pattern unit, which is Dumbbell shape.
  • the first graphic unit is circular, elliptical, dumbbell-shaped or gourd-shaped, which can change the periodic structure generated by diffraction, that is, change the distribution of the diffraction field, thereby reducing the diffraction effect caused by the time difference of external incident light passing through. Moreover, when the first image unit has the above-mentioned shape, the size of the first electrode 111 in the first direction changes continuously or intermittently, and the distance between two adjacent first electrodes 111 in the second direction is in the first direction.
  • first electrode blocks 1111 of the same first electrode 111 in the first direction, two adjacent first electrode blocks 1111 are arranged in a staggered manner. Such an arrangement can further reduce the diffraction effect generated when light incident from outside passes through the first display area 10.
  • two first electrode blocks 1111 arranged at intervals of one first electrode block 1111 overlap along the central axis of the second direction.
  • This arrangement can make the arrangement of the first electrode blocks 1111 more regular, so that the arrangement of the light-emitting structure blocks arranged above the plurality of first electrode blocks 1111 is more regular, and then the opening arrangement of the mask plate used for preparing the light-emitting structure blocks Comparison rules.
  • the same mask can be used to manufacture in the same evaporation process. Since the pattern on the mask is relatively uniform, Also reduces the folds of the net.
  • the projection of the light-emitting structure block correspondingly provided on the first electrode block on the substrate is composed of a second graphic unit or a plurality of second graphic units, and the second graphic unit and the first The graphic units are the same or different.
  • the first image unit is different from the second image unit, and the projection of the light-emitting structure block correspondingly provided on the first electrode block 1111 on the substrate is different from that of the first electrode block on the substrate.
  • the projection is different to further reduce the diffraction effect generated when light passes through the first display area 10.
  • the second graphic unit may include a circle, an oval, a dumbbell, a gourd, or a rectangle.
  • the first-type data line 31 is located in a portion of the first display area 10, and the light transmittance of the first electrode and/or the second electrode is greater than or equal to 70%.
  • the first type of data line 31 is located in the portion of the first display area 10, the light transmittance of the first electrode 111 and/or the second electrode may be greater than or equal to 90%, for example, the light transmittance may be 90% , 95%, etc.
  • Such an arrangement can make the light transmittance of the first display area 10 larger, so that the light transmittance of the first display area 10 meets the lighting requirements of the photosensitive device disposed below it.
  • the first type of data line 31 is located in the part of the first display area 10, and the material of the first electrode 111 and/or the second electrode may include indium tin oxide, indium zinc oxide, silver-doped indium tin oxide And at least one of silver-doped indium zinc oxide.
  • the first type of data line 31 is prepared in the part of the first display area 10, and the transparent material of the first electrode 111 and/or the second electrode is silver-doped indium tin oxide or doped
  • the silver indium zinc oxide can reduce the resistance of the first electrode and/or the second electrode of the part of the first type data line 31 located in the first display area 10 on the basis of ensuring the high light transmittance of the first display area.
  • the first display area 10 of the display substrate 100 provided by the embodiment of the present application may have a shape such as a drop shape, a circle, a rectangle, a semicircle, a semiellipse, or an ellipse. However, it is not limited to this, and the first display area 10 can also have other shapes according to actual conditions.
  • first direction and the second direction may be perpendicular to each other.
  • first direction may be a column direction, and the second direction may be a row direction; or, the first direction may be a row direction, and the second direction may be a column direction.
  • first direction is the column direction and the second direction is the row direction as an example for description, and other cases are not shown.
  • the embodiment of the present application also provides a display panel, which includes the above-mentioned display substrate 100 and an encapsulation layer.
  • the encapsulation layer is disposed on the side of the display substrate 100 away from the substrate.
  • the first display area 10 is at least partially surrounded by the second display area 20.
  • the first display area 10 shown in FIG. 1 is partially surrounded by the second display area 20.
  • the first display area 10 may also be completely surrounded by the second display area 20.
  • the encapsulation layer may include a polarizer, and the polarizer covers at least the second display area 20. Further, the polarizer does not cover the first display area 10, and a photosensitive device that emits or collects light through the first display area 10 may be disposed under the first display area 10. The polarizer can dissipate the reflected light on the surface of the display panel and improve the user experience.
  • the first display area 10 is not provided with a polarizer, which can increase the light transmittance of the first display area 10 and ensure the normal operation of the photosensitive device arranged under the first display area 10.
  • the photosensitive device can be arranged under the first display area 10 to ensure normal operation of the photosensitive device. Under the premise of achieving a full-screen display of the display substrate 100.
  • the first-type pixel group 101 Since the pixel circuit 12 of the first sub-pixel 11 and the pixel circuit 22 of the second sub-pixel 21 in the same first-type pixel group 101 are connected to the same first-type data line 31, the first-type pixel group 101 The sub-pixel 11 and the second sub-pixel 21 can be driven by the same first-type data line 31, thereby reducing the wiring complexity in the display area of the display substrate 100, and simultaneously enabling the display of the first display area 10 and the second display area 20 The effect is more consistent, which is conducive to improving the user experience. Since the first-type data line 31 is located in the portion of the first display area 10, for example, the fifth segment 312 is located on the same layer as the first electrode 111, the power line is located in the portion 16 of the first display area 10.
  • the power line located in the portion 16 of the first display area 10 can reduce the portion of the first-type data line 31 located in the first display area 10 and the first display area.
  • Signal interference between other signal lines (such as gate lines) located below the power line in the area improves the stability of the signals received by the first-type data line and other signal lines located under the power line in the first display area, and thereby Improve the display effect of the display substrate.
  • the embodiment of the present application also provides a display device, which includes an equipment body and the above-mentioned display panel.
  • the device body has a device area, and the display panel covers the device body.
  • the device area is located below the first display area, and the device area is provided with a photosensitive device that collects light through the first display area.
  • the photosensitive device may include a camera and/or a light sensor.
  • Devices other than photosensitive devices such as gyroscopes or earpieces, can also be arranged in the device area.
  • the device area may be a slotted area, and the first display area of the display panel may be arranged corresponding to the slotted area, so that the photosensitive device can emit or collect light through the first display area.
  • the above-mentioned display device may be a digital device such as a mobile phone, a tablet, a palm computer, or an iPod.
  • the photosensitive device can be arranged under the first display area 10 to ensure normal operation of the photosensitive device. Under the premise of achieving a full-screen display of the display substrate 100.
  • the first-type pixel group 101 Since the pixel circuit 12 of the first sub-pixel 11 and the pixel circuit 22 of the second sub-pixel 21 in the same first-type pixel group 101 are connected to the same first-type data line 31, the first-type pixel group 101 The sub-pixel 11 and the second sub-pixel 21 can be driven by the same first-type data line 31, thereby reducing the wiring complexity in the display area of the display substrate 100, and simultaneously enabling the display of the first display area 10 and the second display area 20 The effect is more consistent, which is conducive to improving the user experience. Since the portion 311 of the first-type data line 31 located in the first display area 10 and the first electrode 111 are located on the same layer, the portion 16 of the power supply line located in the first display area 10 is located in the first display area.
  • the first type of data line 31 is located below the portion of the first display area, and the portion of the power line located in the first display area 10 can reduce the portion of the first type data line 31 located in the first display area 10 and the portion of the first display area located in the power line
  • Signal interference between other signal lines (such as gate lines) below improves the stability of the signals received by the first-type data lines and other signal lines located below the power lines in the first display area, thereby improving the display of the display substrate effect.

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Abstract

本申请提供了一种显示基板、显示面板及显示装置。显示基板包括第一显示区和第二显示区，显示基板包括多个子像素，被划分为沿第二方向排布的多个像素组包括第一类像素组和第二类像素组。第一类像素组包括位于第一显示区的第一子像素和位于第二显示区的第二子像素。第二类像素组仅包括第二子像素。第一类像素组和第二像素组中的至少一者的第二子像素排布在沿第一方向位于第一显示区两侧的区域。同一第一类像素组中第一子像素和第二子像素的像素电路连接至同一第一类数据线。同一第二类像素组中第二子像素的像素电路连接至同一第二类数据线。位于第一显示区的电源线设置在位于第一显示区的第一类数据线下方。

Description

显示基板、显示面板及显示装置
相关申请
本申请要求2019年05月31日申请的，申请号为201910470777.7，名称为“显示基板、显示面板及显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示基板、显示面板及显示装置。
背景技术
随着电子设备的快速发展，用户对屏占比的要求越来越高，使得电子设备的全面屏显示受到业界越来越多的关注。传统的电子设备如手机、平板电脑等，由于需要集成诸如前置摄像头、听筒以及红外感应元件等，故而可通过在显示屏上开槽(Notch)，在开槽区域设置摄像头、听筒以及红外感应元件等。对于实现摄像功能的电子设备来说，外界光线可通过屏幕上的开槽处进入位于屏幕下方的感光元件。但是显示屏的开槽区域并不能用来显示画面，因此均不是真正意义上的全面屏。
发明内容
一种显示基板，包括显示区，所述显示区包括第一显示区和第二显示区，所述第一显示区的透光率大于所述第二显示区的透光率；
所述显示区包括多个子像素，所述多个子像素被划分为沿第二方向排布的多个像素组，所述沿第二方向排布的多个像素组包括多个第一类像素组和多个第二类像素组；
所述多个子像素包括设置在所述第一显示区内的多个第一子像素和设置在所述第二显示区内的多个第二子像素，所述多个第一子像素的分布密度小于所述多个第二子像素的分布密度；
每一第一类像素组包括沿第一方向排布的所述多个第一子像素中的一些和所述多个第二子像素中的一些，每一第二类像素组仅包括沿所述第一方向排布的所述多个第二子像素中的另一些，所述每一第一类像素组和所述每一第二类像素组中的一者或两者的所述第二子像素排布在沿第一方向位于所述第一显示区两侧的区域；
所述显示区包括多个第一类数据线、多个第二类数据线、电源线以及与所述多个子像素一一对应的多个像素电路，同一第一类像素组中各第一子像素和各第二子像素的像素电路连接至同一第一类数据线，同一第二类像素组中的各第二子像素的像素电路连接至同一第二类数据线；
所述电源线位于所述第一显示区的部分设置在至少一第一类数据线位于所述第一显示区的部分的沿所述显示基板的厚度方向的下方。
可选地，每一第一子像素包括第一电极、位于所述第一电极上的第一发光结构及位于所述第一发光结构上的第二电极，每一所述多个第一类数据线位于所述第一显示区的部分与所述第一电极设置在同一层。
可选地，所述至少一第一类数据线位于所述第一显示区的部分与所述至少一第一类数据线位于所述第二显示区的部分位于不同层；所述显示基板还包括绝缘层；所述至少一第一类 数据线位于所述第一显示区的部分与所述至少一第一类数据线位于所述第二显示区的部分设置在所述绝缘层相对的两个表面，并通过所述绝缘层上设置的第一通孔连接。
可选地，所述多个第一类数据线与所述多个第二类数据线交替排布；或者，所述多个第二类数据线分布在所述多个第一类数据线整体的两侧。
可选地，每一所述多个第一子像素的像素电路包括第一电容，所述第一电容包括相对设置的下极板和上极板，所述上极板为所述电源线位于所述第一显示区的所述部分。
可选地，所述多个沿第二方向排布的像素组还包括第五类像素组，所述第五类像素组仅包括所述多个第二子像素中的又一些，同一第五类像素组中的所述第二子像素均位于所述第一显示区沿所述第二方向的同一侧；
所述显示区还包括多个第三类数据线，同一第五类像素组中各第二子像素的像素电路连接至同一第三类数据线。
可选地，所述每一第二类像素组的所述第二子像素排布在沿所述第一方向位于所述第一显示区两侧的区域，所述第二类数据线包括第一段、第二段及第三段，所述第一段和所述第二段在所述第一方向上分别位于所述第一显示区的两侧，所述第三段连接在所述第一段和所述第二段之间，所述第三段位于所述第一显示区。
可选地，所述第三段的透光率大于或等于70％。
可选地，所述第三段的材料包括氧化铟锡、氧化铟锌、掺杂银的氧化铟锡及者掺杂银的氧化铟锌中的至少一种。
可选地，所述第一段与所述第二段设置在同一层，所述第一段与所述第三段位于不同层，所述显示基板还包括沿所述显示基板的厚度方向设置在所述第三段与所述第一段之间的绝缘层，所述绝缘层上设置有第二通孔，所述第一段和所述第二段分别通过所述第二通孔与所述第三段连接。
可选地，每一第一子像素包括第一电极、位于所述第一电极上的第一发光结构及位于所述第一发光结构上的第二电极；所述第三段与所述第一电极设置在同一层，所述第一段和所述第二段分别与所述电源线设置在同一层。
可选地，所述显示基板还包括衬底，所述第一电极、所述多个第一类数据线、所述多个第二类数据线及所述电源线位于所述衬底上方，所述第一电极在所述衬底上的投影落在所述电源线位于所述第一显示区的部分在所述衬底上的投影内。
可选地，所述显示区还包括位于所述第一显示区和所述第二显示区之间的第三显示区，所述第三显示区内未设置子像素；
所述第二类像素组的所述第二子像素排布在沿所述第一方向位于所述第一显示区两侧的区域，所述第二类数据线包括第一段、第二段及第三段，所述第一段和所述第二段在所述第一方向上分别位于所述第一显示区的两侧，所述第三段连接在所述第一段和所述第二段之间，所述第三段设置在所述第三显示区内；所述第三段包括顺次连接的第四子段、第五子段和第六子段，所述第四子段和所述第六子段沿所述第二方向延伸，所述第五子段沿所述第一方向延伸，所述第四子段与所述第一段连接，所述第六子段与所述第三段连接。
可选地，所述多个子像素还被划分为沿第一方向排布的多个像素组，所述沿第一方向排布的多个像素组包括多个第三类像素组和多个第四类像素组；
每一第三类像素组包括沿所述第二方向排布的所述多个第一子像素中的一些和所述多个第二子像素中的一些，每一第四类像素组仅包括沿所述第二方向排布的所述多个所述第二子 像素中的另一些，所述每一第三类像素组和所述每一第四类像素组中的一者或两者的所述第二子像素排布在沿所述第二方向位于所述第一显示区两侧的区域；
所述显示区还包括多个第一类发光控制线和多个第二类发光控制线，同一第三类像素组中各第一子像素和各第二子像素的像素电路连接至同一第一类发光控制线，同一第四类像素组中各第二子像素的像素电路连接至同一第二类发光控制线；所述第一类发光控制线和所述第二类发光控制线用于为所述多个子像素提供发光控制信号。
可选地，所述每一第四类像素组中的所述第二子像素排布在沿所述第二方向位于所述第一显示区两侧的区域，所述第二类发光控制线包括第十段、第十一段和第十二段，所述第十段和所述第十一段位于所述第二显示区内且在所述第二方向上分别位于所述第一显示区两侧，所述第十二段连接在所述第十段和所述第十一段之间，所述第十二段位于所述第一显示区。
可选地，所述多个子像素还被划分为沿第一方向排布的多个像素组，所述沿第一方向排布的多个像素组包括多个第三类像素组和多个第四类像素组；
每一所述第三类像素组包括沿所述第二方向排布的所述多个第一子像素中的一些和所述多个第二子像素中的一些，每一第四类像素组仅包括沿所述第二方向排布的所述多个第二子像素中的另一些，所述每一第三类像素组及所述每一第四类像素组中的一者或两者的所述第二子像素排布在沿所述第二方向位于所述第一显示区两侧的区域；
所述显示区还包括多个第一类扫描线和多个第二类扫描线，同一第三类像素组中各第一子像素和各第二子像素的像素电路连接至同一第一类扫描线，同一第四类像素组中各第二子像素的像素电路连接至同一第二类扫描线；所述第一类扫描线和所述第二类扫描线用于为子像素提供扫描信号。
可选地，所述每一第四类像素组中的所述第二子像素排布在沿所述第二方向位于所述第一显示区两侧的区域，所述第二类扫描线包括第七段、第八段和第九段，所述第七段和所述第八段位于所述第二显示区内且在所述第二方向上分别位于所述第一显示区两侧，所述第九段连接在所述第七段和所述第八段之间，所述第九段位于所述第一显示区。
可选地，每一第一子像素包括第一电极、位于所述第一电极上的发光结构及位于所述发光结构上的第二电极，所述第一电极包括沿所述第一方向相互间隔排布的多个第一电极块和设置在相邻的两个第一电极块之间的连接部，所述多个第一电极块在所述第二方向上错位排布。
一种显示面板，其中，所述显示面板包括权利要求1所述的显示基板，以及封装所述显示基板的封装结构。
一种显示装置，其中，包括：
设备本体，具有器件区；以及
所述的显示面板，覆盖在所述设备本体上；
其中，所述器件区位于所述第一显示区下方，且所述器件区中设置有透过所述第一显示区发射或者采集光线的感光器件。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施，下面将对实施例中所使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例的示意图，对于本领域普通技术人员来说，在不付出创造性劳动的前提下，还可以根据提供的附图获得其它的附图。
图1是本申请提供的一种显示基板的实施例的俯视图。
图2A是本申请提供的另一种显示基板的实施例的俯视图；
图2B是本申请提供的又一种显示基板的实施例的俯视图，第一显示区的位置与图2A中不同。
图2C是本申请提供的再一种显示基板的实施例的俯视图，第一显示区的位置与图2A中不同。
图3是图1所示的显示基板的实施例中子像素排布的局部示意图。
图4是与图3对应的显示基板的实施例中数据线的排布示意图。
图5是图1所示的显示基板的另一种子像素排布的局部示意图。
图6是与图5对应的显示基板的数据线的排布示意图。
图7A是图1所示的显示基板的实施例的沿第一方向的剖视图。
图7B是图1所示的显示基板的实施例的仅显示绝缘层与第一类数据线的沿第二方向的剖视图。
图8是图1所示的显示基板的实施例的局部结构示意图。
图9是图1所示的显示基板的实施例中发光控制线的排布示意图。
图10是图1所示的显示基板的实施例中扫描线的排布示意图。
图11是本申请提供的第一电极的一实施例在衬底上的投影示意图。
图12是本申请提供的第一电极的另一实施例在衬底上的投影示意图，第一电极的形状与图11不同。
图13是本申请提供的第一电极的又一实施例在衬底上的投影示意图，第一电极的形状与图11不同。
图14是本申请提供的第一显示区的实施例的结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
在电子设备中设置非透明显示屏和透明显示屏，将感光器件设置在透明显示屏下方，可在保证感光器件正常工作的前提下实现电子设备的全面屏显示。非透明显示屏的驱动方式为主动驱动，透明显示屏的驱动方式为被动驱动。当电子设备中既设置透明显示屏，又设置非透明显示屏时，在屏体上需要两种驱动方案，这将大大增加全面屏驱动的复杂度。本申请实施例提供了一种显示基板、显示面板及显示装置，其能够很好的解决上述问题。
下面结合附图，对本申请实施例中的显示基板、显示面板及显示装置进行详细说明。在不冲突的情况下，下述的实施例及实施方式中的特征可以相互补充或相互组合。
本申请实施例提供了一种显示基板。参见图1、图2A至图2C，所述显示基板100的显示区包括第一显示区10和第二显示区20，所述第一显示区10的透光率大于所述第二显示区 20。所述显示基板100的显示区包括多个子像素，所述多个子像素按阵列方式排布，可被划分多个像素组。可选地，所述多个子像素被沿第二方向划分为沿第二方向排布的多个像素组，每一像素组包括沿第一方向排布的多个子像素。
参见图3和图5，多个像素组包括第一类像素组101和第二类像素组102。所述第一显示区10内设有多个第一子像素11，所述第二显示区20内设有多个第二子像素21。所述第一子像素11的分布密度小于所述第二子像素21的分布密度，其中分布密度指显示区单位面积中子像素的数量。所述第一类像素组101包括第一子像素11和第二子像素21。所述第二类像素组102仅包括第二子像素21。第一类像素组101中的第二子像素21排布在沿第一方向位于所述第一显示区10两侧的区域，和/或，第二类像素组102的第二子像素21排布在沿第一方向位于所述第一显示区10两侧的区域。
参见图4和图6，所述显示基板100内设置有第一类数据线31、第二类数据线32、与第一子像素11一一对应的像素电路12、与第二子像素21一一对应的像素电路22及电源线。可选地，所述电源线为连接至ELVDD的引线。同一第一类像素组101中各第一子像素11的像素电路12和各第二子像素21的像素电路22连接至同一第一类数据线31。同一第二类像素组102中各第二子像素21的像素电路22连接至同一第二类数据线32。第一子像素11的像素电路12可设置在第一显示区10中，第二子像素21的像素电路22可设置在第二显示区20中。可选地，像素电路对应子像素的位置，沿显示基板100的厚度方向一一对应的设置在子像素的下方。
参见图7A，所述电源线位于所述第一显示区10的部分16沿显示基板100的厚度方向设置在所述第一类数据线31位于第一显示区10的部分下方。可选地，所述第一类数据线31位于第一显示区10的部分为所述第一类数据线31的第五段312。
本申请实施例提供的显示基板100，由于第一显示区10的透光率大于第二显示区20的透光率，则可将感光器件设置在第一显示区10下方，在保证感光器件正常工作的前提下实现显示基板100的全面屏显示。由于同一第一类像素组101中的第一子像素11的像素电路12和第二子像素21的像素电路22连接至同一第一类数据线31，则第一类像素组101中的第一子像素11和第二子像素21可由同一第一类数据线31驱动，从而可降低显示基板100的显示区内的布线复杂度，同时可使第一显示区10和第二显示区20的显示效果更一致，有利于提升用户的使用体验。由于所述电源线位于所述第一显示区10的部分16设置在所述第一类数据线31位于第一显示区10的部分的下方，则电源线位于第一显示区10的部分16可降低第一类数据线31位于第一显示区10的部分与第一显示区10中位于电源线下方的其他信号线(例如栅线)之间的信号干扰，提高第一类数据线31及第一显示区10中位于电源线下方的其他信号线接收到的信号的稳定性，进而提高显示基板的显示效果。
本申请实施例提供的显示基板100，可以如图1所示，第一显示区10全部被第二显示区20包围，或者也可以是第一显示区10部分被第二显示区20包围。如图2A和2B所示，第一显示区10的一个边缘与显示区的一个边缘重合，且显示区的该边缘沿第一方向延伸。如图2C所示，第一显示区10相对的两个的边缘均与显示区相对的两个边缘重合，且显示区的该两个边缘均沿第一方向延伸。图1至图2C所示的结构中，第一类像素组101和第二类像素组102中的第二子像素21均排布在沿第一方向位于第一显示区10两侧的区域。
在本申请实施例中，第一类像素组101和第二类像素组102包括沿第一方向排布的多个子像素，指的是同一个像素组中的多个子像素大致沿第一方向排布。同一个像素组的多个子 像素的沿第一方向的轴线可重合，也可不重合。例如如图5中所示，同一个像素组的多个子像素在第一方向上呈错位排布，该像素组的多个子像素也认为是沿第一方向间隔排布。
参见图4和图6，第一子像素11对应的像素电路12及第二子像素21对应的像素电路22可为2T1C电路、3T1C电路、或3T2C电路、或7T1C电路、或7T2C电路。其中，T代表晶体管，C代表存储电容。第一子像素11的像素电路和第二子像素21的像素电路的类型可相同，也可不同。
参见图7A，所述第一子像素11包括第一电极111、位于所述第一电极111上的第一发光结构112及位于所述第一发光结构112上的第二电极113，所述第二子像素21包括第三电极211、位于所述第三电极211上的第二发光结构212及位于所述第二发光结构212上的第四电极213。
显示基板100还可包括衬底410、位于衬底410上的缓冲层420、形成于缓冲层420上的半导体层26和半导体层14、形成于半导体层26和半导体层14上的栅极绝缘层430、位于栅极绝缘层430上方的电容绝缘层44、位于电容绝缘层44上方的层间介质层45、位于层间介质层45上方的平坦化层46、位于平坦化层46上的像素限定层47。
第二子像素21的像素电路22包括第二晶体管25和第二电容。第二晶体管25包括源极251、漏极252和栅极253。栅极253位于栅极绝缘层430和电容绝缘层44之间。源极251和漏极252位于层间介质层45上且通过栅极绝缘层430、电容绝缘层44和层间介质层45上的通孔与半导体层26接触。第二电容包括上极板271和下极板272，上极板271位于电容绝缘层44和层间介质层45之间。下极板272位于栅极绝缘层430和电容绝缘层44之间。第三电极211位于平坦化层46与像素限定层47之间。
第一子像素11的像素电路12包括第一晶体管13和第一电容。第一晶体管13包括源极131、漏极132和栅极133。栅极133位于栅极绝缘层430和电容绝缘层44之间。源极131和漏极132位于层间介质层45上且通过栅极绝缘层430、电容绝缘层44和层间介质层45上的通孔与半导体层14接触。第一电容包括上极板152和下极板151。上极板152位于电容绝缘层44和层间介质层45之间。下极板151位于栅极绝缘层430和电容绝缘层44之间。第一电极111位于平坦化层46与像素限定层47之间。
可选地，所述第一显示区10内可设置有第一导电层17。所述第一导电层17可一部分作为第一电容的上极板152，另一部分作为所述电源线位于第一显示区10的部分16。如此设置，电源线位于第一显示区10的部分16及第一电容的上极板152可通过同一步骤形成，并且无需在电源线与第一电容的上极板152形成之后再制备二者之间的连接结构，可简化显示基板100的制备工艺流程。
可选地，第一类数据线31位于第一显示区10的部分(例如第五段312)与第一电极111可设置在同一层。如此设置，第一类数据线31位于第一显示区10的部分与第一电极111可在同一工艺步骤中形成，从而可降低制备工艺的复杂度。可选地，所述第一类数据线31位于所述第二显示区20的部分与所述第一类数据线31位于所述第一显示区10的部分可设置在不同层。所述第一类数据线31位于所述第一显示区10的部分与所述第一类数据线31位于所述第二显示区20的部分之间设置有绝缘层。请参阅图7B，第一类数据线31位于第一显示区10的部分31’与第一类数据线31位于第二显示区20的部分31”设置在绝缘层相对的两个表面。该绝缘层上设置有第一通孔461。第一类数据线31位于所述第一显示区10的部分与所述第二类数据线31位于所述第二显示区20的部分通过绝缘层上的第一通孔461连接。可选 地，该绝缘层为平坦化层46。
参见图4和图6，第一类数据线31可包括顺次连接的第四段311、第五段312和第六段313。第四段311和第六段313位于第二显示区20中。第五段312为第一类数据线31位于第一显示区10中的部分。第五段312位于第一显示区10的部分与第一电极111可位于同一层。
第四段311、第六段313及第二晶体管25的源极251、漏极252可在同一工艺步骤中形成。第一类数据线31位于第一显示区10的部分与第一电极111设置在同一层时，第四段311及第六段313与第五段312之间的绝缘层包括平坦化层46。
可选地，所述第二类像素组102的第二子像素21排布在沿第一方向位于所述第一显示区10两侧的区域时，参见图4和图6，所述第二类数据线32可包括第一段321、第二段322和第三段323。所述第一段321和所述第三段323位于第二显示区20中，且在所述第一方向上分别位于所述第一显示区10的两侧。所述第三段323将所述第一段321和所述第二段322连接。第三段323的设置方式可有如下两种。
第一种方式中，参见图4，所述第三段323位于所述第一显示区10中。
可选地，所述第三段323的透光率可大于或等于70％。可选地，第三段323的透光率可大于或等于90％，例如该第三段323的透光率可以为90％、95％等。如此设置可使得第一显示区10的透光率较大，进而使得第一显示区10的透光率满足其下方设置的感光器件的采光需求。
所述第三段323的材料可包括氧化铟锡、氧化铟锌、掺杂银的氧化铟锡及者掺杂银的氧化铟锌中的至少一种。可选地，制备第三段323的材料采用掺杂银的氧化铟锡或者掺杂银的氧化铟锌，以在保证第一显示区10的高透光率的基础上，减小第三段323的电阻。
可选地，所述第一段321与所述第二段322可设置在同一层，也即是，第一段321与第二段322在同一工艺步骤中形成，且所述第一段321与所述第三段323位于不同层。所述第三段323与所述第一段321之间设置有绝缘层。所述绝缘层上设置有多个第二通孔，所述第一段321和所述第二段322分别通过对应的第二通孔与所述第三段323连接。可以理解，在将绝缘层两侧的其他导电元件之间通孔连接时，例如此处的第一段321和第二段322分别通过第二通孔与第三段323连接，均可通过与图7B所示相同或相似的结构实现。
可选地，所述第三段323与所述第一电极111可设置在同一层。所述第一段321、所述第二段322可分别与所述电源线位于同一层。如此，第三段323与第一电极111在同一工艺步骤中形成，第一段321、所述第二段322及所述电源线位于第二显示区20的部分可在同一工艺步骤中形成，从而可降低显示基板的制备工艺的复杂度，简化制备流程。在该实施例中，第一段321与第三段323之间的绝缘层为平坦化层46。
参见图8，所述第三段323可围绕部分所述第一电极111设置。所述第三段323包括顺次连接的第一子段3234、第二子段3235和第三子段3236。所述第二子段3235沿所述第一方向延伸。所述第一子段3234和所述第三子段3236沿所述第二方向延伸。所述第一子段3234与所述第一段321连接。所述第三子段3236与所述第二段322连接。如此设置，第一电极111与第三段323同层设置时，由于第三段323环绕第一电极111设置，则第三段323对第一电极111的位置及大小的影响较小。
所述第一类数据线31、所述第二类数据线32及所述电源线可均位于所述衬底410上方。所述第一电极111在所述衬底410上的投影的至少一部分落在所述电源线位于所述第一显示区10的部分16在所述衬底410上的投影内。如此设置，电源线位于第一显示区10的部分 16可屏蔽第一电极111与位于电源线沿显示基板100的厚度方向的下方的信号线(例如扫描线)之间的电场，避免信号线接收到的信号不稳定，提高第一子像素11接收的信号的稳定性，从而改善第一显示区10的显示效果。
所述像素电路22中的第二晶体管25的漏极252与所述第一段321、所述第二段322可在同一工艺步骤中形成。如此设置，可简化显示基板的制备工艺流程，降低制备工艺的复杂度。
可选地，参见图14，第一电极111与第一类数据线31的第五段312位于同一层。电源线位于第一显示区10的部分16、第二类数据线31的第三段323以及电容的上极板152位于同一层，且与所述第一电极111及所述第五段312位于不同层。第二类数据线31的第三段323可位于电源线位于第一显示区10的部分16与电容的上极板152之间。其中，电源线位于第一显示区10的部分16的面积可大于上极板152的面积，上极板152的面积可大于第二类数据线31的第三段323的面积。
在垂直于第一类数据线31的延伸方向上，电源线位于第一显示区10的部分16与第三段323之间的距离可连续变化或间断变化，第三段323与上极板152之间的距离可连续变化或间断变化。如此设置，电源线位于第一显示区10的部分16与第三段323、以及第三段323与上极板152产生的衍射条纹的位置不同，不同位置处的衍射效应相互抵消，从而可以有效减弱衍射效应，进而确保设置在第一显示区10下方的摄像头拍摄得到的图形具有较高的清晰度。
其中，第二类数据线31的第三段323、第三段323及上极板152的形状可呈长条形、波浪形、葫芦形、哑铃型等。
在另一个实施例中，所述第一段321、所述第二段322及所述第三段323位于同一层，所述第一段321和所述第二段322分别与所述第三段323搭接。如此设置，无需在绝缘层上设置通孔来实现第一段321与第三段323、以及第三段323与第二段322的连接，简化了第二类数据线32的制备工艺。
第三段323与电源线位于第一显示区10中的部分16可设置在同一层，也即是，第三段323与电源线位于第一显示区10中的部分在同一工艺步骤中形成。
所述第二子像素21的像素电路22中第二晶体管25的漏极251可与所述第一段321及所述第二段322在同一工艺步骤中形成。如此设置，可进一步简化显示基板100的制备工艺流程。
第二种方式中，参见图6，所述第二类数据线32的第三段323围绕部分所述第一显示区10。第三段323围绕第一显示区10设置，相对于将第三段323设置在第一显示区10中，可降低第一显示区10的结构复杂度，有助于提高第一显示区10的透光率，并可降低由于第一显示区10的结构复杂导致外部光线入射第一显示区10时产生的衍射。
所述第三段323可包括顺次连接的第四子段3231、第五子段3232和第六子段3233。所述第四子段3231和所述第六子段3233沿所述第二方向延伸。所述第五子段3232沿所述第一方向延伸。所述第四子段3231与所述第一段321连接。所述第六子段3233与所述第三段323连接。
所述第一段321、所述第二段322和所述第三段323可位于同一层。如此设置，所述第一段321、所述第二段322和所述第三段323可在同一工艺步骤中形成，可简化显示基板100的制备工艺流程。
所述第二子像素21的像素电路22的第二晶体管25的漏极252、源极251与所述第一段321、所述第二段322及所述第三段323可在同一工艺步骤中形成。如此设置，通过同一工艺步骤即可制备得到第二晶体管25的漏极252、源极251、第一段321、第二段322和第三段323，可进一步简化显示基板100的制备工艺流程。
所述第一类数据线31、所述第二类数据线32及所述电源线可位于所述衬底410上方。所述第一电极111在所述衬底410上的投影至少部分落在所述电源线位于所述第一显示区10的部分16在所述衬底410上的投影内。如此设置，电源线位于第一显示区10的部分16可屏蔽第一电极111与位于电源线沿显示基板100的厚度方向的下方的信号线(例如扫描线)之间的电场，避免信号线接收到的信号不稳定，提高第一子像素接收的信号的稳定性，从而改善第一显示区10的显示效果。
在一个实施中，再次参见图6，显示基板100的显示区还可包括位于第一显示区10与第二显示区20之间的第三显示区30。第二类数据线32的第三段323可设置在所述第三显示区30内。
可选地，第三显示区30中可不设置子像素，在显示时，第三显示区30显示黑色图像，也即是第三显示区30呈黑色环状。在其他实施例中，第三显示区30内也可设置子像素。
可选地，靠近第三显示区30的第一子像素11的像素电路12可设置在第三显示区30中。如此设置，可进一步降低第一显示区10的结构复杂度，降低衍射，提高第一显示区10的透光率。
可选地，参见图4，所述第一类数据线31与所述第二类数据线32交替排布。图4中仅以相邻两个第一类数据线31之间设置有一个第二类数据线32为例进行示意。在其他实施例中，相邻两个第一类数据线31之间也可设置两个或者更多个第二类数据线32；或者，相邻两个第二类数据线32之间设置两个或者更多个第一类数据线31。
在另一个实施例中，参见图6，所述第二类数据线32分布在多个第一类数据线31整体的两侧。且第一类数据线31的数量为两个以上时，两个以上第一类数据线31相邻设置。位于所述第一类数据线32同一侧的第二类数据线32的数量为两个以上时，位于第一类数据线32同一侧的两个以上的第二类数据线32相邻设置。如此更便于将第二类数据线32的第三段323设置在第二显示区20内，工艺更容易实现。
可选地，参见图3和图5，显示基板100的显示区中的多个像素组还可包括第五类像素组103。第五类像素组103包括多个第二子像素21。同一第五像素组103的多个第二子像素21位于第一显示区10在第二方向上的同一侧，且多个第二子像素21的多个第二子像素21沿第一方向间隔排布。参见图4，显示基板100内还可设有第三类数据线33，同一第五类像素组103中的多个第二子像素21对应的像素电路22连接至同一第三类数据线33。
可选地，再次参见图3，显示基板100的显示区内的子像素还可被划分为第三类像素组201、第四类像素组202和第六类像素组203。所述第三类像素组201、所述第四类像素组202和所述第六类像素组203沿所述第一方向排布。所述第三类像素组201包括多个第一子像素11和多个第二子像素21。所述第四类像素组202仅包括多个所述第二子像素21。所述第三类像素组201及所述第四类像素组202中的多个子像素均沿所述第二方向间隔排布。
可以理解，第一类像素组101、第二类像素组102和第五类像素组103，以一种方式，例如在第二方向上划分多个子像素。第三类像素组201、第四类像素组202和第六类像素组203，以另一种方式，例如在第一方向上再次划分这些子像素。因此，同一子像素可以既属于第一 类像素组101、第二类像素组102和第五类像素组103中的一个组，又属于第三类像素组201、第四类像素组202和第六类像素组203中的一个组。然而，同一子像素不能同时属于第一类像素组101、第二类像素组102和第五类像素组103中的多个组，也不能同时属于第三类像素组201、第四类像素组202和第六类像素组203中的多个组。
第一子像素11对应的像素电路12及第二子像素21对应的像素电路22为3T1C电路、或3T2C电路、或7T1C电路、或7T2C电路时，且显示区的发光控制线为单边驱动时，参见图9，显示基板100的显示区内还设置有第一类发光控制线41和第二类发光控制线42。每一所述第三类像素组201中各第一子像素11的像素电路21和各第二子像素21的像素电路22连接至同一所述第一类发光控制线41。每一所述第四类像素组202中各第二子像素21的像素电路22连接至同一第二类发光控制线42。所述第一类发光控制线41和所述第二类发光控制线42用于为子像素提供发光控制信号。由于同一第三类像素组201中的第一子像素11的像素电路12和第二子像素21的像素电路22连接至同一第一类发光控制线41，则第三类像素组201中的第一子像素11和第二子像素21可由同一第一类发光控制线41驱动，从而可降低显示基板100的显示区内的布线复杂度，同时可使第一显示区10和第二显示区20的显示效果更一致，有利于提升用户的使用体验。
可选地，再次参见图3，每一所述第三类像素组201中的第二子像素21排布在沿所述第二方向位于所述第一显示区10两侧的区域，和/或，所述第四类像素组202中的第二子像素21排布在沿所述第二方向位于所述第一显示区10两侧的区域。所述第四类像素组202中的第二子像素21排布在沿所述第二方向位于所述第一显示区10两侧的区域时，所述第二类发光控制线42可包括第十段421、第十一段422和第十二段423。所述第十段421和所述第十一段422位于所述第二显示区20内且位于所述第一显示区10两侧。所述第十二段423将所述第十段421和所述第十一段422连接。
所述第十段421、所述第十一段422与所述第十二段423可位于同一层，所述第十二段423可分别与所述第十段421及所述第十一段422搭接。如此设置，无需在绝缘层上设置通孔来实现第十段421与第十二段423、以及第十一段422与第十二段423的连接，简化了第二类发光控制线42的制备工艺。
可选地，所述第十二段423可位于所述第一显示区10内，所述第十二段423的透光率大于或等于70％。可选地，第十二段423的透光率可大于或等于90％，例如该第十二段423的透光率可以为90％、95％等。如此设置可使得第一显示区10的透光率较大，进而使得第一显示区10的透光率满足其下方设置的感光器件的采光需求。
所述第十二段423的材料可包括氧化铟锡、氧化铟锌、掺杂银的氧化铟锡及者掺杂银的氧化铟锌中的至少一种。可选地，制备第十二段423的材料采用掺杂银的氧化铟锡或者掺杂银的氧化铟锌，以在保证第一显示区10的高透光率的基础上，减小第十二段423的电阻。
在另一实施例中，所述第十二段423可环绕部分所述第一显示区10。将第十二段423环绕第一显示区10设置，相对于将第十二段423设置在第一显示区10中，可降低第一显示区10的结构复杂度，有助于提高第一显示区10的透光率，并可降低由于第一显示区10的结构复杂导致外部光线入射第一显示区10时产生的衍射。
可选地，第十二段423可设置在第三显示区30中。
可选地，参见图3，第六类像素组203可包括多个第二子像素21。第六类像素组203的多个第二子像素21分布在沿第一方向位于第一显示区10的侧部的区域，且多个第二子像素 21的多个第二子像素21沿第二方向间隔排布。显示基板100内还可设有第三类发光控制线43，同一第六类像素组203中的多个第二子像素21对应的像素电路22连接至同一第三类发光控制线43。
可选地，显示区的扫描线为单边驱动时，参见图10，所述显示区内还可设置有第一类扫描线51和第二类扫描线52。每一第三类像素组201中各第一子像素11的像素电路12和各第二子像素21的像素电路22连接至同一第一类扫描线51。每一第四类像素组202中各第二子像素21的像素电路22连接至同一第二类扫描线52。所述第一类扫描线51和所述第二类扫描线52用于为子像素提供扫描信号。由于同一第三类像素组201中的第一子像素11的像素电路12和第二子像素21的像素电路22连接至同一第一类扫描线51，则第三类像素组201中的第一子像素11和第二子像素21可由同一第一类扫描线51驱动，从而可降低显示基板100的显示区内的布线复杂度，同时可使第一显示区10和第二显示区20的显示效果更一致，有利于提升用户的使用体验。
可选地，再次参见图3，每一所述第三类像素组201中的第二子像素21排布在沿所述第二方向位于所述第一显示区10两侧的区域，和/或，所述第四类像素组202中的第二子像素21排布在沿所述第二方向位于所述第一显示区10两侧的区域。参见图10，所述第四类像素组202中的第二子像素21排布在沿所述第二方向位于所述第一显示区10两侧的区域时，所述第二类扫描线52可包括第七段521、第八段522和第九段523。所述第七段521和所述第八段522位于所述第二显示区20内且位于所述第一显示区10两侧。所述第九段523将所述第七段521和所述第八段522连接。
所述第七段521、所述第八段522和所述第九段523可位于同一层，所述第九段523可分别与所述第七段521及所述第八段522搭接。如此设置，无需在绝缘层上设置通孔来实现第七段521与第九段523、以及第八段522与第九段523的连接，简化了第二类扫描线52的制备工艺。
可选地，所述第九段523可位于所述第一显示区10内，所述第九段523的透光率大于或等于70％。可选地，第九段523的透光率可大于或等于90％，例如该第九段523的透光率可以为90％、95％等。如此设置可使得第一显示区10的透光率较大，进而使得第一显示区10的透光率满足其下方设置的感光器件的采光需求。
所述第九段523的材料可包括氧化铟锡、氧化铟锌、掺杂银的氧化铟锡及者掺杂银的氧化铟锌中的至少一种。可选地，制备第九段523的材料采用掺杂银的氧化铟锡或者掺杂银的氧化铟锌，以在保证第一显示区10的高透光率的基础上，减小第九段523的电阻。
在另一实施例中，所述第九段523可环绕部分所述第一显示区10。将第九段523环绕第一显示区10设置，相对于将第九段523设置在第一显示区10中，可降低第一显示区10的结构复杂度，有助于提高第一显示区10的透光率，并可降低由于第一显示区10的结构复杂导致外部光线入射第一显示区10时产生的衍射。
可选地，第九段523可设置在第三显示区30中。
可选地，第六类像素组203包括多个第二子像素21。第六类像素组203的多个第二子像素21分布在沿第一方向位于第一显示区10的一侧，且多个第二子像素21的多个第二子像素21沿第二方向间隔排布。显示基板100内还可设有第三类扫描线53，同一第六类像素组203中的多个第二子像素21对应的像素电路22连接至同一第三类扫描线53。
可选地，每一所述第一子像素11的第一电极111可包括至少一个第一电极块，发光结构 包括对应设置在每一第一电极块上的发光结构块。
可选地，参见图11至图13，所述第一电极111包括两个或两个以上的第一电极块1111，且两个或两个以上的第一电极块1111沿第一方向间隔排布。该第一电极111还包括设置在相邻两个第一电极块1111之间的连接部1112，相邻的两个第一电极块1111通过对应的连接部1112电连接。如此设置，第一电极111中的第一电极块1111可由一个数据线或扫描线提供信号，可减小第一显示区内的走线的复杂度，能够有效改善光线透射时第一显示区的走线复杂而导致的衍射叠加现象，进而提升设置在第一显示区的背光面设置的摄像头拍摄的图像质量，避免出现图像失真缺陷。并且，同一第一电极111中的多个第一电极块1111电性连接，从而可控制同一第一电极111的多个第一电极块1111上对应设置的发光结构块同时发光或同时关闭，可简化对第一显示区10的控制。
可选地，同一第一电极111的第一电极块1111及连接部1112设置在同一层。如此设置，同一第一电极111的第一电极块1111及连接部1112可在同一工艺步骤中形成，减小制备工艺的复杂度。
可选地，所述连接部1112在垂直于其延伸方向上的尺寸大于3μm，且小于所述第一电极块1111的最大尺寸的二分之一。通过设置连接部1112在垂直于其延伸方向的尺寸大于3μm，可使得连接部1112的电阻较小；通过设置连接部1112的尺寸小于第一电极块1111的最大尺寸的二分之一，可使得连接部1112的设置对第一电极块1111的尺寸影响较小，避免连接部1112的尺寸较大导致第一电极块1111的尺寸减小，而导致第一显示区10的有效发光面积减小。
可选地，所述第一电极111的第一电极块1111在所述显示基板100的衬底410上的投影由一个第一图形单元或者多个第一图形单元组成。其中，所述第一图形单元可包括圆形、椭圆形、哑铃形、葫芦形或矩形。
图11中所示的第一显示区10的第一电极111包括六个第一电极块1111，每一第一电极块1111在衬底上的投影由一个第一图形单元组成，该第一图形单元为矩形。图12中所示的第一显示区10中的第一电极111包括五个第一电极块1111，每一第一电极块1111在衬底上的投影由一个第一图形单元组成，该第一图形单元为圆形。图13中所示的第一显示区10中的第一电极111包括两个第一电极块1111，该第一电极块1111在衬底上的投影由一个第一图形单元组成，该图形单元为哑铃形。所述第一图形单元为圆形、椭圆形、哑铃形或葫芦形，可改变衍射产生的周期性结构，即改变了衍射场的分布，从而减弱外部入射光通过时差生的衍射效应。并且，第一图像单元为上述形状时，第一电极111在第一方向上的尺寸连续变化或者间断变化，则在第二方向上相邻的两个第一电极111的间距在第一方向上连续变化或者间断变化，从而相邻的两个第一电极111产生衍射的位置不同，不同位置处的衍射效应相互抵消，从而可以有效减弱衍射效应，进而确保第一显示区10下方设置的摄像头拍照得到的图像具有较高的清晰度。
可选地，参见图11和图12，在所述第一方向上，同一第一电极111的多个第一电极块1111中，相邻的两个第一电极块1111错位排布。如此设置可进一步减弱外部入射的光线通过第一显示区10时产生的衍射效应。
可选地，同一第一电极111的多个第一电极块1111中，间隔一个第一电极块1111设置的两个第一电极块1111沿所述第二方向的中轴线重合。如此设置可使第一电极块1111的排布更规则，从而对应设置在多个第一电极块1111上方的发光结构块的排布更规则，进而制备 发光结构块采用的掩模板的开口排布比较规则。并且，在蒸镀包括第一显示区10和第二显示区20的显示基板的发光结构块时，可采用同一掩膜板在同一蒸镀工艺中制作，由于掩膜板上的图形较均匀，也减少了张网褶皱。
可选地，对应设置在第一电极块上的发光结构块在所述衬底上的投影由一个第二图形单元或者多个第二图形单元组成，所述第二图形单元与所述第一图形单元相同或不同。可选地，第一图形单元与第二图像单元不同，则所述第一电极块1111上对应设置的发光结构块在所述衬底上的投影与该第一电极块在所述衬底上的投影不同，以进一步减弱光线通过第一显示区10时产生的衍射效应。
所述第二图形单元可包括圆形、椭圆形、哑铃形、葫芦形或矩形。
可选地，所述第一类数据线31位于所述第一显示区10的部分、所述第一电极和/或所述第二电极的透光率大于或等于70％。可选地，第一类数据线31位于所述第一显示区10的部分、第一电极111和/或第二电极的透光率可大于或等于90％，例如透光率可以为90％、95％等。如此设置可使得第一显示区10的透光率较大，进而使得第一显示区10的透光率满足其下方设置的感光器件的采光需求。
第一类数据线31位于所述第一显示区10的部分、所述第一电极111和/或所述第二电极的材料可包括氧化铟锡、氧化铟锌、掺杂银的氧化铟锡及者掺杂银的氧化铟锌中的至少一种。可选地，制备第一类数据线31位于所述第一显示区10的部分、所述第一电极111和/或所述第二电极的透明材料采用掺杂银的氧化铟锡或者掺杂银的氧化铟锌，以在保证第一显示区高透光率的基础上，减小第一类数据线31位于第一显示区10的部分、第一电极和/或第二电极的电阻。
本申请实施例提供的显示基板100的第一显示区10可呈水滴形、圆形、矩形、半圆形、半椭圆形或椭圆形等形状。但不限于此，也可根据实际情况使第一显示区10为其他形状。
可选地，第一方向与第二方向可互相垂直。其中，第一方向可为列方向，第二方向可为行方向；或者，第一方向可为行方向，第二方向可为列方向。图中仅以第一方向为列方向，第二方向为行方向为例进行说明，其他情况不再进行图示。
本申请实施例还提供了一种显示面板，显示面板包括上述的显示基板100及封装层。封装层设置在显示基板100的背离其衬底的一侧。
可选地，第一显示区10至少部分被第二显示区20包围。图1所示的第一显示区10部分被第二显示区20包围。在其他实施例中，第一显示区10也可全部被第二显示区20包围。
可选地，封装层可包括偏光片，偏光片至少覆盖第二显示区20。进一步地，偏光片未覆盖第一显示区10，第一显示区10下方可设置透过第一显示区10发射或者采集光线的感光器件。偏光片可消散显示面板表面的反射光，改善用户的使用体验。第一显示区10不设置偏光片，可提高第一显示区10的透光率，保证第一显示区10下方设置的感光器件的正常工作。
本申请实施例提供的显示面板，由于第一显示区10的透光率大于第二显示区20的透光率，则可将感光器件设置在第一显示区10下方，在保证感光器件正常工作的前提下实现显示基板100的全面屏显示。由于同一第一类像素组101中的第一子像素11的像素电路12和第二子像素21的像素电路22连接至同一第一类数据线31，则第一类像素组101中的第一子像素11和第二子像素21可由同一第一类数据线31驱动，从而可降低显示基板100的显示区内的布线复杂度，同时可使第一显示区10和第二显示区20的显示效果更一致，有利于提升用户的使用体验。由于第一类数据线31位于所述第一显示区10的部分例如第五段312与所述 第一电极111设置在同一层，所述电源线位于所述第一显示区10的部分16设置在所述第一类数据线31位于第一显示区的部分下方，则电源线位于第一显示区10的部分16可降低第一类数据线31位于第一显示区10的部分与第一显示区中位于电源线下方的其他信号线(例如栅线)之间的信号干扰，提高第一类数据线及第一显示区中位于电源线下方的其他信号线接收到的信号的稳定性，进而提高显示基板的显示效果。
本申请实施例还提供了一种显示装置，显示装置包括设备本体及上述的显示面板。设备本体具有器件区，显示面板覆盖在设备本体上。其中，器件区位于第一显示区下方，且器件区中设置有透过第一显示区进行光线采集的感光器件。
其中，感光器件可包括摄像头和/或光线感应器。器件区中还可设置除感光器件的其他器件，例如陀螺仪或听筒等器件。器件区可以是开槽区，显示面板的第一显示区可对应于开槽区贴合设置，以使得感光器件能够透过该第一显示区进行发射或者采集光线。
上述显示装置可以为手机、平板、掌上电脑、ipod等数码设备。
本申请实施例提供的显示装置，由于第一显示区10的透光率大于第二显示区20的透光率，则可将感光器件设置在第一显示区10下方，在保证感光器件正常工作的前提下实现显示基板100的全面屏显示。由于同一第一类像素组101中的第一子像素11的像素电路12和第二子像素21的像素电路22连接至同一第一类数据线31，则第一类像素组101中的第一子像素11和第二子像素21可由同一第一类数据线31驱动，从而可降低显示基板100的显示区内的布线复杂度，同时可使第一显示区10和第二显示区20的显示效果更一致，有利于提升用户的使用体验。由于第一类数据线31位于所述第一显示区10的部分311与所述第一电极111设置在同一层，所述电源线位于所述第一显示区10的部分16设置在所述第一类数据线31位于第一显示区的部分下方，则电源线位于第一显示区10的部分可降低第一类数据线31位于第一显示区10的部分与第一显示区中位于电源线下方的其他信号线(例如栅线)之间的信号干扰，提高第一类数据线及第一显示区中位于电源线下方的其他信号线接收到的信号的稳定性，进而提高显示基板的显示效果。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种显示基板，包括显示区，所述显示区包括第一显示区和第二显示区，所述第一显示区的透光率大于所述第二显示区的透光率；
    所述显示区包括多个子像素，所述多个子像素被划分为沿第二方向排布的多个像素组，所述多个像素组包括多个第一类像素组和多个第二类像素组；
    所述多个子像素包括设置在所述第一显示区内的多个第一子像素和设置在所述第二显示区内的多个第二子像素，所述多个第一子像素的分布密度小于所述多个第二子像素的分布密度；
    每一所述第一类像素组包括所述多个第一子像素中沿第一方向排布的所述多个第一子像素中的一些和所述所述多个第二子像素中沿第一方向排布的所述多个第二子像素中的一些，每一所述第二类像素组包括沿所述第一方向排布的所述多个第二子像素中的另一些，每一所述第一类像素组和每一所述第二类像素组中的一者或两者的所述第二子像素排布在沿第一方向位于所述第一显示区两侧的区域；
    所述显示区包括多个第一类数据线、多个第二类数据线、电源线以及与所述多个子像素一一对应的多个像素电路，同一第一类像素组中各第一子像素和各第二子像素的像素电路连接至同一第一类数据线，同一第二类像素组中的各第二子像素的像素电路连接至同一第二类数据线；
    所述电源线位于所述第一显示区的部分设置在至少一第一类数据线位于所述第一显示区的部分的沿所述显示基板的厚度方向的下方。
  2. 根据权利要求1所述的显示基板，其中，每一所述第一子像素包括第一电极、位于所述第一电极上的第一发光结构及位于所述第一发光结构上的第二电极，每一所述多个第一类数据线位于所述第一显示区的部分与所述第一电极设置在同一层。
  3. 根据权利要求1所述的显示基板，其中，所述至少一个第一类数据线位于所述第一显示区的部分与所述至少一个第一类数据线位于所述第二显示区的部分位于不同层；所述显示基板还包括绝缘层；所述至少一个第一类数据线位于所述第一显示区的部分与所述至少一个第一类数据线位于所述第二显示区的部分设置在所述绝缘层相对的两个表面，并通过所述绝缘层上设置的第一通孔连接。
  4. 根据权利要求1所述的显示基板，其中，所述多个第一类数据线与所述多个第二类数据线交替排布；或者，所述多个第二类数据线分布在所述多个第一类数据线整体的两侧。
  5. 根据权利要求1所述的显示基板，其中，每一所述多个第一子像素的像素电路包括第一电容，所述第一电容包括相对设置的下极板和上极板，所述上极板为所述电源线位于所述第一显示区的所述部分。
  6. 根据权利要求1所述的显示基板，其中，所述多个沿第二方向排布的像素组还包括第五类像素组，所述第五类像素组仅包括所述多个第二子像素中的又一些，同一第五类像素组中的所述第二子像素均位于所述第一显示区沿所述第二方向的同一侧；
    所述显示区还包括多个第三类数据线，同一第五类像素组中各所述第二子像素的像素电路连接至同一第三类数据线。
  7. 根据权利要求1所述的显示基板，其中，所述每一第二类像素组的所述第二子像素排布在沿所述第一方向位于所述第一显示区两侧的区域，所述第二类数据线包括第一段、第二 段及第三段，所述第一段和所述第二段在所述第一方向上分别位于所述第一显示区的两侧，所述第三段连接在所述第一段和所述第二段之间，所述第三段位于所述第一显示区。
  8. 根据权利要求7所述的显示基板，其中，所述第三段的透光率大于或等于70％。
  9. 根据权利要求7所述的显示基板，其中，所述第三段的材料包括氧化铟锡、氧化铟锌、掺杂银的氧化铟锡及者掺杂银的氧化铟锌中的至少一种。
  10. 根据权利要求7所述的显示基板，其中，所述第一段与所述第二段设置在同一层，所述第一段与所述第三段位于不同层，所述显示基板还包括沿所述显示基板的厚度方向设置在所述第三段与所述第一段之间的绝缘层，所述绝缘层上设置有第二通孔，所述第一段和所述第二段分别通过所述第二通孔与所述第三段连接。
  11. 根据权利要求10所述的显示基板，其中，每一所述第一子像素包括第一电极、位于所述第一电极上的第一发光结构及位于所述第一发光结构上的第二电极；所述第三段与所述第一电极设置在同一层，所述第一段和所述第二段分别与所述电源线设置在同一层。
  12. 根据权利要求2所述的显示基板，其中，所述显示基板还包括衬底，所述第一电极、所述多个第一类数据线、所述多个第二类数据线及所述电源线位于所述衬底上方，所述第一电极在所述衬底上的投影的至少一部分落在所述电源线位于所述第一显示区的部分在所述衬底上的投影内。
  13. 根据权利要求1所述的显示基板，其中，所述显示区还包括位于所述第一显示区和所述第二显示区之间的第三显示区，所述第三显示区内未设置子像素；
    所述第二类像素组的所述第二子像素排布在沿所述第一方向位于所述第一显示区两侧的区域，所述第二类数据线包括第一段、第二段及第三段，所述第一段和所述第二段在所述第一方向上分别位于所述第一显示区的两侧，所述第三段连接在所述第一段和所述第二段之间，所述第三段设置在所述第三显示区内；所述第三段包括顺次连接的第四子段、第五子段和第六子段，所述第四子段和所述第六子段沿所述第二方向延伸，所述第五子段沿所述第一方向延伸，所述第四子段与所述第一段连接，所述第六子段与所述第三段连接。
  14. 根据权利要求1所述的显示基板，其中，所述多个子像素还被划分为沿第一方向排布的多个像素组，所述沿第一方向排布的多个像素组包括多个第三类像素组和多个第四类像素组；
    每一第三类像素组包括沿所述第二方向排布的所述多个第一子像素中的一些和所述多个第二子像素中的一些，每一第四类像素组仅包括沿所述第二方向排布的所述多个所述第二子像素中的另一些，所述每一第三类像素组和所述每一第四类像素组中的一者或两者的所述第二子像素排布在沿所述第二方向位于所述第一显示区两侧的区域；
    所述显示区还包括多个第一类发光控制线和多个第二类发光控制线，同一第三类像素组中各所述第一子像素和各所述第二子像素的像素电路连接至同一第一类发光控制线，同一第四类像素组中各所述第二子像素的像素电路连接至同一第二类发光控制线；所述第一类发光控制线和所述第二类发光控制线用于为所述多个子像素提供发光控制信号。
  15. 根据权利要求14所述的显示基板，其中，所述每一第四类像素组中的所述第二子像素排布在沿所述第二方向位于所述第一显示区两侧的区域，所述第二类发光控制线包括第十段、第十一段和第十二段，所述第十段和所述第十一段位于所述第二显示区内且在所述第二方向上分别位于所述第一显示区两侧，所述第十二段连接在所述第十段和所述第十一段之间，所述第十二段位于所述第一显示区。
  16. 根据权利要求1所述的显示基板，其中，所述多个子像素还被划分为沿第一方向排布的多个像素组，所述沿第一方向排布的多个像素组包括多个第三类像素组和多个第四类像素组；
    每一所述第三类像素组包括沿所述第二方向排布的所述多个第一子像素中的一些和所述多个第二子像素中的一些，每一第四类像素组仅包括沿所述第二方向排布的所述多个第二子像素中的另一些，所述每一第三类像素组及所述每一第四类像素组中的一者或两者的所述第二子像素排布在沿所述第二方向位于所述第一显示区两侧的区域；
    所述显示区还包括多个第一类扫描线和多个第二类扫描线，同一第三类像素组中各第一子像素和各第二子像素的像素电路连接至同一第一类扫描线，同一第四类像素组中各第二子像素的像素电路连接至同一第二类扫描线；所述第一类扫描线和所述第二类扫描线用于为子像素提供扫描信号。
  17. 根据权利要求16所述的显示基板，其中，所述每一第四类像素组中的所述第二子像素排布在沿所述第二方向位于所述第一显示区两侧的区域，所述第二类扫描线包括第七段、第八段和第九段，所述第七段和所述第八段位于所述第二显示区内且在所述第二方向上分别位于所述第一显示区两侧，所述第九段连接在所述第七段和所述第八段之间，所述第九段位于所述第一显示区。
  18. 根据权利要求1所述的显示基板，其中，每一所述第一子像素包括第一电极、位于所述第一电极上的发光结构及位于所述发光结构上的第二电极，所述第一电极包括沿所述第一方向相互间隔排布的多个第一电极块和设置在相邻的两个第一电极块之间的连接部，所述多个第一电极块在所述第二方向上错位排布。
  19. 一种显示面板，其中，所述显示面板包括权利要求1所述的显示基板，以及封装所述显示基板的封装结构。
  20. 一种显示装置，其中，包括：
    设备本体，具有器件区；以及
    如权利要求19所述的显示面板，覆盖在所述设备本体上；
    其中，所述器件区位于所述第一显示区下方，且所述器件区中设置有透过所述第一显示区发射或者采集光线的感光器件。
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CN108983872A (zh) * 2018-06-04 2018-12-11 Oppo广东移动通信有限公司 电子装置及其控制方法
CN109599053A (zh) * 2019-01-09 2019-04-09 昆山国显光电有限公司 显示屏及显示装置
CN110767141A (zh) * 2019-05-31 2020-02-07 昆山国显光电有限公司 显示基板、显示面板及显示装置
CN110767662A (zh) * 2019-05-31 2020-02-07 昆山国显光电有限公司 显示基板、显示面板及显示装置

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JP7280432B2 (ja) 2019-12-24 2023-05-23 クンシャン ゴー－ビシオノクス オプト－エレクトロニクス カンパニー リミテッド 透光表示パネル、表示パネル及び表示装置
TWI750940B (zh) * 2020-12-07 2021-12-21 友達光電股份有限公司 顯示裝置

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US11882749B2 (en) 2024-01-23

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