WO2023159512A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023159512A1
WO2023159512A1 PCT/CN2022/078075 CN2022078075W WO2023159512A1 WO 2023159512 A1 WO2023159512 A1 WO 2023159512A1 CN 2022078075 W CN2022078075 W CN 2022078075W WO 2023159512 A1 WO2023159512 A1 WO 2023159512A1
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WO
WIPO (PCT)
Prior art keywords
sub
display
display area
area
region
Prior art date
Application number
PCT/CN2022/078075
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English (en)
French (fr)
Inventor
徐晶晶
方飞
齐璞玉
郑克宁
颜俊
仝可蒙
郝学光
李盼
张玉欣
李春延
王景泉
李新国
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/078075 priority Critical patent/WO2023159512A1/zh
Priority to CN202280000332.2A priority patent/CN117203695A/zh
Publication of WO2023159512A1 publication Critical patent/WO2023159512A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • This article relates to but not limited to the field of display technology, especially a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • LCD Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • the under-screen sensing technology is a brand-new technology proposed to increase the screen-to-body ratio of a display device.
  • An embodiment of the present disclosure provides a display substrate, including:
  • the base substrate includes a display area and a frame area at least on one side of the display area, the display area includes a first display area and a second display area, and the first display area includes a first sub-display area and a first sub-display area area and the first sub-area of the second sub-display area, the second display area includes the second sub-area of the first sub-display area and the second sub-area of the second sub-display area, the first sub-area of the first sub-display area At least partly surrounds the first sub-region of the second sub-display region, the second sub-region of the first sub-display region at least partially surrounds the second sub-region of the second sub-display region, and the first sub-display region first The sub-area and the first sub-display area and the second sub-area form a first sub-display area, and the second sub-display area, the first sub-area and the second sub-display area form a second sub-display area ;
  • a plurality of pixel circuits and a plurality of first light-emitting elements are located in the first sub-display area; the plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits, and the plurality of second pixels The circuits are distributed among the plurality of first pixel circuits; at least one pixel circuit in the plurality of first pixel circuits is connected to at least one light emitting element in the plurality of first light emitting elements;
  • a plurality of second light-emitting elements located in the second sub-display area; at least one pixel circuit in the plurality of second pixel circuits is connected to at least one light-emitting element in the plurality of second light-emitting elements;
  • At least one first data line is located in the first sub-display area;
  • the first data line includes a plurality of interconnected sub-data lines, and each of the sub-data lines extends along the first direction and/or the second direction , the first direction intersects with the second direction;
  • the first data line includes at least one sub-data line connected to the first pixel circuit, and at least another sub-data line connected to the second pixel circuit.
  • the second sub-display area includes a blue light-emitting element, a red light-emitting element, and a green light-emitting element, and the second sub-display area further includes at least one second light-emitting element connected to the blue light-emitting element.
  • a three-pixel circuit, the red light-emitting element is connected to the second pixel circuit located in the first sub-display area;
  • the green light-emitting element is connected to the second pixel circuit located in the first sub-display area; and/or, the second sub-display area further includes at least one fourth pixel circuit connected to the green light-emitting element.
  • the display substrate further includes at least one fifth pixel circuit, a part of the fifth pixel circuit is located in the first sub-display area, and another part of the circuit is located in the second sub-display area .
  • the display substrate further includes a virtual axis between the first sub-display area and the second sub-display area, the virtual axis overlaps with the folding axis, and along the second direction
  • the extended sub-data lines do not overlap with the orthographic projection of the virtual axis on the display substrate.
  • the first data line includes a first sub-data line, a third sub-data line, a data connection line and a second sub-data line connected in sequence;
  • the first sub-display area includes a first part of the first sub-display area and a second part of the first sub-display area located on opposite sides of the second sub-display area in the first direction, and a second part of the second sub-display area located in the second sub-display area.
  • the third part of the first sub-display area on opposite sides;
  • the first sub-data line is located in the first part of the first sub-display area
  • the second sub-data line is located in the second part of the first sub-display area
  • the third sub-data line is located in the first sub-display area.
  • the data connection line is located in the frame area.
  • At least two sub-data lines of the first data line are distributed symmetrically with the center line of the first sub-region of the second sub-display region along the second direction as a symmetry axis.
  • At least one of the first data lines includes a first sub-data line and a second The sub-data line includes a third sub-data line located on the other side of the centerline of the first sub-area of the second sub-display area along the second direction.
  • the first data line overlapping with the centerline of the first sub-area of the second sub-display area along the second direction is located at The first data line overlapping the center line of the first sub-region of the second sub-display region along the second direction is close to one side of the first sub-region of the second sub-display region.
  • At least one of the first data lines includes a part of the sub-data lines located in the first sub-area of the first sub-display area, and includes a part of the sub-data lines located in the second sub-area of the first sub-display area.
  • the display substrate further includes at least one data driving chip, the data driving chip is located in the frame area, and the first sub-area of the second sub-display area is located in the first sub-area of the first sub-display area.
  • the sub-area is far away from the side of the data driving chip, and the second sub-display area is located at the side of the second sub-area of the first sub-display area close to the data driving chip.
  • the display substrate further includes two data driving chips, wherein one of the data driving chips is connected to the data lines of the first display area, and the other of the data driving chips is connected to the The data line connection of the second display area.
  • the first display area and the second display area are distributed symmetrically with the center line of the display substrate along the first direction as a symmetry axis.
  • the first sub-area of the second sub-display area and the second sub-area of the second sub-display area are distributed symmetrically with the center line of the display substrate along the first direction as a symmetry axis, and The first sub-area of the second sub-display area and the second sub-area of the second sub-display area are located between the same plurality of first data lines.
  • the display substrate further includes two data driving chips and a second data line, and the second data line is connected to a column of first pixel circuits, wherein one of the data driving chips is connected to the The first data line is connected, and the other data driving chip is connected to the second data line.
  • the two data driving chips are located on one side of the frame area, or the two data driving chips are located on different sides of the frame area.
  • the first sub-display area includes a base substrate and a driving circuit layer, a light emitting structure layer, An encapsulation layer, a touch structure layer and a color filter layer
  • the second sub-display area includes a base substrate and a light emitting structure layer, an encapsulation layer and a color filter layer sequentially stacked on the base substrate.
  • the color filter layer includes a plurality of color filters of different colors and a black matrix arranged between the plurality of color filters of different colors, and the second sub-display area
  • the thickness of the black matrix along the direction perpendicular to the display substrate is smaller than the thickness of the black matrix of the first sub-display area along the direction perpendicular to the display substrate.
  • the light emitting structure layer includes a pixel definition layer, an anode, a cathode, and an organic light emitting layer, wherein:
  • the pixel definition layer includes a first opening exposing the anode, the black matrix includes a second opening exposing the color filter, and the orthographic projection of the second opening on the base substrate includes the For an orthographic projection of the first opening on the base substrate, the pixel definition layer is made of black material.
  • the touch structure layer includes a plurality of first touch electrodes arranged along a first direction and a plurality of second touch electrodes arranged along a second direction, and the first touch electrodes It includes a plurality of first sub-electrodes connected through a first connection part, the second touch electrode includes a plurality of second sub-electrodes connected through a second connection part, and the second sub-display area is on the base substrate
  • the orthographic projection on the base substrate does not overlap with the orthographic projection of the first connecting portion on the base substrate, and the orthographic projection of the second sub-display area on the base substrate and the second connecting portion The orthographic projections on the substrate substrate do not overlap.
  • An embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.
  • FIG. 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure
  • Fig. 2 is a schematic diagram showing that the substrate shown in Fig. 1 is in a folded state
  • 3A to 3D are partial structural schematic diagrams of the first display area of at least one embodiment of the present disclosure.
  • 3E is another partial structural schematic diagram of the first display area of at least one embodiment of the present disclosure.
  • 4A to 4C are schematic diagrams of start-up voltages of red, green and blue sub-pixels
  • FIG. 4D is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 4E is a working timing diagram of the pixel circuit shown in FIG. 4D;
  • FIG. 5 is a schematic diagram of the arrangement of data lines in the first display area of at least one embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a partial arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 7 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 8 is another schematic diagram of partial arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 9 is another schematic diagram of a partial arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 10 is another schematic diagram of a partial arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 11 is another schematic diagram of a partial arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 12 is another schematic diagram of a partial arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 13 is another schematic diagram of a partial arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure
  • Fig. 14 is another schematic diagram of partial arrangement of data lines of a display substrate in at least one embodiment of the present disclosure.
  • 15 is another schematic diagram of a partial arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure.
  • 16 is another schematic diagram of a partial arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure
  • 17 is a schematic cross-sectional view of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of a touch structure layer of a display substrate according to at least one embodiment of the present disclosure.
  • 19 is another schematic diagram of the touch structure layer of the display substrate according to at least one embodiment of the present disclosure.
  • FIG. 20 is another schematic diagram of the touch structure layer of the display substrate according to at least one embodiment of the present disclosure.
  • 21 is another schematic diagram of the touch structure layer of the display substrate according to at least one embodiment of the present disclosure.
  • 22A is another schematic diagram of the touch structure layer of the display substrate according to at least one embodiment of the present disclosure.
  • FIG. 22B is a schematic diagram of pixel arrangement of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 23 is another schematic diagram of a pixel arrangement of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 24 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the manner and content can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or a connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate, a drain, and a source.
  • a transistor has a channel region between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain and the second electrode may be the source, or the first electrode may be the source and the second electrode may be the drain.
  • the functions of "source” and “drain” may be interchanged. Therefore, in this specification, “source” and “drain” can be interchanged with each other.
  • connection includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° to 100°, and therefore also includes the state of the angle of 85° to 95°.
  • At least one embodiment of the present disclosure provides a display substrate, including:
  • the base substrate includes a first display area and a second display area
  • the first display area includes the first sub-area of the first sub-display area and the first sub-area of the second sub-display area
  • the second display area includes the first sub-display area The second sub-area and the second sub-display area The second sub-area, the first sub-display area The first sub-area at least partially surrounds the second sub-display area The first sub-area, The first sub-display area The second sub-area at least partially surrounds the second sub-area Two sub-display areas
  • the second sub-area, the first sub-display area The first sub-area and the second sub-area of the first sub-display area form the first sub-display area, the second sub-display area The first sub-area and the second sub-display area the second sub-area forms a second sub-display area;
  • a plurality of pixel circuits and a plurality of first light-emitting elements are located in the first sub-display area; the plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits, and the plurality of second pixel circuits are distributed in the plurality of second pixel circuits Between a pixel circuit; at least one pixel circuit in the plurality of first pixel circuits is connected to at least one light-emitting element in the plurality of first light-emitting elements;
  • At least one first data line is located in the first sub-display area; the first data line includes a plurality of interconnected sub-data lines, and each sub-data line extends along the first direction and/or the second direction, and the first direction and the second direction direction crossing;
  • the first data line includes at least one sub-data line connected to the first pixel circuit, and at least another sub-data line connected to the second pixel circuit.
  • the display substrate of this embodiment will be described below through several examples.
  • FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the base substrate of the display substrate includes: a display region and a frame region R3 located at least on one side of the display region.
  • the display area includes: a first display area A and a second display area B, wherein the first display area A includes the first sub-area A-R1 of the first sub-display area and the first sub-area A-R2 of the second sub-display area, The first sub-display area, the first sub-area A-R1 at least partially surrounds the second sub-display area, the first sub-area A-R2; the second display area B includes the first sub-display area, the second sub-area B-R1 and the second sub-area Display area second sub-area B-R2, first sub-display area second sub-area B-R1 at least partially surrounds second sub-display area second sub-area B-R2, first sub-display area first sub-area A-R1
  • the first sub-display area and the second sub-area B-R1 of the first sub-display area form the first sub-display area, the first sub-area A-R2 of the second sub-display area and the second sub-area B-R2 of the
  • first display area A and the second display area B shown in FIG. 1 are respectively located on the left and right sides of the center line of the display area along the second direction D2, and the second sub-display area and the first sub-area shown in FIG. 1 A-R2 and the second sub-region B-R2 of the second sub-display area are respectively located in the middle of the upper part of the first sub-region A-R1 of the first sub-display area and the second sub-region B-R1 of the first sub-display area.
  • the first sub-area A-R1 of the first sub-display area and the second sub-area B-R1 of the first sub-display area respectively have three sides adjacent to the frame area R3, and the first sub-area A-R2 and the second sub-area of the second sub-display area
  • the second sub-region B-R2 of the sub-display region is not adjacent to the frame region R3.
  • the embodiments of the present disclosure are not limited thereto.
  • the first sub-area A-R2 of the second sub-display area and the second sub-area B-R2 of the second sub-display area may respectively have one side adjacent to the border area R3, and the first sub-area A-R2 of the second sub-display area R2 and the second sub-region B-R2 of the second sub-display area can be respectively located at the upper left corner position or the upper right corner position of the first sub-region A-R1 of the first sub-display area and the second sub-region B-R1 of the first sub-display area Wait for other positions.
  • the display area may be a rectangle, for example, a right-angled rectangle, a rounded rectangle, and the like.
  • the shapes of the first sub-region A-R2 of the second sub-display area and the second sub-region B-R2 of the second sub-display area may be the same, for example, the first sub-region of the second sub-display area
  • Both the region A-R2 and the second sub-region B-R2 of the second sub-display region can be in a shape of a circle, a rectangle, an ellipse, and the like.
  • the embodiments of the present disclosure are not limited thereto.
  • the shapes of the first sub-region A-R2 of the second sub-display area and the second sub-region B-R2 of the second sub-display area can also be different.
  • the first sub-region A-R2 of the second sub-display area can be It is circular, and the second sub-region B-R2 of the second sub-display region can be other shapes such as rectangle or ellipse.
  • the first sub-region A-R1 of the first sub-display region and the second sub-region B-R1 of the first sub-display region may be non-light-transmitting display regions, and the first sub-region of the second sub-display region A-R2 and the second sub-display region
  • the second sub-region B-R2 may be a light-transmitting display region. That is, the first sub-area A-R1 of the first sub-display area and the second sub-area B-R1 of the first sub-display area are opaque, and the first sub-area A-R2 of the second sub-display area and the second sub-area of the second sub-display area are opaque.
  • the second sub-region B-R2 can transmit light, the first sub-region A-R1 of the first sub-display region, the second sub-region B-R1 of the first sub-display region, the first sub-region A-R2 and the second sub-display region
  • Both the second sub-region B-R2 of the two sub-display regions have light-emitting units, so that a full-screen display can be realized.
  • the orthographic projection of hardware such as sensors (such as optical sensors, infrared sensors, fingerprint sensors, ultrasonic sensors, etc.) Within the second sub-area B-R2 of the area.
  • the display substrate of this example does not need to be drilled, and can make a true full screen possible under the premise of ensuring the practicability of the display substrate.
  • the display panel may include an axis F, wherein the axis F may extend along the first direction D1, and the axis F may be a virtual line.
  • the first display area A and the second display area B are located on opposite sides of the axis F, respectively.
  • the embodiments of the present disclosure are not limited thereto.
  • the axis F may also extend along the second direction D2.
  • the first direction D1 crosses the second direction D2, for example, the first direction D1 may be perpendicular to the second direction D2.
  • the first direction D1 is parallel to the sub-pixel column direction
  • the second direction D2 is parallel to the sub-pixel row direction.
  • the embodiments of the present disclosure are not limited thereto.
  • the display panel may include a folding shaft, and the folding shaft overlaps the axis F of the display panel to realize a foldable function.
  • the display panel may have a first camera C1 (not shown in the figure), and the first camera C1 overlaps with the first sub-region A-R2 of the second sub-display region.
  • the display panel may have a second camera C2 (not shown in the figure), and the second camera C2 overlaps with the second sub-region B-R2 of the second sub-display region, so that dual cameras can capture images.
  • the embodiments of the present disclosure are not limited thereto.
  • the surfaces of the first display area A and the second display area B are on the same plane, and the first display area A and the second display area B jointly display images.
  • either the first camera C1 or the second camera C2 may collect images, or the first camera C1 and the second camera C2 may simultaneously collect left and right frame images, and the left and right frame images are processed to achieve image enhancement.
  • bending the display panel along the axis F can change the display panel from a flat state (i.e. a non-folded state) to a bent state (i.e. a folded state).
  • the first display area A and the second The display area B is opposite, the first display area A or the second display area B displays images, and the corresponding first camera C1 or second camera C2 is used to capture images.
  • the first camera C1 is used to capture images
  • the first display area A displays the images.
  • the first camera C1 captures a still image
  • the first display area A displays the still image
  • the first display area A displays the image.
  • the camera C1 collects dynamic images, and the first display area A displays the dynamic images.
  • the folding axis of the folding screen is located at the approximate center of the display panel, that is to say, the first display area A and the second display area B are arranged symmetrically about the axis F.
  • the single camera area The camera cannot be set in the center of the entire display panel, but can only be set in the first display area A or the second display area B. Therefore, the image captured by the single camera area will cause image quality degradation due to asymmetry.
  • a dual camera area can be set , so that the problem of image quality degradation caused by the asymmetry of images captured by the cameras in the single camera area can be optimized.
  • images are collected through the dual cameras in the two second sub-display areas, and the images collected by the dual cameras are processed to realize various functions such as depth of field blurring, image quality enhancement, and optical zoom, and optimize graphics collection and display effects.
  • the display substrate may include a plurality of sub-pixels disposed on a base substrate. At least one sub-pixel includes a pixel circuit and a light emitting element.
  • the pixel circuit is configured to drive a light emitting element.
  • the pixel circuit is configured to provide a driving current to drive the light emitting element to emit light.
  • the light-emitting element may be an organic light-emitting diode (OLED), and the light-emitting element emits red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit.
  • OLED organic light-emitting diode
  • the color of light emitted by the light emitting element can be determined according to needs.
  • the light emitting element may include: a first pole (eg, anode), a second pole (eg, cathode), and an organic light emitting layer disposed between the first pole and the second pole. Wherein, the first pole can be connected with the pixel circuit.
  • the embodiments of the present disclosure are not limited thereto.
  • the light emitting element may be a quantum dot light emitting diode (QLED, Quantum Dot Light Emitting Diode), a micro light emitting diode (Micro-LED, Micro Light Emitting Diode), or a miniature diode (Mini-LED).
  • a pixel unit may include three sub-pixels (for example, a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G), and the three sub-pixels may be arranged horizontally, vertically Arranged side by side or by character.
  • one pixel unit may include four sub-pixels (for example, a red sub-pixel R, a blue sub-pixel B, a green sub-pixel G, and a white sub-pixel W, or a red sub-pixel R, a blue sub-pixel Pixel B and two green sub-pixels G), the four sub-pixels can be arranged horizontally, vertically or squarely.
  • the embodiments of the present disclosure are not limited here.
  • FIG. 3A is a schematic diagram of a partial structure of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate includes: a plurality of first pixels located in the first sub-region A-R of the first sub-display region and/or the second sub-region B-R1 of the first sub-display region circuit 10, a plurality of second pixel circuits 20 and a plurality of first light-emitting elements 30, and multiple LEDs located in the first sub-region A-R2 of the second sub-display region and/or the second sub-region B-R2 of the second sub-display region a second light emitting element 40.
  • the plurality of second pixel circuits 20 may be distributed between the plurality of first pixel circuits 10 at intervals, for example, the plurality of first pixel circuits 10 are arranged between two adjacent second pixel circuits 20 in the first direction. At least one first pixel circuit 10 among the plurality of first pixel circuits 10 may be connected to at least one first light emitting element 30 among the plurality of first light emitting elements 30, and at least one first pixel circuit 10 on the base substrate The orthographic projection and the orthographic projection of the at least one first light-emitting element 30 on the base substrate may at least partially overlap.
  • the first pixel circuit 10 can be configured to provide a driving signal to the connected first light emitting element 30 to drive the first light emitting element 30 to emit light.
  • At least one second pixel circuit 20 among the plurality of second pixel circuits 20 may be connected to at least one second light emitting element 40 among the plurality of second light emitting elements 40 through a conductive line L.
  • the second pixel circuit 20 can be configured to provide a driving signal to the connected second light emitting element 40 to drive the second light emitting element 40 to emit light. Since the second light emitting element 40 and the second pixel circuit 20 are located in different regions, there is no overlap between the orthographic projection of at least one second pixel circuit 20 on the base substrate and the orthographic projection of at least one second light emitting element 40 on the base substrate part.
  • the density of the second light-emitting elements 40 in the first sub-region A-R2 of the second sub-display region may be approximately equal to that of the first light-emitting elements 30 in the first sub-region A-R1 of the first sub-display region. Density, the density of the second light-emitting elements 40 in the second sub-region B-R2 of the second sub-display region may be approximately equal to the density of the first light-emitting elements 30 in the second sub-region B-R1 of the first sub-display region.
  • the resolution of the first sub-area A-R2 of the second sub-display area can be approximately the same as the resolution of the first sub-area A-R1 of the first sub-display area, and the resolution of the second sub-area B-R2 of the second sub-display area
  • the resolution may be substantially the same as that of the first sub-display area and the second sub-area B-R1.
  • the embodiments of the present disclosure are not limited thereto.
  • the density of the second light emitting elements 40 may be greater than or less than that of the first light emitting elements 30 .
  • the resolution of the first sub-area A-R2 of the second sub-display area can be greater than or less than the resolution of the first sub-area A-R1 of the first sub-display area, and the resolution of the second sub-area B-R2 of the second sub-display area
  • the resolution may be larger or smaller than that of the second sub-region B-R1 of the first sub-display region.
  • the light emitting area of the second light emitting element 40 may be smaller than the light emitting area of the first light emitting element 30 . That is, the light emitting area of the first light emitting element 30 is larger than the light emitting area of the second light emitting element 40 . Wherein, the light emitting area of the light emitting element may correspond to the area of the opening of the pixel definition layer. In some examples, in the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region, a light-transmitting region is provided between adjacent second light-emitting elements 40 .
  • a plurality of light-transmitting regions are connected to each other to form a continuous light-transmitting region separated by a plurality of second light-emitting elements 40 .
  • the conductive line L can be made of transparent conductive material to increase the light transmittance of the light-transmitting area as much as possible.
  • the first pixel circuit 10 in the first sub-region A-R1 of the first sub-display region and the second sub-region B-R1 of the first sub-display region, the first pixel circuit 10 can be reduced in the second direction D2
  • the above dimensions are used to obtain the area where the second pixel circuit 20 is disposed.
  • the size of the first pixel circuit 10 in the second direction D2 may be smaller than the size of the first light emitting element 30 in the second direction D2.
  • the second direction D2 is, for example, the sub-pixel row direction, but not limited thereto.
  • the second direction D2 may be a sub-pixel column direction. This exemplary embodiment is described by taking the second direction D2 as the sub-pixel row direction as an example.
  • the size of the first pixel circuit 10 and the second pixel circuit 20 in the second direction D2 can be the same, and the size of each pixel circuit in the second direction D2 is the same as the size of the first light emitting element 30 in the second direction D2.
  • the dimensions can vary by about 4 micrometers ( ⁇ m).
  • the size of each pixel circuit in the first direction D1 is substantially the same as the size of the first light emitting element 30 in the first direction D1.
  • the first direction D1 is perpendicular to the second direction D2.
  • the second pixel circuits 20 not connected to light-emitting elements in the first sub-region A-R1 of the first sub-display region and the second sub-region B-R1 of the first sub-display region may be referred to as dummy ( Dummy) pixel circuit.
  • FIG. 3B to 3D are partial structural schematic diagrams of the first sub-display region (the first sub-region A-R1 of the first sub-display region or the second sub-region B-R1 of the first sub-display region) of at least one embodiment of the present disclosure.
  • FIG. 3B shows the sub-pixels of the first sub-region A-R1 of the first sub-display region or the second sub-region B-R1 of the first sub-display region.
  • FIG. 3C shows a schematic diagram of a partial structure (only including pixel circuits) of the first sub-region A-R1 of the first sub-display region or the second sub-region B-R1 of the first sub-display region in Fig. 3B
  • Fig. 3D shows A schematic diagram of a partial structure (including only light-emitting elements) of the first sub-region A-R1 of the first sub-display region or the second sub-region B-R1 of the first sub-display region in FIG. 3B .
  • the size of the pixel circuit in the second direction D2 is smaller than the size of the light emitting element in the second direction D2, so that the second direction from right to left can be
  • the pixel circuits in the first column and the ninth column are not connected to any first light-emitting element 30, and belong to multi-column pixel circuits, which can be used as the second pixel circuit 20 to connect the first sub-region A-R2 or the second sub-region of the second sub-display area.
  • the second light-emitting element 40 in the second sub-region B-R2 of the display area may only serve as an unused second pixel circuit 20 (ie, a dummy pixel circuit). As shown in FIG.
  • any first light emitting element 30 may be one of four types of light emitting elements including RG1BG2.
  • the first electrode E1 of the first light emitting element 30 may be connected to the first transfer electrode CE1 of the first pixel circuit 10 through the second transfer electrode CE2 .
  • R represents a light-emitting element that emits red light
  • G1 represents a light-emitting element that emits green light
  • B represents a light-emitting element that emits blue light
  • G2 represents a light-emitting element that emits green light.
  • At least one second pixel circuit 20 may have a first via electrode
  • at least one second light emitting element 40 may have a second via electrode.
  • connecting at least one second pixel circuit 20 and at least one second light-emitting element 40 through a conductive line L may include: connecting the conductive line L to the first transfer electrode of at least one second pixel circuit 20 and at least one second light-emitting element respectively. 40 for the second relay electrode.
  • the axes of the first via electrode and the second via electrode in the same row of sub-pixels may be located on a straight line.
  • the embodiments of the present disclosure are not limited thereto.
  • one repeating unit RP includes two green (G) sub-pixels arranged in the first direction D1 and two green (G) sub-pixels arranged at the second Red (R) sub-pixels and blue (B) sub-pixels on both sides in the two directions D2.
  • the red sub-pixel and the green sub-pixel can form a pixel unit, and borrow the blue sub-pixel in another repeating unit adjacent to it to form a virtual pixel for display, wherein the blue sub-pixel and the green sub-pixel can form a pixel unit, and use the red sub-pixel in another repeating unit adjacent to it to form a virtual pixel for display.
  • the embodiments of the present disclosure are not limited thereto.
  • the first Sub-region A-R2 and the second sub-display region second sub-region B-R2 are only provided with light-emitting elements, and will drive the second sub-display region first sub-region A-R2 and the second sub-display region second sub-region B-
  • the pixel circuit of the light-emitting element of R2 is arranged in the first sub-region A-R1 of the first sub-display region and the second sub-region B-R1 of the first sub-display region.
  • the light transmittance of the first sub-area A-R2 of the second sub-display area and the second sub-area B-R2 of the second sub-display area are improved by separately setting the light-emitting element and the pixel circuit.
  • no pixel circuit is provided in the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region.
  • light-emitting elements can be arranged in the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region, and the first sub-region of the second sub-display region can be driven A-R2 and the pixel circuit of the light-emitting element in the second sub-region B-R2 of the second sub-display region.
  • the pixel circuits for driving the light-emitting elements of the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region can be set in the first sub-region A-R2 of the second sub-display region.
  • the first sub-region A-R2 of the second sub-display region and the second sub-display region can use transparent metal, such as ITO wiring.
  • the pixel circuits for driving some of the light-emitting elements in the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region may be arranged in the second sub-display region In the first sub-area A-R2 of the second sub-display area and the second sub-area B-R2 of the second sub-display area, the first sub-area A-R2 of the second sub-display area and the second sub-area B-R2 of the second sub-display area will be driven
  • the pixel circuits of another part of the light-emitting elements are arranged in the first sub-region A-R1 of the first sub-display region and the second sub-region B-R1 of the first sub-display region. At this time, at least part of the external pixel circuits need to be wound with data lines.
  • the second sub-display area includes a blue light-emitting element, a red light-emitting element, and a green light-emitting element, and the second sub-display area further includes at least one first light-emitting element connected to the blue light-emitting element.
  • a three-pixel circuit, the red light-emitting element is connected to the second pixel circuit located in the first sub-display area.
  • the first sub-pixel of the second sub-display area can be driven
  • the pixel circuits of the blue light-emitting elements in the area A-R2 and the second sub-display area B-R2 are arranged in the first sub-area A-R2 of the second sub-display area and the second sub-area B of the second sub-display area -
  • the pixel circuit for driving the red light-emitting elements of the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region is arranged in the first sub-region A of the first sub-display region -R1 and the second sub-region B-R1 of the first sub-display area, like this, can increase the first sub-region A-R2 of the second sub-display
  • the green light-emitting element in the second sub-display area can be connected to the second pixel circuit located in the first sub-display area; and/or, as shown in FIG. 3E , the second sub-display area can also be At least one fourth pixel circuit is included, and the green light-emitting element in the second sub-display area can be connected with the fourth pixel circuit.
  • the pixel circuit for driving the green light-emitting elements of the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region can be set in the first sub-region of the second sub-display region.
  • the green color of the first sub-area A-R2 of the second sub-display area and the second sub-area B-R2 of the second sub-display area can also be driven.
  • the pixel circuits of the light emitting elements are disposed in the first sub-region A-R1 of the first sub-display region and the second sub-region B-R1 of the first sub-display region, which is not limited in the present disclosure.
  • the display substrate may further include at least one fifth pixel circuit, and the fifth pixel circuit has The first sub-part of the second sub-region B-R1 and the second sub-part located in the first sub-region A-R2 of the second sub-display region or the second sub-region B-R2 of the second sub-display region, wherein the first The sub-part and the second sub-part jointly drive the same light-emitting unit (the light-emitting unit may be located in the first sub-region A-R1 of the first sub-display area or in the second sub-region B-R1 of the first sub-display area, or may be located in the second sub-region B-R1 of the first sub-display area.
  • the first sub-region A-R2 of the sub-display region or the second sub-region B-R2 of the second sub-display region emits light.
  • the fifth pixel circuit may be 3T1C, 7T1C, 8T1C, etc., which is not limited in the present disclosure. At this time, at least some signal lines (such as data lines) need to be designed for winding.
  • the pixel circuit of this embodiment (the pixel circuit described here may be any one of the first pixel circuit, the second pixel circuit, the third pixel circuit, the fourth pixel circuit and the fifth pixel circuit) is illustrated below. .
  • FIG. 4D is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 4E is a working timing diagram of the pixel circuit shown in FIG. 4D .
  • the pixel circuits of the first sub-region A-R1 of the first sub-display region and the second sub-region B-R1 of the first sub-display region may both have a 7T1C structure.
  • the embodiments of the present disclosure are not limited thereto.
  • the pixel circuit may include other numbers of transistors and capacitors, such as 5T1C or 6T1C structures.
  • each pixel circuit includes six switching transistors ( T1 , T2 , T4 to T7 ), one driving transistor T3 and one storage capacitor Cst.
  • the six switch transistors are data writing transistor T4, threshold compensation transistor T2, first light emission control transistor T5, second light emission control transistor T6, first reset transistor T1, and second reset transistor T7.
  • the light emitting element EL includes a first pole E1, a second pole E2, and an organic light emitting layer between the first pole E1 and the second pole E2.
  • the first pole E1 may be an anode
  • the second pole E2 may be a cathode.
  • the driving transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield rate of the product.
  • the driving transistor and the six switching transistors may include P-type transistors and N-type transistors.
  • the driving transistor and the six switch transistors may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (LTPO) , Low Temperature Polycrystalline Oxide) display substrate, can take advantage of the advantages of both, can achieve low-frequency drive, can reduce power consumption, and can improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • Low Temperature Polycrystalline Oxide Low Temperature Polycrystalline Oxide
  • the display substrate includes scanning lines GL, data lines DL, first power lines PL1, second power lines PL2, light emission control lines EML, first initial signal lines INIT1, a second initial signal line INIT2, a first reset control line RST1 and a second reset control line RST2.
  • the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit
  • the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit
  • the first voltage signal VDD is greater than The second voltage signal VSS.
  • the scan line GL is configured to provide a scan signal SCAN to the pixel circuit
  • the data line DL is configured to provide a data signal DATA to the pixel circuit
  • the light emission control line EML is configured to provide a light emission control signal EM to the pixel circuit
  • the first reset control line RST1 is configured to provide a light emission control signal EM to the pixel circuit.
  • the pixel circuit provides a first reset control signal RESET1
  • the second reset control line RST2 is configured to provide a scan signal SCAN to the pixel circuit.
  • the second reset control line RST2 may be connected to the scan line GL to be input with the scan signal SCAN.
  • the embodiments of the present disclosure are not limited thereto.
  • the second reset control line RST2 may be input with a second reset control signal RESET2.
  • the first reset control line RST1 can be connected to the scan line GL of the n-1th row of pixel circuits, so as to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1 (n) is the same as the scan signal SCAN(n-1).
  • the first reset control line RST1 connected to the pixel circuit in the nth row and the second reset control line RST2 connected to the pixel circuit in the (n ⁇ 1)th row may have an integral structure. In this way, the signal lines of the display substrate can be reduced, and a narrow frame of the display substrate can be realized.
  • the first initial signal line INIT1 and the second initial signal line INIT2 may provide the same initial signal.
  • the first initial signal line INIT1 connected to the pixel circuits in the nth row and the second initial signal line INIT2 connected to the pixel circuits in the (n ⁇ 1)th row may have an integral structure.
  • the embodiments of the present disclosure are not limited thereto.
  • the driving transistor T3 is electrically connected to the light emitting element EL, and is connected to the scanning signal SCAN, the data signal DATA, the first voltage signal VDD, Under the control of the second voltage signal VSS and other signals, the driving current is output to drive the light emitting element EL to emit light.
  • the gate of the data writing transistor T4 is connected to the scan line GL, the first pole of the data writing transistor T4 is connected to the data line DL, and the second pole of the data writing transistor T4 is connected to the first pole of the driving transistor T3.
  • the gate of the threshold compensation transistor T2 is connected to the scan line GL, the first terminal of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3, and the second terminal of the threshold compensation transistor T2 is connected to the second terminal of the driving transistor T3.
  • the gate of the first light emission control transistor T5 is connected to the light emission control line EML, the first electrode of the first light emission control transistor T5 is connected to the first power line PL1, the second electrode of the first light emission control transistor T5 is connected to the first electrode of the driving transistor T3 One pole connected.
  • the gate of the second light emission control transistor T6 is connected to the light emission control line EML, the first pole of the second light emission control transistor T6 is connected to the second pole of the driving transistor T3, and the second pole of the second light emission control transistor T6 is connected to the light emitting element EL.
  • the first pole E1 is connected.
  • the first reset transistor T1 is connected to the gate of the driving transistor T3, and is configured to reset the gate of the driving transistor T3, and the second reset transistor T7 is connected to the first pole E1 of the light emitting element EL, and is configured to reset the gate of the light emitting element EL.
  • the first electrode E1 is reset.
  • the gate of the first reset transistor T1 is connected to the first reset control line RST1, the first pole of the first reset transistor T1 is connected to the first initial signal line INIT1, the second pole of the first reset transistor T1 is connected to the gate of the driving transistor T3 Pole connected.
  • the gate of the second reset transistor T7 is connected to the second reset control line RST2, the first pole of the second reset transistor T7 is connected to the second initial signal line INIT2, and the second pole of the second reset transistor T7 is connected to the first pole of the light emitting element EL.
  • One pole E1 is connected.
  • a first electrode of the storage capacitor Cst is connected to the gate of the driving transistor T3, and a second electrode of the storage capacitor Cst is connected to the first power line PL1.
  • the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the drive transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light emission control transistor T5, the data writing transistor T4 and the
  • the connection point of the drive transistor T3, the third node N3 is the connection point of the drive transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is the second light emission control transistor T6, the second reset transistor T7 and the light emission control transistor T6.
  • the connection point of the element EL is the connection point of the storage capacitor Cst, the first reset transistor T1, the drive transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light emission control transistor T5, the data writing transistor T4 and the
  • the connection point of the drive transistor T3, the third node N3 is the connection point of the drive transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is the second light emission control transistor T
  • the working process of the pixel circuit shown in FIG. 4D will be described below with reference to FIG. 4E .
  • the description will be made by taking a plurality of transistors included in the pixel circuit as P-type transistors as an example.
  • the working process of the pixel circuit with the first structure includes: a first stage A1 , a second stage A2 and a third stage A3 .
  • the first phase A1 is called the reset phase.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, so that the first reset transistor T1 is turned on, and the initial signal Vinit provided by the first initial signal line INIT1 is provided to the first node N1.
  • a node N1 is initialized to clear the original data voltage in the storage capacitor Cst.
  • the scanning signal SCAN provided by the scanning line GL is a high-level signal
  • the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, so that the data is written into the transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, the second The second light emitting control transistor T6 and the second reset transistor T7 are turned off. At this stage, the light emitting element EL does not emit light.
  • the second phase A2 is called a data writing phase or a threshold compensation phase.
  • the scan signal SCAN provided by the scan line GL is a low level signal
  • the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high level signals
  • the data line DL outputs Data signal DATA.
  • the driving transistor T3 since the second electrode of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on.
  • the scan signal SCAN is a low level signal, which turns on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7.
  • the threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DT is provided to the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2 to the second node N2.
  • a node N2, and charge the difference between the data voltage Vdata output by the data line DT and the threshold voltage of the drive transistor T3 into the storage capacitor Cst, and the voltage of the second electrode of the storage capacitor Cst (that is, the first node N1) is Vdata-
  • the second reset transistor T7 is turned on, so that the initial signal Vinit provided by the second initial signal line INIT2 is provided to the first pole E1 of the light-emitting element EL, and the first pole E1 of the light-emitting element EL is initialized (reset), and its internal Prestore the voltage, complete the initialization, and ensure that the light-emitting element EL does not emit light.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal to turn off the first reset transistor T1.
  • the light emission control signal EM provided by the light emission control signal line EML is a high level signal, which turns off the first light emission control transistor T5 and the second light emission control transistor T6.
  • the third stage A3 is called the lighting stage.
  • the emission control signal EM provided by the emission control signal line EML is a low-level signal
  • the scanning signal SCAN provided by the scanning line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals.
  • the light emission control signal EM provided by the light emission control signal line EML is a low-level signal, so that the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the first voltage signal VDD output by the first power line PL1 passes through the turned on
  • the first light emission control transistor T5 , the driving transistor T3 and the second light emission control transistor T6 provide a driving voltage to the first pole E1 of the light emitting element EL to drive the light emitting element EL to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K*[(VDD-Vdata)] 2 .
  • I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first pole of the driving transistor T3
  • Vth is the driving current of the driving transistor T3.
  • Vdata is the data voltage output from the data line DL
  • VDD is the first voltage signal output from the first power line PL1.
  • the pixel circuit of this embodiment can better compensate the threshold voltage of the driving transistor T3.
  • FIG. 5 is a schematic diagram of a local wiring method of data lines in the first display area A.
  • FIG. 5 several data lines and several first pixel circuits 10 and second pixel circuits 20 are taken as examples for illustration.
  • the display substrate has a central axis in the second direction D2, the central axis overlaps the axis F, and the display substrate may be symmetrical about the central axis.
  • the arrangement of data lines in the first display area A is taken as an example below for description.
  • the arrangement of data lines in the second display area B reference can be made to the arrangement of data lines in the first display area A, so details will not be repeated here.
  • the structure shown in this embodiment mode can be appropriately combined with the structures shown in other embodiment modes.
  • the frame region R3 includes a data driving chip region
  • the data driving chip region may include an integrated circuit configured to be connected to a plurality of data lines of the display region.
  • the first sub-region A-R2 of the second sub-display region may be located on a side of the first sub-region A-R1 of the first sub-display region away from the area of the data driving chip.
  • the first sub-display area includes a first part of the first sub-display area and a second part of the first sub-display area located on opposite sides of the second sub-display area in the first direction D1, and a second part of the first sub-display area located on the second The third part of the first sub-display area on opposite sides of the second direction D2 of the sub-display area.
  • the first sub-region A-R1 of the first sub-display region includes: The first sub-area first part A-R11 of the first sub-display area and the second part A-R12 of the first sub-area of the first sub-display area on opposite sides of the first sub-area A-R2 of the second sub-display area, and along the The third part A-R13 of the first sub-region of the first sub-display region located on opposite sides of the first sub-region A-R2 of the second sub-display region in the second direction D2.
  • the first sub-display area, the first sub-area, the third part includes the first sub-display area, the first sub-area, the third part, the first sub-section A-R13a and the first sub-display area, the first sub-area, the third part, the second sub-section A -R13b.
  • the first sub-area first part A-R11 of the first sub-display area is located on the lower side of the first sub-area A-R2 of the second sub-display area
  • the first sub-area second part A-R12 of the first sub-display area is located at the second The upper side of the first sub-area A-R2 of the sub-display area.
  • the first sub-area first part A-R11 of the first sub-display area and the first sub-area second part A-R12 of the first sub-display area are separated by the first sub-area A-R2 of the second sub-display area in the first direction D1.
  • the first sub-display area, the first sub-area, the third part A-R13 is separated by the second sub-display area, the first sub-area A-R2 in the second direction D2, that is, the first sub-display area, the first sub-area
  • the first sub-section A-R13a of the third part and the first sub-section A-R13b of the third part of the first sub-display area are located at the end of the first sub-area A-R2 of the second sub-display area in the second direction D2 opposite sides.
  • this embodiment is not limited to this.
  • the second part A-R12 of the first sub-area of the first sub-display area may be connected in the second direction D2, or may be separated by the first sub-area A-R2 of the second sub-display area.
  • the first sub-display area, the first sub-area, the third part, the first sub-area A-R13a is located on the left side of the second sub-display area, the first sub-area A-R2, and the first sub-display area, the first sub-area, the third part, the second The sub-portion A-R13b is located on the right side of the first sub-area A-R2 of the second sub-display area.
  • the first sub-display area, the first sub-area, the third part, the first sub-section A-R13a and the first sub-display area, the first sub-area, the third part, the second sub-section A-R13b are separated by the first sub-display area, the first sub-section The region first part A-R11, the second sub-display region first sub-region A-R2 and the first sub-display region first sub-region second part A-R12 are separated.
  • the first sub-display area, the first sub-area, the third part, the first sub-section A-R13a and the first sub-display area, the first sub-area, the first part A-R11 and the first sub-display area, the first sub-area, the second part A- R12a is connected, the first sub-display area, the first sub-area, the third part, the second sub-section A-R13b is connected with the first sub-display area, the first sub-area, the first part A-R11 and the first sub-display area, the first sub-area, the second Section A-R12b communicates.
  • the first sub-display area and the second sub-area B-R1 have a similar structure, which will not be repeated here.
  • the first sub-area first part A-R11 of the first sub-display area and the second sub-area first part B-R11 of the first sub-display area form the first part of the first sub-display area
  • the second part A-R12 and the second part B-R12 of the first sub-display area form the second part of the first sub-display area
  • the third part of the first sub-display area first sub-area R13a first sub-display area first sub-area third part second sub-section A-R13b, first sub-display area second sub-area third part first sub-section B-R13a and first sub-display area second sub-section
  • the second sub-section B-R13b of the third section of the area forms the third section of the first sub-display area.
  • the first sub-display area A-R1 is provided with a plurality of first data lines, and the first sub-display area A-R1 It includes the first part A-R11 of the first sub-region of the first sub-display area, the second part A-R12 of the first sub-region of the first sub-display area, and the third part A-R13 of the first sub-region of the first sub-display area.
  • the frame region R3 is provided with a plurality of data connection lines 64 .
  • At least one first data line is connected to at least one pixel circuit in the first part A-R11 of the first sub-region of the first sub-display region, and is connected to the second part of the first sub-region of the first sub-display region through at least one data connection line 64 At least one pixel circuit of A-R12 is connected.
  • at least one first data line is connected to a column of first pixel circuits in the first part A-R11 of the first sub-area of the first sub-display area and a column of first pixel circuits in the second part A-R12 of the first sub-area of the first sub-display area. Pixel circuit connection.
  • At least one first data line includes: a first sub-data line 61 , a second sub-data line 62 and a third sub-data line 63 .
  • the third sub data line 63 is connected between the first sub data line 61 and the second sub data line 62.
  • the first sub-data line 61 is located in the first part A-R11 of the first sub-region of the first sub-display region and is connected to a column of first pixel circuits in the first part A-R11 of the first sub-region of the first sub-display region.
  • the second sub-data line 62 is located in the second part A-R12 of the first sub-region of the first sub-display region and is connected to a column of first pixel circuits in the second part A-R12 of the first sub-region of the first sub-display region.
  • the third sub-data line 63 is located in the third part A-R13 of the first sub-area of the first sub-display area, and extends to the first part A-R11 of the first sub-area of the first sub-display area to connect with the first sub-data line 61, And it is connected with the data connection line 64 of the frame region R3.
  • the third sub-data line 63 is connected to a plurality of second pixel circuits arranged along the first direction D1 in the third part A- R13 of the first sub-region of the first sub-display region.
  • the data connection line 64 of the frame region R3 is connected to the second sub-data line 62 of the first sub-area second part A-R12 of the first sub-display area.
  • the data signal provided by the driving chip area can be transmitted to the second sub-data line 62 through the first sub-data line 61, the third sub-data line 63 and the data connection line 64, and the third sub-data line 63 is used to
  • the third part A-R13 of the first sub-display area of the first sub-display area provides data signals to the pixel circuit of the second part A-R12 of the first sub-area of the first sub-display area after winding, which can prevent the data line from being in the second sub-display
  • the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region are directly wired to affect the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region Light transmittance, thereby improving the display effect.
  • the first sub-region A-R1 of the first sub-display region is provided with pixel circuits arranged in an array.
  • the third part A-R13 of the first sub-area of the first sub-display area is provided with n1 column pixel circuits
  • the first part A-R11 of the first sub-area of the first sub-display area is provided with n2 column pixel circuits
  • the first sub-display area The second part A-R12 of the first sub-area is provided with n3 columns of pixel circuits in total.
  • n3 may be smaller than n2.
  • the embodiments of the present disclosure are not limited thereto.
  • n3 may be equal to n2.
  • the first sub-data lines 61 extend along the first direction D1, and a plurality of The first sub-data lines 61 are sequentially arranged along the second direction D2.
  • One first sub-data line 61 may be connected to a column of first pixel circuits 10 and configured to provide the corresponding first pixel circuits 10 with data signals introduced from the driving chip area.
  • one first sub-data line 61 may be connected to one column of second pixel circuits.
  • the second sub-data lines 62 may extend along the first direction D1, and a plurality of second sub-data lines 62 are sequentially arranged along the second direction D2.
  • One second sub-data line 62 may be connected to a row of first pixel circuits 10 or a row of second pixel circuits 20 in the second part A-R12 of the first sub-region of the first sub-display region.
  • the first sub-data line 61 and the second sub-data line 62 are separated by the first sub-region A-R2 of the second sub-display region.
  • the first sub-data lines 61 and the second sub-data lines 62 may have the same layer structure.
  • the third sub-data line 63 in the third part A-R13 of the first sub-area of the first sub-display area, includes: first line segments connected to each other 631 and the second line segment 632.
  • the first line segment 631 extends along the second direction D2, and a plurality of first line segments 631 are arranged in sequence along the first direction D1.
  • the second line segment 632 extends along the first direction D1, and a plurality of second line segments 632 are sequentially arranged along the second direction D2.
  • first line segment 631 extends to the first part A-R11 of the first sub-area of the first sub-display area and is connected to the first sub-data line 61, and the other end of the first line segment 631 is connected to the first sub-area of the first sub-display area.
  • the district third part A-R13 is connected with the second line segment 632 .
  • the second line segment 632 is connected to a plurality of second pixel circuits 20 arranged along the first direction D1 in the third portion A- R13 of the first sub-region of the first sub-display region.
  • the plurality of second pixel circuits 20 connected by the second line segment 632 are connected with the second light emitting elements 40 of the first sub-region A-R2 of the second sub-display region.
  • the embodiments of the present disclosure are not limited thereto.
  • the plurality of second pixel circuits 20 connected by the second line segment 632 may be dummy pixel circuits, that is, may not be connected to the light emitting element.
  • the first line segment 631 and the second line segment 632 may have a heterogeneous structure.
  • the second line segment 632 and the first sub-data line 61 may have the same layer structure, and the first line segment 631 and the first sub-data line 61 may have a different-layer structure.
  • the first line segment 631 and the second line segment 632 may be of an integrated structure and have a different layer structure with the first sub-data line 61 .
  • the embodiments of the present disclosure are not limited thereto.
  • a plurality of data connection lines 64 are located on the side of the first sub-area A-R2 of the second sub-display area away from the driver chip area, for example, in the upper frame area Inside, thereby expanding the wiring space and improving the PPI.
  • the at least one data connection line 64 includes: a first sub-data connection line 641 , a second sub-data connection line 642 and a third sub-data connection line 643 .
  • the first sub-data connection line 641 and the third sub-data connection line 643 extend along the first direction D1, and the second sub-data connection line 642 extends along the second direction D2.
  • the lengths of the plurality of second sub-data connection lines 642 along the second direction D2 may be the same.
  • a plurality of first sub-data connection lines 641 and a plurality of third sub-data connection lines 643 are sequentially arranged along the second direction D2, and a plurality of second sub-data connection lines 642 are sequentially arranged along the first direction D1.
  • the second sub-data connection line 642 is respectively connected to the first sub-data connection line 641 and the third sub-data connection line 643 .
  • the first sub-data connection line 641 is connected to the second segment 632 of the third sub-data line 63
  • the third sub-data connection line 643 is connected to the second sub-data line 62.
  • the first sub-data connection line 641 and the third sub-data connection line 643 are of the same layer structure, and are of a different-layer structure from the second sub-data connection line 642 .
  • the second sub-data connection line 642 may have the same layer structure as the second segment 632 of the third sub-data line 63 and the second sub-data line 62 .
  • the embodiments of the present disclosure are not limited thereto.
  • the orthographic projection of the data connection line extending along the second direction D2 (that is, the second sub-data connection line 642 ) on the display substrate does not overlap with the orthographic projection of the axis F on the display substrate, so as to avoid In order to prevent repeated folding from causing damage to the data line, such as short circuit, etc., it improves reliability.
  • the first light-emitting element connected to the first pixel circuit connected to the first sub-data line 61 and the second light-emitting element connected to the second pixel circuit connected to the corresponding third sub-data line 63 may be Located in the same column, the first light-emitting element connected to the first pixel circuit connected to the first sub-data line 61 and the first light-emitting element connected to the first pixel circuit connected to the corresponding second sub-data line 62 may be located in the same column.
  • the embodiments of the present disclosure are not limited thereto.
  • the first line segments 631 of the plurality of third sub-data lines 63 are arranged along the first direction D1, the closer to the second sub-display area and the first sub-area.
  • the first line segment 631 of A-R2 is connected with the first sub-data line 61 closer to the central axis F;
  • the second line segment 632 connects.
  • the lengths of the plurality of second line segments 632 in the first direction D2 gradually decrease.
  • the lengths of the plurality of first line segments 631 in the second direction D2 gradually decrease.
  • the embodiments of the present disclosure are not limited thereto.
  • the lengths of the plurality of first line segments 631 in the second direction D2 remain unchanged.
  • the lengths of the plurality of second line segments 632 in the first direction D2 gradually increase.
  • the first sub-region A- R1 of the first sub-display region is further provided with a plurality of second data lines 71 .
  • the plurality of second data lines 71 all extend along the first direction D1 and are sequentially arranged along the second direction D2.
  • the second data line 71 in the first sub-region A-R1 of the first sub-display region does not need to be designed for routing.
  • At least one second data line 71 may be connected to a column of pixel circuits (first pixel circuit or second pixel circuit).
  • a part of the second pixel circuits 20 and the second part of the third sub-data line 63 The line segment 632 is connected, and another part may be connected to the second data line 71 , and the second line segment 632 of the third sub-data line 63 is disconnected from the second data line 71 .
  • the orthographic projection of the sub-data line extending along the second direction D2 that is, the first line segment 631 of the third sub-data line 63 ) on the display substrate and the orthographic projection of the axis F on the display substrate
  • Non-overlapping avoids bad data lines caused by repeated folding, such as short circuit, etc., and improves reliability.
  • the first display area A and the second display area B may be symmetrically disposed about the axis F. Referring to FIG.
  • the data line windings around the first sub-region A-R2 of the second sub-display region are arranged symmetrically with respect to the central axis E of the first sub-region A-R2 of the second sub-display region along the second direction D2 .
  • the data line windings around the second sub-region B-R2 of the second sub-display region are arranged symmetrically with respect to the central axis E along the second direction D2 of the first sub-region A-R2 of the second sub-display region.
  • the first sub-region A- R2 of the second sub-display area is disposed on a side of the first display area A close to the axis F.
  • the second sub-display area The second sub-area B-R2 is set to the side of the second display area B close to the axis F.
  • the first sub-region A-R2 of the second sub-display region has a centerline (geometric center) E along the second direction D2. Due to the limitation of wiring space close to the axis F, the first sub-region A-R1 of the first sub-display area is provided with at least part of the first data lines, and this part of the first data lines includes the second sub-data lines located on the side of the central line E 62 (marked as 62-1) and the first sub-data line 61 (marked as 61-1) and the second line segment 632 (marked as 632-1) on the other side of the central line E, and this part of the first data line
  • the first line segment 631 (marked as 631 - 1 ) of the first data line overlaps the central line E
  • the data connection line 64 (marked as 64 - 1 ) of this part of the first data line overlaps the central line E.
  • another part of the first data lines can also be set in the first sub-region A-R1 of the first sub-display area, and each sub-data line of the other part of the first data lines is located on the central line E to the axis F.
  • the second sub-region B-R2 of the second sub-display region may have the same wiring method, which will not be repeated here.
  • the data connection line 64-1 in the above-mentioned part of the first data line is For line 64, closer to the first sub-region A-R2 of the second sub-display area, the second line segment 632-1 in the above-mentioned part of the first data line is closer to other second line segments 632 on the other side of the central line E. Close to the first sub-area A-R2 of the second sub-display area, the first line segment 631-1 of the above-mentioned part of the first data line is closer to the second sub-area than other first line segments 631 on the other side of the central line E. Display area first sub-area A-R2.
  • the first display area A and the second display area B are arranged symmetrically, and the first sub-area A-R2 of the second sub-display area and the second sub-area B-R2 of the second sub-display area An even number of third sub-data lines 63 are provided for winding.
  • the three sub-data lines 63 are wound so that the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region can be arranged closer together. That is, the cameras of the first sub-area A-R2 of the second sub-display area and the second sub-area B-R2 of the second sub-display area are closer to the axis F, but do not overlap with the axis F, which is conducive to optimizing image acquisition.
  • the display substrate may be provided with at least one first data line, the first data line is used to drive the pixel columns located in the first display area A, but has a pixel column located in the second display area
  • the data line windings of B are used to drive the pixel columns located in the second display area B, but have the data line windings located in the first display area A.
  • both the second sub-data line 62-2 and the first sub-data line 61-2 are located in the first display area A
  • the second line segment 632-2 is located in the second display area B
  • the first sub-data line 632-2 is located in the second display area B.
  • the total lengths of the left and right winding data lines of the first sub-region A-R2 and the second sub-region B-R2 of the second sub-display region are similar, so that the resistance values of the data lines are similar to achieve a uniform display effect.
  • the area sizes of the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region may be approximately the same, or, the first sub-region of the second sub-display region
  • the area size of the area A-R2 and the second sub-area B-R2 of the second sub-display area may be different.
  • the data line wiring can be compensated according to the above design rules to optimize the actual display effect.
  • different sensors can be set in the first sub-area A-R2 of the second sub-display area and the second sub-area B-R2 of the second sub-display area respectively according to actual needs, for example, in the first sub-area of the second sub-display area
  • the area A-R2 and the second sub-area B-R2 of the second sub-display area are respectively provided with two primary and secondary image acquisition sensors of different sizes.
  • the first sub-area A-R2 of the second sub-display area and the second sub-area B-R2 of the second sub-display area may be provided with one or more different sensors, including but not limited to: 1 Image acquisition sensor; 2Face recognition sensor (3D imaging technology can be used, for example, using structured light 3D imaging method or time-of-flight method, a face recognition sensor can include multiple cameras and depth sensors); 3Fingerprint recognition Sensors, etc.
  • the first sub-area A-R2 of the second sub-display area and the second sub-area B-R2 of the second sub-display area can be arranged and combined according to actual needs, and one or more sensors among a plurality of different sensors can be arranged.
  • the first sub-area A-R2 of the second sub-display area can be provided with a plurality of sensors, for example, 1 image acquisition sensor + 1 face recognition sensor; the second sub-area B-R2 of the second sub-display area can be A fingerprint recognition sensor and the like are provided.
  • the first sub-region A-R2 of the second sub-display area is located on the side of the first display area A away from the data driver chip (ie, the side close to the upper frame of the display substrate), and the second sub-display area The second sub-region B-R2 is located on the side of the second display region B away from the data driving chip (ie, the side close to the upper border of the display substrate).
  • the embodiment of the present disclosure is not limited thereto, and the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region can be arranged at any position of the display substrate according to actual needs.
  • the first sub-region A-R2 of the second sub-display area is located on the side of the first display area A away from the data driving chip (that is, the side close to the upper border of the display substrate)
  • the second sub-display area is located on the side of the second display area B close to the data drive chip (that is, the side close to the lower border of the display substrate); or, the first sub-area A of the second sub-display area -R2 is located on the side of the first display area A close to the data driving chip (that is, the side close to the lower border of the display substrate), and the second sub-display area B-R2 is located on the side of the second display area B away from the data driving chip One side (that is, the side close to the upper frame of the display substrate).
  • the display substrate includes a data driving chip, and the data driving chip is respectively connected to the data lines of the first display area and the second display area.
  • the first sub-region A-R2 of the second sub-display area and the second sub-region B-R2 of the second sub-display area are both close to the upper frame area, and the display substrate also includes a data driver chip located in the lower frame area (Drive IC, DIC).
  • the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region respectively cover a plurality of different data lines.
  • the display substrate includes two data driving chips C-1 and C-2, wherein one data driving chip C-1 is connected to the data line of the first display area A, Another data driving chip C-2 is connected to the data line of the second display area B.
  • the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region are arranged along the first direction D1, and the second sub-display region
  • the first sub-area A-R2 of the area and the second sub-area B-R2 of the second sub-display area are connected to at least one same data line.
  • the first sub-region A-R2 of the second sub-display area and the second sub-region B-R2 of the second sub-display area are located on the same columns of data lines. At this time, these columns of data lines need to be wound twice. Wire.
  • the winding rules are the same as those in the above-mentioned other embodiments, and the total length of the data lines should be consistent as far as possible, so as to improve display uniformity.
  • at least one row of data line windings located close to the frame area may be located in the frame area.
  • the display substrate includes two data driving chips, wherein one data driving chip is used to drive the first data line, and the other data driving chip is used to drive the second data line.
  • the first data line has windings at the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region, and the second data line has no windings.
  • the two data driving chips can be located on the same side of the display substrate, or, as shown in FIG. 16 , the two data driving chips can be located on different sides of the display substrate. As shown in FIG. 15 and FIG. 16 , both data driving chips can be bent to the backside of the display substrate to realize a narrow frame.
  • the length of the data line connected to the data driver chip C-1 has a compensation design, and for some data lines with shorter lengths, it should be set to a position relatively far away from C-1. area, or use curved wires to increase the resistance to compensate; on the contrary, for some data lines with longer lengths, the width of the data lines can be thickened in the peripheral area to reduce the resistance, so that the total length of the data lines driving the entire column is similar to Achieve similar resistance and uniform display effect.
  • FIG. 17 is a schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a sub-pixel of the OLED display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on the base substrate 100 , and a light emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the base substrate 100 And the encapsulation layer 104 disposed on the side of the light emitting structure layer 103 away from the base substrate 100 .
  • the display substrate may include other film layers, such as spacer pillars, etc., which are not limited in this disclosure.
  • the base substrate 100 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit, and only one transistor 101 and one storage capacitor 101A are taken as an example in FIG. 3 .
  • the light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 is connected to the drain electrode of the drive transistor 101 through a via hole.
  • the pixel definition layer 302 includes a first opening exposing the anode 301.
  • the light-emitting layer 303 is connected to the anode 301
  • the cathode 304 is connected to the organic light-emitting layer 303
  • the organic light-emitting layer 303 is driven by the anode 301 and the cathode 304 to emit light of a corresponding color.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials
  • the second encapsulation layer 402 may be made of organic materials. material
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 , which can ensure that external water vapor cannot enter the light emitting structure layer 103 .
  • the organic light-emitting layer 303 may include a stacked hole injection layer (Hole Injection Layer, referred to as HIL), a hole transport layer (Hole Transport Layer, referred to as HTL), an electron blocking layer (Electron Block Layer) , referred to as EBL), light emitting layer (Emitting Layer, referred to as EML), hole blocking layer (Hole Block Layer, referred to as HBL), electron transport layer (Electron Transport Layer, referred to as ETL) and electron injection layer (Electron Injection Layer, referred to as EIL) ).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EML electron blocking layer
  • EML light emitting layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the electron injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be A common layer connected together
  • the electron transport layer of all sub-pixels can be a common layer connected together
  • the hole blocking layer of all sub-pixels can be a common layer connected together
  • the light-emitting layer of adjacent sub-pixels can have a small amount of overlap, or may be isolated
  • the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • the display substrate may further include a touch control structure layer 105 disposed on the side of the encapsulation layer 104 away from the base substrate 100
  • the touch structure layer 105 may include a first touch structure layer, cover the first touch The first coating protection layer of the control structure and the second touch structure layer arranged on the first coating protection layer
  • the second touch structure layer may include a plurality of first touch electrodes 231, a plurality of second touch The electrode 232 and a plurality of first connection parts
  • the first touch structure layer may include a plurality of second connection parts, at least one of the first touch electrode 231 and the second touch electrode 232 passes through the first coating protection layer
  • the via holes are connected to the second connecting part, and the multiple first touch electrodes 231, the multiple second touch electrodes 232 and the multiple first connecting parts can be formed by the same patterning process, the first touch electrodes and the first The connection part may be an integral structure connected to each other.
  • the second connection part can connect adjacent second touch electrodes to each other through via holes.
  • the first touch electrode 231 may include a plurality of first sub-electrodes connected through a first connection portion
  • the second touch electrode 232 may include a plurality of second sub-electrodes connected through a second connection portion. electrode.
  • a plurality of first touch electrodes 231, a plurality of second touch electrodes 232 and a plurality of first connecting parts can be arranged on the same layer on the first touch structure layer, and the second connecting parts can be arranged At the bridging layer, this disclosure is not limited.
  • the first touch electrode 231 may be a driving electrode (Tx)
  • the second touch electrode 232 may be a sensing electrode (Rx)
  • the first touch electrode 231 may be a sensing electrode (Rx)
  • the second touch electrode 232 may be a driving electrode (Tx).
  • the touch structure layer in the embodiments of the present disclosure may also be an On Cell Touch structure, which is not limited in the present disclosure.
  • the first touch electrodes 231 and the second touch electrodes 232 may have a rhombus shape, such as a regular rhombus, or a horizontally long rhombus, or a vertically long rhombus.
  • the first touch electrodes 231 and the second touch electrodes 232 may have any one or more of triangles, squares, trapezoids, parallelograms, pentagons, hexagons and other polygons. , the present disclosure is not limited here.
  • the first touch electrode 231 and the second touch electrode 232 may be in the form of a metal grid
  • the metal grid is formed by interweaving a plurality of metal wires
  • the metal grid includes a plurality of grid patterns
  • the grid A pattern is a polygon formed by a plurality of metal lines.
  • the first touch electrode and the second touch electrode formed in the form of a metal mesh have the advantages of small resistance, small thickness, fast response speed and the like.
  • the area surrounded by the metal lines in a grid pattern includes sub-pixel areas in the display structure layer, and the metal lines are located between adjacent sub-pixels.
  • the area of the sub-pixel can be the light-emitting area defined by the pixel defining layer in the light-emitting structure layer, the area surrounded by the metal lines includes the light-emitting area, and the metal line is located at the corresponding pixel defining layer. location, that is, in the non-luminous area.
  • the display substrate may further include a color filter layer 106 disposed on the side of the touch structure layer 105 away from the base substrate 100.
  • the color filter layer 106 may include color filters 1062 of different colors and arranged on
  • the black matrix 1061 between the color filters 1062 of different colors, the black matrix 1061 includes a second opening exposing the color filters 1062 . Due to poor foldability and poor light transmittance of conventional polarizers, the embodiments of the present disclosure use CF on Encapsulation (COE) instead of polarizers to form a display with multi-functional layer stacking and better foldability. Substrate structure.
  • COE CF on Encapsulation
  • the orthographic projection of the touch structure layer 105 on the base substrate 100 is within the range of the orthographic projection of the pixel definition layer 302 on the base substrate, and the color filter 1062 is on the base substrate 100
  • the orthographic projection of includes the orthographic projection of the organic light emitting layer 303 on the base substrate 100 .
  • the display substrate may further include an anti-reflection layer 107 covering the color filter layer 106 and a cover plate 108 disposed above the anti-reflection layer 107. reflectance of light.
  • At least one of the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region may only include the base substrate 100 and the The light-emitting structure layer 103, the encapsulation layer 104 and the color filter layer 106 on the 100, that is, at least one of the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region may not be provided.
  • the driving circuit layer 102 and the touch structure layer 105 may be provided.
  • At least one of the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region may only include the base substrate 100 and the The light emitting structure layer 103, the encapsulation layer 104, the touch control structure layer 105 and the color filter layer 106 on the substrate 100, that is, the first sub-region A-R2 of the second sub-display region and the second sub-region B-R2 of the second sub-display region At least one of them may not be provided with the driving circuit layer 102 .
  • the pixel definition layer 302 may be a black material, so as to distinguish the first sub-region A-R1 of the first sub-display region from the first sub-region A-R2 of the second sub-display region, or, the first sub-region The second sub-area B-R1 of the display area and the second sub-area B-R2 of the second sub-display area.
  • the thickness of the black matrix 1061 in the direction perpendicular to the display substrate in the first sub-region A-R2 of the second sub-display region or the second sub-region B-R2 of the second sub-display region is smaller than that in the direction perpendicular to the display substrate.
  • the thickness of the black matrix 1061 of the first sub-region A-R1 of the first sub-display region or the second sub-region B-R1 of the first sub-display region in the direction perpendicular to the display substrate is to further increase the thickness of the first sub-region of the second sub-display region.
  • the light transmittance of the region A-R2 or the second sub-region B-R2 of the second sub-display region is to further increase the thickness of the first sub-region of the second sub-display region.
  • the maximum thickness of the color filter 1062 in the direction perpendicular to the display substrate is greater than the maximum thickness of the black matrix 1061 in the direction perpendicular to the display substrate, and the color filter 1062 at least partially covers the black matrix 1061.
  • the color filter 1062 has a convex structure, forming the effect of a convex lens, and further improving light extraction efficiency.
  • the touch structure layer 105 may be located in the first sub-region A-R1 of the first sub-display region and the second sub-region B-R1 of the first sub-display region.
  • the layer 105 may also include a plurality of touch signal lines TCL, which are used to transmit the touch signals loaded on the corresponding touch electrodes to the touch driving circuit, and the second sub-display area and the first sub-area A-R2
  • the touch structure layer 105 of the second sub-region B-R2 of the second sub-display area is removed, because the structure of the touch structure layer is a metal mesh (Metal Mesh) structure, the first sub-region A of the second sub-display area is removed -R2 and the touch structure layer 105 of the second sub-region B-R2 of the second sub-display region can increase the transmittance.
  • Metal Mesh Metal Mesh
  • the orthographic projection of the second sub-display area on the base substrate does not overlap with the orthographic projection of the first connecting portion on the base substrate, and the orthographic projection of the second sub-display area on the base substrate The projection does not overlap with the orthographic projection of the second connecting portion on the base substrate. As shown in FIG.
  • a transparent display area (the first sub-area A-R2 of the second sub-display area or the second sub-area B-R2 of the second sub-display area) is basically the same size as a touch electrode block (approximately 4mm), therefore, taking a digging hole in the first sub-area A-R2 of the second sub-display area or the second sub-area B-R2 of the second sub-display area as an example, the digging hole can be set just at one touch point
  • the touch electrode block can be an RX electrode block or a TX electrode block, so that the hole-digging area can be avoided from the touch bridge and the transparent display area can be set corresponding to a touch electrode block to simplify the display substrate. design.
  • the embodiments of the present disclosure do not limit this.
  • the black matrix 1061 located in the hole-digging area may have a ring structure (surrounding the sub-pixel), and the cathode 304 is discontinuous in the hole-digging area.
  • the touch electrodes around the first sub-region A-R2 of the second sub-display region or the second sub-region B-R2 of the second sub-display region can be controlled.
  • the control electrode is used for compensation design.
  • the compensation electrode is designed in the area surrounding the dug hole.
  • the compensation electrode is also a metal grid structure to optimize visibility and reduce Mura (referring to the phenomenon of uneven brightness of the display and various traces) .
  • the touch structure layer 105 can also include a plurality of dummy (Dummy) touch electrodes 24, part of the dummy touch electrodes 24 and the touch pads surrounding the hole-digging area. Electrode block connection.
  • the first touch electrodes 231 , the second touch electrodes 232 , and the dummy touch electrodes 24 are all arranged around the sub-pixels (ie, the openings in the pixel definition layer).
  • the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 that emits light of the first color, and a sub-pixel that emits light of the second color.
  • each of the four sub-pixels may include a circuit unit and a light emitting device, and the circuit unit may include a scanning signal line, a data signal line and a light-emitting signal line and a pixel driving circuit, the pixel driving circuit is respectively connected to the scanning signal line, the data signal line and the light-emitting signal line, and the pixel driving circuit is configured to receive data transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line The corresponding data voltage is output to the light emitting device.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel to emit light with a corresponding brightness.
  • the first sub-display area in the transparent display area (the first sub-area A-R2 of the second sub-display area or the second sub-area B-R2 of the second sub-display area), the first sub-display area
  • the orthographic projection of the opening of the pixel definition layer of the pixel P1 on the base substrate is in the shape of a water drop
  • the orthographic projection of the opening of the pixel definition layer of the second sub-pixel P2 on the base substrate is circular
  • the third sub-pixel P3 The figure of the orthographic projection of the opening of the pixel definition layer on the base substrate is circular.
  • the first sub-pixel P1 may be a red sub-pixel (R) that emits red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light
  • the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) emitting green light.
  • the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the pixel unit P may include three sub-pixels, and the three sub-pixels may be arranged horizontally, vertically, or vertically, which is not limited in this disclosure.
  • the display substrate of the embodiment of the present disclosure further provides a pixel array, which includes multiple rows of first pixel rows 1 and multiple rows of second pixel rows 2, and the first pixel Rows 1 and second rows of pixels 2 are arranged alternately.
  • the first pixel row 1 is formed by alternating red sub-pixels 01 and blue sub-pixels 03 , and the red sub-pixels 01 and blue sub-pixels 03 in the same column in multiple first pixel rows 1 are also alternately arranged.
  • the second pixel row 2 is formed by a plurality of green sub-pixels 02 arranged side by side, and the green sub-pixels 02 are arranged alternately with the red sub-pixels 01 and blue sub-pixels 03 in adjacent rows.
  • the sequential connection of the centers of two red sub-pixels 01 and two blue sub-pixels 03 arranged in an array forms a first virtual quadrilateral 10, and a green sub-pixel 02 is set in each first virtual quadrilateral 10; wherein, At least part of the internal angles of the first virtual quadrilateral 10 are not equal to 90°; at least one of the red sub-pixel 01, the green sub-pixel 02, and the blue sub-pixel 03, the intersection of the extension lines of the two sides of at least one vertex to the sub-pixel The distance from the center is not equal to the distance from the intersection of the extension lines of the two diagonal sides to the center of the sub-pixel.
  • the shapes of some sub-pixels are adjusted so that at least part of the internal angles of the first virtual quadrilateral 10 formed by the connecting line between the centers of the red sub-pixel 01 and the blue sub-pixel 03 are not equal to 90°, and The distance from the intersection point of the extension line on both sides of at least one vertex of at least one of the red sub-pixel 01, green sub-pixel 02, and blue sub-pixel 03 to the center of the sub-pixel, and the intersection point of the extension line on both sides of its diagonal The distances to the centers of the sub-pixels are different, so as to adjust the actual brightness centers in each virtual pixel unit, so that the distribution of each actual brightness center in the entire display panel is more uniform.
  • the distance from the vertex of the first corner of the blue sub-pixel O3 to the boundary of the light-emitting layer is the same as that of other vertices
  • the vertices of the corners are at varying distances from the border of the light emitting layer. For example, there is a certain distance from the vertex of the first corner of the blue sub-pixel 03 to the boundary, while the distances from other vertex corners to the pixel boundary are approximately 0. That is, the distance from the vertex at the first corner of the blue sub-pixel 03 to the border is greater than the distance from vertices at other corners to the border of the blue sub-pixel 03 .
  • each first virtual quadrilateral 10 is formed by sequentially connecting the centers of two red sub-pixels 01 and two blue sub-pixels 03 arranged in an array, that is, each first virtual quadrilateral Two red sub-pixels 01 and two blue sub-pixels 03 are respectively set at the four corner positions of 10, wherein the two red sub-pixels 01 are set at two opposite corner positions of the first virtual quadrilateral 10, Two blue sub-pixels 03 are arranged at the other two opposite corners of the first virtual quadrilateral 10 , and a green sub-pixel 02 is arranged at the center of each first virtual quadrilateral 10 .
  • Four first virtual quadrilaterals 10 form a second virtual quadrilateral 200 , and adjacent first virtual quadrilaterals 10 share a side.
  • the first corner of the blue sub-pixel 03 is rounded, and the second, third and fourth corners all include similar right angles.
  • Two blue sub-pixels 03 located in the same column are arranged symmetrically along the row direction. For two adjacent first pixel rows 1 , the orientations of the first corners of the respective blue sub-pixels 03 are the same, and the orientations of the first corners of the respective blue sub-pixels 03 in the other row are opposite.
  • the first first imaginary quadrilateral 10 in the upper left corner has a pair of equal angles (92° in the illustration), and the other angle is 90°.
  • the other first imaginary quadrilaterals 10 At least one angle is 90°, and the apex of the 90° angle is located at the center of the red pixel; the diagonal blue sub-pixel 03 around each red sub-pixel 01 is symmetrical to the center of the red sub-pixel 01 .
  • the connecting line between the centers of the adjacent red sub-pixel 01 and blue sub-pixel 03 in the same column is h
  • the second virtual quadrilateral 100 is A square with a side length of 2h
  • its central position is a red sub-pixel 01
  • the center of each green sub-pixel 02 in the first virtual quadrilateral 10 is located in the red sub-pixel 01
  • the anodes 301 may be arranged in Magic (that is, the arrangement shown in FIG. 23 , similar to a third-order Rubik's cube).
  • the shape of the first opening of the pixel definition layer 302 may be consistent with the shape of the edge of the anode 301 .
  • the shape of the second opening of the black matrix 1061 may be consistent with the shape of the first opening of the pixel definition layer 302 .
  • the second openings of the black matrix 1061 may extend outward from the first openings of the pixel definition layer 302 , and at this time, the pixel definition layer 302 may use a black material to improve the viewing angle.
  • the second opening of the black matrix 1061 can be retracted into the first opening of the pixel definition layer 302 , at this time, the color of the pixel definition layer 302 is not limited, the optical effect is improved, and the reflection is reduced.
  • the orthographic projection of the second opening of the black matrix 1061 on the display substrate may overlap with the orthographic projection of the first opening of the pixel definition layer 302 on the display substrate.
  • the anodes 301 may be in a Magic arrangement (that is, the arrangement shown in FIG. 23 ).
  • the shape of the first opening of the pixel definition layer 302 may be consistent with the shape of the edge of the anode 301 .
  • the shape of the second opening of the black matrix 1061 can be circular or substantially circular, and this solution can further improve the color separation in the dark state.
  • the second opening of the black matrix 1061 can extend outward from the opening of the pixel definition layer 302. At this time, the pixel definition layer 302 can use black material to improve the viewing angle.
  • the second opening of the black matrix 1061 can be retracted into the first opening of the pixel definition layer 302 , at this time, the color of the pixel definition layer 302 is not limited, the optical effect is improved, and the reflection is reduced.
  • the orthographic projection of the second opening of the black matrix 1061 on the display substrate may overlap with the orthographic projection of the first opening of the pixel definition layer 302 on the display substrate.
  • the anode 301 can be arranged in Magic (that is, the arrangement shown in FIG. 23 ), and the shape of the first opening of the pixel definition layer 302 and the shape of the second opening of the black matrix 1061 can be both Round or roughly round, this solution can also improve dark color separation.
  • the second openings of the black matrix 1061 may extend outward from the first openings of the pixel definition layer 302 , and at this time, the pixel definition layer 302 may use a black material to improve the viewing angle.
  • the second opening of the black matrix 1061 can be retracted into the first opening of the pixel definition layer 302 , at this time, the color of the pixel definition layer 302 is not limited, the optical effect is improved, and the reflection is reduced.
  • the orthographic projection of the second opening of the black matrix 1061 on the display substrate may overlap with the orthographic projection of the first opening of the pixel definition layer 302 on the display substrate.
  • the display substrate in a direction perpendicular to the display substrate, includes a plurality of insulating layers, and the insulating layers may all be made of black materials.
  • the distance between the boundary of the second opening of the black matrix 1061 and the boundary of the first opening of the pixel definition layer 302 may be 0 to 6 micrometers ( ⁇ m).
  • FIG. 24 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the present embodiment provides a display device 91 including the display substrate 910 of the foregoing embodiments.
  • the display substrate 910 may be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device 91 may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • the embodiments of the present disclosure are not limited thereto.

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Abstract

一种显示基板（910），包括：衬底基板（100），包括显示区域和边框区域（R3），显示区域包括第一显示区（A）和第二显示区（B），第一显示区（A）和第二显示区（B）均包括第一子显示区和第二子显示区；多个像素电路和多个第一发光元件（30），位于第一子显示区；多个像素电路包括多个第一像素电路（10）和多个第二像素电路（20），多个第二像素电路（20）分布在多个第一像素电路（10）之间；多个第一像素电路（10）中的至少一个与多个第一发光元件（30）中的至少一个连接；多个第二发光元件（40），位于第二子显示区；多个第二像素电路（20）中的至少一个与多个第二发光元件（40）中的至少一个连接；至少一条第一数据线，位于第一子显示区；第一数据线至少包括一条子数据线（61，62，63）与第一像素电路（10）连接，且至少包括另一条子数据线（61，62，63）与第二像素电路（20）连接。

Description

显示基板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(TFT，Thin Film Transistor)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
屏下传感技术是为了提高显示装置的屏占比所提出的一种全新的技术。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板，包括：
衬底基板，包括显示区域和至少位于所述显示区域一侧的边框区域，所述显示区域包括第一显示区和第二显示区，所述第一显示区包括第一子显示区第一子区和第二子显示区第一子区，所述第二显示区包括第一子显示区第二子区和第二子显示区第二子区，所述第一子显示区第一子区至少部分包围所述第二子显示区第一子区，所述第一子显示区第二子区至少部分包围所述第二子显示区第二子区，所述第一子显示区第一子区与所述第一子显示区第二子区形成第一子显示区，所述第二子显示区第一子区与所述第二子显示区第二子区形成第二子显示区；
多个像素电路和多个第一发光元件，位于所述第一子显示区；所述多个像素电路包括：多个第一像素电路和多个第二像素电路，所述多个第二像素电路分布在所述多个第一像素电路之间；所述多个第一像素电路中的至少一 个像素电路与所述多个第一发光元件中的至少一个发光元件连接；
多个第二发光元件，位于所述第二子显示区；所述多个第二像素电路中的至少一个像素电路与所述多个第二发光元件中的至少一个发光元件连接；
至少一条第一数据线，位于所述第一子显示区；所述第一数据线包括多条相互连接的子数据线，每条所述子数据线沿第一方向和/或第二方向延伸，所述第一方向与第二方向交叉；
所述第一数据线至少包括一条子数据线与所述第一像素电路连接，且至少包括另一条子数据线与所述第二像素电路连接。
在一些示例性实施方式中，所述第二子显示区包括蓝色发光元件、红色发光元件和绿色发光元件，所述第二子显示区还包括至少一个与所述蓝色发光元件连接的第三像素电路，所述红色发光元件与位于所述第一子显示区的第二像素电路连接；
所述绿色发光元件与位于所述第一子显示区的第二像素电路连接；和/或，所述第二子显示区还包括至少一个与所述绿色发光元件连接的第四像素电路。
在一些示例性实施方式中，所述显示基板还包括至少一个第五像素电路，所述第五像素电路的一部分电路位于所述第一子显示区，另一部分电路位于所述第二子显示区。
在一些示例性实施方式中，所述显示基板还包括位于所述第一子显示区和第二子显示区之间的虚拟轴线，所述虚拟轴线与折叠轴交叠，沿所述第二方向延伸的子数据线与所述虚拟轴线在所述显示基板上的正投影不交叠。
在一些示例性实施方式中，所述第一数据线包括依次连接的第一子数据线、第三子数据线、数据连接线和第二子数据线；
所述第一子显示区包括位于所述第二子显示区第一方向相对两侧的第一子显示区第一部和第一子显示区第二部、以及位于第二子显示区第二方向相对两侧的第一子显示区第三部；
所述第一子数据线位于所述第一子显示区第一部，所述第二子数据线位于所述第一子显示区第二部，所述第三子数据线位于所述第一子显示区第三 部，所述数据连接线位于所述边框区域。
在一些示例性实施方式中，至少两条所述第一数据线的子数据线以所述第二子显示区第一子区沿第二方向的中心线为对称轴对称分布。
在一些示例性实施方式中，至少一条所述第一数据线包括位于所述第二子显示区第一子区沿所述第二方向的中心线的一侧的第一子数据线和第二子数据线，且包括位于所述第二子显示区第一子区沿所述第二方向的中心线的另一侧的第三子数据线。
在一些示例性实施方式中，在所述第一显示区内，与所述第二子显示区第一子区沿所述第二方向的中心线交叠的所述第一数据线，位于未与所述第二子显示区第一子区沿所述第二方向的中心线交叠的所述第一数据线靠近所述第二子显示区第一子区的一侧。
在一些示例性实施方式中，至少一条所述第一数据线包括位于所述第一子显示区第一子区的部分子数据线，且包括位于所述第一子显示区第二子区的部分子数据线。
在一些示例性实施方式中，所述显示基板还包括至少一个数据驱动芯片，所述数据驱动芯片位于边框区域，所述第二子显示区第一子区位于所述第一子显示区第一子区远离所述数据驱动芯片的一侧，所述第二子显示区第二子区位于所述第一子显示区第二子区靠近所述数据驱动芯片的一侧。
在一些示例性实施方式中，所述显示基板还包括两个数据驱动芯片，其中，一个所述数据驱动芯片与所述第一显示区的数据线连接，另一个所述数据驱动芯片与所述第二显示区的数据线连接。
在一些示例性实施方式中，所述第一显示区和第二显示区以所述显示基板沿第一方向的中心线为对称轴对称分布。
在一些示例性实施方式中，所述第二子显示区第一子区以及所述第二子显示区第二子区以所述显示基板沿第一方向的中心线为对称轴对称分布，且所述第二子显示区第一子区以及所述第二子显示区第二子区位于相同的多根所述第一数据线之间。
在一些示例性实施方式中，所述显示基板还包括两个数据驱动芯片和第 二数据线，所述第二数据线与一列第一像素电路连接，其中，一个所述数据驱动芯片与所述第一数据线连接，另一个所述数据驱动芯片与所述第二数据线连接。
在一些示例性实施方式中，所述两个数据驱动芯片均位于所述边框区域的一侧，或者，所述两个数据驱动芯片位于所述边框区域的不同侧。
在一些示例性实施方式中，在垂直于所述显示基板的平面上，所述第一子显示区包括衬底基板以及依次叠设在所述衬底基板上的驱动电路层、发光结构层、封装层、触控结构层和彩膜层，所述第二子显示区包括衬底基板以及依次叠设在所述衬底基板上的发光结构层、封装层和彩膜层。
在一些示例性实施方式中，所述彩膜层包括多个不同颜色的彩色滤光片以及设置在所述多个不同颜色的彩色滤光片之间的黑矩阵，所述第二子显示区的黑矩阵沿垂直于所述显示基板方向的厚度小于所述第一子显示区的黑矩阵沿垂直于所述显示基板方向的厚度。
在一些示例性实施方式中，所述发光结构层包括像素定义层、阳极、阴极和有机发光层，其中：
所述像素定义层包括暴露所述阳极的第一开口，所述黑矩阵包括暴露所述彩色滤光片的第二开口，所述第二开口在所述衬底基板上的正投影包含所述第一开口在所述衬底基板上的正投影，所述像素定义层为黑色材料。
在一些示例性实施方式中，所述触控结构层包括沿第一方向排列的多个第一触控电极以及沿第二方向排列的多个第二触控电极，所述第一触控电极包括通过第一连接部连接的多个第一子电极，所述第二触控电极包括通过第二连接部连接的多个第二子电极，所述第二子显示区在所述衬底基板上的正投影与所述第一连接部在所述衬底基板上的正投影不重叠，且所述第二子显示区在所述衬底基板上的正投影与所述第二连接部在所述衬底基板上的正投影不重叠。
本公开实施例还提供了一种显示装置，包括如上所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示基板的示意图；
图2为图1所示的显示基板处于折叠态的示意图；
图3A至图3D为本公开至少一实施例的第一显示区的局部结构示意图；
图3E为本公开至少一实施例的第一显示区的另一局部结构示意图；
图4A至图4C为红绿蓝子像素的启动电压示意图；
图4D为本公开至少一实施例的像素电路的等效电路图；
图4E为图4D所示的像素电路的工作时序图；
图5为本公开至少一实施例的第一显示区的数据线的排布示意图；
图6为本公开至少一实施例的显示基板的数据线的局部排布示意图；
图7为本公开至少一实施例的显示基板的另一示意图；
图8为本公开至少一实施例的显示基板的数据线的另一局部排布示意图；
图9为本公开至少一实施例的显示基板的数据线的又一局部排布示意图；
图10为本公开至少一实施例的显示基板的数据线的又一局部排布示意图；
图11为本公开至少一实施例的显示基板的数据线的又一局部排布示意图；
图12为本公开至少一实施例的显示基板的数据线的又一局部排布示意图；
图13为本公开至少一实施例的显示基板的数据线的又一局部排布示意图；
图14为本公开至少一实施例的显示基板的数据线的又一局部排布示意 图；
图15为本公开至少一实施例的显示基板的数据线的又一局部排布示意图；
图16为本公开至少一实施例的显示基板的数据线的又一局部排布示意图；
图17为本公开至少一实施例的显示基板的剖面示意图；
图18为本公开至少一实施例的显示基板的触控结构层示意图；
图19为本公开至少一实施例的显示基板的触控结构层另一示意图；
图20为本公开至少一实施例的显示基板的触控结构层又一示意图；
图21为本公开至少一实施例的显示基板的触控结构层又一示意图；
图22A为本公开至少一实施例的显示基板的触控结构层又一示意图；
图22B为本公开至少一实施例的显示基板的像素排列示意图；
图23为本公开至少一实施例的显示基板的像素排列另一示意图；
图24为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成 要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂 直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
本公开至少一实施例提供一种显示基板，包括：
衬底基板，包括第一显示区和第二显示区，第一显示区包括第一子显示区第一子区和第二子显示区第一子区，第二显示区包括第一子显示区第二子区和第二子显示区第二子区，第一子显示区第一子区至少部分包围第二子显示区第一子区，第一子显示区第二子区至少部分包围第二子显示区第二子区，第一子显示区第一子区与第一子显示区第二子区形成第一子显示区，第二子显示区第一子区与第二子显示区第二子区形成第二子显示区；
多个像素电路和多个第一发光元件，位于第一子显示区；多个像素电路包括：多个第一像素电路和多个第二像素电路，多个第二像素电路分布在多个第一像素电路之间；多个第一像素电路中的至少一个像素电路与多个第一发光元件中的至少一个发光元件连接；
多个第二发光元件，位于第二子显示区；多个第二像素电路中的至少一个像素电路与多个第二发光元件中的至少一个发光元件连接；
至少一条第一数据线，位于第一子显示区；第一数据线包括多条相互连接的子数据线，每条子数据线沿第一方向和/或第二方向延伸，第一方向与第二方向交叉；
第一数据线至少包括一条子数据线与第一像素电路连接，且至少包括另一条子数据线与第二像素电路连接。
下面通过多个示例对本实施例的显示基板进行举例说明。
图1为本公开至少一实施例的显示基板的示意图。在一些示例性实施方式中，如图1所示，显示基板的衬底基板包括：显示区域和至少位于显示区域一侧的边框区域R3。显示区域包括：第一显示区A和第二显示区B，其中，第一显示区A包括第一子显示区第一子区A-R1和第二子显示区第一子区A-R2，第一子显示区第一子区A-R1至少部分包围第二子显示区第一子区 A-R2；第二显示区B包括第一子显示区第二子区B-R1和第二子显示区第二子区B-R2，第一子显示区第二子区B-R1至少部分包围第二子显示区第二子区B-R2，第一子显示区第一子区A-R1和第一子显示区第二子区B-R1形成第一子显示区，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2形成第二子显示区。例如，图1示出的第一显示区A和第二显示区B分别位于显示区域沿第二方向D2的中心线的左右两侧位置，图1示出的第二子显示区第一子区A-R2、第二子显示区第二子区B-R2分别位于第一子显示区第一子区A-R1、第一子显示区第二子区B-R1的上部正中间位置，第一子显示区第一子区A-R1和第一子显示区第二子区B-R1分别具有三侧与边框区域R3相邻，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2与边框区域R3均不相邻。然而，本公开实施例对此并不限定。例如，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2可以均分别有一侧与边框区域R3相邻，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2可以分别位于第一子显示区第一子区A-R1和第一子显示区第二子区B-R1的左上角位置或右上角位置等其他位置。
在一些示例性实施方式中，如图1所示，显示区域可以为矩形，例如，直角矩形、圆角矩形等。在一些示例性实施方式中，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的形状可以相同，示例性的，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2可以均为圆形、矩形、椭圆形等形状中的一种形状。然而，本公开实施例对此并不限定。例如，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的形状也可以不同，示例性的，第二子显示区第一子区A-R2可以为圆形，第二子显示区第二子区B-R2可以为矩形或椭圆形等其他形状。
在一些示例性实施方式中，第一子显示区第一子区A-R1和第一子显示区第二子区B-R1可以为非透光显示区，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2可以为透光显示区。即，第一子显示区第一子区A-R1和第一子显示区第二子区B-R1不透光，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2可透光，第一子显示区第一子区A-R1、第一子显示区第二子区B-R1、第二子显示区第一子区A-R2和第二子显示区第二子区 B-R2均具有发光单元，从而可以实现全面屏显示。例如，传感器(如，光学传感器、红外传感器、指纹传感器、超声波传感器等)等硬件在显示基板上的正投影可以位于显示基板的第二子显示区第一子区A-R2和第二子显示区第二子区B-R2内。本示例的显示基板无需打孔，在确保显示基板的实用性的前提下，可以使真全面屏成为可能。
在一些示例性实施方式中，显示面板可以包括一轴线F，其中，轴线F可以沿第一方向D1延伸，轴线F可以是虚设的线。第一显示区A和第二显示区B分别位于轴线F相对两侧。然而，本公开实施例对此并不限定。例如，轴线F也可以沿第二方向D2延伸。
在一些示例性实施方式中，第一方向D1与第二方向D2交叉，例如，第一方向D1可以垂直于第二方向D2。在一些示例中，第一方向D1平行于子像素列方向，第二方向D2平行于子像素行方向。然而，本公开实施例对此并不限定。
在一些示例性实施方式中，显示面板可以包括一折叠轴，折叠轴与显示面板的轴线F相交叠，实现可折叠功能。在一些示例性实施方式中，显示面板可以具有第一摄像头C1(图中未示出)，第一摄像头C1与第二子显示区第一子区A-R2相交叠。显示面板可以具有第二摄像头C2(图中未示出)，第二摄像头C2与第二子显示区第二子区B-R2相交叠，从而可以实现双摄像头采集图像。然而，本公开实施例对此并不限定。
如图1所示，当显示面板处于非折叠态时，第一显示区A的表面和第二显示区B的表面处于同一平面，第一显示区A和第二显示区B共同显示图像。此时，可以是第一摄像头C1或者第二摄像头C2任一采集图像，也可以是第一摄像头C1和第二摄像头C2同时采集左右画幅图像，左右画幅图像经过处理后实现图像增强。
如图2所示，沿轴线F将显示面板弯折，可将显示面板从平面状态(即非折叠态)变为弯折状态(即折叠态)，此时，第一显示区A和第二显示区B相对，第一显示区A或者第二显示区B显示图像，对应的第一摄像头C1或者第二摄像头C2用于采集图像。例如，假设使用第一摄像头C1采集图像、第一显示区A显示图像，当用户拍摄照片时，第一摄像头C1采集静态图像， 第一显示区A显示静态图像；当用户拍摄视频时，第一摄像头C1采集动态图像，第一显示区A显示动态图像。
通常折叠屏的折叠轴位于显示面板的大致居中的位置，也就是说，第一显示区A和第二显示区B关于轴线F对称设置，此时，如果使用单摄像头区，那么，单摄像头区的摄像头不能设置于整个显示面板的居中位置，只能设置到第一显示区A或者第二显示区B，因此，该单摄像头区采集的图像会由于不对称产生图像质量劣化问题。本公开实施例的显示面板，通过设置两个第二子显示区：第二子显示区第一子区A-R2和第二子显示区第二子区B-R2，即可以设置双摄像头区，从而可以优化因单摄像头区的摄像头采集图像不对称产生的图像质量劣化问题。此外，通过两个第二子显示区的双摄像头采集图像，双摄像头采集的图像经过图像处理，可以实现景深虚化、图像质量增强以及光学变焦等多种功能，优化图形采集与显示效果。
在一些示例性实施方式中，显示基板可以包括设置在衬底基板上的多个子像素。至少一个子像素包括像素电路和发光元件。像素电路配置为驱动发光元件。例如，像素电路配置为提供驱动电流以驱动发光元件发光。例如，发光元件可以为有机发光二极管(OLED)，发光元件在其对应的像素电路的驱动下发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：第一极(例如，阳极)、第二极(例如，阴极)以及设置在第一极和第二极之间的有机发光层。其中，第一极可以与像素电路连接。然而，本公开实施例对此并不限定。在一些示例中，发光元件可以为量子点发光二极管(QLED，Quantum Dot Light Emitting Diode)、微发光二极管(Micro-LED，Micro Light Emitting Diode)、或者迷你二极管(Mini-LED)。
在一些示例性实施方式中，一个像素单元可以包括三个子像素(例如，一个红色子像素R、一个蓝色子像素B，以及一个绿色子像素G)，三个子像素可以采用水平并列、竖直并列或品字方式排列。例如，一个像素单元可以包括四个子像素(例如，一个红色子像素R、一个蓝色子像素B、一个绿色子像素G以及一个白色子像素W，或者，一个红色子像素R、一个蓝色子像素B以及两个绿色子像素G)，四个子像素可以采用水平并列、竖直并列 或正方形方式排列。然而，本公开实施例在此不做限定。
图3A为本公开至少一实施例的显示基板的局部结构示意图。在一些示例性实施方式中，如图3A所示，显示基板包括：位于第一子显示区第一子区A-R和/或第一子显示区第二子区B-R1的多个第一像素电路10、多个第二像素电路20和多个第一发光元件30，以及位于第二子显示区第一子区A-R2和/或第二子显示区第二子区B-R2的多个第二发光元件40。多个第二像素电路20可以间隔分布于多个第一像素电路10之间，例如，在第一方向上相邻两个第二像素电路20之间排布多个第一像素电路10。多个第一像素电路10中的至少一个第一像素电路10可以与多个第一发光元件30中的至少一个第一发光元件30连接，且至少一个第一像素电路10在衬底基板上的正投影与至少一个第一发光元件30在衬底基板上的正投影可以至少部分交叠。第一像素电路10可以配置为给所连接的第一发光元件30提供驱动信号，以驱动第一发光元件30发光。多个第二像素电路20中的至少一个第二像素电路20可以与多个第二发光元件40中的至少一个第二发光元件40通过导电线L连接。第二像素电路20可以配置为给所连接的第二发光元件40提供驱动信号，以驱动第二发光元件40发光。由于第二发光元件40与第二像素电路20位于不同区域，至少一个第二像素电路20在衬底基板上的正投影与至少一个第二发光元件40在衬底基板上的正投影不存在重叠部分。
在一些示例性实施方式中，第二子显示区第一子区A-R2的第二发光元件40的密度可以约等于第一子显示区第一子区A-R1的第一发光元件30的密度，第二子显示区第二子区B-R2的第二发光元件40的密度可以约等于第一子显示区第二子区B-R1的第一发光元件30的密度。即，第二子显示区第一子区A-R2的分辨率可以与第一子显示区第一子区A-R1的分辨率大致相同，第二子显示区第二子区B-R2的分辨率可以与第一子显示区第二子区B-R1的分辨率大致相同。然而，本公开实施例对此并不限定。例如，第二发光元件40的密度可以大于或小于第一发光元件30的密度。即，第二子显示区第一子区A-R2的分辨率可以大于或小于第一子显示区第一子区A-R1的分辨率，第二子显示区第二子区B-R2的分辨率可以大于或小于第一子显示区第二子区B-R1的分辨率。
在一些示例性实施方式中，第二发光元件40的发光面积可以小于第一发光元件30的发光面积。即，第一发光元件30的发光面积大于第二发光元件40的发光面积。其中，发光元件的发光面积可以对应于像素定义层的开口的面积。在一些示例中，在第二子显示区第一子区A-R2和第二子显示区第二子区B-R2中，相邻的第二发光元件40之间设有透光区。例如，多个透光区彼此相连，形成被多个第二发光元件40间隔的连续透光区。导电线L可以采用透明导电材料制作以尽可能地提高透光区的透光率。
在一些示例性实施方式中，在第一子显示区第一子区A-R1和第一子显示区第二子区B-R1内，可以通过减小第一像素电路10在第二方向D2上的尺寸来获得设置第二像素电路20的区域。例如，第一像素电路10在第二方向D2上的尺寸可以小于第一发光元件30在第二方向D2上的尺寸。第二方向D2例如为子像素行方向，但不限于此。在另一些实施例中，第二方向D2可以为子像素列方向。本示例性实施方式以第二方向D2为子像素行方向为例进行说明。例如，第一像素电路10和第二像素电路20在第二方向D2上的尺寸可以相同，且每个像素电路在第二方向D2上的尺寸与第一发光元件30在第二方向D2上的尺寸可以相差约4微米(μm)。每个像素电路在第一方向D1上的尺寸与第一发光元件30在第一方向D1上的尺寸大致相同。其中，第一方向D1与第二方向D2垂直。
在一些示例性实施方式中，第一子显示区第一子区A-R1和第一子显示区第二子区B-R1内未与发光元件连接的第二像素电路20可以称为虚拟(Dummy)像素电路。
图3B至图3D为本公开至少一实施例的第一子显示区(第一子显示区第一子区A-R1或第一子显示区第二子区B-R1)的局部结构示意图。为了进一步体现出压缩像素电路后，多出多列像素电路，图3B示出了第一子显示区第一子区A-R1或第一子显示区第二子区B-R1的子像素的一种结构示意图。图3C示出了图3B中第一子显示区第一子区A-R1或第一子显示区第二子区B-R1的部分结构(仅包括像素电路)的示意图，图3D示出了图3B中第一子显示区第一子区A-R1或第一子显示区第二子区B-R1的部分结构(仅包括发光元件)的示意图。
在一些示例性实施方式中，如图3B至图3D所示，像素电路在第二方向D2上的尺寸较发光元件在第二方向D2上的尺寸小，如此，可以使得从右往左第2列和第9列的像素电路不连接任何第一发光元件30，属于多出列像素电路，其可以作为第二像素电路20以连接第二子显示区第一子区A-R2或第二子显示区第二子区B-R2内的第二发光元件40，或者仅作为不使用的第二像素电路20(即虚拟像素电路)。如图3D所示，任一第一发光元件30可以为RG1BG2共4种发光元件的一种。第一发光元件30的第一极E1可以通过第二转接电极CE2与第一像素电路10的第一转接电极CE1连接。R表示发红光的发光元件，G1表示发绿光的发光元件，B表示发蓝光的发光元件，G2表示发绿光的发光元件。至少一个第二像素电路20可以具有第一转接电极，至少一个第二发光元件40可以具有第二转接电极。例如，至少一个第二像素电路20和至少一个第二发光元件40通过导电线L连接可以包括：导电线L分别连接至少一个第二像素电路20的第一转接电极以及至少一个第二发光元件40的第二转接电极。为了具有充足的空间用来设置导电线L，同一行子像素中的第一转接电极和第二转接电极的轴线可以位于一条直线上。然而，本公开实施例对此并不限定。
在一些示例性实施方式中，图3D所示的子像素排列中，一个重复单元RP包括在第一方向D1上排列的两个绿色(G)子像素和分设在该两个绿色子像素在第二方向D2上的两侧的红色(R)子像素和蓝色(B)子像素。其中红色子像素和绿色子像素可以构成一个像素单元，并借用与其相邻的另一重复单元中的蓝色子像素构成一个虚拟像素以进行显示，其中蓝色子像素和绿色子像素可以构成一个像素单元，并借用与其相邻的另一重复单元中的红色子像素构成一个虚拟像素以进行显示。然而，本公开实施例对此并不限定。
在一些示例性实施方式中，为了提高第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的光透过率，可以在第二子显示区第一子区A-R2和第二子显示区第二子区B-R2仅设置发光元件，而将驱动第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的发光元件的像素电路设置在第一子显示区第一子区A-R1和第一子显示区第二子区B-R1内。即，通过发光元件和像素电路分离设置的方式来提高第二子显示区第一子区A-R2和第二 子显示区第二子区B-R2的光透过率。在本示例中，在第二子显示区第一子区A-R2和第二子显示区第二子区B-R2，不设置像素电路。
在另一些示例性实施方式中，可以在第二子显示区第一子区A-R2和第二子显示区第二子区B-R2设置发光元件以及驱动第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的发光元件的像素电路。例如，可以将驱动第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的发光元件的像素电路均设置在第二子显示区第一子区A-R2和第二子显示区第二子区B-R2内，此时，数据线可以没有额外的绕线。为提高第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的光透过率，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的信号线(包括但不限于数据线、电源线、扫描线等)可以使用透明金属，比如ITO走线。
在又一些示例性实施方式中，可以将驱动第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的部分发光元件的像素电路设置在第二子显示区第一子区A-R2和第二子显示区第二子区B-R2内，将驱动第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的另一部分发光元件的像素电路设置在第一子显示区第一子区A-R1和第一子显示区第二子区B-R1内。此时，至少部分外置的像素电路需要进行数据线的绕线。
在一些示例性实施方式中，如图3E所示，第二子显示区包括蓝色发光元件、红色发光元件和绿色发光元件，第二子显示区还包括至少一个与蓝色发光元件连接的第三像素电路，红色发光元件与位于第一子显示区的第二像素电路连接。
如图4A、4B和4C所示，考虑RGB子像素的启亮电压V R、V G、V B的关系如下:V R＜V G＜V B，可以将驱动第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的蓝色发光元件的像素电路设置在第二子显示区第一子区A-R2和第二子显示区第二子区B-R2内，将驱动第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的红色发光元件的像素电路设置在第一子显示区第一子区A-R1和第一子显示区第二子区B-R1内，这样，可以通过降低数据线绕线的电阻，来增加第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的红色发光元件的启亮电压，以避免红色子像素和蓝色子 像素启亮不一致。
在一些示例性实施方式中，第二子显示区中的绿色发光元件可以与位于第一子显示区的第二像素电路连接；和/或，如图3E所示，第二子显示区还可以包括至少一个第四像素电路，第二子显示区中的绿色发光元件可以与第四像素电路连接。
本实施例中，可以将驱动第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的绿色发光元件的像素电路设置在第二子显示区第一子区A-R2和第二子显示区第二子区B-R2内，也可以将驱动第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的绿色发光元件的像素电路设置在第一子显示区第一子区A-R1和第一子显示区第二子区B-R1内，本公开对此不作限制。
在一些示例性实施方式中，如图3E所示，显示基板还可以包括至少一个第五像素电路，该第五像素电路具有位于第一子显示区第一子区A-R1或第一子显示区第二子区B-R1的第一子部分以及位于第二子显示区第一子区A-R2或第二子显示区第二子区B-R2的第二子部分，其中，第一子部分和第二子部分共同驱动同一发光单元(该发光单元可以位于第一子显示区第一子区A-R1或第一子显示区第二子区B-R1内，也可以位于第二子显示区第一子区A-R2或第二子显示区第二子区B-R2)发光。该第五像素电路可以是3T1C、7T1C、8T1C等，本公开对此不做限制。此时，至少部分信号线(比如数据线)需要进行绕线设计。
下面对本实施例的像素电路(此处所述的像素电路可以是前述第一像素电路、第二像素电路、第三像素电路、第四像素电路和第五像素电路中的任意一个)进行举例说明。
图4D为本公开至少一实施例的像素电路的等效电路图。图4E为图4D所示的像素电路的工作时序图。
在一些示例性实施方式中，第一子显示区第一子区A-R1和第一子显示区第二子区B-R1的像素电路可以均为7T1C结构。然而，本公开实施例对此并不限定。例如，像素电路可以包括其他数目的晶体管和电容器，例如，可以为5T1C或6T1C等结构。
在一些示例性实施方式中，如图4D所示，像素电路均包括六个开关晶体管(T1、T2、T4至T7)、一个驱动晶体管T3和一个存储电容Cst。六个开关晶体管分别为数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1、以及第二复位晶体管T7。发光元件EL包括第一极E1、第二极E2以及位于第一极E1和第二极E2之间的有机发光层。例如，第一极E1可以为阳极，第二极E2可以为阴极。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一些可能的实现方式中，驱动晶体管和六个开关晶体管可以包括P型晶体管和N型晶体管。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例性实施方式中，如图4D和图4E所示，显示基板包括扫描线GL、数据线DL、第一电源线PL1、第二电源线PL2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2、第一复位控制线RST1和第二复位控制线RST2。在一些示例中，第一电源线PL1配置为向像素电路提供恒定的第一电压信号VDD，第二电源线PL2配置为向像素电路提供恒定的第二电压信号VSS，并且第一电压信号VDD大于第二电压信号VSS。扫描线GL配置为向像素电路提供扫描信号SCAN，数据线DL配置为向像素电路提供数据信号DATA，发光控制线EML配置为向像素电路提供发光控制信号EM，第一复位控制线RST1配置为向像素电路提供第一复位控制信号 RESET1，第二复位控制线RST2配置为向像素电路提供扫描信号SCAN。例如，在一行像素电路中，第二复位控制线RST2可以与扫描线GL相连，以被输入扫描信号SCAN。然而，本公开实施例对此并不限定。例如，第二复位控制线RST2可以被输入第二复位控制信号RESET2。例如，在第n行像素电路中，第一复位控制线RST1可以与第n-1行像素电路的扫描线GL连接，以被输入扫描信号SCAN(n-1)，即第一复位控制信号RESET1(n)与扫描信号SCAN(n-1)相同。在本示例中，第n行像素电路连接的第一复位控制线RST1与第n-1行像素电路连接的第二复位控制线RST2可以为一体结构。如此，可以减少显示基板的信号线，实现显示基板的窄边框。
在一些示例中，第一初始信号线INIT1和第二初始信号线INIT2可以提供相同的初始信号。例如，第n行像素电路连接的第一初始信号线INIT1与第n-1行像素电路连接的第二初始信号线INIT2可以为一体结构。然而，本公开实施例对此并不限定。
在一些示例性实施方式中，如图4D所示，在本实施例提供的像素电路中，驱动晶体管T3与发光元件EL电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号VDD、第二电压信号VSS等信号的控制下输出驱动电流以驱动发光元件EL发光。数据写入晶体管T4的栅极与扫描线GL相连，数据写入晶体管T4的第一极与数据线DL相连，数据写入晶体管T4的第二极与驱动晶体管T3的第一极相连。阈值补偿晶体管T2的栅极与扫描线GL相连，阈值补偿晶体管T2的第一极与驱动晶体管T3的栅极相连，阈值补偿晶体管T2的第二极与驱动晶体管T3的第二极相连。第一发光控制晶体管T5的栅极与发光控制线EML相连，第一发光控制晶体管T5的第一极与第一电源线PL1相连，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极相连。第二发光控制晶体管T6的栅极与发光控制线EML相连，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极相连，第二发光控制晶体管T6的第二极与发光元件EL的第一极E1相连。第一复位晶体管T1与驱动晶体管T3的栅极相连，并配置为对驱动晶体管T3的栅极进行复位，第二复位晶体管T7与发光元件EL的第一极E1相连，并配置为对发光元件EL的第一电极E1进行复位。第一复位晶体管T1的栅极与第一复位控制线RST1 相连，第一复位晶体管T1的第一极与第一初始信号线INIT1相连，第一复位晶体管T1的第二极与驱动晶体管T3的栅极相连。第二复位晶体管T7的栅极与第二复位控制线RST2相连，第二复位晶体管T7的第一极与第二初始信号线INIT2相连，第二复位晶体管T7的第二极与发光元件EL的第一极E1相连。存储电容Cst的第一电极与驱动晶体管T3的栅极相连，存储电容Cst的第二电极与第一电源线PL1相连。在本示例中，第一节点N1为存储电容Cst、第一复位晶体管T1、驱动晶体管T3和阈值补偿晶体管T2的连接点，第二节点N2为第一发光控制晶体管T5、数据写入晶体管T4和驱动晶体管T3的连接点，第三节点N3为驱动晶体管T3、阈值补偿晶体管T2和第二发光控制晶体管T6的连接点，第四节点N4为第二发光控制晶体管T6、第二复位晶体管T7和发光元件EL的连接点。
下面参照图4E对图4D示意的像素电路的工作过程进行说明。以像素电路包括的多个晶体管均为P型晶体管为例进行说明。
在一些示例性实施方式中，如图4E所示，在一帧显示时间段，第一结构的像素电路的工作过程包括：第一阶段A1、第二阶段A2和第三阶段A3。
第一阶段A1，称为复位阶段。第一复位控制线RST1提供的第一复位控制信号RESET1为低电平信号，使第一复位晶体管T1导通，第一初始信号线INIT1提供的初始信号Vinit被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中原有数据电压。扫描线GL提供的扫描信号SCAN为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6以及第二复位晶体管T7断开。此阶段发光元件EL不发光。
第二阶段A2，称为数据写入阶段或者阈值补偿阶段。扫描线GL提供的扫描信号SCAN为低电平信号，第一复位控制线RST1提供的第一复位控制信号RESET1和发光控制线EML提供的发光控制信号EM均为高电平信号，数据线DL输出数据信号DATA。此阶段由于存储电容Cst的第二电极为低电平，因此，驱动晶体管T3导通。扫描信号SCAN为低电平信号，使阈值补偿晶体管T2、数据写入晶体管T4和第二复位晶体管T7导通。阈值补偿 晶体管T2和数据写入晶体管T4导通，使得数据线DT输出的数据电压Vdata经过第二节点N2、导通的驱动晶体管T3、第三节点N3、导通的阈值补偿晶体管T2提供至第一节点N2，并将数据线DT输出的数据电压Vdata与驱动晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第二电极(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线DT输出的数据电压，Vth为驱动晶体管T3的阈值电压。第二复位晶体管T7导通，使得第二初始信号线INIT2提供的初始信号Vinit提供至发光元件EL的第一极E1，对发光元件EL的第一极E1进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件EL不发光。第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号，使第一复位晶体管T1断开。发光控制信号线EML提供的发光控制信号EM为高电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6断开。
第三阶段A3，称为发光阶段。发光控制信号线EML提供的发光控制信号EM为低电平信号，扫描线GL提供的扫描信号SCAN和第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号。发光控制信号线EML提供的发光控制信号EM为低电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6导通，第一电源线PL1输出的第一电压信号VDD通过导通的第一发光控制晶体管T5、驱动晶体管T3和第二发光控制晶体管T6向发光元件EL的第一极E1提供驱动电压，驱动发光元件EL发光。
在像素电路驱动过程中，流过驱动晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(VDD-Vdata+|Vth|)-Vth] 2＝K*[(VDD-Vdata)] 2。
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为驱动晶体管T3的栅极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据线DL输出的数据电压，VDD为第一电源线PL1输出的第一电压信号。
由上式中可以看到流经发光元件EL的电流与驱动晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿驱动晶体管T3的阈值电 压。
图5是第一显示区A的数据线局部布线方式示意图。图5中仅以若干条数据线和若干个第一像素电路10和第二像素电路20为例进行示意。在本示例中，显示基板在第二方向D2上具有中轴线，中轴线与轴线F交叠，显示基板可以关于中轴线对称。下面以第一显示区A的数据线排布为例进行说明。关于第二显示区B的数据线排布方式可以参照第一显示区A的数据线排布方式，故于此不再赘述。本实施方式所示的结构可以与其它实施方式所示的结构适当地组合。
在一些示例性实施方式中，边框区域R3包括数据驱动芯片区域，数据驱动芯片区域可以包括集成电路，配置为与显示区域的多条数据线连接。第二子显示区第一子区A-R2可以位于第一子显示区第一子区A-R1远离数据驱动芯片区域的一侧。
在一些示例性实施方式中，第一子显示区包括位于第二子显示区第一方向D1相对两侧的第一子显示区第一部和第一子显示区第二部、以及位于第二子显示区第二方向D2相对两侧的第一子显示区第三部。
示例性的，以第一子显示区第一子区A-R1为例，如图1和图5所示，第一子显示区第一子区A-R1包括：沿第一方向D1上位于第二子显示区第一子区A-R2相对两侧的第一子显示区第一子区第一部A-R11和第一子显示区第一子区第二部A-R12、以及沿第二方向D2上位于第二子显示区第一子区A-R2相对两侧的第一子显示区第一子区第三部A-R13。第一子显示区第一子区第三部包括第一子显示区第一子区第三部第一子部A-R13a和第一子显示区第一子区第三部第二子部A-R13b。第一子显示区第一子区第一部A-R11位于第二子显示区第一子区A-R2的下侧，第一子显示区第一子区第二部A-R12位于第二子显示区第一子区A-R2的上侧。第一子显示区第一子区第一部A-R11和第一子显示区第一子区第二部A-R12在第一方向D1上被第二子显示区第一子区A-R2隔开，第一子显示区第一子区第三部A-R13在第二方向D2上被第二子显示区第一子区A-R2隔开，即第一子显示区第一子区第三部第一子部A-R13a和第一子显示区第一子区第三部第二子部A-R13b在第二方向D2上位于第二子显示区第一子区A-R2的相对两侧。然而，本实施例 对此并不限定。例如，第一子显示区第一子区第二部A-R12在第二方向D2上可以连通，也可以被第二子显示区第一子区A-R2隔开。第一子显示区第一子区第三部第一子部A-R13a位于第二子显示区第一子区A-R2的左侧，第一子显示区第一子区第三部第二子部A-R13b位于第二子显示区第一子区A-R2的右侧。第一子显示区第一子区第三部第一子部A-R13a和第一子显示区第一子区第三部第二子部A-R13b之间被第一子显示区第一子区第一部A-R11、第二子显示区第一子区A-R2和第一子显示区第一子区第二部A-R12隔开。第一子显示区第一子区第三部第一子部A-R13a与第一子显示区第一子区第一部A-R11及第一子显示区第一子区第二部A-R12a连通，第一子显示区第一子区第三部第二子部A-R13b与第一子显示区第一子区第一部A-R11及第一子显示区第一子区第二部A-R12b连通。第一子显示区第二子区B-R1具有相似结构，在此不再赘述。第一子显示区第一子区第一部A-R11与第一子显示区第二子区第一部B-R11形成第一子显示区第一部，第一子显示区第一子区第二部A-R12与第一子显示区第二子区第二部B-R12形成第一子显示区第二部，第一子显示区第一子区第三部第一子部A-R13a、第一子显示区第一子区第三部第二子部A-R13b、第一子显示区第二子区第三部第一子部B-R13a与第一子显示区第二子区第三部第二子部B-R13b形成第一子显示区第三部。
在一些示例性实施方式中，如图1和图5所示，第一子显示区第一子区A-R1设置有多条第一数据线，第一子显示区第一子区A-R1包括第一子显示区第一子区第一部A-R11、第一子显示区第一子区第二部A-R12、第一子显示区第一子区第三部A-R13。边框区域R3设置有多条数据连接线64。至少一条第一数据线与第一子显示区第一子区第一部A-R11的至少一个像素电路连接，并通过至少一条数据连接线64与第一子显示区第一子区第二部A-R12的至少一个像素电路连接。例如，至少一条第一数据线与第一子显示区第一子区第一部A-R11的一列第一像素电路和第一子显示区第一子区第二部A-R12的一列第一像素电路连接。
在一些示例性实施方式中，如图1和图5所示，至少一条第一数据线包括：第一子数据线61、第二子数据线62和第三子数据线63。第三子数据线 63连接在第一子数据线61和第二子数据线62之间。第一子数据线61位于第一子显示区第一子区第一部A-R11并与第一子显示区第一子区第一部A-R11的一列第一像素电路连接。第二子数据线62位于第一子显示区第一子区第二部A-R12并与第一子显示区第一子区第二部A-R12的一列第一像素电路连接。第三子数据线63位于第一子显示区第一子区第三部A-R13，并延伸到第一子显示区第一子区第一部A-R11与第一子数据线61连接，以及与边框区域R3的数据连接线64连接。第三子数据线63与第一子显示区第一子区第三部A-R13中沿第一方向D1排布的多个第二像素电路连接。边框区域R3的数据连接线64与第一子显示区第一子区第二部A-R12的第二子数据线62连接。在本示例中，通过第一子数据线61、第三子数据线63和数据连接线64可以将驱动芯片区域提供的数据信号传输至第二子数据线62，利用第三子数据线63在第一子显示区第一子区第三部A-R13绕线后给第一子显示区第一子区第二部A-R12的像素电路提供数据信号，可以避免数据线在第二子显示区第一子区A-R2和第二子显示区第二子区B-R2直接布线而影响第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的光透过率，从而提高显示效果。
在一些示例性实施方式中，第一子显示区第一子区A-R1设置有阵列排布的像素电路。例如，第一子显示区第一子区第三部A-R13设置有n1列像素电路，第一子显示区第一子区第一部A-R11设置有n2列像素电路，第一子显示区第一子区第二部A-R12共设置有n3列像素电路。在本示例中，n3可以小于n2。然而，本公开实施例对此并不限定。例如，n3可以等于n2。
在一些示例性实施方式中，如图5和图6所示，在第一子显示区第一子区第一部A-R11内，第一子数据线61沿第一方向D1延伸，多条第一子数据线61沿第二方向D2依次排布。一条第一子数据线61可以与一列第一像素电路10连接，配置为将从驱动芯片区域引入的数据信号提供给对应的第一像素电路10。或者，一条第一子数据线61可以与一列第二像素电路连接。在第一子显示区第一子区第二部A-R12内，第二子数据线62可以沿第一方向D1延伸，多条第二子数据线62沿第二方向D2依次排布。一条第二子数据线62可以与第一子显示区第一子区第二部A-R12内的一列第一像素电路10 或一列第二像素电路20连接。第一子数据线61和第二子数据线62被第二子显示区第一子区A-R2隔断。在一些示例中，第一子数据线61和第二子数据线62可以为同层结构。
在一些示例性实施方式中，如图5和图6所示，在第一子显示区第一子区第三部A-R13内，第三子数据线63包括：相互连接的第一线段631和第二线段632。第一线段631沿第二方向D2延伸，多条第一线段631沿第一方向D1依次排布。第二线段632沿第一方向D1延伸，多条第二线段632沿第二方向D2依次排布。第一线段631的一端延伸到第一子显示区第一子区第一部A-R11与第一子数据线61连接，第一线段631的另一端在第一子显示区第一子区第三部A-R13与第二线段632连接。第二线段632与第一子显示区第一子区第三部A-R13内的多个沿第一方向D1排布的第二像素电路20连接。在一些示例中，第二线段632连接的多个第二像素电路20与第二子显示区第一子区A-R2的第二发光元件40连接。然而，本公开实施例对此并不限定。例如，第二线段632连接的多个第二像素电路20可以为虚拟像素电路，即可以不与发光元件连接。在一些示例中，第一线段631和第二线段632可以为异层结构。例如，第二线段632与第一子数据线61可以为同层结构，第一线段631与第一子数据线61可以为异层结构。在一些示例中，第一线段631和第二线段632可以为一体结构，且与第一子数据线61为异层结构。然而，本公开实施例对此并不限定。
在一些示例性实施方式中，如图5和图6所示，多条数据连接线64位于第二子显示区第一子区A-R2远离驱动芯片区域的一侧，例如，位于上边框区域内，从而扩大了布线空间，提升了PPI。至少一条数据连接线64包括：第一子数据连接线641、第二子数据连接线642和第三子数据连接线643。第一子数据连接线641和第三子数据连接线643沿第一方向D1延伸，第二子数据连接线642沿第二方向D2延伸。例如，多条第二子数据连接线642沿第二方向D2的长度可以相同。多条第一子数据连接线641和多条第三子数据连接线643沿第二方向D2依次排布，多条第二子数据连接线642沿第一方向D1依次排布。第二子数据连接线642分别与第一子数据连接线641和第三子数据连接线643连接。第一子数据连接线641与第三子数据线63的第 二线段632连接，第三子数据连接线643与第二子数据线62连接。在一些示例中，第一子数据连接线641和第三子数据连接线643为同层结构，且与第二子数据连接线642为异层结构。第二子数据连接线642可以与第三子数据线63的第二线段632和第二子数据线62为同层结构。然而，本公开实施例对此并不限定。
在一些示例性实施方式中，沿第二方向D2延伸的数据连接线(即第二子数据连接线642)在显示基板上的正投影与轴线F在显示基板上的正投影不交叠，避免了反复折叠对数据线造成不良，比如短路等，提升信赖性。
在一些示例性实施方式中，第一子数据线61连接的第一像素电路所连接的第一发光元件与其对应的第三子数据线63连接的第二像素电路所连接的第二发光元件可以位于同一列，第一子数据线61连接的第一像素电路所连接的第一发光元件与其对应的第二子数据线62连接的第一像素电路所连接的第一发光元件可以位于同一列。然而，本公开实施例对此并不限定。
在一些示例性实施方式中，如图5和图6所示，多条第三子数据线63的第一线段631沿第一方向D1排布，越靠近第二子显示区第一子区A-R2的第一线段631与越靠近中轴线F的第一子数据线61连接；越靠近第二子显示区第一子区A-R2的第一线段631与越远离中轴线F的第二线段632连接。沿着远离第二子显示区第一子区A-R2的第二方向D2，多条第二线段632在第一方向D2上的长度逐渐减小。沿着远离第二子显示区第一子区A-R2的第一方向D1，多条第一线段631在第二方向D2上的长度逐渐减小。然而，本公开实施例对此并不限定。例如，沿着远离第二子显示区第一子区A-R2的第一方向D1，多条第一线段631在第二方向D2上的长度不变。例如，沿着远离第二子显示区第一子区A-R2的第二方向D2，多条第二线段632在第一方向D2上的长度逐渐增加。
在一些示例性实施方式中，第一子显示区第一子区A-R1还设置有多条第二数据线71。多条第二数据线71均沿第一方向D1延伸，且沿着第二方向D2依次排布。第一子显示区第一子区A-R1内的第二数据线71无需进行绕线设计。至少一条第二数据线71可以与一列像素电路(第一像素电路或第二像素电路)连接。在一些示例性实施方式中，在第一子显示区第一子区第三 部A-R13内，针对一列第二像素电路20，一部分第二像素电路20与第三子数据线63的第二线段632连接，另一部分可以与第二数据线71连接，且第三子数据线63的第二线段632和第二数据线71断开。
在一些示例性实施方式中，沿第二方向D2延伸的子数据线(即第三子数据线63的第一线段631)在显示基板上的正投影与轴线F在显示基板上的正投影不交叠，避免了反复折叠对数据线造成不良，比如短路等，提升信赖性。
在一些示例性实施方式中，第一显示区A和第二显示区B可以关于轴线F对称设置。
在一些示例性实施方式中，第二子显示区第一子区A-R2周围的数据线绕线关于第二子显示区第一子区A-R2沿第二方向D2的中心轴E对称设置。第二子显示区第二子区B-R2周围的数据线绕线关于第二子显示区第一子区A-R2沿第二方向D2的中心轴E对称设置。
在一些示例性实施方式中，如图7和图8所示，第二子显示区第一子区A-R2设置到第一显示区A靠近轴线F的一侧。第二子显示区第二子区B-R2设置到第二显示区B靠近轴线F的一侧。
在一些示例性实施方式中，如图8所示，第二子显示区第一子区A-R2沿第二方向D2具有一中心线(几何中心)E。因靠近轴线F的布线空间的限制，第一子显示区第一子区A-R1设置有至少部分第一数据线，该部分第一数据线包括位于中心线E一侧的第二子数据线62(标记为62-1)和第一子数据线61(标记为61-1)以及位于中心线E另一侧的第二线段632(标记为632-1)，且该部分第一数据线的第一线段631(标记为631-1)与中心线E交叠，该部分第一数据线的数据连接线64(标记为64-1)与中心线E交叠。本实施例中，如图8所示，第一子显示区第一子区A-R1还可以设置另一部分第一数据线，该另一部分第一数据线的各个子数据线均位于中心线E到轴线F之间。第二子显示区第二子区B-R2可以具有同样的布线方式，在此不再赘述。
在一些示例性实施方式中，为了使得数据线总长度一致，达到更均一的显示效果，上述部分第一数据线中的数据连接线64-1相对于位于中心线E 另一侧的其他数据连接线64来说，更靠近第二子显示区第一子区A-R2，上述部分第一数据线中的第二线段632-1相对于位于中心线E另一侧的其他第二线段632更靠近第二子显示区第一子区A-R2，上述部分第一数据线中的第一线段631-1相对于位于中心线E另一侧的其他第一线段631更靠近第二子显示区第一子区A-R2。
在一些示例性实施方式中，第一显示区A和第二显示区B对称设置，则第二子显示区第一子区A-R2和第二子显示区第二子区B-R2之间设置有偶数条第三子数据线63绕线。
在一些示例性实施方式中，如图9所示，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2之间(箭头P的范围)不具有第三子数据线63绕线，从而可以将第二子显示区第一子区A-R2和第二子显示区第二子区B-R2布置的更为靠近。即第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的摄像头都更为靠近轴线F，但又与轴线F不交叠，有利于优化图像采集。
在一些示例性实施方式中，如图10所示，显示基板可以设置至少一条第一数据线，该第一数据线用于驱动位于第一显示区A的像素列，但具有位于第二显示区B的数据线绕线，或者，用于驱动位于第二显示区B的像素列，但具有位于第一显示区A的数据线绕线。示例性的，如图10所示，第二子数据线62-2和第一子数据线61-2均位于第一显示区A，第二线段632-2位于第二显示区B，第一线段631-2以及数据连接线64-2均跨越轴线F，即第一线段631-2以及数据连接线64-2均与轴线F具有交叠区域，如此，可以使得第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的左右绕线的各数据线总长度类似，进而使得各数据线的电阻值类似，达到均一的显示效果。
在一些示例性实施方式中，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的面积大小可以接近相同，或者，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的面积大小可以不同。当第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的面积大小不同时，数据线布线可以依据上述设计规则进行补偿设计，以优化实际显示效果。此时，可以根据实际需求在第二子显示区第一子区A-R2和第二子显示区第二子区B-R2 分别设置不同的传感器，例如，在第二子显示区第一子区A-R2和第二子显示区第二子区B-R2分别设置2个大小不同的主副图像采集传感器。
在一些示例性实施方式中，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2均可以设置一个或多个不同传感器，传感器包括但不限于：①图像采集传感器；②人脸识别传感器(可以采用3D成像技术，示例性的，如采用结构光3D成像法或飞行时间法，一个人脸识别传感器可以包括多个摄像头和深度传感器)；③指纹识别传感器等，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2均可以根据实际需求排列组合设置多个不同传感器中的一个或多个传感器。示例性的，第二子显示区第一子区A-R2可以设置有多个传感器，比如，1个图像采集传感器+1个人脸识别传感器；第二子显示区第二子区B-R2可以设置有指纹识别传感器等。
在一些示例性实施方式中，第二子显示区第一子区A-R2位于第一显示区A远离数据驱动芯片的一侧(即靠近显示基板上边框的一侧)，第二子显示区第二子区B-R2位于第二显示区B远离数据驱动芯片的一侧(即靠近显示基板上边框的一侧)。但本公开实施例对此不作限定，可以根据实际需要将第二子显示区第一子区A-R2和第二子显示区第二子区B-R2设置在显示基板的任意位置。
在一些示例性实施方式中，如图11所示，第二子显示区第一子区A-R2位于第一显示区A远离数据驱动芯片的一侧(即靠近显示基板上边框的一侧)，第二子显示区第二子区B-R2位于第二显示区B靠近数据驱动芯片的一侧(即靠近显示基板下边框的一侧)；或者，第二子显示区第一子区A-R2位于第一显示区A靠近数据驱动芯片的一侧(即靠近显示基板下边框的一侧)，第二子显示区第二子区B-R2位于第二显示区B远离数据驱动芯片的一侧(即靠近显示基板上边框的一侧)。
在一些示例性实施方式中，显示基板包括一个数据驱动芯片，该数据驱动芯片与第一显示区和第二显示区的数据线分别连接。如图12所示，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2均靠近上边框区域，显示基板还包括位于下边框区域的一个数据驱动芯片(Drive IC，DIC)。此时，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2分别覆盖不同的 多条数据线。
在一些示例性实施方式中，如图13所示，显示基板包括两个数据驱动芯片C-1、C-2，其中，一个数据驱动芯片C-1与第一显示区A的数据线连接，另一个数据驱动芯片C-2与第二显示区B的数据线连接。
在一些示例性实施方式中，如图14所示，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2沿第一方向D1设置，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2与至少一条相同的数据线连接。示例性的，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2位于同几列数据线上，此时，这几列数据线需要进行两次绕线。绕线规则同上述其他实施例，尽量使得数据线总长一致，以便于提升显示均一性。在一些示例性实施方式中，位于靠近边框区域的至少一列数据线的部分绕线可以位于边框区域。
在一些示例性实施方式中，如图15和图16所示，显示基板包括两个数据驱动芯片，其中，一个数据驱动芯片用于驱动第一数据线，另一个数据驱动芯片用于驱动第二数据线，第一数据线在第二子显示区第一子区A-R2和第二子显示区第二子区B-R2处具有绕线，第二数据线没有绕线。此时，如图15所示，两个数据驱动芯片可以位于显示基板的同侧，或者，如图16所示，两个数据驱动芯片可以位于显示基板的不同侧。如图15和图16所示，两个数据驱动芯片均可以弯折(bending)到显示基板的背侧，以实现窄边框。
在一些示例性实施方式中，如图16所示，与数据驱动芯片C-1连接的数据线长短有补偿设计，对于部分长度较短的的数据线，则应该设置到相对远离C-1的区域，或者用曲线绕线增加电阻进行补偿；相反，对于部分长度较长的数据线，则可以在周边区加粗数据线宽度，以减少电阻，使得驱动整列的数据线的总长度相近，以实现电阻相近，均一化显示效果。
图17为本公开示例性实施例一种显示基板的剖面结构示意图，示意了OLED显示基板一个子像素的结构。如图17所示，在垂直于显示基板的平面上，显示基板可以包括设置在衬底基板100上的驱动电路层102、设置在驱动电路层102远离衬底基板100一侧的发光结构层103以及设置在发光结构层103远离衬底基板100一侧的封装层104。在一些可能的实现方式中，显 示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在一些示例性实施方式中，衬底基板100可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容，图3中仅以一个晶体管101和一个存储电容101A作为示例。发光结构层103可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与驱动晶体管101的漏电极连接，像素定义层302包括暴露阳极301的第一开口，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在一些示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在一些示例性实施方式中，显示基板还可以包括设置在封装层104远离衬底基板100一侧的触控结构层105，触控结构层105可以包括第一触控结构层、覆盖第一触控结构的第一涂覆保护层以及设置在第一涂覆保护层上的第二触控结构层，第二触控结构层可以包括多个第一触控电极231、多个第二触控电极232和多个第一连接部，第一触控结构层可以包括多个第二连接 部，第一触控电极231和第二触控电极232中的至少一个通过贯穿第一涂覆保护层的过孔与第二连接部连接，多个第一触控电极231、多个第二触控电极232和多个第一连接部可以通过同一次构图工艺形成，第一触控电极和第一连接部可以为相互连接的一体结构。第二连接部可以通过过孔使相邻的第二触控电极相互连接。在一些可能的实现方式中，第一触控电极231可以包括通过第一连接部连接的多个第一子电极，第二触控电极232可以包括通过第二连接部连接的多个第二子电极。在一些可能的实现方式中，多个第一触控电极231、多个第二触控电极232和多个第一连接部可以同层设置在第一触控结构层，第二连接部可以设置在桥接层，本公开对此不作限制。在示例性实施方式中，第一触控电极231可以是驱动电极(Tx)，第二触控电极232可以是感应电极(Rx)，或者，第一触控电极231可以是感应电极(Rx)，第二触控电极232可以是驱动电极(Tx)。在另一些示例性实施例中，本公开实施例的触控结构层也可以是外嵌式触控(On Cell Touch)结构，本公开对此不作限制。
在示例性实施方式中，第一触控电极231和第二触控电极232可以具有菱形状，例如可以是正菱形，或者是横长的菱形，或者是纵长的菱形。在一些可能的实现方式中，第一触控电极231和第二触控电极232可以具有三角形、正方形、梯形、平行四边形、五边形、六边形和其它多边形中的任意一种或多种，本公开在此不做限定。
在示例性实施方式中，第一触控电极231和第二触控电极232可以是金属网格形式，金属网格由多条金属线交织形成，金属网格包括多个网格图案，网格图案是由多条金属线构成的多边形。所形成的金属网格式的第一触控电极和第二触控电极具有电阻小、厚度小和反应速度快等优点。在示例性实施方式中，一个网格图案中金属线所围成的区域包含显示结构层中子像素的区域，金属线所在位置位于相邻子像素之间。例如，当显示结构层为OLED显示结构层时，子像素的区域可以是发光结构层中像素界定层限定的发光区域，金属线所围成的区域包含发光区域，金属线位于像素界定层的对应位置，即位于非发光区域中。
在一些示例性实施方式中，显示基板还可以包括设置在触控结构层105 远离衬底基板100一侧的彩膜层106，彩膜层106可以包括不同颜色的彩色滤光片1062和设置在不同颜色的彩色滤光1062之间的黑矩阵1061，黑矩阵1061包括暴露彩色滤光片1062的第二开口。因常规的偏光片可折叠性较差，且透光率较差，本公开实施例利用彩膜层(CF on Encapsulation，COE)替代偏光片，形成了多功能层堆叠且折叠性较好的显示基板结构。
在一些示例性实施方式中，触控结构层105在衬底基板100上的正投影位于像素定义层302在衬底基板上的正投影范围之内，彩色滤光片1062在衬底基板100上的正投影包含有机发光层303在衬底基板100上的正投影。
在一些示例性实施方式中，显示基板还可以包括覆盖彩膜层106的降反射层107和设置在降反射层107上方的盖板108，降反射层107用于降低对于来自显示基板的出光侧的光线的反射率。
在一些示例性实施方式中，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2中的至少一个可以只包括衬底基板100以及设置在衬底基板100上的发光结构层103、封装层104和彩膜层106，即第二子显示区第一子区A-R2和第二子显示区第二子区B-R2中的至少一个可以不设置驱动电路层102和触控结构层105。
在另一些示例性实施方式中，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2中的至少一个可以只包括衬底基板100以及设置在衬底基板100上的发光结构层103、封装层104、触控结构层105和彩膜层106，即第二子显示区第一子区A-R2和第二子显示区第二子区B-R2中的至少一个可以不设置驱动电路层102。
在一些示例性实施方式中，像素定义层302可以为黑色材料，以区分第一子显示区第一子区A-R1和第二子显示区第一子区A-R2，或者，第一子显示区第二子区B-R1和第二子显示区第二子区B-R2。
在一些示例性实施方式中，位于第二子显示区第一子区A-R2或第二子显示区第二子区B-R2的黑矩阵1061在垂直于显示基板方向上的厚度，小于位于第一子显示区第一子区A-R1或第一子显示区第二子区B-R1的黑矩阵1061在垂直于显示基板方向上的厚度，以进一步提升第二子显示区第一子区A-R2或第二子显示区第二子区B-R2的光透光率。
在一些示例性实施方式中，彩色滤光片1062在垂直于显示基板方向上的最大厚度，大于黑矩阵1061在垂直于显示基板方向上的最大厚度，且彩色滤光片1062至少部分覆盖黑矩阵1061。本实施例中，彩色滤光片1062具有凸起的结构，形成凸透镜的效果，进一步提升出光效率。
在一些示例性实施方式中，如图18所示，触控结构层105可以位于第一子显示区第一子区A-R1和第一子显示区第二子区B-R1，触控结构层105还可以包括多根触控信号线TCL，触控信号线TCL用于将对应触控电极上加载的触控信号传输至触控驱动电路，第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的触控结构层105被去掉，因触控结构层的结构为金属网格(Metal Mesh)结构，去掉第二子显示区第一子区A-R2和第二子显示区第二子区B-R2的触控结构层105可以提升透过率。
在一些示例性实施方式中，第二子显示区在衬底基板上的正投影与第一连接部在衬底基板上的正投影不重叠，且第二子显示区在衬底基板上的正投影与第二连接部在衬底基板上的正投影不重叠。如图19所示，目前一个透明显示区(第二子显示区第一子区A-R2或第二子显示区第二子区B-R2)与一个触控电极块的大小基本一致(约4mm左右)，因此，以第二子显示区第一子区A-R2或第二子显示区第二子区B-R2中的1个挖孔为例，该挖孔可以刚好设置于一个触控电极块中，该触控电极块可以为RX电极块或TX电极块，从而可以使得挖孔区域避开触控桥而将透明显示区与一个触控电极块对应设置，以简化显示基板的设计。然而，本公开实施例对此不作限制。
在一些示例性实施方式中，位于挖孔区域的黑矩阵1061可以为环形结构(环绕子像素一圈)，且阴极304在挖孔区域不连续。
在一些示例性实施方式中，由于挖孔导致触控电极的电容值降低，可以对第二子显示区第一子区A-R2或第二子显示区第二子区B-R2周边的触控电极进行补偿设计。示例性的，如图20所示，在环绕挖孔的区域设计补偿电极，补偿电极同样为金属网格结构，优化可视性、降低Mura(指显示器亮度不均匀,产生各种痕迹的现象)。
在一些示例性实施方式中，如图21和图22A所示，触控结构层105还可以包括多个虚拟(Dummy)触控电极24，部分虚拟触控电极24与环绕挖 孔区域的触控电极块连接。
在一些示例性实施方式中，如图22A所示，第一触控电极231、第二触控电极232、虚拟触控电极24均绕着子像素(即像素定义层开口)设置。
在一些示例性实施方式中，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括一个出射第一颜色光线的第一子像素P1、一个出射第二颜色光线的第二子像素P2和二个出射第三颜色光线的第三子像素P3和第四子像素P4，四个子像素可以均包括电路单元和发光器件，电路单元可以包括扫描信号线、数据信号线和发光信号线和像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在一些示例性实施方式中，如图22B所示，在透明显示区(第二子显示区第一子区A-R2或第二子显示区第二子区B-R2)内，第一子像素P1的像素定义层开口在衬底基板上的正投影的图形呈水滴形，第二子像素P2的像素定义层开口在衬底基板上的正投影的图形呈圆形，第三子像素P3的像素定义层开口在衬底基板上的正投影的图形呈圆形。
在一些示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形。在另一些示例性实施方式中，像素单元P可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在一些示例性实施方式中，如图23所示，本公开实施例的显示基板还提供一种像素阵列，其包括多行第一像素行1和多行第二像素行2，且第一像素行1和第二像素行2交替设置。第一像素行1由交替设置的红色子像素01和蓝色子像素03交替设置形成，且多行第一像素行1中位于同一列的红色子像素01和蓝色子像素03同样交替设置。第二像素行2由多个绿色子像素02 并排设置形成，且绿色子像素02与相邻行中的红色子像素01和蓝色子像素03的交错设置。呈阵列排布的两个红色子像素01和两个蓝色子像素03中心的依次连线构成第一虚拟四边形10，且在每个第一虚拟四边形10内设置一个绿色子像素02；其中，第一虚拟四边形10的至少部分内角不等于90°；红色子像素01、绿色子像素02、蓝色子像素03中至少一者中的至少一个顶角的两边的延长线的交点到该子像素中心的距离，与其对角的两边的延长线的交点到该子像素的中心的距离不等。
在本公开实施例中通过对部分子像素的形状进行调整，使得由红色子像素01和蓝色子像素03的中心连线所形成的第一虚拟四边形10的至少部分内角不等于90°，且红色子像素01、绿色子像素02、蓝色子像素03中至少一者中的至少一个顶角的两边的延长线的交点到该子像素中心的距离，与其对角的两边的延长线的交点到该子像素的中心的距离不等，以调整每个虚拟像素单元中的实际亮度中心，使得整个显示面板中各个实际亮度中心分布更加均匀。
在一些示例性实施方式中，若蓝色子像素的03的第一角部为圆倒角和平倒角时，蓝色子像素的03第一角部的顶点到发光层边界的距离与其他顶角的顶点到发光层边界的距离不等。例如，蓝色子像素的03第一角部的顶点到边界存在一定的距离，而对于其他顶角则到该像素边界的距离大致为0。也即蓝色子像素的03第一角部的顶点到边界的距离大于其他顶角的顶点到蓝色子像素03边界的距离。
在一些示例性实施方式中，每个第一虚拟四边形10由呈阵列排布的两个红色子像素01和两个蓝色子像素03的中心依次连线形成，也即每个第一虚拟四边形10的四个顶角位置处分别设置两个红色子像素01和两个蓝色子像素03，其中两个红色子像素01设置在第一虚拟四边形10的两个相对设置的顶角位置处，两个蓝色子像素03设置在第一虚拟四边形10的另外两个相对设置的顶角位置处，每个第一虚拟四边形10的中心位置设置有一个绿色子像素02。四个第一虚拟四边形10组成一个第二虚拟四边形200，相邻的设置的第一虚拟四边形10共边。
在一些示例性实施方式中，如图23所示，蓝色子像素03的第一角部为 圆倒角，第二角部、第三角部及第四角部均包括类似直角。位于同一列的两个蓝色子像素03沿行方向对称设置。对于两相邻的第一像素行1中的一行各个蓝色子像素03的第一角部的朝向相同，另一行中的各个蓝色子像素03的第一角部朝向相反。
在一些示例性实施方式中，如图23所示，左上角第一个第一虚拟四边形10有一对角相等(图示为92°)，且另一角为90°，其他的第一虚拟四边形10至少有一角为90°，且该90°角的顶点位于红色像素的中心；每个红色子像素01周围的对角蓝色子像素03关于红色子像素01中心对称。
在一些示例性实施方式中，如图23所示，假设位于同一列的相邻设置的红色子像素01和蓝色子像素03的中心的连线为h，此时第二虚拟四边形100的为一个边长为2h的正方形，其中心位置为一个红色子像素01，对于每个第一虚拟四边形10内的绿色子像素02的中心位于在行方向或者列方向相邻设置的红色子像素01和蓝色子像素03中心连线的中线上。另外，如图23所示，每个第一虚拟四边形10内的绿色子像素02的中心到红色子像素01和蓝色子像素03发光区边界的垂直距离分别为a和b，其中，a＝b。
在一些示例性实施方式中，阳极301可以为Magic排布(即图23所示的排布方式，类似三阶魔方)。像素定义层302的第一开口的形状可以与阳极301边缘的形状一致。黑矩阵1061的第二开口的形状可以与像素定义层302的第一开口的形状一致。在一些示例性实施方式中，黑矩阵1061的第二开口可以外扩于像素定义层302的第一开口，此时像素定义层302可以采用黑色材料，以提升视角。在另一些示例性实施方式中，黑矩阵1061的第二开口可以内缩于像素定义层302的第一开口，此时，不限制像素定义层302的颜色，提升光学效果，降低反射。在又一些示例性实施方式中，黑矩阵1061的第二开口在显示基板上的正投影可以与像素定义层302的第一开口在显示基板上的正投影相交叠。
在一些示例性实施方式中，阳极301可以为Magic排布(即图23所示的排布方式)。像素定义层302的第一开口的形状可以与阳极301边缘的形状一致。黑矩阵1061的第二开口的形状可以为圆形或大致的圆形，本方案可以进一步改善暗态色分离。在一些示例性实施方式中，黑矩阵1061的第二开 口可以外扩于像素定义层302的开口，此时像素定义层302可以采用黑色材料，以提升视角。在另一些示例性实施方式中，黑矩阵1061的第二开口可以内缩于像素定义层302的第一开口，此时，不限制像素定义层302的颜色，提升光学效果，降低反射。在又一些示例性实施方式中，黑矩阵1061的第二开口在显示基板上的正投影可以与像素定义层302的第一开口在显示基板上的正投影相交叠。
在一些示例性实施方式中，阳极301可以为Magic排布(即图23所示的排布方式)，像素定义层302的第一开口的形状与黑矩阵1061的第二开口的形状可以均为圆形或大致的圆形，本方案也可以改善暗态色分离。在一些示例性实施方式中，黑矩阵1061的第二开口可以外扩于像素定义层302的第一开口，此时像素定义层302可以采用黑色材料，以提升视角。在另一些示例性实施方式中，黑矩阵1061的第二开口可以内缩于像素定义层302的第一开口，此时，不限制像素定义层302的颜色，提升光学效果，降低反射。在又一些示例性实施方式中，黑矩阵1061的第二开口在显示基板上的正投影可以与像素定义层302的第一开口在显示基板上的正投影相交叠。
在一些示例性实施方式中，在垂直于显示基板的方向上，显示基板包括多个绝缘层，绝缘层可以均采用黑色材料。
在一些示例性实施方式中，黑矩阵1061的第二开口的边界和像素定义层302的第一开口的边界之间的距离可以为0至6微米(μm)。
图24为本公开至少一实施例的显示装置的示意图。如图24所示，本实施例提供一种显示装置91，包括前述实施例的显示基板910。在一些示例中，显示基板910可以为OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。显示装置91可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本公开实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或 者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (20)

  1. 一种显示基板，包括：
    衬底基板，包括显示区域和至少位于所述显示区域一侧的边框区域，所述显示区域包括第一显示区和第二显示区，所述第一显示区包括第一子显示区第一子区和第二子显示区第一子区，所述第二显示区包括第一子显示区第二子区和第二子显示区第二子区，所述第一子显示区第一子区至少部分包围所述第二子显示区第一子区，所述第一子显示区第二子区至少部分包围所述第二子显示区第二子区，所述第一子显示区第一子区与所述第一子显示区第二子区形成第一子显示区，所述第二子显示区第一子区与所述第二子显示区第二子区形成第二子显示区；
    多个像素电路和多个第一发光元件，位于所述第一子显示区；所述多个像素电路包括：多个第一像素电路和多个第二像素电路，所述多个第二像素电路分布在所述多个第一像素电路之间；所述多个第一像素电路中的至少一个像素电路与所述多个第一发光元件中的至少一个发光元件连接；
    多个第二发光元件，位于所述第二子显示区；所述多个第二像素电路中的至少一个像素电路与所述多个第二发光元件中的至少一个发光元件连接；
    至少一条第一数据线，位于所述第一子显示区；所述第一数据线包括多条相互连接的子数据线，所述子数据线沿第一方向和/或第二方向延伸，所述第一方向与第二方向交叉；所述第一数据线至少包括一条子数据线与所述第一像素电路连接，且至少包括另一条子数据线与所述第二像素电路连接。
  2. 根据权利要求1所述的显示基板，其中，所述第二子显示区包括蓝色发光元件、红色发光元件和绿色发光元件，所述第二子显示区还包括至少一个与所述蓝色发光元件连接的第三像素电路，所述红色发光元件与位于所述第一子显示区的第二像素电路连接；
    所述绿色发光元件与位于所述第一子显示区的第二像素电路连接；和/或，所述第二子显示区还包括至少一个与所述绿色发光元件连接的第四像素电路。
  3. 根据权利要求1所述的显示基板，还包括至少一个第五像素电路，所述第五像素电路的一部分电路位于所述第一子显示区，另一部分电路位于所述第二子显示区。
  4. 根据权利要求1所述的显示基板，还包括位于所述第一子显示区和第二子显示区之间的虚拟轴线，所述虚拟轴线与折叠轴交叠，沿所述第二方向延伸的子数据线与所述虚拟轴线在所述显示基板上的正投影不交叠。
  5. 根据权利要求1所述的显示基板，其中，所述第一数据线包括依次连接的第一子数据线、第三子数据线、数据连接线和第二子数据线；
    所述第一子显示区包括位于所述第二子显示区第一方向相对两侧的第一子显示区第一部和第一子显示区第二部、以及位于第二子显示区第二方向相对两侧的第一子显示区第三部；
    所述第一子数据线位于所述第一子显示区第一部，所述第二子数据线位于所述第一子显示区第二部，所述第三子数据线位于所述第一子显示区第三部，所述数据连接线位于所述边框区域。
  6. 根据权利要求5所述的显示基板，其中，至少两条所述第一数据线的子数据线以所述第二子显示区第一子区沿第二方向的中心线为对称轴对称分布。
  7. 根据权利要求5所述的显示基板，其中，至少一条所述第一数据线包括位于所述第二子显示区第一子区沿所述第二方向的中心线的一侧的第一子数据线和第二子数据线，且包括位于所述第二子显示区第一子区沿所述第二方向的中心线的另一侧的第三子数据线。
  8. 根据权利要求7所述的显示基板，其中，在所述第一显示区内，与所述第二子显示区第一子区沿所述第二方向的中心线交叠的所述第一数据线，位于未与所述第二子显示区第一子区沿所述第二方向的中心线交叠的所述第一数据线靠近所述第二子显示区第一子区的一侧。
  9. 根据权利要求5所述的显示基板，其中，至少一条所述第一数据线包 括位于所述第一子显示区第一子区的部分子数据线，且包括位于所述第一子显示区第二子区的部分子数据线。
  10. 根据权利要求1所述的显示基板，还包括至少一个数据驱动芯片，所述数据驱动芯片位于边框区域，所述第二子显示区第一子区位于所述第一子显示区第一子区远离所述数据驱动芯片的一侧，所述第二子显示区第二子区位于所述第一子显示区第二子区靠近所述数据驱动芯片的一侧。
  11. 根据权利要求1所述的显示基板，还包括两个数据驱动芯片，其中，一个所述数据驱动芯片与所述第一显示区的数据线连接，另一个所述数据驱动芯片与所述第二显示区的数据线连接。
  12. 根据权利要求1所述的显示基板，其中，所述第一显示区和第二显示区以所述显示基板沿第一方向的中心线为对称轴对称分布。
  13. 根据权利要求12所述的显示基板，其中，所述第二子显示区第一子区以及所述第二子显示区第二子区以所述显示基板沿第一方向的中心线为对称轴对称分布，且所述第二子显示区第一子区以及所述第二子显示区第二子区位于相同的多根所述第一数据线之间。
  14. 根据权利要求13所述的显示基板，还包括两个数据驱动芯片和第二数据线，所述第二数据线与一列第一像素电路连接，其中，一个所述数据驱动芯片与所述第一数据线连接，另一个所述数据驱动芯片与所述第二数据线连接。
  15. 根据权利要求14所述的显示基板，其中，所述两个数据驱动芯片均位于所述边框区域的一侧，或者，所述两个数据驱动芯片位于所述边框区域的不同侧。
  16. 根据权利要求1所述的显示基板，其中，在垂直于所述显示基板的平面上，所述第一子显示区包括衬底基板以及依次叠设在所述衬底基板上的驱动电路层、发光结构层、封装层、触控结构层和彩膜层，所述第二子显示区包括衬底基板以及依次叠设在所述衬底基板上的发光结构层、封装层和彩 膜层。
  17. 根据权利要求16所述的显示基板，其中，所述彩膜层包括多个不同颜色的彩色滤光片以及设置在所述多个不同颜色的彩色滤光片之间的黑矩阵，所述第二子显示区的黑矩阵沿垂直于所述显示基板方向的厚度小于所述第一子显示区的黑矩阵沿垂直于所述显示基板方向的厚度。
  18. 根据权利要求17所述的显示基板，其中，所述发光结构层包括像素定义层、阳极、阴极和有机发光层，其中：
    所述像素定义层包括暴露所述阳极的第一开口，所述黑矩阵包括暴露所述彩色滤光片的第二开口，所述第二开口在所述衬底基板上的正投影包含所述第一开口在所述衬底基板上的正投影，所述像素定义层为黑色材料。
  19. 根据权利要求16所述的显示基板，其中，所述触控结构层包括沿第一方向排列的多个第一触控电极以及沿第二方向排列的多个第二触控电极，所述第一触控电极包括通过第一连接部连接的多个第一子电极，所述第二触控电极包括通过第二连接部连接的多个第二子电极，所述第二子显示区在所述衬底基板上的正投影与所述第一连接部在所述衬底基板上的正投影不重叠，且所述第二子显示区在所述衬底基板上的正投影与所述第二连接部在所述衬底基板上的正投影不重叠。
  20. 一种显示装置，包括：如权利要求1至19中任一项所述的显示基板。
PCT/CN2022/078075 2022-02-25 2022-02-25 显示基板及显示装置 WO2023159512A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110767662A (zh) * 2019-05-31 2020-02-07 昆山国显光电有限公司 显示基板、显示面板及显示装置
CN111180483A (zh) * 2019-04-04 2020-05-19 昆山国显光电有限公司 Oled阵列基板、显示面板及显示装置
CN111863920A (zh) * 2020-07-29 2020-10-30 京东方科技集团股份有限公司 显示面板及显示装置
CN111916486A (zh) * 2020-08-27 2020-11-10 武汉天马微电子有限公司 显示面板及显示装置
CN113327543A (zh) * 2021-05-28 2021-08-31 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置
CN113410269A (zh) * 2021-06-03 2021-09-17 武汉天马微电子有限公司 显示面板及显示装置
CN113972237A (zh) * 2020-07-24 2022-01-25 京东方科技集团股份有限公司 一种显示面板及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111180483A (zh) * 2019-04-04 2020-05-19 昆山国显光电有限公司 Oled阵列基板、显示面板及显示装置
CN110767662A (zh) * 2019-05-31 2020-02-07 昆山国显光电有限公司 显示基板、显示面板及显示装置
CN113972237A (zh) * 2020-07-24 2022-01-25 京东方科技集团股份有限公司 一种显示面板及显示装置
CN111863920A (zh) * 2020-07-29 2020-10-30 京东方科技集团股份有限公司 显示面板及显示装置
CN111916486A (zh) * 2020-08-27 2020-11-10 武汉天马微电子有限公司 显示面板及显示装置
CN113327543A (zh) * 2021-05-28 2021-08-31 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置
CN113410269A (zh) * 2021-06-03 2021-09-17 武汉天马微电子有限公司 显示面板及显示装置

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