WO2020238199A1 - 一种双面钝化接触的p型高效电池及其制备方法 - Google Patents

一种双面钝化接触的p型高效电池及其制备方法 Download PDF

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WO2020238199A1
WO2020238199A1 PCT/CN2019/129545 CN2019129545W WO2020238199A1 WO 2020238199 A1 WO2020238199 A1 WO 2020238199A1 CN 2019129545 W CN2019129545 W CN 2019129545W WO 2020238199 A1 WO2020238199 A1 WO 2020238199A1
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layer
oxide layer
polysilicon layer
ultra
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王涛
余波
杨蕾
张鹏
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通威太阳能（安徽）有限公司
通威太阳能（成都）有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
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    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the technical field of battery passivation, in particular to a P-type high-efficiency battery with double-sided passivation contact and a preparation method thereof.
  • HIT heterojunction structures
  • TOPCon tunnel oxide passivation contact
  • the aluminum oxide coating on the back side has the function of passivating the surface, it is inherently insulating and requires the use of laser to make grooves to make the back side aluminum back field contact with silicon to collect carriers.
  • the size of the laser aperture will affect The degree of surface recombination, but the disadvantage is that it will cause the battery's fill factor FF to be low, which has certain limitations and limits the further improvement of PERC battery efficiency.
  • the purpose of the present invention is to provide a P-type high-efficiency battery with double-sided passivation contacts and a preparation method thereof, so as to solve the problems raised in the background art.
  • a P-type high-efficiency battery with double-sided passivation contacts comprising P-type monocrystalline silicon, the P-type monocrystalline silicon is provided with an N-type emitter on the front side, and the N-type emitter is far away from the P-type monocrystalline silicon with a front side.
  • An ultra-thin silicon oxide layer, an N-type polysilicon layer is arranged above the front ultra-thin silicon oxide layer, and an oxide layer is arranged on both sides of the same plane of the front ultra-thin silicon oxide layer, and the N-type polysilicon layer and the oxide layer are arranged above There is a SiNx anti-reflection layer, and an Ag gate line is arranged on the N-type polysilicon layer, and the Ag gate line passes through the SiNx anti-reflection layer and is connected to the N-type polysilicon layer;
  • the back side of the P-type monocrystalline silicon is provided with a back ultra-thin silicon oxide layer
  • the back side of the ultra-thin silicon oxide layer is provided with a P-type polycrystalline silicon layer on the side away from the P-type monocrystalline silicon
  • Al is provided under the P-type polycrystalline silicon layer. Back field.
  • a method for preparing a P-type high-efficiency battery with double-sided passivation contact including the following steps: S1, cleaning and texturing: P-type monocrystalline silicon is cleaned to prepare a special texture structure to control the surface reflectivity of P-type monocrystalline silicon At 9-11%;
  • Preparation of front polysilicon prepare a front ultra-thin silicon oxide layer and an N-type polysilicon layer on the front surface of the P-type monocrystalline silicon that has been prepared.
  • the thickness of the front ultra-thin silicon oxide layer is controlled at 1-2nm. It is prepared by hot HNO 3 solution oxidation or dry oxidation, the thickness of the N-type polysilicon layer is controlled at 30-50nm, and it is prepared by PECVD;
  • Mask preparation a mask is prepared on the surface of the N-type polysilicon layer by screen printing, and the pattern of the mask is consistent with the pattern of the Ag gate line;
  • Etching Use a mixed solution of HNO 3 and HF to etch the front surface of the silicon wafer to remove the front ultra-thin silicon oxide layer and N-type polysilicon layer in the non-masked area, and then remove the mask;
  • Preparation of back polysilicon layer prepare a back ultra-thin silicon oxide layer and a P-type polysilicon layer on the back of P-type monocrystalline silicon.
  • the thickness of the back ultra-thin silicon oxide layer is controlled at 1-2nm, which uses thermal HNO. 3
  • the thickness of the P-type polysilicon layer is controlled at 30-50nm, which is prepared by PECVD;
  • SiNx anti-reflective layer on the front side prepare the SiNx anti-reflective layer on the front side of the silicon wafer by PECVD, with a thickness of 60-90nm and a refractive index of 2.08-2.12;
  • Printing Print Ag gate lines on the N-type polysilicon layer on the front side, and print Al back field on the P-type polysilicon layer on the back side.
  • the suede structure includes a pyramid shape and an inverted pyramid shape.
  • the concentration ratio of HNO 3 to HF used is 45%-50%:6%-8%.
  • the tunnel oxide layer passivation contact (TOPCon) structure of the present invention not only has a good chemical passivation effect, but also uses an ultra-thin oxide layer that allows electron hole tunneling and a layer of N-type or P-type doped polysilicon.
  • TOPCon tunnel oxide layer passivation contact
  • different doping types have different carrier selectivities, while avoiding direct contact between the metal electrode and the silicon substrate, reducing recombination and improving battery efficiency.
  • the invention uses the tunnel oxide layer to passivate the contact structure on both the front and back of the battery, and has a good surface passivation effect.
  • the silicon surface is passivated directly under the metal gate line on the front and under the aluminum back field on the back, avoiding metal Direct contact with the silicon base reduces surface recombination and improves battery conversion efficiency.
  • Figure 1 is a schematic diagram of the overall structure of the present invention.
  • Figure 2 is a flow chart of the preparation method of the present invention.
  • 1 P-type monocrystalline silicon 2 front ultra-thin silicon oxide layer, 3 N-type polysilicon layer, 4 N-type emitter, 5 oxide layer, 6 back ultra-thin silicon oxide layer, 7 P-type polysilicon layer, 8 SiNx Anti-reflection layer, 9 Ag grid lines, 10 Al back field.
  • a P-type high-efficiency battery with double-sided passivation contacts comprising P-type monocrystalline silicon 1, an N-type emitter 4 is arranged on the front of the P-type monocrystalline silicon 1, and the N-type emitter 4 is arranged far away from the P-type monocrystalline silicon 1.
  • the front ultra-thin silicon oxide layer 2 is provided with an N-type polysilicon layer 3 above the front ultra-thin silicon oxide layer 2, and the front ultra-thin silicon oxide layer 2 and the N-type polysilicon layer 3 are in the same vertical plane, and the N-type polysilicon layer 3
  • the front ultra-thin silicon oxide layer 2 is completely covered to form a very good tunnel oxide passivation contact structure.
  • the front ultra-thin silicon oxide layer 2 is provided with an oxide layer 5 on both sides of the same plane, which is formed by subsequent annealing and oxidation. It is a silicon oxide layer with the same thickness as the ultra-thin silicon oxide layer 2 on the front side.
  • a SiNx anti-reflection layer 8 is provided above the N-type polysilicon layer 3 and the oxide layer 5, and an Ag gate line 9 is provided on the N-type polysilicon layer 3. The wire 9 passes through the SiNx anti-reflection layer 8 and is connected to the N-type polysilicon layer 3.
  • the back side of the P-type single crystal silicon 1 is provided with a back ultra-thin silicon oxide layer 6, and the back side of the ultra-thin silicon oxide layer 6 is provided with a P-type polysilicon layer 7 on the side away from the P-type single crystal silicon 1, forming a passivation contact of the tunnel oxide layer on the back side Structure, an Al back field 10 is provided under the P-type polysilicon layer 7.
  • a method for preparing a P-type high-efficiency battery with double-sided passivation contact includes the following steps: S1, cleaning and texturing: P-type monocrystalline silicon 1 is cleaned to prepare a special suede structure, the suede structure includes pyramidal and inverted Pyramid shape, control the surface reflectivity of P-type monocrystalline silicon 1 at 9-11%;
  • Preparation of front polysilicon prepare a front ultra-thin silicon oxide layer 2 and an N-type polysilicon layer 3 on the front surface of the P-type monocrystalline silicon 1 where the texture has been prepared.
  • the thickness of the front ultra-thin silicon oxide layer 2 is controlled within 1-2nm, which is prepared by hot HNO3 solution oxidation or dry oxidation, the thickness of the N-type polysilicon layer 3 is controlled at 30-50nm, which is prepared by PECVD;
  • a mask is prepared on the surface of the N-type polysilicon layer 3 by screen printing, and the pattern of the mask is consistent with the pattern of the Ag gate line 9;
  • Preparation of the back polysilicon layer prepare a back ultra-thin silicon oxide layer 6 and a P-type polysilicon layer 7 on the back of the P-type single crystal silicon 1, and the thickness of the back ultra-thin silicon oxide layer 6 is controlled at 1-2nm, It is prepared by hot HNO 3 solution oxidation or dry oxidation, the thickness of the P-type polysilicon layer 7 is controlled at 30-50 nm, and it is prepared by PECVD;
  • SiNx anti-reflective layer 8 on the front side prepare SiNx anti-reflective layer 8 on the front side of the silicon wafer by PECVD method, with a thickness of 60-90 nm and a refractive index of 2.08-2.12;
  • Printing Print Ag gate lines 9 on the N-type polysilicon layer 3 on the front, the pattern is consistent with the mask pattern in S3, and print Al backfield 10 on the P-type polysilicon layer 7 on the back.
  • a method for preparing a P-type high-efficiency battery with double-sided passivation contacts includes the following steps:
  • the P-type monocrystalline silicon 1 is cleaned to prepare a special suede structure.
  • the suede structure includes a pyramid shape and an inverted pyramid shape, and the surface reflectance of the P-type monocrystalline silicon 1 is controlled to 10%;
  • Preparation of front polysilicon prepare a front ultra-thin silicon oxide layer 2 and an N-type polysilicon layer 3 on the front surface of the P-type monocrystalline silicon 1 where the texture has been prepared.
  • the thickness of the front ultra-thin silicon oxide layer 2 is controlled within 1nm, which is prepared by dry oxidation, the thickness of the N-type polysilicon layer 3 is controlled at 30nm, which is prepared by PECVD;
  • Mask preparation prepare a mask on the surface of the N-type polysilicon layer 3 by screen printing.
  • the pattern of the mask is consistent with the pattern of the Ag gate line 9.
  • Preparation of the backside polysilicon layer prepare a backside ultra-thin silicon oxide layer 6 and a P-type polysilicon layer 7 on the backside of the P-type single crystal silicon 1.
  • the thickness of the backside ultra-thin silicon oxide layer 6 is controlled at 1 nm, which uses It is prepared by hot HNO 3 solution oxidation or dry oxidation, and the thickness of the P-type polysilicon layer 7 is controlled at 30 nm, which is prepared by PECVD;
  • SiNx anti-reflection layer 8 is prepared on the front side of the silicon wafer by PECVD, and the thickness is controlled to be 60nm and the refractive index is 2.10;

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Abstract

一种双面钝化接触的P型高效电池以及制备方法。电池包括：P型单晶硅（1），N型发射极（4），远离P型单晶硅（1）设置的正面超薄氧化硅层（2），在P型单晶硅（1）的背面设置的背面超薄氧化硅层（6）。制备方法包括以下步骤：S1、清洗制绒；S2、正面多晶硅制备；S3、制备掩膜；S4、刻蚀；S5、扩散；S6、清洗；S7、退火；S8、背面多晶硅层制备；S9、正面SiNx减反射层制备；S10、印刷。

Description

一种双面钝化接触的P型高效电池及其制备方法 技术领域
本发明涉及电池钝化技术领域，具体为一种双面钝化接触的P型高效电池及其制备方法。
背景技术
统晶硅太阳能电池的效率近年来上升很快，市场对高效电池的需求与期望越来越高，各种新技术、新结构被采用在最近的高效电池生产中，比如异质结结构(HIT)和隧道氧化层钝化接触(TOPCon)结构等。
在太阳能电池的各项损失中，表面复合的损失占据了相当大的比重，而金属与硅基接触位置的复合损失也难以忽略。
在传统PERC电池中，正面栅线与发射极的接触不可避免，尽管可以使用选择性发射极(SE)技术使表面复合降低，但缺点是：金属与半导体的接触依然带来大量复合，使开路电压Voc和短路电流Isc受到损失。
背面的氧化铝镀层虽然起到了钝化表面的作用，但其本身具有绝缘性，需要使用激光进行开槽才能使背面铝背场与硅接触从而收集载流子，激光开口率的大小会影响到表面复合的程度，但缺点是：会导致电池的填充因子FF偏低，有一定局限性，限制了PERC电池效率的进一步提升。
上述使用选择性发射极(SE)和激光开槽的方式去减少表面复合降低，效果均不够好，缺陷较为明显，所以需要一种新型的双面钝化接触的电池去减小表面复合。
发明内容
本发明的目的在于提供一种双面钝化接触的P型高效电池及其制备方法，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：
一种双面钝化接触的P型高效电池，包括P型单晶硅，所述P型单晶硅 正面设置有N型发射极，所述N型发射极远离P型单晶硅设置有正面超薄氧化硅层，所述正面超薄氧化硅层上方设置有N型多晶硅层，且正面超薄氧化硅层同一平面的两侧设置有氧化层，所述N型多晶硅层和氧化层上方设置有SiNx减反射层，且N型多晶硅层上设置有Ag栅线，所述Ag栅线穿过SiNx减反射层连接于N型多晶硅层上；
所述P型单晶硅背面设置有背面超薄氧化硅层，所述背面超薄氧化硅层远离P型单晶硅一侧设置有P型多晶硅层，所述P型多晶硅层下方设置有Al背场。
一种双面钝化接触的P型高效电池的制备方法，包括以下步骤：S1、清洗制绒：将P型单晶硅经清洗后制备特殊绒面结构，控制P型单晶硅表面反射率在9-11％；
S2、正面多晶硅制备：在已制备出绒面的P型单晶硅正面制备一层正面超薄氧化硅层和一层N型多晶硅层，正面超薄氧化硅层的厚度控制在1-2nm，其采用热HNO 3溶液氧化或干法氧化法制备，N型多晶硅层的厚度控制在30-50nm，其采用PECVD法制备；
S3、制备掩膜：在N型多晶硅层表面用网版印刷法制备一层掩膜，掩膜的图形与Ag栅线图形一致；
S4、刻蚀：使用HNO 3与HF的混合溶液，对硅片正面进行刻蚀，去除非掩膜区域的正面超薄氧化硅层和N型多晶硅层，随后去除掩膜；
S5、扩散：在硅片的正面进行高温扩散，形成N型发射极；
S6、清洗：去除扩散形成的磷硅玻璃和边缘PN结；
S7、退火：在硅片的正面超薄氧化硅层平面上形成氧化层；
S8、背面多晶硅层制备：在P型单晶硅的背面制备一层背面超薄氧化硅层和一层P型多晶硅层，背面超薄氧化硅层的厚度控制在1-2nm，其采用热HNO 3溶液氧化或干法氧化法制备，P型多晶硅层的厚度控制在30-50nm，其采 用PECVD法制备；
S9、正面SiNx减反射层制备：在硅片正面以PECVD法制备SiNx减反射层，控制厚度在60-90nm、折射率在2.08-2.12；
S10、印刷：在正面的N型多晶硅层上印刷Ag栅线，并在背面的P型多晶硅层上印刷Al背场。
优选的，绒面结构包括金字塔形和倒金字塔形。
优选的，步骤S4中，所使用的HNO 3与HF浓度比为45％-50％：6％-8％。
与现有技术相比，本发明的有益效果是：
本发明的隧道氧化层钝化接触(TOPCon)结构不仅具备良好的化学钝化效果，利用一层超薄的允许电子空穴隧穿的氧化层与一层N型或P型掺杂的多晶硅组成的，不同的掺杂类型具备不同的载流子选择性，同时避免了金属电极与硅基体的直接接触，减小了复合，提高电池效率。
本发明在电池的正反两面均利用隧道氧化层钝化接触结构，具备良好的表面钝化效果，在正面金属栅线正下方和背面铝背场下方对硅表面进行了钝化，避免了金属与硅基的直接接触，减小表面复合，提升电池转换效率。
附图说明
图1为本发明的整体结构示意图；
图2为本发明的制备方法流程框图。
图中：1 P型单晶硅、2 正面超薄氧化硅层、3 N型多晶硅层、4 N型发射极、5 氧化层、6 背面超薄氧化硅层、7 P型多晶硅层、8 SiNx减反射层、9 Ag栅线、10 Al背场。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做 出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1-2，本发明提供一种技术方案：
一种双面钝化接触的P型高效电池，包括P型单晶硅1，P型单晶硅1正面设置有N型发射极4，N型发射极4远离P型单晶硅1设置有正面超薄氧化硅层2，正面超薄氧化硅层2上方设置有N型多晶硅层3，正面超薄氧化硅层2和N型多晶硅层3处于同一竖直面内，且N型多晶硅层3完全盖住正面超薄氧化硅层2，形成非常好的隧道氧化层钝化接触结构，正面超薄氧化硅层2同一平面的两侧设置有氧化层5，通过后续退火氧化形成，氧化层5为氧化硅层，与正面超薄氧化硅层2厚度相同，N型多晶硅层3和氧化层5上方设置有SiNx减反射层8，且N型多晶硅层3上设置有Ag栅线9，Ag栅线9穿过SiNx减反射层8连接于N型多晶硅层3上。
P型单晶硅1背面设置有背面超薄氧化硅层6，背面超薄氧化硅层6远离P型单晶硅1一侧设置有P型多晶硅层7，形成背面的隧道氧化层钝化接触结构，P型多晶硅层7下方设置有Al背场10。
一种双面钝化接触的P型高效电池的制备方法，包括以下步骤：S1、清洗制绒：将P型单晶硅1经清洗后制备特殊绒面结构，绒面结构包括金字塔形和倒金字塔形，控制P型单晶硅1表面反射率在9-11％；
S2、正面多晶硅制备：在已制备出绒面的P型单晶硅1正面制备一层正面超薄氧化硅层2和一层N型多晶硅层3，正面超薄氧化硅层2的厚度控制在1-2nm，其采用热HNO3溶液氧化或干法氧化法制备，N型多晶硅层3的厚度控制在30-50nm，其采用PECVD法制备；
S3、制备掩膜：在N型多晶硅层3表面用网版印刷法制备一层掩膜，掩膜的图形与Ag栅线9图形一致；
S4、刻蚀：使用HNO 3与HF的混合溶液，所使用的HNO 3与HF浓度比为45％-50％：6％-8％，对硅片正面进行刻蚀，去除非掩膜区域的正面超薄氧化硅 层2和N型多晶硅层3，随后去除掩膜；
S5、扩散：在硅片的正面进行高温扩散，形成N型发射极4；
S6、清洗：去除扩散形成的磷硅玻璃和边缘PN结；
S7、退火：在硅片的正面超薄氧化硅层2平面上形成氧化层5；
S8、背面多晶硅层制备：在P型单晶硅1的背面制备一层背面超薄氧化硅层6和一层P型多晶硅层7，背面超薄氧化硅层6的厚度控制在1-2nm，其采用热HNO 3溶液氧化或干法氧化法制备，P型多晶硅层7的厚度控制在30-50nm，其采用PECVD法制备；
S9、正面SiNx减反射层8制备：在硅片正面以PECVD法制备SiNx减反射层8，控制厚度在60-90nm、折射率在2.08-2.12；
S10、印刷：在正面的N型多晶硅层3上印刷Ag栅线9，图形与S3中的掩膜图形一致，并在背面的P型多晶硅层7上印刷Al背场10。
实施例一：
一种双面钝化接触的P型高效电池的制备方法，包括以下步骤：
S1、清洗制绒：将P型单晶硅1经清洗后制备特殊绒面结构，绒面结构包括金字塔形和倒金字塔形，控制P型单晶硅1表面反射率在10％；
S2、正面多晶硅制备：在已制备出绒面的P型单晶硅1正面制备一层正面超薄氧化硅层2和一层N型多晶硅层3，正面超薄氧化硅层2的厚度控制在1nm，其采用干法氧化法制备，N型多晶硅层3的厚度控制在30nm，其采用PECVD法制备；
S3、制备掩膜：在N型多晶硅层3表面用网版印刷法制备一层掩膜，掩膜的图形与Ag栅线9图形一致，将正面超薄氧化硅层2和N型多晶硅层3遮掩住；
S4、刻蚀：使用HNO 3与HF的混合溶液，所使用的HNO 3与HF浓度比为50％：8％，对硅片正面进行刻蚀，去除非掩膜区域的正面超薄氧化硅层2和N型多 晶硅层3，即将正面超薄氧化硅层2两侧的正面超薄氧化硅层2和N型多晶硅层3均去除掉，随后去除N型多晶硅层3上的掩膜；
S5、扩散：在硅片的正面进行高温扩散，形成N型发射极4；
S6、清洗：去除扩散形成的磷硅玻璃和边缘PN结；
S7、退火：在硅片的正面超薄氧化硅层2平面上形成氧化层5；
S8、背面多晶硅层制备：在P型单晶硅1的背面制备一层背面超薄氧化硅层6和一层P型多晶硅层7，背面超薄氧化硅层6的厚度控制在1nm，其采用热HNO 3溶液氧化或干法氧化法制备，P型多晶硅层7的厚度控制在30nm，其采用PECVD法制备；
S9、正面SiNx减反射层8制备：在硅片正面以PECVD法制备SiNx减反射层8，控制厚度在60nm、折射率在2.10；
S10、印刷：在正面的N型多晶硅层3上印刷Ag栅线9，并在背面的P型多晶硅层7上印刷Al背场10。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (4)

  1. 一种双面钝化接触的P型高效电池，包括P型单晶硅(1)，其特征在于：所述P型单晶硅(1)正面设置有N型发射极(4)，所述N型发射极(4)远离P型单晶硅(1)设置有正面超薄氧化硅层(2)，所述正面超薄氧化硅层(2)上方设置有N型多晶硅层(3)，且正面超薄氧化硅层(2)同一平面的两侧设置有氧化层(5)，所述N型多晶硅层(3)和氧化层(5)上方设置有SiNx减反射层(8)，且N型多晶硅层(3)上设置有Ag栅线(9)，所述Ag栅线(9)穿过SiNx减反射层(8)连接于N型多晶硅层(3)上；
    所述P型单晶硅(1)背面设置有背面超薄氧化硅层(6)，所述背面超薄氧化硅层(6)远离P型单晶硅(1)一侧设置有P型多晶硅层(7)，所述P型多晶硅层(7)下方设置有Al背场(10)。
  2. 一种双面钝化接触的P型高效电池的制备方法，其特征在于，包括以下步骤：S1、清洗制绒：将P型单晶硅(1)经清洗后制备特殊绒面结构，控制P型单晶硅(1)表面反射率在9-11％；
    S2、正面多晶硅制备：在已制备出绒面的P型单晶硅(1)正面制备一层正面超薄氧化硅层(2)和一层N型多晶硅层(3)，正面超薄氧化硅层(2)的厚度控制在1-2nm，其采用热HNO 3溶液氧化或干法氧化法制备，N型多晶硅层(3)的厚度控制在30-50nm，其采用PECVD法制备；
    S3、制备掩膜：在N型多晶硅层(3)表面用网版印刷法制备一层掩膜，掩膜的图形与Ag栅线(9)图形一致；
    S4、刻蚀：使用HNO 3与HF的混合溶液，对硅片正面进行刻蚀，去除非掩膜区域的正面超薄氧化硅层(2)和N型多晶硅层(3)，随后去除掩膜；
    S5、扩散：在硅片的正面进行高温扩散，形成N型发射极(4)；
    S6、清洗：去除扩散形成的磷硅玻璃和边缘PN结；
    S7、退火：在硅片的正面超薄氧化硅层(2)平面上形成氧化层(5)；
    S8、背面多晶硅层制备：在P型单晶硅(1)的背面制备一层背面超薄氧 化硅层(6)和一层P型多晶硅层(7)，背面超薄氧化硅层(6)的厚度控制在1-2nm，其采用热HNO 3溶液氧化或干法氧化法制备，P型多晶硅层(7)的厚度控制在30-50nm，其采用PECVD法制备；
    S9、正面SiNx减反射层(8)制备：在硅片正面以PECVD法制备SiNx减反射层(8)，控制厚度在60-90nm、折射率在2.08-2.12；
    S10、印刷：在正面的N型多晶硅层(3)上印刷Ag栅线(9)，并在背面的P型多晶硅层(7)上印刷Al背场(10)。
  3. 根据权利要求2所述的一种双面钝化接触的P型高效电池的制备方法，其特征在于：绒面结构包括金字塔形和倒金字塔形。
  4. 根据权利要求2所述的一种双面钝化接触的P型高效电池的制备方法，其特征在于：步骤S4中，所使用的HNO 3与HF浓度比为45％-50％：6％-8％。
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