WO2020233385A1 - 一种用于极低功耗电源转换器的模式控制电路 - Google Patents

一种用于极低功耗电源转换器的模式控制电路 Download PDF

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Publication number
WO2020233385A1
WO2020233385A1 PCT/CN2020/087986 CN2020087986W WO2020233385A1 WO 2020233385 A1 WO2020233385 A1 WO 2020233385A1 CN 2020087986 W CN2020087986 W CN 2020087986W WO 2020233385 A1 WO2020233385 A1 WO 2020233385A1
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Prior art keywords
drain
control circuit
metal oxide
type metal
oxide transistor
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PCT/CN2020/087986
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English (en)
French (fr)
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陈超
杨军
刘新宁
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东南大学
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Priority to US16/968,594 priority Critical patent/US11196335B2/en
Publication of WO2020233385A1 publication Critical patent/WO2020233385A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0041—Control circuits in which a clock signal is selectively enabled or disabled
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/1563—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators without using an external clock
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention relates to a control circuit, in particular to a mode control circuit for a very low power consumption power converter, and belongs to the technical field of analog circuits.
  • switched capacitor power converters have become one of the important structures for realizing the conversion of IO voltage to core voltage.
  • the above-mentioned power supply needs a continuous clock signal to maintain operation, and convert the IO voltage of about 3V to the core voltage of about 1V.
  • Clock generation circuits often use the core voltage to supply power to achieve optimal energy efficiency.
  • the power converter usually has a built-in clock generation circuit for startup.
  • the mode control signal is floating, and the control circuit needs to activate the built-in clock source by itself. After the core voltage is turned off, the circuit needs to switch from the external clock mode to the built-in clock mode by itself.
  • the present invention is aimed at the problems existing in the prior art and provides a mode control circuit for extremely low power consumption power converters.
  • the technical solution is used for the clock mode control of switched capacitor power converters.
  • the control circuit has the following requirements: at the beginning of power-on, the built-in clock of the power supply needs to be started to support the power converter; when the core voltage is established, the control circuit determines whether to switch to an external clock according to the level of the mode selection signal; After the voltage is off, the control circuit automatically wakes up the built-in clock to work.
  • a mode control circuit for a very low power consumption power converter is characterized in that the control circuit includes a first P-type metal oxide transistor PM1, a second P Type metal oxide transistor PM2, third P type metal oxide transistor PM3, fourth P type metal oxide transistor PM4, first N type metal oxide transistor NM1, second N type metal oxide transistor NM2, third N Type metal oxide transistor NM3, fourth N type metal oxide transistor NM4, fifth N type metal oxide transistor NM5 and sixth N type metal oxide transistor NM6, first capacitor C1 and second capacitor, first inverting
  • the source of the first P-type metal oxide transistor PM1 is connected to the power supply voltage
  • the gate of PM1 is connected to the first bias voltage VB1
  • the drain of PM1 is connected to the transimpedance amplifier.
  • the source of the second PMOS tube PM2 is connected to the input terminal of the transimpedance amplifier, the gate of PM2 is connected to the drain of the fifth PMOS tube PM5, and the drain of PM2 is connected to the output terminal of the transimpedance amplifier;
  • the source of the fifth PMOS tube PM5 is connected to the input terminal of the transimpedance amplifier, the gate of PM5 is connected to the drain of PM5;
  • the source of the third PMOS tube PM3 is connected to the input terminal of the transimpedance amplifier, and the gate of PM3 is connected to the second bias Set the voltage VB2,
  • the drain of PM3 is connected to the drain of the first N-type metal oxide transistor (hereinafter referred to as NMOS transistor) NM1, the gate of NM1 is connected to the third bias voltage VB3, and the source of NM1 is grounded;
  • the second NMOS transistor The gate of NM2 is connected to the drain of NM1, the drain of NM2 is connected to the drain of PM5, and the source of NM2 is
  • the circuit latches the initial value of the control voltage to the built-in clock source state through the capacitor C2, activates the built-in clock source and establishes the core voltage. After the core voltage is established, the mode selection control signal becomes effective. At this stage, in order to avoid the uncertainty caused by the floating of the control signal, a high-value resistor composed of NMOS transistors in the cut-off area is responsible for pulling the control signal to the ground, and a high-value resistor composed of PMOS transistors in the cut-off area is responsible for the control mode The status is locked in the built-in clock mode.
  • the circuit When the core voltage is powered down, the circuit locks the internal latch into the built-in clock mode through the PMOS high-value resistor to re-establish the core voltage.
  • the control circuit first starts the power built-in clock to support the power converter; when the core voltage is established, the control circuit determines whether to switch to an external clock according to the level of the mode selection signal ; When the core voltage is powered off, the control circuit automatically wakes up the built-in clock to work. This circuit has the characteristics of low power consumption and reliable operation.
  • the control circuit when the chip is powered on and the core voltage has not been established, the control circuit first starts the power built-in clock to support the work of the power converter; when the core voltage is established, the control circuit decides according to the level of the mode selection signal Whether to switch to an external clock; when the core voltage is powered off, the control circuit automatically wakes up the built-in clock to work.
  • the switched-capacitor power converter mode control circuit proposed by the present invention starts the built-in clock during the chip power-on phase to support the power converter; when the core voltage is established, the mode is selected
  • the signal level determines whether to switch to an external clock; when the core voltage is powered off, the control circuit can automatically wake up the built-in clock to work.
  • the circuit has the characteristics of low power consumption and reliable work.
  • the circuit has the function of automatically activating the on-chip clock and restoring the power supply.
  • Fig. 1 is a structural diagram of the power converter mode control circuit of the present invention
  • Figure 2 shows the mode control input, external clock enable control output, internal clock enable control output, and core voltage (top-down) of the power converter of the present invention in the startup state and the mode switching state.
  • Embodiment 1 Referring to Figure 1 and Figure 2, a mode control circuit for a very low-power power converter.
  • the control circuit includes a first P-type metal oxide transistor PM1 and a second P-type metal oxide transistor PM2, third P-type metal oxide transistor PM3, fourth P-type metal oxide transistor PM4, first N-type metal oxide transistor NM1, second N-type metal oxide transistor NM2, third N-type metal oxide transistor NM3, fourth N-type metal oxide transistor NM4, fifth N-type metal oxide transistor NM5, and sixth N-type metal oxide transistor NM6, first capacitor C1 and second capacitor, first inverter I1 and second Inverter I2, the source of the first P-type metal oxide transistor (hereinafter referred to as PMOS transistor) PM1 is connected to the high power supply voltage, the gate of PM1 is connected to the drain of the second PMOS transistor PM2, and the drain of PM1 is connected to the first N The drain of NM1 type metal oxide transistor (hereinafter referred to as NMOS transistor).
  • PMOS transistor the source of the first
  • the gate of NM1 is connected to the mode selection switch, the source of NM1 is grounded; the source of PM2 is connected to the high power supply voltage, the gate of PM2 is connected to the drain of PM1; the drain of the second NMOS tube NM2 is connected to the drain of PM2, and the drain of NM2
  • the gate is connected to the drain of the fourth NMOS tube NM4, the source of NM2 is grounded; the gate of NM4 is connected to the mode selection switch, the source of NM4 is grounded; the gate of the third NMOS tube NM3 is grounded, and the drain of NM3 is connected to the mode selection Switch, the source of NM3 is grounded; the positive electrode of the first capacitor C1 is connected to the mode selection switch, the negative electrode of C1 is grounded; the positive electrode of the second capacitor C2 is connected to the high power supply voltage, the negative electrode of C2 is connected to the drain of NM4; the third PMOS tube PM3 The source is connected to the high power supply voltage, the gate of PM3 is connected to
  • the source is connected to the core voltage; the input of the first inverter I1 is connected to the drain of PM2, and the output is connected to the external clock enable signal; the input of the second inverter I2 is connected to the drain of PM1, and the output is connected to the built-in clock enable signal.
  • FIG. 2 shows the mode control input, external clock enable control output, internal clock enable control output, and core voltage (top-down) of the power converter of the present invention in the startup state and the mode switching state;
  • the controller turns on the built-in clock enable to quickly establish the core voltage.
  • the controller quickly switches to the external clock mode.
  • the mode control output signal automatically switches to the built-in clock mode, restarts the built-in oscillator and drives the power supply within 0.1 milliseconds
  • the converter re-establishes the core voltage.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

本发明公开了一种用于极低功耗电源转换器的模式控制电路，由电平移位电路、启动电路、静态箝位电路、控制电路等四个模块组成。当芯片上电，内核电压尚未建立时，控制电路先启动电源内建时钟以支持电源转换器工作；当内核电压建立完成，控制电路根据模式选择信号的电平决定是否切换到外接时钟；当内核电压掉电后，控制电路自动唤醒内建时钟工作。

Description

一种用于极低功耗电源转换器的模式控制电路 技术领域
本发明涉及一种控制电路，具体涉及一种用于极低功耗电源转换器的模式控制电路，属于模拟电路技术领域。
背景技术
为追求高能量转换效率，开关电容电源转换器成为实现IO电压向内核电压转换的重要结构之一。与传统的静态线性稳压器不同的是，上述电源需要持续的时钟信号来维持运作，将3V左右的IO电压转换为1V附近的内核电压。时钟产生电路往往使用内核电压供电以达到最优能效。而在电源转换器启动瞬间，输出内核电压尚未建立，此时时钟电路将无法启动，会造成电源转换器锁死的情况。为克服此问题，电源转换器中通常内建时钟产生电路用于启动，当内核电压建立完毕后可以选择继续使用内建时钟或者使用低频常开振荡器时钟。此外，在上电伊始模式控制信号悬空，需要控制电路自行激活内建时钟源。在内核电压关闭后，需要电路自行由外部时钟模式切换至内建时钟模式。
发明内容
本发明正是针对现有技术中存在的问题，提供一种用于极低功耗电源转换器的模式控制电路，该技术方案用于开关电容电源转换器的时钟模式控制，开关电容电源转换器对控制电路有以下需求：在上电初始，需要先启动电源内建时钟以支持电源转换器工作；当内核电压建立完成，控制电路根据模式选择信号的电平决定是否切换到外接时 钟；当内核电压掉电后，控制电路自动唤醒内建时钟工作。
为了实现上述目的，本发明的技术方案如下，一种用于极低功耗电源转换器的模式控制电路，其特征在于，所述控制电路包括第一P型金属氧化物晶体管PM1、第二P型金属氧化物晶体管PM2、第三P型金属氧化物晶体管PM3、第四P型金属氧化物晶体管PM4、第一N型金属氧化物晶体管NM1、第二N型金属氧化物晶体管NM2、第三N型金属氧化物晶体管NM3、第四N型金属氧化物晶体管NM4、第五N型金属氧化物晶体管NM5以及第六N型金属氧化物晶体管NM6，第一电容C1和第二电容，第一反相器I1和第二反相器I2，所述第一P型金属氧化物晶体管PM1的源极接电源电压，PM1的栅极接第一偏置电压VB1，PM1的漏极接所述跨阻放大器的输入端；第二PMOS管PM2的源极接所述跨阻放大器的输入端，PM2的栅极接第五PMOS管PM5的漏极，PM2的漏极接所述跨阻放大器的输出端；第五PMOS管PM5的源极接跨阻放大器的输入端，PM5的栅极接PM5的漏极；第三PMOS管PM3的源极接跨阻放大器的输入端，PM3的栅极接第二偏置电压VB2，PM3的漏极接第一N型金属氧化物晶体管(以下简称NMOS管)NM1的漏极，NM1的栅极接第三偏置电压VB3，NM1的源极接地；第二NMOS管NM2的栅极接NM1的漏极，NM2的漏极接PM5的漏极，NM2的源极接地；第一电阻R1的正极接跨阻放大器的输出端，R1的负极接地；第四PMOS管PM4的源极接电源电压，PM4的栅极接第一偏置电压VB1，PM4的漏极接PM5的漏极。当输入高电压电源上电，电路通过电容C2将控制电压初始值锁存至内建时钟源状态，激活内建时钟 源并建立内核电压。内核电压建立完成后，模式选择控制信号开始有效。在此阶段为避免控制信号浮空造成的不确定性，一个由截止区NMOS晶体管组成的高值电阻负责将控制信号拉到地，而一个由截止区PMOS管构成的高值电阻负责将控制模式的状态锁定在内建时钟模式。当内核电压掉电时，电路通过PMOS高值电阻使内部锁存器锁定在内建时钟模式，重新建立内核电压。当芯片上电，电源转换器尚未建立内核电压时，控制电路先启动电源内建时钟以支持电源转换器工作；当内核电压建立完成，控制电路根据模式选择信号的电平决定是否切换到外接时钟；当内核电压掉电后，控制电路自动唤醒内建时钟工作。该电路具有功耗低、工作可靠的特点。
作为本发明的一种改进，当芯片上电，内核电压尚未建立时，控制电路先启动电源内建时钟以支持电源转换器工作；当内核电压建立完成，控制电路根据模式选择信号的电平决定是否切换到外接时钟；当内核电压掉电后，控制电路自动唤醒内建时钟工作。
相对于现有技术，本发明具有如下优点，本发明提出的开关电容电源转换器模式控制电路，在芯片上电阶段启动内建时钟以支持电源转换器工作；当内核电压建立完成，根据模式选择信号的电平决定是否切换到外接时钟；当内核电压掉电后，控制电路可自动唤醒内建时钟工作。该电路具有功耗低、工作可靠的特点，同时，当输入时钟受外界干扰掉电时，该电路具备自动激活片内时钟，恢复供电的功能。
附图说明
图1为本发明的电源转换器模式控制电路结构图；
图2为本发明的电源转换器在启动状态和模式切换状态的模式控制输入、外部时钟使能控制输出、内部时钟使能控制输出、内核电压(自上而下)。
具体实施方式
为了加深对本发明的理解，下面结合附图对本实施例做详细的说明。
实施例1：参见图1、图2，一种用于极低功耗电源转换器的模式控制电路，所述控制电路包括第一P型金属氧化物晶体管PM1、第二P型金属氧化物晶体管PM2、第三P型金属氧化物晶体管PM3、第四P型金属氧化物晶体管PM4、第一N型金属氧化物晶体管NM1、第二N型金属氧化物晶体管NM2、第三N型金属氧化物晶体管NM3、第四N型金属氧化物晶体管NM4、第五N型金属氧化物晶体管NM5以及第六N型金属氧化物晶体管NM6，第一电容C1和第二电容，第一反相器I1和第二反相器I2，第一P型金属氧化物晶体管(以下简称PMOS管)PM1的源极接高电源电压，PM1的栅极接第二PMOS管PM2的漏极，PM1的漏极接第一N型金属氧化物晶体管(以下简称NMOS管)NM1的漏极。NM1的栅极接模式选择开关，NM1的源极接地；PM2的源极接高电源电压，PM2的栅极接PM1的漏极；第二NMOS管NM2的漏极接PM2的漏极，NM2的栅极接第四NMOS管NM4的漏极，NM2的源极接地；NM4的栅极接模式选择开关，NM4的源极接地；第三NMOS管NM3的栅极接地，NM3的漏极接模式选择开关，NM3的源极接地；第一电容C1的正极接模式选择开关，C1的负极接地；第二电容C2的正极接高电源 电压，C2的负极接NM4的漏极；第三PMOS管PM3的源极接高电源电压，PM3的栅极接高电源电压，PM3的漏极接NM4的漏极；第五NMOS管NM5的漏极接NM2的漏极，NM5的栅极接第六NMOS管NM6的漏极，NM5的源极接地；NM6的栅极接模式选择开关，NM6的源极接地；第四PMOS管PM4的漏极接NM6的漏极，PM4的栅极接模式选择开关，PM4的源极接内核电压；第一反相器I1的输入接PM2的漏极，输出接外接时钟使能信号；第二反相器I2的输入接PM1的漏极，输出接内置时钟使能信号。
图2所示为图2为本发明的电源转换器在启动状态和模式切换状态的模式控制输入、外部时钟使能控制输出、内部时钟使能控制输出、内核电压(自上而下)；从图中可以看出，在上电初始阶段，内核电压尚未建立，此时控制器开启内建时钟使能，快速建立内核电压。当输入控制信号切换至外接时钟模式，控制器迅速切换到外接时钟模式。当电源电压因突发状况掉电，并引发外部时钟和输入控制信号同时掉电，此时模式控制输出信号自行切换至内建时钟模式，在0.1毫秒时间内重新启动内建振荡器并驱动电源转换器重新建立内核电压。
工作原理：参见图1、图2，当输入高电压电源上电，电路通过电容C2将控制电压初始值锁存至内建时钟源状态，激活内建时钟源并建立内核电压。内核电压建立完成后，模式选择控制信号开始有效。在此阶段为避免控制信号浮空造成的不确定性，一个由截止区晶体管NM3组成的高值电阻负责将控制信号拉到地，而一个由截止区PMOS管PM3构成的高值电阻负责将控制模式的状态锁定在内建时钟模式。 当内核电压掉电时，电路通过PM3高值电阻使内部锁存器锁定在内建时钟模式，重新建立内核电压。
需要说明的是上述实施例，并非用来限定本发明的保护范围，在上述技术方案的基础上所作出的等同变换或替代均落入本发明权利要求所保护的范围。

Claims (2)

  1. 一种用于极低功耗电源转换器的模式控制电路，其特征在于，所述控制电路包括第一P型金属氧化物晶体管PM1、第二P型金属氧化物晶体管PM2、第三P型金属氧化物晶体管PM3、第四P型金属氧化物晶体管PM4、第一N型金属氧化物晶体管NM1、第二N型金属氧化物晶体管NM2、第三N型金属氧化物晶体管NM3、第四N型金属氧化物晶体管NM4、第五N型金属氧化物晶体管NM5以及第六N型金属氧化物晶体管NM6，第一电容C1和第二电容，第一反相器I1和第二反相器I2，所述第一P型金属氧化物晶体管PM1的源极接电源电压，PM1的栅极接第一偏置电压VB1，PM1的漏极接所述跨阻放大器的输入端；第二PMOS管PM2的源极接所述跨阻放大器的输入端，PM2的栅极接第五PMOS管PM5的漏极，PM2的漏极接所述跨阻放大器的输出端；第五PMOS管PM5的源极接跨阻放大器的输入端，PM5的栅极接PM5的漏极；第三PMOS管PM3的源极接跨阻放大器的输入端，PM3的栅极接第二偏置电压VB2，PM3的漏极接第一N型金属氧化物晶体管(以下简称NMOS管)NM1的漏极，NM1的栅极接第三偏置电压VB3，NM1的源极接地；第二NMOS管NM2的栅极接NM1的漏极，NM2的漏极接PM5的漏极，NM2的源极接地；第一电阻R1的正极接跨阻放大器的输出端，R1的负极接地；第四PMOS管PM4的源极接电源电压，PM4的栅极接第一偏置电压VB1，PM4的漏极接PM5的漏极。
  2. 根据权利要求1所述的用于极低功耗电源转换器的模式控制电路，其特征在于：当芯片上电，内核电压尚未建立时，控制电路先启 动电源内建时钟以支持电源转换器工作；当内核电压建立完成，控制电路根据模式选择信号的电平决定是否切换到外接时钟；当内核电压掉电后，控制电路自动唤醒内建时钟工作。
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