WO2020232920A1 - 阵列基板及其制备方法 - Google Patents

阵列基板及其制备方法 Download PDF

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Publication number
WO2020232920A1
WO2020232920A1 PCT/CN2019/105900 CN2019105900W WO2020232920A1 WO 2020232920 A1 WO2020232920 A1 WO 2020232920A1 CN 2019105900 W CN2019105900 W CN 2019105900W WO 2020232920 A1 WO2020232920 A1 WO 2020232920A1
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dielectric
layer
dielectric pattern
array substrate
pattern
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PCT/CN2019/105900
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English (en)
French (fr)
Inventor
贺超
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武汉华星光电技术有限公司
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Priority to US16/614,565 priority Critical patent/US11069632B2/en
Publication of WO2020232920A1 publication Critical patent/WO2020232920A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves

Definitions

  • This application relates to the field of display technology, in particular to an array substrate and a preparation method thereof.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • CRT Cathode Radial Tube
  • plasma displays In the production process of TFT-LCD display panels, the gate insulating layer in the array substrate is relatively Static electricity is likely to occur, which can damage the thin film transistors in the array substrate and cause poor display.
  • an auxiliary dielectric pattern is added to the array substrate in this application, so that the auxiliary dielectric pattern absorbs most of the static electricity in the gate insulating layer, thereby reducing the phenomenon of poor display of the array substrate.
  • an array substrate which includes:
  • a plurality of shielding layers arranged at intervals are arranged on the substrate;
  • a dielectric layer is laid on the substrate and covers a shielding layer, the dielectric layer includes a patterned dielectric pattern, the dielectric pattern includes a main dielectric pattern, and is located on at least one side of the main dielectric pattern Auxiliary dielectric pattern;
  • the gate insulating layer is arranged on the dielectric layer.
  • the dielectric layer is used to absorb static electricity in the gate insulating layer, and the cross-sectional area of the auxiliary dielectric pattern is larger than the cross-sectional area of the main dielectric pattern.
  • the main dielectric pattern partially overlaps with the shielding layer, forming an overlapping area and a non-overlapping area;
  • the auxiliary dielectric pattern does not overlap with the shielding layer, and the auxiliary dielectric pattern is provided between two adjacent main dielectric patterns.
  • the array substrate further includes a thin film transistor layer disposed above the gate insulating layer, the thin film transistor layer includes a plurality of thin film transistors, and the position of the thin film transistor is different from the position of the thin film transistor.
  • the position of the main dielectric pattern corresponds;
  • the source of the thin film transistor is at the overlapping area, and the drain of the thin film transistor at the non-overlapping area is electrically connected to the dielectric layer through via holes.
  • the dielectric layer is used to absorb static electricity in the gate insulating layer, and the cross-sectional area of the auxiliary dielectric pattern is larger than the cross-sectional area of the main dielectric pattern .
  • conductive particles for absorbing static electricity in the gate insulating layer are implanted in the dielectric layer, and the number of positively charged particles and negatively charged particles in the conductive particles are the same .
  • the array substrate further includes a metal shielding layer for shielding static electricity in the gate insulating layer;
  • the metal shielding layer includes a first shielding layer and a second shielding layer, the first shielding layer is disposed between the shielding layer and the dielectric layer, and the second shielding layer is disposed on the gate. Between the polar insulating layer and the dielectric layer.
  • the auxiliary dielectric pattern is provided with a first dielectric capacitor
  • the main dielectric pattern is provided with a second dielectric capacitor
  • the dielectric of the first dielectric capacitor is The dielectric constant is greater than the dielectric constant of the second dielectric capacitor.
  • the distance between the main dielectric pattern and the auxiliary dielectric pattern is less than or equal to the distance between the adjacent shielding layers.
  • the cross-sectional area of the auxiliary dielectric pattern is in the range of 40-50 square microns, and the cross-sectional area of the main dielectric pattern is in the range of 10-15 square microns.
  • the present application also provides a method for manufacturing an array substrate, the method including:
  • a dielectric layer is formed on a plurality of shielding layers arranged at intervals, the dielectric layer includes a patterned dielectric pattern, the dielectric pattern includes a main dielectric pattern, and at least one side of the main dielectric pattern Auxiliary dielectric pattern;
  • a gate insulating layer is photoetched on the dielectric layer.
  • the photoetching of the dielectric layer on the surface provided with a plurality of shielding layers arranged at intervals specifically includes:
  • Conductive particles are implanted into the dielectric layer material after photolithography to form the dielectric layer.
  • the main dielectric pattern partially overlaps the shielding layer to form an overlapping area and a non-overlapping area, and a gate insulating layer is formed above the dielectric layer
  • the main dielectric pattern partially overlaps the shielding layer to form an overlapping area and a non-overlapping area, and a gate insulating layer is formed above the dielectric layer
  • the thin film transistor layer including a plurality of thin film transistors, the positions of the thin film transistors correspond to the positions of the main dielectric pattern;
  • the source of the thin film transistor is at the overlapping area, and the drain of the thin film transistor at the non-overlapping area is electrically connected to the dielectric layer through via holes.
  • the application also provides an array substrate, which includes:
  • a plurality of shielding layers arranged at intervals are arranged on the substrate;
  • a dielectric layer is laid on the substrate and covers a shielding layer, the dielectric layer includes a patterned dielectric pattern, the dielectric pattern includes a main dielectric pattern, and is located on at least one side of the main dielectric pattern Auxiliary dielectric pattern;
  • a gate insulating layer disposed on the dielectric layer
  • the main dielectric pattern partially overlaps with the shielding layer, forming an overlapping area and a non-overlapping area;
  • the auxiliary dielectric pattern and the shielding layer do not overlap, and the auxiliary dielectric pattern is provided between two adjacent main dielectric patterns;
  • the dielectric layer is used to absorb static electricity in the gate insulating layer, and the cross-sectional area of the auxiliary dielectric pattern is larger than the cross-sectional area of the main dielectric pattern.
  • the dielectric layer is used to absorb static electricity in the gate insulating layer, and the cross-sectional area of the auxiliary dielectric pattern is larger than that of the main dielectric pattern. Cross-sectional area.
  • the array substrate further includes a thin film transistor layer disposed above the gate insulating layer, the thin film transistor layer includes a plurality of thin film transistors, and the position of the thin film transistor Corresponding to the position of the main dielectric pattern;
  • the source of the thin film transistor is at the overlapping area, and the drain of the thin film transistor at the non-overlapping area is electrically connected to the dielectric layer through via holes.
  • conductive particles for absorbing static electricity in the gate insulating layer are implanted in the dielectric layer, and the positively charged particles and the negatively charged particles in the conductive particles The number is the same.
  • the array substrate further includes a metal shielding layer for shielding static electricity in the gate insulating layer;
  • the metal shielding layer includes a first shielding layer and a second shielding layer, the first shielding layer is disposed between the shielding layer and the dielectric layer, and the second shielding layer is disposed on the gate. Between the polar insulating layer and the dielectric layer.
  • a first dielectric capacitor is provided in the auxiliary dielectric pattern
  • a second dielectric capacitor is provided in the main dielectric pattern
  • the first dielectric The dielectric constant of the capacitor is greater than the dielectric constant of the second dielectric capacitor.
  • the distance between the main dielectric pattern and the auxiliary dielectric pattern is less than or equal to the distance between the adjacent shielding layers.
  • the beneficial effect of the present application is that the present application adds an auxiliary dielectric pattern to the array substrate, and the cross-sectional area of the auxiliary dielectric pattern is larger than the cross-sectional area of the main dielectric pattern, so that the auxiliary dielectric pattern absorbs Most of the static electricity in the gate insulating layer further reduces the display defects of the array substrate.
  • FIG. 1 is a schematic diagram of a film structure of an array substrate provided by an embodiment of the application.
  • FIG. 2 is a schematic top view of an array substrate provided by an embodiment of the application.
  • FIG. 3 is a schematic front cross-sectional view of the array substrate in FIG. 2.
  • FIG. 4 is a schematic flow chart of a manufacturing method of an array substrate provided by an embodiment of the application.
  • an auxiliary dielectric pattern is added to the array substrate in this application, so that the auxiliary dielectric pattern absorbs most of the static electricity in the gate insulating layer, thereby reducing the phenomenon of poor display of the array substrate.
  • FIG. 1 is a schematic diagram of a film structure of an array substrate provided by an embodiment of the present application.
  • the array substrate 10 includes:
  • a plurality of shielding layers 2 arranged at intervals are arranged on the substrate 1;
  • the dielectric layer 3 is laid on the substrate 1 and covers the shielding layer 2.
  • the dielectric layer 3 includes a patterned dielectric pattern.
  • the dielectric pattern includes a main dielectric pattern 31 and a dielectric pattern located on the main body.
  • the auxiliary dielectric pattern 32 on at least one side of the electrical pattern 31;
  • the gate insulating layer 4 is disposed on the dielectric layer 3.
  • the dielectric layer 3 is used to absorb static electricity in the gate insulating layer 4, and the cross-sectional area of the auxiliary dielectric pattern 32 is larger than the cross-sectional area of the main dielectric pattern 31, so that The amount of static electricity absorbed by the auxiliary dielectric pattern 32 is greater than the amount of static electricity absorbed by the main dielectric pattern 31, so that the auxiliary dielectric pattern 32 absorbs most of the static electricity in the gate insulating layer 4, thereby reducing poor display of the array substrate The phenomenon.
  • the substrate 1 may be an organic solid, an inorganic solid, or a combination of an organic solid and an inorganic solid.
  • the substrate 1 may be rigid or flexible, and may be processed as a discrete single component (such as a sheet or wafer) or processed as a continuous roll.
  • Typical substrate materials include glass, plastics, metals, ceramics, semiconductors, metal oxides, metal nitrides, metal sulfides, oxide semiconductors, nitride semiconductors, sulfide semiconductors, carbon, or combinations of these materials, or are generally Any other material used to form an OLED device that can be a passive matrix device or an active matrix device.
  • the substrate 1 may be a homogeneous mixture of materials, a composite of materials, or multiple layers of materials.
  • the substrate 1 may be an OLED substrate, that is, a substrate commonly used for preparing OLED devices, such as an active matrix low-temperature polysilicon or amorphous silicon TFT substrate.
  • OLED substrate that is, a substrate commonly used for preparing OLED devices, such as an active matrix low-temperature polysilicon or amorphous silicon TFT substrate.
  • the transmission characteristics of the base are not important, so it can transmit light, absorb light, or reflect light.
  • the cross-sectional area of the auxiliary dielectric pattern is in the range of 40-50 square microns, and the cross-sectional area of the main dielectric pattern is in the range of 10-15 square microns.
  • the glass substrate 1 and covering the shielding layer 2 also includes a first interlayer insulating layer 5 and a second interlayer insulating layer 6, the first interlayer insulating layer 5 and the second interlayer insulating layer
  • the material of 6 forms the buffer layer of the array substrate to prevent the film structure in the array substrate 10 from being distorted and deformed; the material can be a combination of a nitrogen-silicon compound and an oxygen-silicon compound, for example, the first interlayer insulating layer 5 is a nitrogen-silicon compound, and the second interlayer insulating layer 6 is an oxygen-silicon compound.
  • FIG. 2 is a schematic top view of the array substrate provided by an embodiment of the application.
  • the main dielectric pattern 31 partially overlaps the shielding layer 2, and the main dielectric pattern 31 is formed with an overlapping area A and a non-overlapping area B on the shielding layer 2;
  • the auxiliary dielectric pattern 32 and the shielding layer 2 do not overlap, and the auxiliary dielectric pattern 32 is provided between two adjacent main dielectric patterns 31. Further, it can be arranged on at least one side of every two overlapping areas A.
  • FIG. 2 and FIG. 3 is a schematic front sectional view of the array substrate in FIG. 2 along the S-S' direction.
  • the array substrate 10 further includes a thin film transistor layer 7 disposed above the gate insulating layer 4, the thin film transistor layer 7 includes a plurality of thin film transistors 70, and the position of the thin film transistor 70 is The position of the main dielectric pattern 31 corresponds, that is, the thin film transistor 70 corresponds to the projection position of the non-overlapping region B in the main dielectric pattern 31;
  • the source 701 of the thin film transistor 70 is at the overlapping area A
  • the drain 702 of the thin film transistor 70 is at the non-overlapping area B, and both are electrically connected to the dielectric layer 3 through the via 8 connection.
  • the material of the dielectric layer 3 is one or more combinations of crystalline silicon, amorphous silicon, polycrystalline silicon, monocrystalline silicon, or oxidized amorphous silicon. Specifically, such a silicide material enables integration When the chip is applied to the panel substrate, the feasibility of integrating the chip is strong, and the stability of the array substrate is strong.
  • conductive particles for absorbing static electricity in the gate insulating layer 4 are implanted in the dielectric layer 3, and positively charged particles and negatively charged particles in the conductive particles The number of charged particles is the same.
  • the negative charge in the dielectric layer 3 is combined with the negative charge in the gate insulating layer 4 to absorb the negative charge in the gate insulating layer 4 Static electricity
  • the positive charge in the dielectric layer 3 is combined with the positive charge in the gate insulating layer 4 to absorb the gate insulating layer 4 Static electricity
  • the array substrate 10 further includes a metal shielding layer (not shown in the figure) for shielding static electricity in the gate insulating layer; wherein, the metal shielding layer includes a first shielding layer And a second shielding layer (not shown in the figure), the first shielding layer is disposed between the shielding layer 2 and the dielectric layer 3, and the second shielding layer is disposed on the gate insulating layer 4 and the dielectric layer 3.
  • the metal shielding layer includes a first shielding layer And a second shielding layer (not shown in the figure)
  • the first shielding layer is disposed between the shielding layer 2 and the dielectric layer 3
  • the second shielding layer is disposed on the gate insulating layer 4 and the dielectric layer 3.
  • the metal shielding layer may be a metal mesh woven structure that wraps the main dielectric pattern 31.
  • the material of the metal shielding layer is generally red copper or tin-plated copper, which can prevent static electricity from entering the inner layer of the main dielectric pattern 31. This prevents the thin film transistor 70 corresponding to the main dielectric pattern 31 from being damaged by static electricity, and further reduces the problem of poor display of the array substrate.
  • the auxiliary dielectric pattern 32 is provided with a first dielectric capacitor (not shown in the figure), and the main dielectric pattern 31 is provided with a second dielectric capacitor (not shown in the figure). ), and the dielectric constant of the first dielectric capacitor is greater than the dielectric constant of the second dielectric capacitor.
  • the distance between the main dielectric pattern 31 and the auxiliary dielectric pattern 32 is not greater than the distance between adjacent shielding layers 2.
  • An embodiment of the present application also provides a method for preparing an array substrate. Please refer to FIG. 4, which is a schematic flow chart of a method for preparing an array substrate provided by an embodiment of the application.
  • the preparation method includes the following steps:
  • a dielectric layer is formed on a plurality of shielding layers arranged at intervals, the dielectric layer includes a patterned dielectric pattern, the dielectric pattern includes a bulk dielectric pattern, and the bulk dielectric pattern is at least Auxiliary dielectric pattern on one side.
  • the dielectric layer can absorb static electricity in the gate insulating layer, and the cross-sectional area of the auxiliary dielectric pattern is larger than the cross-sectional area of the main dielectric pattern, so that the auxiliary dielectric
  • the amount of static electricity absorbed by the electrical pattern is greater than the amount of static electricity absorbed by the main dielectric pattern, so that the auxiliary dielectric pattern absorbs most of the static electricity in the gate insulating layer 4, thereby reducing the phenomenon of poor display of the array substrate.
  • the substrate and covering the shielding layer further include a first interlayer insulating layer and a second interlayer insulating layer.
  • the materials of the first interlayer insulating layer and the second interlayer insulating layer form the array substrate
  • the buffer layer is used to prevent the film structure in the array substrate 10 from being twisted and deformed.
  • the material of the dielectric layer is one or more combinations of crystalline silicon, amorphous silicon, polycrystalline silicon, monocrystalline silicon, or oxidized amorphous silicon. This material has a strong feasibility for applying integrated chips to the panel substrate, so that The array substrate has strong stability.
  • this step S30 may specifically include:
  • S302 Design a mask according to the dielectric pattern, and use the mask to perform photolithography on the dielectric layer material.
  • the main dielectric pattern partially overlaps the shielding layer to form an overlapping area and a non-overlapping area.
  • the thin film transistor layer includes a plurality of thin film transistors, and the position of the thin film transistor corresponds to the position of the main dielectric pattern;
  • the source of the thin film transistor is at the overlapping area, and the drain of the thin film transistor at the non-overlapping area is electrically connected to the dielectric layer through via holes.
  • the source of the thin film transistor and the overlapping area, and the drain of the thin film transistor and the non-overlapping area are all electrically connected to the dielectric layer through via holes.
  • an embodiment of the present application also provides a display panel, including the array substrate provided by any embodiment of the present application.
  • an embodiment of the present invention provides a display device, including: the liquid crystal display panel provided in any embodiment of the present application.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the beneficial effect is that this application adds an auxiliary dielectric pattern to the array substrate, and the cross-sectional area of the auxiliary dielectric pattern is larger than the cross-sectional area of the main dielectric pattern, so that the auxiliary dielectric pattern absorbs the gate electrode. Most of the static electricity in the insulating layer reduces the display defects of the array substrate.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板（10），所述阵列基板（10）包括：多个间隔设置的遮挡层（2），设置于玻璃基板（1）上；介电层（3），铺设于玻璃基板（1）上且覆盖遮挡层（2），介电层（3）包括图案化的介电图案，介电图案包括主体介电图案（31），和位于主体介电图案（31）至少一侧的辅助介电图案（32）；栅极绝缘层（4），设置于介电层（3）上。

Description

阵列基板及其制备方法 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制备方法。
 背景技术
随着移动显示的日益普及，薄膜晶体管-液晶显示器（Thin Film Transistor-Liquid Crystal Display，TFT-LCD）全面取代阴极射线管（Cathode Radial Tube，CRT）与等离子体显示器；但在TFT-LCD显示面板的生产过程中，其阵列基板中的栅极绝缘层较易发生静电，进而击伤阵列基板中的薄膜晶体管，造成显示不良。
 技术问题
本申请提供的阵列基板及其制备方法，本申请通过在阵列基板中增设辅助介电图案，以使辅助介电图案吸收该栅极绝缘层中大部分静电，进而减轻阵列基板显示不良的现象。
 技术解决方案
为了解决上述问题，本申请实施例提供了一种阵列基板，该阵列基板包括：
多个间隔设置的遮挡层，设置于基板上；
介电层，铺设于所述基板上且覆盖遮挡层，所述介电层包括图案化的介电图案，所述介电图案包括主体介电图案，和位于所述主体介电图案至少一侧的辅助介电图案；
栅极绝缘层，设置于所述介电层上。
在本申请所提供的阵列基板中，所述介电层用于吸收所述栅极绝缘层中的静电，所述辅助介电图案的横截面积大于所述主体介电图案的横截面积。
在本申请所提供的阵列基板中，所述主体介电图案与所述遮挡层部分重叠，形成有重叠区域与非重叠区域；
所述辅助介电图案与所述遮挡层不重叠，且相邻两个所述主体介电图案之间设有所述辅助介电图案。
在本申请所提供的阵列基板中，所述阵列基板还包括设置于所述栅极绝缘层上方的薄膜晶体管层，所述薄膜晶体管层包括多个薄膜晶体管，所述薄膜晶体管的位置与所述主体介电图案的位置对应；
其中，所述薄膜晶体管的源极在所述重叠区域处，以及所述薄膜晶体管的漏极在所述非重叠区域处，均通过过孔与所述介电层电连接。
在本申请所提供的阵列基板中，所述介电层用于吸收所述栅极绝缘层中的静电，且所述辅助介电图案的横截面积大于所述主体介电图案的横截面积。
在本申请所提供的阵列基板中，所述介电层内植入有用于吸收所述栅极绝缘层中的静电的导电粒子，所述导电粒子中的正电荷粒子与负电荷粒子的数量相同。
在本申请所提供的阵列基板中，所述阵列基板中还包括用于屏蔽所述栅极绝缘层中的静电的金属屏蔽层；
其中，所述金属屏蔽层包括第一屏蔽层与第二屏蔽层，所述第一屏蔽层设置于所述遮挡层与所述介电层之间，所述第二屏蔽层设置于所述栅极绝缘层与所述介电层之间。
在本申请所提供的阵列基板中，所述辅助介电图案内设有第一介电电容，所述主体介电图案内设有第二介电电容，且所述第一介电电容的介电常数大于所述第二介电电容的介电常数。
在本申请所提供的阵列基板中，所述主体介电图案与所述辅助介电图案的间距小于或等于相邻所述遮挡层之间的间距。
在本申请所提供的阵列基板中，所述辅助介电图案的横截面积的范围为40-50平方微米，所述主体介电图案的横截面积的范围为10-15平方微米。
本申请还提供一种阵列基板的制备方法，所述方法包括：
提供玻璃基板；
在所述玻璃基板上形成多个间隔设置的遮挡层；
在设置有多个间隔设置的遮挡层上形成介电层，所述介电层包括图案化的介电图案，所述介电图案包括主体介电图案，和所述主体介电图案至少一侧的辅助介电图案；
在所述介电层上方光刻出栅极绝缘层。
在本申请所提供的阵列基板的制备方法中，所述在设置有多个间隔设置的遮挡层的表面光刻出介电层，具体包括：
在设置有多个间隔设置的遮挡层表面涂覆介电层材料；
根据所述介电图案设计掩模板，并利用所述掩模板对所述介电层材料进行光刻；
对光刻后的所述介电层材料植入导电粒子，以形成所述介电层。
在本申请所提供的阵列基板的制备方法中，所述主体介电图案与所述遮挡层部分重叠，形成有重叠区域与非重叠区域，所述在所述介电层上方形成栅极绝缘层之后，还包括：
在所述栅极绝缘层上形成薄膜晶体管层，所述薄膜晶体管层包括多个薄膜晶体管，所述薄膜晶体管的位置与所述主体介电图案的位置对应；
其中，所述薄膜晶体管的源极在所述重叠区域处，以及所述薄膜晶体管的漏极在所述非重叠区域处，均通过过孔与所述介电层电连接。
本申请还提供一种阵列基板，所述阵列基板包括：
多个间隔设置的遮挡层，设置于基板上；
介电层，铺设于所述基板上且覆盖遮挡层，所述介电层包括图案化的介电图案，所述介电图案包括主体介电图案，和位于所述主体介电图案至少一侧的辅助介电图案；
栅极绝缘层，设置于所述介电层上；
其中，所述主体介电图案与所述遮挡层部分重叠，形成有重叠区域与非重叠区域；
所述辅助介电图案与所述遮挡层不重叠，且相邻两个所述主体介电图案之间设有所述辅助介电图案；
其中，所述介电层用于吸收所述栅极绝缘层中的静电，且所述辅助介电图案的横截面积大于所述主体介电图案的横截面积。
在本申请所提供的阵列基板的制备方法中，所述介电层用于吸收所述栅极绝缘层中的静电，所述辅助介电图案的横截面积大于所述主体介电图案的横截面积。
在本申请所提供的阵列基板的制备方法中，所述阵列基板还包括设置于所述栅极绝缘层上方的薄膜晶体管层，所述薄膜晶体管层包括多个薄膜晶体管，所述薄膜晶体管的位置与所述主体介电图案的位置对应；
其中，所述薄膜晶体管的源极在所述重叠区域处，以及所述薄膜晶体管的漏极在所述非重叠区域处，均通过过孔与所述介电层电连接。
在本申请所提供的阵列基板的制备方法中，所述介电层内植入有用于吸收所述栅极绝缘层中的静电的导电粒子，所述导电粒子中的正电荷粒子与负电荷粒子的数量相同。
在本申请所提供的阵列基板的制备方法中，所述阵列基板中还包括用于屏蔽所述栅极绝缘层中的静电的金属屏蔽层；
其中，所述金属屏蔽层包括第一屏蔽层与第二屏蔽层，所述第一屏蔽层设置于所述遮挡层与所述介电层之间，所述第二屏蔽层设置于所述栅极绝缘层与所述介电层之间。
在本申请所提供的阵列基板的制备方法中，所述辅助介电图案内设有第一介电电容，所述主体介电图案内设有第二介电电容，且所述第一介电电容的介电常数大于所述第二介电电容的介电常数。
在本申请所提供的阵列基板的制备方法中，所述主体介电图案与所述辅助介电图案的间距小于或等于相邻所述遮挡层之间的间距。
 有益效果
本申请的有益效果为：本申请通过在阵列基板中增设辅助介电图案，且所述辅助介电图案的横截面积大于所述主体介电图案的横截面积，以使辅助介电图案吸收该栅极绝缘层中大部分静电，进而减轻阵列基板显示不良的现象。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例所提供的阵列基板的膜层结构示意图。
图2为本申请实施例所提供的阵列基板的俯视示意图。
图3为图2中阵列基板的主视剖视示意图。
图4为本申请实施例提供的阵列基板的制备方法流程示意图。
 本发明的实施方式
本申请提供的阵列基板及其制备方法，本申请通过在阵列基板中增设辅助介电图案，以使辅助介电图案吸收该栅极绝缘层中大部分静电，进而减轻阵列基板显示不良的现象。
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
需要说明的是，本发明附图中各层的厚度和形状不反映真实比例，目的只是示意说明本申请实施例内容。
请参见图1，该图1本申请实施例所提供的阵列基板的膜层结构示意图，所述阵列基板10包括：
多个间隔设置的遮挡层2，设置于基板1上；
介电层3，铺设于所述基板1上且覆盖遮挡层2，所述介电层3包括图案化的介电图案，所述介电图案包括主体介电图案31，和位于所述主体介电图案31至少一侧的辅助介电图案32；
栅极绝缘层4，设置于所述介电层3上。
进一步的，所述介电层3用于吸收所述栅极绝缘层4中的静电，所述辅助介电图案32的横截面积大于所述主体介电图案31的横截面积，以使所述辅助介电图案32吸收的静电的数量大于所述主体介电图案31吸收的静电的数量，以使辅助介电图案32吸收该栅极绝缘层4中大部分静电，进而减轻阵列基板显示不良的现象。
需要说明的是，基板1可以是有机固体、无机固体、或者是有机固体与无机固体的组合。基板1可以是刚性或柔性的，并且可以被加工为分立的单个部件(如片或晶圆)或者被加工为连续的卷(roll)。典型的基板材料包括玻璃、塑料、金属、陶瓷、半导体、金属氧化物、金属氮化物、金属硫化物、氧化物半导体、氮化物半导体、硫化物半导体、碳、或这些材料的组合，或者普遍被用于形成可以是无源矩阵器件或有源矩阵器件的OLED器件的任何其它材料。基板1可以是材料的均匀混合物、材料的复合物、或多层材料。基板1可以是OLED基板，即普遍地用于制备OLED器件的基板，例如有源矩阵低温多晶硅或非晶硅TFT基板。对于通过顶部电极而观看到有机发光器件发光的本实施方式来说底座的透射特性并不重要，因此其可以透光、吸光或反光。
进一步的，该辅助介电图案的横截面积的范围为40-50平方微米，该主体介电图案的横截面积的范围为10-15平方微米。
除此之外，该玻璃基板1上且覆盖于遮挡层2还包括第一层间绝缘层5与第二层间绝缘层6，该第一层间绝缘层5与该第二层间绝缘层6的材质形成该阵列基板的缓冲层，用于防止该阵列基板10中的膜层结构发生扭曲变形；其材料可为氮硅化合物与氧硅化合物的组合，譬如，该第一层间绝缘层5为氮硅化合物，该第二层间绝缘层6为氧硅化合物。
为更清楚描述图案化的介电层3，请参见图2，该图2为本申请实施例所提供的阵列基板的俯视示意图。在该阵列基板10中，所述主体介电图案31与所述遮挡层2部分重叠，所述主体介电图案31在所述遮挡层2形成有重叠区域A与非重叠区域B；
所述辅助介电图案32与所述遮挡层2不重叠，且相邻两个所述主体介电图案31之间设有所述辅助介电图案32。进一步的，可设置于每两个所述重叠区域A的至少一侧。
进一步的，请参见图2与图3，该图3为图2中阵列基板中延S-S’方向的主视剖视示意图。在该图2中，所述阵列基板10还包括设置于所述栅极绝缘层4上方的薄膜晶体管层7，所述薄膜晶体管层7包括多个薄膜晶体管70，所述薄膜晶体管70的位置与所述主体介电图案31的位置对应，即所述薄膜晶体管70与所述主体介电图案31中的所述非重叠区域B的投影位置对应；
其中，所述薄膜晶体管70的源极701在所述重叠区域A处，所述薄膜晶体管70的漏极702在所述非重叠区域B处，均通过过孔8与所述介电层3电连接。
在一些实施例中，所述介电层3的材料为结晶硅、非晶硅、多晶硅、单晶硅或者氧化非晶硅的一种或者多种组合，具体的，此种硅化物材料使得集成芯片在应用于面板基板中，其集成芯片的可行性强，且该阵列基板的稳定性强。
在一些实施例中，所述介电层3内植入有用于吸收所述栅极绝缘层4中的静电的导电粒子（图中未示出），所述导电粒子中的正电荷粒子与负电荷粒子的数量相同。譬如，当栅极绝缘层4中的静电的总体电荷量呈正电荷时，该介电层3中的负电荷与该栅极绝缘层4中的负电荷结合，以吸收栅极绝缘层4中的静电；当栅极绝缘层4中的静电的总体电荷量呈负电荷时，该介电层3中的正电荷与该栅极绝缘层4中的正电荷结合，以吸收栅极绝缘层4中的静电
在一些实施例中，所述阵列基板10中还包括用于屏蔽所述栅极绝缘层中的静电的金属屏蔽层（图中未示出）；其中，所述金属屏蔽层包括第一屏蔽层与第二屏蔽层（图中未示出），所述第一屏蔽层设置于所述遮挡层2与所述介电层3之间，所述第二屏蔽层设置于所述栅极绝缘层4与所述介电层3之间。
譬如，该金属屏蔽层可以为包裹该主体介电图案31的金属网状编制结构，该金属屏蔽层的材料一般是红铜或者镀锡铜，可避免静电进入主体介电图案31的内层，使得该主体介电图案31对应的薄膜晶体管70避免被静电炸伤，进一步的减少阵列基板显示不良的问题。
在一些实施例中，所述辅助介电图案32内设有第一介电电容（图中未示出），所述主体介电图案31内设有第二介电电容（图中未示出），且所述第一介电电容的介电常数大于所述第二介电电容的介电常数。
在一些实施例中，所述主体介电图案31与所述辅助介电图案32的间距不大于相邻所述遮挡层2之间的间距。
本申请实施例还提供一种阵列基板的制备方法，请参见图4，该图4为本申请实施例提供的阵列基板的制备方法流程示意图，该制备方法包括如下步骤：
S10，提供基板。
S20，在所述基板上形成多个间隔设置的遮挡层。
S30，在设置有多个间隔设置的遮挡层上形成介电层，所述介电层包括图案化的介电图案，所述介电图案包括主体介电图案，和所述主体介电图案至少一侧的辅助介电图案。
S40，在所述介电层上形成栅极绝缘层。
需要说明的是，所述介电层可吸收所述栅极绝缘层中的静电，所述辅助介电图案的横截面积大于所述主体介电图案的横截面积，以使所述辅助介电图案吸收的静电的数量大于所述主体介电图案吸收的静电的数量，以使辅助介电图案吸收该栅极绝缘层4中大部分静电，进而减轻阵列基板显示不良的现象。
除此之外，该基板上且覆盖于遮挡层还包括第一层间绝缘层与第二层间绝缘层，该第一层间绝缘层与该第二层间绝缘层的材质形成该阵列基板的缓冲层，用于防止该阵列基板10中的膜层结构发生扭曲变形。
所述介电层的材料为结晶硅、非晶硅、多晶硅、单晶硅或者氧化非晶硅的一种或者多种组合，此种材料将集成芯片应用于面板基板上的可行性强，使得该阵列基板的稳定性强。
在一些实施例中，该步骤S30具体可以包括：
S301，在设置有多个间隔设置的遮挡层表面涂覆介电层材料。
S302，根据所述介电图案设计掩模板，并利用所述掩模板对所述介电层材料进行光刻。
S303，对光刻后的所述介电层材料植入导电粒子，以形成所述介电层。
在一些实施例中，所述主体介电图案与所述遮挡层部分重叠，形成有重叠区域与非重叠区域，该步骤S40之后，还包括：
S50，在所述栅极绝缘层上形成薄膜晶体管层，所述薄膜晶体管层包括多个薄膜晶体管，所述薄膜晶体管的位置与所述主体介电图案的位置对应；
其中，所述薄膜晶体管的源极在所述重叠区域处，以及所述薄膜晶体管的漏极在所述非重叠区域处，均通过过孔与所述介电层电连接。
需要说明的是，所述薄膜晶体管的源极与所述重叠区域，所述薄膜晶体管的漏极与所述非重叠区域，均通过过孔与所述介电层电连接。
基于同一申请构思，本申请实施例还提供了一种显示面板，包括本申请任意实施例提供的阵列基板。
基于同一申请构思，本发明实施例提供了一种显示装置，包括：本申请任意实施例提供的液晶显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
有益效果为：本申请通过在阵列基板中增设辅助介电图案，且所述辅助介电图案的横截面积大于所述主体介电图案的横截面积，以使辅助介电图案吸收该栅极绝缘层中大部分静电，进而减轻阵列基板显示不良的现象。
除上述实施例外，本申请还可以有其他实施方式。凡采用等同替换或等效替换形成的技术方案，均落在本申请要求的保护范围。
综上所述，虽然本申请已将优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，其包括：
    多个间隔设置的遮挡层，设置于基板上；
    介电层，铺设于所述基板上且覆盖遮挡层，所述介电层包括图案化的介电图案，所述介电图案包括主体介电图案，和位于所述主体介电图案至少一侧的辅助介电图案；
    栅极绝缘层，设置于所述介电层上；
    其中，所述主体介电图案与所述遮挡层部分重叠，形成有重叠区域与非重叠区域；
    所述辅助介电图案与所述遮挡层不重叠，且相邻两个所述主体介电图案之间设有所述辅助介电图案；
    其中，所述介电层用于吸收所述栅极绝缘层中的静电，且所述辅助介电图案的横截面积大于所述主体介电图案的横截面积。
  2. 根据权利要求1所述的阵列基板，其中，所述介电层用于吸收所述栅极绝缘层中的静电，所述辅助介电图案的横截面积大于所述主体介电图案的横截面积。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括设置于所述栅极绝缘层上方的薄膜晶体管层，所述薄膜晶体管层包括多个薄膜晶体管，所述薄膜晶体管的位置与所述主体介电图案的位置对应；
    其中，所述薄膜晶体管的源极在所述重叠区域处，以及所述薄膜晶体管的漏极在所述非重叠区域处，均通过过孔与所述介电层电连接。
  4. 根据权利要求1所述的阵列基板，其中，所述介电层内植入有用于吸收所述栅极绝缘层中的静电的导电粒子，所述导电粒子中的正电荷粒子与负电荷粒子的数量相同。
  5. 根据权利要求1所述的阵列基板，其中，所述阵列基板中还包括用于屏蔽所述栅极绝缘层中的静电的金属屏蔽层；
    其中，所述金属屏蔽层包括第一屏蔽层与第二屏蔽层，所述第一屏蔽层设置于所述遮挡层与所述介电层之间，所述第二屏蔽层设置于所述栅极绝缘层与所述介电层之间。
  6. 根据权利要求1所述的阵列基板，其中，所述辅助介电图案内设有第一介电电容，所述主体介电图案内设有第二介电电容，且所述第一介电电容的介电常数大于所述第二介电电容的介电常数。
  7. 根据权利要求1所述的阵列基板，其中，所述主体介电图案与所述辅助介电图案的间距小于或等于相邻所述遮挡层之间的间距。
  8. 一种阵列基板，其包括：
    多个间隔设置的遮挡层，设置于基板上；
    介电层，铺设于所述基板上且覆盖遮挡层，所述介电层包括图案化的介电图案，所述介电图案包括主体介电图案，和位于所述主体介电图案至少一侧的辅助介电图案；
    栅极绝缘层，设置于所述介电层上。
  9. 根据权利要求8所述的阵列基板，其中，所述介电层用于吸收所述栅极绝缘层中的静电，所述辅助介电图案的横截面积大于所述主体介电图案的横截面积。
  10. 根据权利要求8所述的阵列基板，其中，所述主体介电图案与所述遮挡层部分重叠，形成有重叠区域与非重叠区域；
    所述辅助介电图案与所述遮挡层不重叠，且相邻两个所述主体介电图案之间设有所述辅助介电图案。
  11. 根据权利要求10所述的阵列基板，其中，所述阵列基板还包括设置于所述栅极绝缘层上方的薄膜晶体管层，所述薄膜晶体管层包括多个薄膜晶体管，所述薄膜晶体管的位置与所述主体介电图案的位置对应；
    其中，所述薄膜晶体管的源极在所述重叠区域处，以及所述薄膜晶体管的漏极在所述非重叠区域处，均通过过孔与所述介电层电连接。
  12. 根据权利要求8所述的阵列基板，其中，所述介电层用于吸收所述栅极绝缘层中的静电，且所述辅助介电图案的横截面积大于所述主体介电图案的横截面积。
  13. 根据权利要求8所述的阵列基板，其中，所述介电层内植入有用于吸收所述栅极绝缘层中的静电的导电粒子，所述导电粒子中的正电荷粒子与负电荷粒子的数量相同。
  14. 根据权利要求8所述的阵列基板，其中，所述阵列基板中还包括用于屏蔽所述栅极绝缘层中的静电的金属屏蔽层；
    其中，所述金属屏蔽层包括第一屏蔽层与第二屏蔽层，所述第一屏蔽层设置于所述遮挡层与所述介电层之间，所述第二屏蔽层设置于所述栅极绝缘层与所述介电层之间。
  15. 根据权利要求8所述的阵列基板，其中，所述辅助介电图案内设有第一介电电容，所述主体介电图案内设有第二介电电容，且所述第一介电电容的介电常数大于所述第二介电电容的介电常数。
  16. 根据权利要求8所述的阵列基板，其中，所述主体介电图案与所述辅助介电图案的间距小于或等于相邻所述遮挡层之间的间距。
  17. 根据权利要求8所述的阵列基板，其中，所述辅助介电图案的横截面积的范围为40-50平方微米，所述主体介电图案的横截面积的范围为10-15平方微米。
  18. 一种阵列基板的制备方法，其中，所述方法包括：
    提供基板；
    在所述基板上形成多个间隔设置的遮挡层；
    在设置有多个间隔设置的遮挡层上形成介电层，所述介电层包括图案化的介电图案，所述介电图案包括主体介电图案，和所述主体介电图案至少一侧的辅助介电图案；
    在所述介电层上形成栅极绝缘层。
  19. 根据权利要求18所述的阵列基板的制备方法，其中，所述在设置有多个间隔设置的遮挡层上形成介电层，具体包括：
    在设置有多个间隔设置的遮挡层表面涂覆介电层材料；
    根据所述介电图案设计掩模板，并利用所述掩模板对所述介电层材料进行光刻；
    对光刻后的所述介电层材料植入导电粒子，以形成所述介电层。
  20. 根据权利要求18所述的阵列基板的制备方法，其中，所述主体介电图案与所述遮挡层部分重叠，形成有重叠区域与非重叠区域，所述在所述介电层上方形成栅极绝缘层之后，还包括：
    在所述栅极绝缘层上形成薄膜晶体管层，所述薄膜晶体管层包括多个薄膜晶体管，所述薄膜晶体管的位置与所述主体介电图案的位置对应；
    其中，所述薄膜晶体管的源极在所述重叠区域处，以及所述薄膜晶体管的漏极在所述非重叠区域处，均通过过孔与所述介电层电连接。
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