WO2020228188A1 - Goa电路及液晶显示器 - Google Patents

Goa电路及液晶显示器 Download PDF

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Publication number
WO2020228188A1
WO2020228188A1 PCT/CN2019/104099 CN2019104099W WO2020228188A1 WO 2020228188 A1 WO2020228188 A1 WO 2020228188A1 CN 2019104099 W CN2019104099 W CN 2019104099W WO 2020228188 A1 WO2020228188 A1 WO 2020228188A1
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Prior art keywords
thin film
film transistor
circuit
pull
goa
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PCT/CN2019/104099
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English (en)
French (fr)
Inventor
陈帅
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深圳市华星光电技术有限公司
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Publication of WO2020228188A1 publication Critical patent/WO2020228188A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the invention relates to the field of display technology, in particular to a GOA circuit and a liquid crystal display.
  • the array substrate line scan drive (Gate Driver On Array, GOA) technology uses the thin film transistor liquid crystal display Array process to fabricate the Gate line scan drive signal on the Array substrate.
  • a technology that realizes the gate progressive scan driving method has been widely used in our panels.
  • GOA technology has many advantages, which can improve product yield and realize borderless design.
  • the embodiments of the present invention provide a GOA circuit and a liquid crystal display.
  • the GOA units between two adjacent stages in the GOA circuit are reduced, and the cost of the GOA circuit is saved. Occupied space, and at the same time improve the efficiency of the circuit in the TFT device, which is conducive to the narrow frame design of the liquid crystal display.
  • the present application provides a GOA circuit for liquid crystal displays.
  • the GOA circuit includes 2N GOA units.
  • the Nth level GOA unit and the N+1th level GOA The cells share the same pull-down sustain circuit, where N is a positive integer.
  • the Nth level GOA unit sequentially charges the Nth level horizontal scan lines of the display area, and the Nth level GOA unit includes a pull-up control circuit, a pull-up circuit, a downstream circuit, a pull-down circuit and a clock signal line;
  • the N-stage pull-up control circuit and the N+1-stage pull-up control circuit use the same control signal.
  • the pull-up control circuit includes a first thin film transistor T11, the gate of the first thin film transistor T11 is used to receive the trigger signal of the GOA unit of the N-4th stage, and the source of the first thin film transistor T11 is Describe the downstream circuit connection;
  • M is greater than or equal to 2
  • N is greater than 4.
  • the signal transmission circuit includes a second thin film transistor T22, the gate of the second thin film transistor T22 is connected to the source of the first thin film transistor T11, and the drain of the second thin film transistor T22 is connected to the clock
  • the signal line is connected, the source of the second thin film transistor T22 is connected to the pull-down unit, and the signal download circuit is used to control the on and off of the signal in the next-stage GOA unit.
  • the pull-up circuit includes a third thin film transistor T21, and the drain of the third thin film transistor T21 is connected to the scan line of the same level of the GOA unit to which the current signal download circuit belongs.
  • the signal pull-down circuit includes a fourth thin film transistor T41 and a fifth thin film transistor T31, the gate of the fourth thin film transistor T41 is connected to the gate of the fifth thin film transistor T31, and the fourth thin film transistor T41
  • the drain of the second thin film transistor T22 is connected to the gate of the second thin film transistor T22
  • the source of the fourth thin film transistor T41 is connected to the pull-down signal line of the same level as the GOA unit to which the current signal pull-down circuit belongs
  • the fifth thin film transistor T31 The gate of the fifth thin film transistor T41 is connected to the gate of the fourth thin film transistor T41
  • the drain of the fifth thin film transistor T31 is connected to the scan line in the current GOA circuit
  • the source of the fifth thin film transistor T31 is pulled down with the current signal Connect the pull-down signal line of the same level of GOA unit to which the circuit belongs.
  • the pull-down sustain circuit includes a sixth thin film transistor T51, a seventh thin film transistor T52, an eighth thin film transistor T53, and a ninth thin film transistor T54; the gate of the sixth thin film transistor T51 and the drain of the sixth thin film transistor T51
  • the source of the sixth thin film transistor T51 is connected to the drain of the seventh thin film transistor T52; the source of the seventh thin film transistor T52 is at the same level as the GOA unit to which the current signal pull-down circuit belongs
  • the pull-down signal line is connected; the gate of the seventh thin film transistor T52 is connected to the drain of the first thin film transistor T11.
  • the gate of the eighth thin film transistor T53 is connected to the source of the sixth thin film transistor T51, the source of the eighth thin film transistor T53 is connected to the drain of the ninth thin film transistor T54, so The drain of the eighth thin film transistor T53 is connected to the drain of the sixth thin film transistor T51; the gate of the ninth thin film transistor T54 is connected to the drain of the first thin film transistor T11, and the The source of the thin film transistor T54 is connected to the pull-down signal line of the same level as the GOA unit to which the current signal pull-down circuit belongs.
  • the GOA unit further includes a bootstrap capacitor circuit, one end of the bootstrap capacitor circuit is a first node, and the bootstrap capacitor circuit is connected to the source of the first thin film transistor T11 through the first node.
  • the bootstrap capacitor circuit is used to maintain the current potential of the gate signal point in the GOA unit.
  • the pull-down sustain circuit is an inverter.
  • the present invention also applies for a liquid crystal display, which includes the GOA circuit described in any of the above.
  • the GOA circuit includes 2N GOA units.
  • the Nth level GOA unit and the N+1th level GOA unit share the same pull-down sustaining circuit, where N is a positive integer.
  • the Nth level GOA unit sequentially charges the Nth level horizontal scan lines of the display area, and the Nth level GOA unit includes a pull-up control circuit, a pull-up circuit, a downstream circuit, a pull-down circuit and a clock signal line;
  • the N-stage pull-up control circuit and the N+1-stage pull-up control circuit use the same control signal.
  • the pull-up control circuit includes a first thin film transistor T11, the gate of the first thin film transistor T11 is used to receive the trigger signal of the GOA unit of the N-4th stage, and the source of the first thin film transistor T11 is Describe the downstream circuit connection;
  • M is greater than or equal to 2
  • N is greater than 4.
  • the signal transmission circuit includes a second thin film transistor T22, the gate of the second thin film transistor T22 is connected to the source of the first thin film transistor T11, and the drain of the second thin film transistor T22 is connected to the clock
  • the signal line is connected, the source of the second thin film transistor T22 is connected to the pull-down unit, and the signal download circuit is used to control the on and off of the signal in the next-stage GOA unit.
  • the pull-up circuit includes a third thin film transistor T21, and the drain of the third thin film transistor T21 is connected to the scan line of the same level of the GOA unit to which the current signal download circuit belongs.
  • the signal pull-down circuit includes a fourth thin film transistor T41 and a fifth thin film transistor T31, the gate of the fourth thin film transistor T41 is connected to the gate of the fifth thin film transistor T31, and the fourth thin film transistor T41
  • the drain of the second thin film transistor T22 is connected to the gate of the second thin film transistor T22
  • the source of the fourth thin film transistor T41 is connected to the pull-down signal line of the same level as the GOA unit to which the current signal pull-down circuit belongs
  • the fifth thin film transistor T31 The gate of the fifth thin film transistor T41 is connected to the gate of the fourth thin film transistor T41
  • the drain of the fifth thin film transistor T31 is connected to the scan line in the current GOA circuit
  • the source of the fifth thin film transistor T31 is pulled down with the current signal
  • the GOA unit to which the circuit belongs is connected to the pull-down signal line of the same level.
  • the pull-down sustain circuit includes a sixth thin film transistor T51, a seventh thin film transistor T52, an eighth thin film transistor T53, and a ninth thin film transistor T54; the gate of the sixth thin film transistor T51 and the drain of the sixth thin film transistor T51
  • the source of the sixth thin film transistor T51 is connected to the drain of the seventh thin film transistor T52; the source of the seventh thin film transistor T52 is at the same level as the GOA unit to which the current signal pull-down circuit belongs
  • the pull-down signal line is connected; the gate of the seventh thin film transistor T52 is connected to the drain of the first thin film transistor T11.
  • the gate of the eighth thin film transistor T53 is connected to the source of the sixth thin film transistor T51, the source of the eighth thin film transistor T53 is connected to the drain of the ninth thin film transistor T54, so The drain of the eighth thin film transistor T53 is connected to the drain of the sixth thin film transistor T51; the gate of the ninth thin film transistor T54 is connected to the drain of the first thin film transistor T11, and the The source of the thin film transistor T54 is connected to the pull-down signal line of the same level as the GOA unit to which the current signal pull-down circuit belongs.
  • the GOA unit further includes a bootstrap capacitor circuit, one end of the bootstrap capacitor circuit is a first node, and the bootstrap capacitor circuit is connected to the source of the first thin film transistor T11 through the first node.
  • the bootstrap capacitor circuit is used to maintain the current potential of the gate signal point in the GOA unit.
  • the GOA circuit and the liquid crystal display provided by the present invention reduce the number of circuits in the GOA circuit by sharing a pull-down sustain circuit, thereby saving the space occupied by the GOA circuit on the liquid crystal display, and improving the circuit in the TFT device.
  • the efficiency of use is conducive to the narrow bezel design of the LCD.
  • FIG. 1 is a schematic diagram of an embodiment of the connection relationship of various circuits in a GOA circuit provided by the present invention
  • FIG. 2 is a waveform diagram of an embodiment of various positions in a GOA circuit provided by the present invention.
  • FIG. 3 is a schematic diagram of an embodiment of a pull-down sustain circuit provided by the present invention.
  • Fig. 4 is a diagram of specific connection relations of components in the GOA circuit provided by the present invention.
  • FIG. 1 is a schematic diagram of an embodiment of the connection relationship of each circuit in a GOA circuit provided by the present invention.
  • the following takes the Nth level GOA unit and the N+1th level GOA unit as examples.
  • the GOA circuit may include: N-level pull-up control circuit, N-level pull-up circuit, N-level download circuit, N-level pull-down circuit, N-level bootstrap capacitor and N+1 pull-up control circuit, N+1 level pull-up circuit, N+1 level Downstream circuit, N+1 level pull-down circuit, N+1 level pull-down sustain circuit, N+1 level bootstrap capacitor.
  • the N-stage pull-up circuit and the pull-down sustain circuit are respectively connected to the N-th gate signal point Q(N) and the N-th horizontal scan line G(N).
  • the N-stage pull-up control circuit, the N-stage pull-down circuit and the first The N-level gate signal point Q(N) is connected.
  • the N+1-stage pull-up circuit and the pull-down sustain circuit are respectively connected to the gate signal point Q(N+1) of the N+1th stage and the horizontal scan line G(N+1) of the N+1th stage.
  • the pull-down control circuit and the N+1-stage pull-down circuit are connected to the gate signal point Q(N+1) of the N+1th stage.
  • the pull-down sustain circuit maintains the potentials of the N-th gate signal point Q(N) and the N-th horizontal scanning line G(N) to a low potential after the N-th horizontal scan line G(N) is charged.
  • the level horizontal scanning line G(N+1) is charged to maintain the potentials of the N+1th level gate signal point Q(N+1) and the Nth level horizontal scanning line G(N+1) to a low level.
  • the N-level pull-up control circuit raises the potential value of the N-th gate signal point Q(N) to a high level and controls the N-level pull-up circuit to turn on, and receives the N-level clock signal CK(N), thereby Charge the N-th level horizontal scan line G(N).
  • the N-level pull-down circuit pulls down the potential of the N-th gate signal point Q(N) to a low level, and at the same time closes the N-level pull-up circuit and pulls down the sustain circuit Pull down and maintain the potentials of the Nth level gate signal point Q(N) and the Nth level horizontal scanning line G(N) to a low level and maintain a low level.
  • the pull-down sustain circuit simultaneously pulls down the potential of the two-stage circuit to a low potential and maintains the low potential under the control of the first clock signal CK1 and the second clock signal CK2.
  • FIG. 2 for a waveform diagram of an embodiment of various positions in a GOA circuit provided by the present invention.
  • this embodiment couples adjacent two-stage GOA units so that the two-stage GOA units share the same pull-down sustaining circuit.
  • the pull-down sustaining circuit maintains the first stage after the first-stage GOA circuit is charged.
  • the GOA circuit goes to a low potential, and the second-stage GOA circuit is maintained to a low potential after the second-stage GOA circuit is charged. In this way, the number of circuits in the GOA circuit can be reduced, thereby saving the space occupied by the GOA circuit, which is beneficial to the narrow frame design of the liquid crystal display.
  • the GOA units sharing the same pull-down sustain circuit may also be two or more adjacent pull-down sustain circuits.
  • the GOA units sharing the same pull-down sustain circuit may be the first-level and second-level GOA units.
  • the GOA units sharing the same pull-down sustain circuit may be multiple GOA units such as the first stage, the second stage, and the third stage.
  • the GOA units sharing the same pull-down sustain circuit may also be two or more GOA units that are not adjacent.
  • the GOA units sharing the same pull-down sustain circuit can be the first-level and third-level GOA units.
  • the GOA units sharing the same pull-down sustaining circuit may be the first-stage, third-stage, and fifth-stage GOA units.
  • the pull-down sustain circuit may be an inverter, where the LC terminal is a high level signal, and the VSS terminal is a low level signal.
  • the Input terminal inputs a high level signal
  • the output terminal outputs a low potential signal
  • the Output terminal outputs a high potential signal.
  • the pull-up control circuit includes a first thin film transistor T11, the gate of the first thin film transistor T11 receives a control signal, and the source of the first thin film transistor T11 is connected to the downstream circuit;
  • the gate of the first thin film transistor T11 can receive a signal triggered by the GOA unit of the N-4th stage, and N is greater than 4.
  • the signal transmission circuit may include a second thin film transistor T22, the gate of the second thin film transistor T22 is connected to the source of the first thin film transistor T11, and the second thin film transistor The drain of T22 is connected to the clock signal line, the source of the second thin film transistor T22 is connected to the pull-down unit, and the signal download circuit is used to control the on and off of the signal in the next-stage GOA unit.
  • the pull-up circuit may include a third thin film transistor T21, and the drain of the third thin film transistor T21 is connected to the scan line of the same level of the GOA unit to which the current signal download circuit belongs.
  • the source of the third thin film transistor T21 is connected to the clock signal line of the same level of the GOA unit to which the current pull-down circuit belongs.
  • the signal pull-down circuit may include a fourth thin film transistor T41 and a fifth thin film transistor T31, the gate of the fourth thin film transistor T41 and the gate of the fifth thin film transistor T31 Connected, the drain of the fourth thin film transistor T41 is connected to the gate of the second thin film transistor T22, and the source of the fourth thin film transistor T41 is the pull-down signal line of the same level as the GOA unit to which the current signal pull-down circuit belongs Connected, the gate of the fifth thin film transistor T31 is connected to the gate of the fourth thin film transistor T41, the drain of the fifth thin film transistor T31 is connected to the scan line in the current GOA circuit, and the fifth thin film The source of the transistor T31 is connected to the pull-down signal line of the same level as the GOA unit to which the current signal pull-down circuit belongs.
  • the pull-down sustain circuit may include a sixth thin film transistor T51, a seventh thin film transistor T52, an eighth thin film transistor T53, and a ninth thin film transistor T54; the sixth thin film transistor T51 The gate of the sixth thin film transistor T51 is connected to a high-level signal; the source of the sixth thin film transistor T51 is connected to the drain of the seventh thin film transistor T52; the source of the seventh thin film transistor T52 The electrode is connected to the pull-down signal line; the gate of the seventh thin film transistor T52 is connected to the drain of the first thin film transistor T11.
  • the gate of the eighth thin film transistor T53 is connected to the source of the sixth thin film transistor T51, and the source of the eighth thin film transistor T53 is connected to the drain of the ninth thin film transistor T54,
  • the drain of the eighth thin film transistor T53 is connected to the drain of the sixth thin film transistor T51;
  • the gate of the ninth thin film transistor T54 is connected to the drain of the first thin film transistor T11, and the The source of the nine thin film transistor T54 is connected to the pull-down signal line of the same level as the GOA unit to which the current pull-down sustain circuit belongs.
  • the GOA unit may also include a bootstrap capacitor circuit, one end of the bootstrap capacitor circuit is the gate signal point Q(N), and the bootstrap capacitor circuit passes all The gate signal point Q(N) and the source of the first thin film transistor T11 are connected to the bootstrap capacitor circuit to maintain the potential of the gate signal point Q(N) in the current GOA unit.
  • a liquid crystal display including the above GOA circuit is provided.
  • the working principle of the liquid crystal display provided in this embodiment is consistent with the working principle of the aforementioned GOA circuit embodiment, and the specific structural relationship and working principle can be referred to the aforementioned GOA circuit embodiment, which will not be repeated here.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Computer Hardware Design (AREA)
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Abstract

公开了一种GOA电路及液晶显示器。该GOA电路包括2N个GOA单元，该2N个GOA单元中第N级GOA单元与第N+1级GOA单元共用同一个下拉维持电路，N为正整数。通过共用一个下拉维持电路，减少了GOA电路中电路的数量，从而节省了GOA电路在液晶显示器上所占据的空间，同时提高了TFT器件中电路的使用效率，有利于液晶显示器的窄边框设计。

Description

GOA电路及液晶显示器 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路及液晶显示器。
 背景技术
随着薄膜晶体管（Thin Film Transistor，TFT）性能的提升，数组基板行扫描驱动（Gate Driver On Array，GOA）技术是利用薄膜晶体管液晶显示器Array制程，将Gate行扫描驱动信号制作在Array基板上，实现对Gate逐行扫描的驱动方式的一项技术，目前已经普遍应用于我们的面板中，GOA技术具有很多的优点，可以提升产品良率，实现无边框设计等。
 技术问题
随着市场对产品要求的不断提高，大尺寸、高分辨率、高刷新频率的液晶面板成为各大厂商竞相发展的目标，随着窄边框设计的日益流行，面板设计的周边空间被逐渐压缩，在传统的GOA电路设计中，每一级GOA电路的布线空间高度h和对应的像素尺寸是一致的，现在4k或者更高分辨率 (pixel per inch，PPI)产品的逐渐普及，像素的尺寸越来越小，留给GOA电路进行布线的空间高度也随之减小，由于高度受到限制，在布线时只能用更大的宽度来进行弥补，且GOA电路本身的尺寸也越来越大，功能越来越复杂导致边框变得越来越宽，对窄边框的设计非常不利。
 技术解决方案
本发明实施例提供一种GOA电路及液晶显示器，通过将GOA电路中相邻两级之间的GOA单元设置为共用同一个下拉维持电路，减少了GOA电路中电路的数量，节省了GOA电路所占据的空间，且同时提高了TFT器件中电路的使用效率，有利于液晶显示器的窄边框设计。
为了解决上述问题，第一方面，本申请提供一种GOA电路，用于液晶显示器，该GOA电路包括2N个GOA单元，所述2N个GOA单元中第N级GOA单元与第N+1级GOA单元共用同一个下拉维持电路，其中，N为正整数。
进一步的，该第N级GOA单元依次对显示区域的第N级水平扫描线充电，所述第N级GOA单元包括上拉控制电路、上拉电路、下传电路、下拉电路和时钟信号线；
其中，所述N级上拉控制电路与所述N+1级上拉控制电路采用相同的控制信号。
进一步的，该上拉控制电路包括第一薄膜晶体管T11，所述第一薄膜晶体管T11的栅极用以接受第N-4级的GOA单元的触发信号，第一薄膜晶体管T11的源极与所述下传电路连接；
其中，M大于或等于2，N大于4。
进一步的，该信号下传电路包括第二薄膜晶体管T22，所述第二薄膜晶体管T22的栅极与所述第一薄膜晶体管T11的源极连接，所述第二薄膜晶体管T22的漏极与时钟信号线连接，所述第二薄膜晶体管T22的源极与所述下拉单元连接，所述信号下传电路用以控制下一级GOA单元中信号的打开和关闭。
进一步的，该上拉电路包括第三薄膜晶体管T21，所述第三薄膜晶体管T21的漏极与当前信号下传电路所属的GOA单元同级的扫描线连接。
进一步的，该信号下拉电路包括第四薄膜晶体管T41和第五薄膜晶体管T31，所述第四薄膜晶体管T41的栅极与所述第五薄膜晶体管T31的栅极连接，所述第四薄膜晶体管T41的漏极与所述第二薄膜晶体管T22的栅极连接，所述第四薄膜晶体管T41的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接，所述第五薄膜晶体管T31的栅极与所述第四薄膜晶体管T41的栅极连接，所述第五薄膜晶体管T31的漏极与当前GOA电路中的扫描线连接，所述第五薄膜晶体管T31的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接。
进一步的，该下拉维持电路包括第六薄膜晶体管T51、第七薄膜晶体管T52、第八薄膜晶体管T53和第九薄膜晶体管T54；所述第六薄膜晶体管T51的栅极与第六薄膜晶体管T51的漏极连接高电平信号所述第六薄膜晶体管T51的源极与所述第七薄膜晶体管T52的漏极连接；所述第七薄膜晶体管T52的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接；所述第七薄膜晶体管T52的栅极和第一薄膜晶体管T11漏极相连接。
进一步的，该第八薄膜晶体管T53的栅极与所述第六薄膜晶体管T51的源极连接，所述第八薄膜晶体管T53的源极与所述第九薄膜晶体管T54的漏极相连接，所述第八薄膜晶体管T53的漏极与所述第六薄膜晶体管T51的漏极相连接；所述第九薄膜晶体管T54的栅极与所述第一薄膜晶体管T11的漏极连接，所述第九薄膜晶体管T54的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接。
进一步的，该GOA单元还包括自举电容电路，所述自举电容电路的一端为第一节点，所述自举电容电路通过所述第一节点与第一薄膜晶体管T11的源极连接所述自举电容电路用以维持当前GOA单元中栅极信号点的电位。
进一步的，所述下拉维持电路为反相器。
第二方面，本发明还申请一种液晶显示器，所述液晶显示器包括如上任一项所述的GOA电路。
进一步的，该GOA电路包括2N个GOA单元，所述2N个GOA单元中第N级GOA单元与第N+1级GOA单元共用同一个下拉维持电路，其中，N为正整数。
进一步的，该第N级GOA单元依次对显示区域的第N级水平扫描线充电，所述第N级GOA单元包括上拉控制电路、上拉电路、下传电路、下拉电路和时钟信号线；
其中，所述N级上拉控制电路与所述N+1级上拉控制电路采用相同的控制信号。
进一步的，该上拉控制电路包括第一薄膜晶体管T11，所述第一薄膜晶体管T11的栅极用以接受第N-4级的GOA单元的触发信号，第一薄膜晶体管T11的源极与所述下传电路连接；
其中，M大于或等于2，N大于4。
进一步的，该信号下传电路包括第二薄膜晶体管T22，所述第二薄膜晶体管T22的栅极与所述第一薄膜晶体管T11的源极连接，所述第二薄膜晶体管T22的漏极与时钟信号线连接，所述第二薄膜晶体管T22的源极与所述下拉单元连接，所述信号下传电路用以控制下一级GOA单元中信号的打开和关闭。
进一步的，该上拉电路包括第三薄膜晶体管T21，所述第三薄膜晶体管T21的漏极与当前信号下传电路所属的GOA单元同级的扫描线连接。
进一步的，该信号下拉电路包括第四薄膜晶体管T41和第五薄膜晶体管T31，所述第四薄膜晶体管T41的栅极与所述第五薄膜晶体管T31的栅极连接，所述第四薄膜晶体管T41的漏极与所述第二薄膜晶体管T22的栅极连接，所述第四薄膜晶体管T41的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接，所述第五薄膜晶体管T31的栅极与所述第四薄膜晶体管T41的栅极连接，所述第五薄膜晶体管T31的漏极与当前GOA电路中的扫描线连接，所述第五薄膜晶体管T31的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接。
进一步的，该下拉维持电路包括第六薄膜晶体管T51、第七薄膜晶体管T52、第八薄膜晶体管T53和第九薄膜晶体管T54；所述第六薄膜晶体管T51的栅极与第六薄膜晶体管T51的漏极连接高电平信号所述第六薄膜晶体管T51的源极与所述第七薄膜晶体管T52的漏极连接；所述第七薄膜晶体管T52的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接；所述第七薄膜晶体管T52的栅极和第一薄膜晶体管T11漏极相连接。
进一步的，该第八薄膜晶体管T53的栅极与所述第六薄膜晶体管T51的源极连接，所述第八薄膜晶体管T53的源极与所述第九薄膜晶体管T54的漏极相连接，所述第八薄膜晶体管T53的漏极与所述第六薄膜晶体管T51的漏极相连接；所述第九薄膜晶体管T54的栅极与所述第一薄膜晶体管T11的漏极连接，所述第九薄膜晶体管T54的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接。
进一步的，该GOA单元还包括自举电容电路，所述自举电容电路的一端为第一节点，所述自举电容电路通过所述第一节点与第一薄膜晶体管T11的源极连接所述自举电容电路用以维持当前GOA单元中栅极信号点的电位。
 有益效果
有益效果：本发明提供的GOA电路及液晶显示器，通过共用一个下拉维持电路，减少了GOA电路中电路的数量，从而节省了GOA电路在液晶显示器上所占据的空间，同时提高了TFT器件中电路的使用效率，有利于液晶显示器的窄边框设计。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明所提供的一种GOA电路中各个电路的连接关系一实施例示意图；
图2为本发明提供的一种GOA电路中各个位置的一实施例波形图；
图3为本发明提供的一种下拉维持电路的一实施例示意图；
图4为本发明提供的GOA电路中元器件的具体连接关系图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是用以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度都是任意示出的，但是本发明不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了理解方便和便于描述，夸大了一些层和区域的厚度。需要说明的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时。所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其他组件。此外在说明书中，“在……上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本发明为达成预定发明所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明提出的GOA电路及液晶显示器，其具体实施方式、结构、特征及其功效，详细说明如下。
请参阅图1，为本发明所提供的一种GOA电路中各个电路的连接关系一实施例示意图，下面以第N级GOA单元和第N+1级GOA单元为例，该GOA电路可以包括：N级上拉控制电路、N级上拉电路、N级下传电路、N级下拉电路、N级自举电容和N+1上拉控制电路、N+1级上拉电路、N+1级下传电路、N+1级下拉电路、N+1级下拉维持电路、N+1级自举电容。
其中，N级上拉电路及下拉维持电路分别与第N级栅极信号点Q(N)和第N级水平扫描线G(N)连接，N级上拉控制电路、N级下拉电路与第N级栅极信号点Q(N)连接。
N+1级上拉电路及下拉维持电路分别与第N+1级栅极信号点Q(N+1)和第N+1级水平扫描线G(N+1)连接，N+1级上拉控制电路、N+1级下拉电路与第N+1级栅极信号点Q(N+1)连接。
下拉维持电路在第N级水平扫描线G(N)充电后维持第N级栅极信号点Q(N)及第N级水平扫描线G(N)的电位至低电位，在第 N+1级水平扫描线G(N+1)充电后维持第N+1级栅极信号点Q(N+1) 及第N级水平扫描线G(N+1)的电位至低电位。
具体地，N级上拉控制电路在接收信号后抬高第N级栅极信号点Q(N)的电位值高电位并控制N级上拉电路打开，接收N级时钟信号CK(N)从而对第N级水平扫描线G(N)充电，充电完成后，N级下拉电路下拉第N级栅极信号点Q(N)的电位至低电位，同时关闭N级上拉电路，下拉维持电路下拉并维持第N级栅极信号点Q(N)和第N级水平扫描线G(N)的电位至低电位并维持低电位。
两级电路的工作期间，下拉维持电路在第一时钟信号CK1和第二时钟信号CK2的控制下同时下拉两级电路的电位至低电位并维持低电位。
参阅图2为本发明所提供的一种GOA电路中各个位置的一实施例波形图。
在本发明一实施例中，由于第N级和第N+1级的上拉控制单元采用相同的控制信号，均为ST(N-4)和G(N-4)，因此Q(N)点和Q(N+1)点第一阶段的充电是同一时间开始的，但由于时钟信号的差异，第二充电阶段却是不同时间完成的。
区别于现有技术，本实施方式通过将相邻的两级GOA单元进行耦合，使两级GOA单元共用同一个下拉维持电路，该下拉维持电路在第一级GOA电路充电完后维持第一级GOA电路至低电位，在第二级GOA电路充电完后维持第二级GOA电路至低电位。采用这样的方式可以减少GOA电路中的电路数量，从而节省GOA电路所占据的空间，有利于液晶显示器的窄边框设计。
在本发明的一些实施例中，共用同一个下拉维持电路的GOA单元也可以为相邻的两个或多个下拉维持电路。例如，共用同一个下拉维持电路的GOA单元可以为第一级、第二级GOA单元。或者，共用同一个下拉维持电路的GOA单元可以为第一级、第二级、第三级等多个GOA单元。
在本发明的一些其他实施例中，共用同一个下拉维持电路的GOA单元也可以为并不相邻的两个或多个GOA单元。例如，共用同一个下拉维持电路的GOA单元可以为第一级、第三级GOA单元。或者，共用同一个下拉维持电路的GOA单元可以为第一级、第三级、第五级GOA单元。
参阅图3，在本发明的一些实施例中，该下拉维持电路可以为一种反相器，其中，LC端为高电平信号，VSS端为低电平信号，当Input端输入高电位信号时，Output端输出低电位信号，当Input端输入低电位信号时，Output端输出高电位信号。
请参阅图4为本发明所提供的GOA电路中元器件的具体连接关系图。其中，上拉控制电路包括第一薄膜晶体管T11，第一薄膜晶体管T11的栅极接收控制信号，第一薄膜晶体管T11的源极与所述下传电路连接；
优选的，本发明一实施例中，第一薄膜晶体管T11的栅极可以接收来自第N-4级GOA单元触发的信号，N大于4。
在本发明的一些实施例中，信号下传电路可以包括第二薄膜晶体管T22，所述第二薄膜晶体管T22的栅极与所述第一薄膜晶体管T11的源极连接，所述第二薄膜晶体管T22的漏极与时钟信号线连接，所述第二薄膜晶体管T22的源极与所述下拉单元连接，所述信号下传电路用以控制下一级GOA单元中信号的打开和关闭。
该上拉电路可以包括第三薄膜晶体管T21，所述第三薄膜晶体管T21的漏极与当前信号下传电路所属的GOA单元同级的扫描线连接。第三薄膜晶体管T21的源极与当前下拉电路所属的GOA单元同级的时钟信号线连接。
在本发明的一些其他实施例中，所述信号下拉电路可以包括第四薄膜晶体管T41和第五薄膜晶体管T31，所述第四薄膜晶体管T41的栅极与所述第五薄膜晶体管T31的栅极连接，所述第四薄膜晶体管T41的漏极与所述第二薄膜晶体管T22的栅极连接，所述第四薄膜晶体管T41的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接，所述第五薄膜晶体管T31的栅极与所述第四薄膜晶体管T41的栅极连接，所述第五薄膜晶体管T31的漏极与当前GOA电路中的扫描线连接，所述第五薄膜晶体管T31的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接。
优选的，在本发明的一些实施例中，所述下拉维持电路可以包括第六薄膜晶体管T51、第七薄膜晶体管T52、第八薄膜晶体管T53和第九薄膜晶体管T54；所述第六薄膜晶体管T51的栅极与第六薄膜晶体管T51的漏极连接高电平信号；所述第六薄膜晶体管T51的源极与所述第七薄膜晶体管T52的漏极连接；所述第七薄膜晶体管T52的源极与所述下拉信号线连接；所述第七薄膜晶体管T52的栅极和第一薄膜晶体管T11漏极相连接。
优选的，所述第八薄膜晶体管T53的栅极与所述第六薄膜晶体管T51的源极连接，所述第八薄膜晶体管T53的源极与所述第九薄膜晶体管T54的漏极相连接，所述第八薄膜晶体管T53的漏极与所述第六薄膜晶体管T51的漏极相连接；所述第九薄膜晶体管T54的栅极与所述第一薄膜晶体管T11的漏极连接，所述第九薄膜晶体管T54的源极与所述当前下拉维持电路所属的GOA单元同级的下拉信号线连接。
优选的，在本发明所提供的GOA电路中，该GOA单元还可以包括自举电容电路，所述自举电容电路的一端为栅极信号点Q（N），所述自举电容电路通过所述栅极信号点Q（N）与第一薄膜晶体管T11的源极连接所述自举电容电路用以维持当前GOA单元中栅极信号点Q（N）的电位。
根据本发明的上述目的，提出一种液晶显示器，包括上述的GOA电路。本实施例提供的液晶显示器的工作原理，与前述GOA电路的实施例工作原理一致，具体结构关系及工作原理参见前述GOA电路实施例，此处不再赘述。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种GOA电路，用于液晶显示器，其中，所述GOA电路包括2N个GOA单元，所述2N个GOA单元中第N级GOA单元与第N+1级GOA单元共用同一个下拉维持电路，其中，N为正整数。
  2. 根据权利要求1所述的GOA电路，其中，所述第N级GOA单元依次对显示区域的第N级水平扫描线充电，所述第N级GOA单元包括上拉控制电路、上拉电路、下传电路、下拉电路和时钟信号线；
    其中，所述N级上拉控制电路与所述N+1级上拉控制电路采用相同的控制信号。
  3. 根据权利要求2所述的GOA电路，其中，所述上拉控制电路包括第一薄膜晶体管(T11)，所述第一薄膜晶体管(T11)的栅极用以接受第N+M级的GOA单元的触发信号，第一薄膜晶体管(T11)的源极与所述下传电路连接；
    其中，M大于或等于2，N大于4。
  4. 根据权利要求3所述的GOA电路，其中，所述信号下传电路包括第二薄膜晶体管(T22)，所述第二薄膜晶体管(T22)的栅极与所述第一薄膜晶体管(T11)的源极连接，所述第二薄膜晶体管(T22)的漏极与时钟信号线连接，所述第二薄膜晶体管(T22)的源极与所述下拉单元连接，所述信号下传电路用以控制下一级GOA单元中信号的打开和关闭。
  5. 根据权利要求2所述的GOA电路，其中，所述上拉电路包括第三薄膜晶体管(T21)，所述第三薄膜晶体管(T21)的漏极与当前信号下传电路所属的GOA单元同级的扫描线连接。
  6. 根据权利要求2所述的GOA电路，其中，所述信号下拉电路包括第四薄膜晶体管(T41)和第五薄膜晶体管(T31)，所述第四薄膜晶体管(T41)的栅极与所述第五薄膜晶体管(T31)的栅极连接，所述第四薄膜晶体管(T41)的漏极与所述第二薄膜晶体管(T22)的栅极连接，所述第四薄膜晶体管(T41)的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接，所述第五薄膜晶体管(T31)的栅极与所述第四薄膜晶体管(T41)的栅极连接，所述第五薄膜晶体管(T31)的漏极与当前GOA电路中的扫描线连接，所述第五薄膜晶体管(T31)的源极与所述当前信号下拉电路所属的GOA单元同级的下拉信号线连接。
  7. 根据权利要求1所述的GOA电路，其中，所述下拉维持电路包括第六薄膜晶体管(T51)、第七薄膜晶体管(T52)、第八薄膜晶体管(T53)和第九薄膜晶体管(T54)；所述第六薄膜晶体管(T51)的栅极与第六薄膜晶体管(T51)的漏极连接高电平信号所述第六薄膜晶体管(T51)的源极与所述第七薄膜晶体管(T52)的漏极连接；所述第七薄膜晶体管(T52)的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接；所述第七薄膜晶体管(T52)的栅极和第一薄膜晶体管(T11)漏极相连接。
  8. 根据权利要求7所述的GOA电路，其中，所述第八薄膜晶体管(T53)的栅极与所述第六薄膜晶体管(T51)的源极连接，所述第八薄膜晶体管(T53)的源极与所述第九薄膜晶体管(T54)的漏极相连接，所述第八薄膜晶体管(T53)的漏极与所述第六薄膜晶体管(T51)的漏极相连接；所述第九薄膜晶体管(T54)的栅极与所述第一薄膜晶体管(T11)的漏极连接，所述第九薄膜晶体管(T54)的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接。
  9. 根据权利要求2所述的GOA电路，其中，所述GOA单元还包括自举电容电路，所述自举电容电路的一端为第一节点，所述自举电容电路通过所述第一节点与第一薄膜晶体管(T11)的源极连接，所述自举电容电路用以维持当前GOA单元中栅极信号点的电位。
  10. 根据权利要求1所述的GOA电路，其中，所述下拉维持电路为反相器。
  11. 一种液晶显示器，其中，所述液晶显示器包括如权利要求1所述的GOA电路。
  12. 根据权利要求11所述的液晶显示器，其中，所述GOA电路包括2N个GOA单元，所述2N个GOA单元中第N级GOA单元与第N+1级GOA单元共用同一个下拉维持电路，其中，N为正整数。
  13. 根据权利要求12所述的液晶显示器，其中，所述第N级GOA单元依次对显示区域的第N级水平扫描线充电，所述第N级GOA单元包括上拉控制电路、上拉电路、下传电路、下拉电路和时钟信号线；
    其中，所述N级上拉控制电路与所述N+1级上拉控制电路采用相同的控制信号。
  14. 根据权利要求13所述的液晶显示器，其中，所述上拉控制电路包括第一薄膜晶体管(T11)，所述第一薄膜晶体管(T11)的栅极用以接受第N+M级的GOA单元的触发信号，第一薄膜晶体管(T11)的源极与所述下传电路连接；
    其中，M大于或等于2，N大于4。
  15. 根据权利要求14所述的液晶显示器，其中，所述信号下传电路包括第二薄膜晶体管(T22)，所述第二薄膜晶体管(T22)的栅极与所述第一薄膜晶体管(T11)的源极连接，所述第二薄膜晶体管(T22)的漏极与时钟信号线连接，所述第二薄膜晶体管(T22)的源极与所述下拉单元连接，所述信号下传电路用以控制下一级GOA单元中信号的打开和关闭。
  16. 根据权利要求13所述的液晶显示器，其中，所述上拉电路包括第三薄膜晶体管(T21)，所述第三薄膜晶体管(T21)的漏极与当前信号下传电路所属的GOA单元同级的扫描线连接。
  17. 根据权利要求13所述的液晶显示器，其中，所述信号下拉电路包括第四薄膜晶体管(T41)和第五薄膜晶体管(T31)，所述第四薄膜晶体管(T41)的栅极与所述第五薄膜晶体管(T31)的栅极连接，所述第四薄膜晶体管(T41)的漏极与所述第二薄膜晶体管(T22)的栅极连接，所述第四薄膜晶体管(T41)的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接，所述第五薄膜晶体管(T31)的栅极与所述第四薄膜晶体管(T41)的栅极连接，所述第五薄膜晶体管(T31)的漏极与当前GOA电路中的扫描线连接，所述第五薄膜晶体管(T31)的源极与所述当前信号下拉电路所属的GOA单元同级的下拉信号线连接。
  18. 根据权利要求12所述的液晶显示器，其中，所述下拉维持电路包括第六薄膜晶体管(T51)、第七薄膜晶体管(T52)、第八薄膜晶体管(T53)和第九薄膜晶体管(T54)；所述第六薄膜晶体管(T51)的栅极与第六薄膜晶体管(T51)的漏极连接高电平信号所述第六薄膜晶体管(T51)的源极与所述第七薄膜晶体管(T52)的漏极连接；所述第七薄膜晶体管(T52)的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接；所述第七薄膜晶体管(T52)的栅极和第一薄膜晶体管(T11)漏极相连接。
  19. 根据权利要求18所述的液晶显示器，其中，所述第八薄膜晶体管(T53)的栅极与所述第六薄膜晶体管(T51)的源极连接，所述第八薄膜晶体管(T53)的源极与所述第九薄膜晶体管(T54)的漏极相连接，所述第八薄膜晶体管(T53)的漏极与所述第六薄膜晶体管(T51)的漏极相连接；所述第九薄膜晶体管(T54)的栅极与所述第一薄膜晶体管(T11)的漏极连接，所述第九薄膜晶体管(T54)的源极与当前信号下拉电路所属的GOA单元同级的下拉信号线连接。
  20. 根据权利要求13所述的液晶显示器，其中，所述GOA单元还包括自举电容电路，所述自举电容电路的一端为第一节点，所述自举电容电路通过所述第一节点与第一薄膜晶体管(T11)的源极连接，所述自举电容电路用以维持当前GOA单元中栅极信号点的电位。
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