WO2020228149A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

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Publication number
WO2020228149A1
WO2020228149A1 PCT/CN2019/099263 CN2019099263W WO2020228149A1 WO 2020228149 A1 WO2020228149 A1 WO 2020228149A1 CN 2019099263 W CN2019099263 W CN 2019099263W WO 2020228149 A1 WO2020228149 A1 WO 2020228149A1
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WO
WIPO (PCT)
Prior art keywords
metal layer
layer
capacitor
light
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/099263
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English (en)
French (fr)
Inventor
蔡振飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/616,502 priority Critical patent/US11329259B2/en
Publication of WO2020228149A1 publication Critical patent/WO2020228149A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • This application relates to the field of electronic display, and in particular to a display panel and a manufacturing method thereof.
  • Active matrix organic light-emitting diodes have high contrast, wide viewing angle and fast response speed, and are the mainstream choice for next-generation displays.
  • the storage capacitor in the pixel driving circuit needs to be large enough.
  • the capacitor structure is a flat capacitor structure that forms an overlapped top and bottom.
  • the active area 040 and the anode 080 are electrically connected through the through holes to form the first plate of the capacitor structure; the source and drain metal layers form the second plate of the capacitor structure. Since the two plates are only separated by an insulating layer, when there are foreign objects or defects in the interlayer dielectric layer or the planarization layer, it will often cause a short circuit of the capacitor. Once a short circuit occurs, the pixel cannot emit light normally due to the failure of the capacitor. Therefore, it is urgent to solve this problem.
  • the present application provides a display panel and a manufacturing method thereof, so as to solve the technical problem that the display panel in the prior art is prone to failure due to capacitor short circuit.
  • the present application provides a display panel, the display panel includes a capacitor structure, the first electrode plate of the capacitor structure includes an active area electrically connected and a light-shielding metal layer, and the second electrode plate includes an electrical connection The anode and capacitor metal layer; among them,
  • the anode and the active area are arranged correspondingly, and at least two insulating layers are arranged between the anode and the active area;
  • the light-shielding metal layer and the capacitor metal layer are arranged correspondingly, and at least two insulating layers are arranged between the light-shielding metal layer and the capacitor metal layer.
  • the two insulating layers disposed between the anode and the active region include an interlayer dielectric layer and a planarization layer.
  • the two insulating layers disposed between the light-shielding metal layer and the capacitor metal layer include a buffer layer and an interlayer dielectric layer.
  • the display panel includes:
  • the light-shielding metal layer is located on the substrate, the buffer layer covers the light-shielding metal layer; the active area is located on the buffer layer, and is electrically connected to the light-shielding metal layer through a first through hole, the The active region includes a channel region and source and drain regions located on both sides of the channel region;
  • a gate stack the gate stack is located above the active region and covers the channel region, and the interlayer dielectric layer covers the active region and the gate stack;
  • a source-drain metal layer the source-drain metal layer is located above the interlayer dielectric layer, and is electrically connected to the source-drain region through a second through hole penetrating the interlayer dielectric layer;
  • the capacitor metal layer is located on the Above the interlayer dielectric layer, it is arranged spaced apart from the source and drain metal layers;
  • the planarization layer covers the source and drain metal layers and the capacitor metal layer;
  • the anode is located on the planarization layer and is connected to The source and drain metal layers and the capacitor metal layers are electrically connected respectively;
  • a light emitting structure the light emitting structure is located on the anode.
  • the projection of the capacitive metal layer on the substrate and the projection of the active area on the substrate do not overlap.
  • the projection of the light shielding metal layer on the substrate covers the projection of the capacitor metal layer on the substrate.
  • the projection of the anode on the substrate covers the projection of the active area on the substrate.
  • the present invention provides a manufacturing method of a display panel, which includes the following steps:
  • An anode and a capacitor metal layer are formed on the at least two insulating layers to form the second plate of the capacitor structure;
  • the anode and the active area are arranged correspondingly, and at least two insulating layers are arranged between the anode and the active area;
  • the light-shielding metal layer and the capacitor metal layer are arranged correspondingly, and at least two insulating layers are arranged between the light-shielding metal layer and the capacitor metal layer;
  • a light emitting structure is formed on the second electrode plate.
  • the at least two insulating layers disposed between the anode and the active region include an interlayer dielectric layer and a planarization layer.
  • the two insulating layers disposed between the light-shielding metal layer and the capacitor metal layer include a buffer layer and an interlayer dielectric layer.
  • the method of forming the first plate includes the following steps:
  • An active region is formed, the active region is located on the buffer layer and is electrically connected to the light-shielding metal layer through a first through hole, the active region includes a channel region and source and drain located on both sides of the channel region Area.
  • the method further includes the following steps:
  • An interlayer dielectric layer covering the active area and the gate stack is formed.
  • the method for forming the second plate includes the following steps:
  • Source-drain metal layer located above the interlayer dielectric layer, the source-drain metal layer being electrically connected to the source and drain regions through through holes penetrating the interlayer dielectric layer;
  • the capacitor metal layer is located above the interlayer dielectric layer and is spaced apart from the source and drain metal layers;
  • planarization layer Forming the planarization layer, the planarization layer covering the source and drain metal layers and the capacitor metal layer;
  • Forming the anode which is located on the planarization layer and is electrically connected to the source/drain metal layer and the capacitor metal layer through through holes;
  • the light-emitting structure is formed, and the light-emitting structure is located on the anode.
  • the projection of the capacitive metal layer on the substrate and the projection of the active area on the substrate do not overlap.
  • the projection of the light shielding metal layer on the substrate covers the projection of the capacitor metal layer on the substrate.
  • the projection of the anode on the substrate covers the projection of the active area on the substrate.
  • This application changes the structure of the two plates of the capacitor structure of the display panel in the prior art.
  • the anode of the display panel in this application is electrically connected with the capacitor metal layer to form the first electrode plate of the capacitor structure; at the same time, the active area and the light-shielding metal layer are electrically connected to form the second electrode plate of the capacitor structure. Since at least two insulating layers are spaced between the anode and the active region, and at least two insulating layers are also spaced between the light-shielding metal and the capacitor metal layer, the display panel of the present application can effectively avoid capacitor short circuits, thereby improving the display panel The reliability and service life.
  • FIG. 1 is a schematic diagram of the structure of a display panel in the prior art
  • FIG. 2 is a schematic diagram of the structure of the display panel in a specific embodiment of the application during the manufacturing process
  • FIG. 3 is a schematic diagram of the structure after the active area is fabricated on the display panel in FIG. 2;
  • FIG. 4 is a schematic diagram of the structure after the gate stack is fabricated on the display panel in FIG. 3;
  • FIG. 5 is a schematic diagram of the structure after the source and drain regions are formed on the display panel in FIG. 4;
  • FIG. 6 is a schematic diagram of the structure after the source and drain metal layers are fabricated on the display panel in FIG. 5;
  • FIG. 7 is a schematic diagram of the structure after the anode is fabricated on the display panel in FIG. 6;
  • FIG. 8 is a schematic structural diagram of a display panel in a specific embodiment of the application.
  • FIG. 1 is a schematic diagram of the structure of a display panel in the prior art.
  • the display panel includes a substrate 010, a light shielding layer 020, a buffer layer 030, an active region 040, a gate stack 050, an interlayer dielectric layer 060, a source and drain metal layer 070, a capacitor metal layer 072, a planarization layer 074, and a
  • the light-emitting structure includes an anode 080, a pixel defining layer 090, a light-emitting material 092, and a cathode 094.
  • the capacitor structure is a flat-plate capacitor structure overlapping up and down.
  • the active area 040 and the anode 080 are usually electrically connected to form one plate of the capacitor structure through a through hole, and the source and drain metal layers form the other plate of the capacitor structure. . Since the two plates are only separated by an insulating layer, when there are foreign objects or defects in the interlayer dielectric layer or the planarization layer, it will often cause a short circuit of the capacitor. Once a short circuit occurs, the pixel cannot emit light normally due to the failure of the capacitor.
  • the light shielding layer and the anode are used as the two plates of the capacitor structure, which will cause the distance between the two plates to be too large, resulting in a serious small capacitance value, which will also affect The display function of the display panel.
  • the present application provides a display panel and a manufacturing method thereof to solve the technical problem that the display panel in the prior art is prone to failure due to short-circuit of the capacitor.
  • FIG. 8 is a schematic structural diagram of a display panel in a specific embodiment of the application.
  • the display panel includes: a substrate 10, a light-shielding metal layer 20, a buffer layer 30, an active area 40, a gate stack 50, an interlayer dielectric layer 60, a source and drain metal layer 70, a capacitor metal layer 72, and a planarization layer 74 , Anode 80 and light emitting structure.
  • the light emitting structure is located on the anode 80.
  • the first electrode plate of the capacitor structure includes an active area 40 and a light-shielding metal layer 20 electrically connected
  • the second electrode plate includes an anode 80 and a capacitor metal layer 72 electrically connected.
  • the anode 80 and the active area 40 are arranged correspondingly, and at least two insulating layers are arranged between the anode 80 and the active area 40.
  • the light-shielding metal layer 20 and the capacitor metal layer 72 are arranged correspondingly, and at least two insulating layers are provided between the light-shielding metal layer 20 and the capacitor metal layer 72.
  • the two insulating layers disposed between the anode 80 and the active region 40 include an interlayer dielectric layer 60 and a planarization layer 74.
  • the two insulating layers disposed between the light-shielding metal layer 20 and the capacitor metal layer 72 include a buffer layer 30 and an interlayer dielectric layer 60.
  • the display panel is a liquid crystal panel or an organic light emitting diode display panel.
  • the substrate 10 may be a rigid substrate, such as glass; or a flexible substrate, such as a polyimide film.
  • the light-shielding metal layer 20 is located on the substrate 10.
  • the light-shielding metal layer 20 is used to shield the light entering the active area from the outside, so as to prevent the carrier mobility of the active area from being affected by light. Therefore, the light-shielding metal layer 20 is disposed corresponding to the gate stack 50.
  • the projection of the light shielding metal layer 20 on the substrate 10 completely covers the projection of the gate stack 50 on the substrate 10.
  • the buffer layer 30 covers the light shielding metal layer 20.
  • the buffer layer 30 has at least one first through hole, and the first through hole exposes the light shielding metal layer 20.
  • the active region 40 is located on the buffer layer 30 and is electrically connected to the light-shielding metal layer 20 through a first through hole.
  • the active region 40 includes a channel region and source and drain regions located on both sides of the channel region .
  • the gate stack 50 is located above the active region 40 and covers the channel region.
  • the gate stack 50 includes a gate dielectric layer and a gate metal layer.
  • the interlayer dielectric layer 60 covers the active region 40 and the gate stack 50.
  • the interlayer dielectric layer 60 has at least one second through hole exposing the active region 40.
  • the source and drain metal layer 70 is located above the interlayer dielectric layer 60 and is electrically connected to the source and drain regions through a second through hole penetrating the interlayer dielectric layer 60.
  • the capacitor metal layer 72 is located above the interlayer dielectric layer 60 and is spaced apart from the source and drain metal layer 70.
  • the planarization layer 74 covers the source and drain metal layer 70 and the capacitor metal layer 72.
  • the planarization layer 74 has at least one third through hole exposing the source and drain metal layer 70 and the capacitor metal layer 72.
  • the anode 80 is located on the planarization layer 74 and is electrically connected to the source/drain metal layer 70 and the capacitor metal layer 72 through the third through hole, and the light emitting structure is located on the anode 80.
  • the light-emitting structure includes a pixel defining layer 90, a light-emitting material 92 and a cathode 94.
  • the pixel defining layer 90 has a through hole exposing the anode 80.
  • the luminescent material 92 is located on the anode 80, and the cathode 94 covers the luminescent material 92.
  • the anode 80 and the capacitor metal layer 72 are connected to the same potential to form the first plate of the capacitor structure.
  • the active region 40 and the light-shielding metal 20 are connected to the same potential to form a second plate of the capacitor structure.
  • the minimum distance between the two plates of the capacitor structure is the distance between the active region 40 and the capacitor metal layer 72.
  • the projection of the capacitor metal layer 72 on the substrate 10 and the projection of the active area 40 on the substrate 10 do not overlap or partially overlap.
  • the projection of the light shielding metal layer 20 on the substrate 10 covers the projection of the capacitor metal layer 72 on the substrate 10.
  • the projection of the anode 80 on the substrate 10 covers the projection of the active region 40 layer on the substrate 10.
  • the display panel further includes a second gate stack and a second interlayer dielectric layer located between the interlayer dielectric layer 60 and the planarization layer 74.
  • the second gate stack is located directly above the gate stack 50.
  • the second gate dielectric layer covers the second gate stack and the interlayer dielectric layer 60.
  • the source/drain metal layer 70 is located above the second interlayer dielectric layer, and is electrically connected to the source/drain regions through via holes.
  • the arrangement of the second gate structure can increase the gate control capability of the thin film transistor, and at the same time can increase the distance between the two plates of the capacitor structure, and reduce the risk of short circuit between the two plates of the capacitor structure.
  • the present application also provides a manufacturing method of the display panel.
  • the method includes the following steps:
  • An anode 80 and a capacitor metal layer 72 are formed on the at least two insulating layers to form the second plate of the capacitor structure;
  • the anode 80 and the active area 40 are arranged correspondingly, and at least two insulating layers are arranged between the anode 80 and the active area 40;
  • the light-shielding metal layer 20 and the capacitor metal layer 72 are arranged correspondingly, and at least two insulating layers are provided between the light-shielding metal layer 20 and the capacitor metal layer 72;
  • a light emitting structure is formed on the second electrode plate.
  • a substrate 10 is provided first, and a light-shielding metal layer 20 is formed on the substrate 10, and then a buffer layer 30 covering the light-shielding metal layer 20 is formed.
  • the substrate 10 may be a rigid substrate, such as glass; or a flexible substrate, such as a polyimide film.
  • the light-shielding metal layer 20 is located on the substrate 10.
  • the light-shielding metal layer 20 is used to shield the light entering the active area from the outside, so as to prevent the carrier mobility of the active area from being affected by light. Therefore, the light-shielding metal layer 20 is disposed corresponding to the gate stack 50.
  • the projection of the light shielding metal layer 20 on the substrate 10 completely covers the projection of the gate stack 50 on the substrate 10.
  • the buffer layer 30 covers the light shielding metal layer 20.
  • the buffer layer 30 has at least one first through hole, and the first through hole exposes the light shielding metal layer 20.
  • an active region 40 is formed.
  • the active region 40 is located on the buffer layer 30 and is electrically connected to the light-shielding metal layer 20 through a first through hole.
  • the active region 40 includes a channel Area.
  • a gate stack 50 covering the channel region is formed above the active region 40.
  • the gate stack 50 includes a gate dielectric layer and a gate metal layer.
  • the active region 40 is conductorized using the gate stack as a mask to form a channel region and source and drain regions on both sides of the channel region.
  • the method of conductorization is ion implantation.
  • an interlayer dielectric layer 60 covering the active region 40 and the gate stack, and a source and drain metal layer 70 and a capacitor metal layer 72 located above the interlayer dielectric layer 60 are formed.
  • the interlayer dielectric layer 60 covers the active region 40 and the gate stack 50.
  • the interlayer dielectric layer 60 has at least one second through hole exposing the active region 40.
  • the source/drain metal layer 70 is electrically connected to the source/drain region through a through hole penetrating the interlayer dielectric layer 60.
  • the capacitor metal layer 72 is located above the interlayer dielectric layer 60 and is spaced apart from the source and drain metal layer 70.
  • the source and drain metal layer 70 is located above the interlayer dielectric layer 60 and is electrically connected to the source and drain regions through a second through hole penetrating the interlayer dielectric layer 60.
  • the capacitor metal layer 72 is located above the interlayer dielectric layer 60 and is spaced apart from the source and drain metal layer 70.
  • a planarization layer 74 and an anode 80 on the planarization layer 74 are formed.
  • the planarization layer 74 covers the source and drain metal layer 70 and the capacitor metal layer 72.
  • the planarization layer 74 has at least one third through hole exposing the source and drain metal layer 70 and the capacitor metal layer 72.
  • the anode 80 is located on the planarization layer 74 and is electrically connected to the source/drain metal layer 70 and the capacitor metal layer 72 through through holes.
  • the light emitting structure includes a pixel defining layer 90, a light emitting material 92 and a cathode 94.
  • the pixel defining layer 90 has a through hole exposing the anode 80.
  • the luminescent material 92 is located on the anode 80, and the cathode 94 covers the luminescent material 92.
  • the anode 80 and the capacitor metal layer 72 are connected to the same potential to form the first plate of the capacitor structure.
  • the active region 40 and the light-shielding metal 20 are connected to the same potential to form a second plate of the capacitor structure.
  • the minimum distance between the two plates of the capacitor structure is the distance between the active region 40 and the capacitor metal layer 72.
  • the projection of the capacitor metal layer 72 on the substrate 10 and the projection of the active area 40 on the substrate 10 do not overlap or partially overlap.
  • the projection of the light shielding metal layer 20 on the substrate 10 covers the projection of the capacitor metal layer 72 on the substrate 10.
  • the projection of the anode 80 on the substrate 10 covers the projection of the active region 40 layer on the substrate 10.
  • the method further includes: forming on the interlayer dielectric layer 60 located on the gate stack The second gate stack directly above the layer 50; and a second gate dielectric layer covering the second gate stack and the interlayer dielectric layer 60 is formed.
  • the arrangement of the second gate structure can increase the gate control capability of the thin film transistor, and at the same time can increase the distance between the two plates of the capacitor structure, and reduce the risk of short circuit between the two plates of the capacitor structure.
  • This application changes the structure of the two plates of the capacitor structure of the display panel in the prior art.
  • the anode of the display panel in this application is electrically connected with the capacitor metal layer to form the first electrode plate of the capacitor structure; at the same time, the active area and the light shielding metal layer are electrically connected to form the second electrode plate of the capacitor structure. Since at least two insulating layers are spaced between the anode and the active region, and at least two insulating layers are also spaced between the light-shielding metal and the capacitor metal layer, the display panel of the present application can effectively avoid capacitor short circuits, thereby improving the display panel The reliability and service life.

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

本申请提供了一种显示面板及其制作方法。所述显示面板包括电容结构，所述电容结构的第一极板包括电连接的有源区和遮光金属层，第二极板包括电连接的阳极和电容金属层；其中，所述阳极和有源区对应设置，所述阳极和有源区之间设置有至少两层绝缘层；所述遮光金属层和电容金属层对应设置，所述遮光金属层和电容金属层之间设置有至少两层绝缘层。

Description

显示面板及其制作方法 技术领域
本申请涉及电子显示领域，尤其涉及一种显示面板及其制作方法。
 背景技术
主动矩阵有机发光二极体的对比度高、可视角度广且响应速度快，是下一代显示器的主流选择。显示面板中，为了保证每帧数据正常写入，保证像素点正常发光，需要像素驱动电路中的存储电容足够大。
 技术问题
参见图1，在目前的显示面板中，电容结构为形成上下交叠的平板电容结构。其中，有源区040和阳极080通过通孔电连接，构成电容结构的第一极板；源漏金属层构成电容结构的第二极板。由于两个极板之间仅仅通过一层绝缘层隔离，当层间介质层或者平坦化层中存在异物或缺陷时，往往会造成电容短路。一旦发生短路，像素就因为电容失效而不能正常发光。因此，亟需解决这一问题。
 技术解决方案
本申请提供了一种显示面板及其制作方法，以解决现有技术中的显示面板容易由于电容短路而失效的技术问题。
为解决上述问题，本申请提供了一种显示面板，所述显示面板包括电容结构，所述电容结构的第一极板包括电连接的有源区和遮光金属层，第二极板包括电连接的阳极和电容金属层；其中，
所述阳极和有源区对应设置，所述阳极和有源区之间设置有至少两层绝缘层；
所述遮光金属层和电容金属层对应设置，所述遮光金属层和电容金属层之间设置有至少两层绝缘层。
根据本申请的其中一个方面，设置于所述阳极和有源区之间的两层绝缘层包括层间介质层和平坦化层。
根据本申请的其中一个方面，设置于所述遮光金属层和电容金属层之间的两层绝缘层包括缓冲层和层间介质层。
根据本申请的其中一个方面，所述显示面板包括：
基板；
所述遮光金属层位于所述基板上，所述缓冲层覆盖所述遮光金属层；所述有源区位于所述缓冲层上，通过第一通孔与所述遮光金属层电连接，所述有源区包括沟道区和位于沟道区两侧的源漏区；
栅极叠层，所述栅极叠层位于所述有源区上方，并覆盖所述沟道区，所述层间介质层覆盖所述有源区和栅极叠层；
源漏金属层，所述源漏金属层位于所述层间介质层上方，通过贯穿所述层间介质层的第二通孔与所述源漏区电连接；所述电容金属层位于所述层间介质层上方，与所述源漏金属层间隔设置；所述平坦化层覆盖所述源漏金属层和电容金属层；所述阳极位于所述平坦化层上，通过第三通孔与所述源漏金属层和电容金属层分别电连接；
发光结构，所述发光结构位于所述阳极上。
根据本申请的其中一个方面，所述电容金属层在所述基板上的投影与所述有源区在基板上的投影不重叠。
根据本申请的其中一个方面，所述遮光金属层在所述基板上的投影覆盖所述电容金属层在基板上的投影。
根据本申请的其中一个方面，所述阳极在所述基板上的投影覆盖所述有源区在基板上的投影。
相应的，本发明提供了一种显示面板的制作方法，该方法包括以下步骤：
提供基板；
在所述基板上形成遮光金属层和有源区，构成电容结构的第一极板；
形成覆盖所述第一极板的至少两层绝缘层；
在所述至少两层绝缘层上形成阳极和电容金属层，构成电容结构的第二极板；其中，
所述阳极和有源区对应设置，所述阳极和有源区之间设置有至少两层绝缘层；
所述遮光金属层和电容金属层对应设置，所述遮光金属层和电容金属层之间设置有至少两层绝缘层；
在所述第二极板上形成发光结构。
根据本申请的其中一个方面，设置于所述阳极和有源区之间的至少两层绝缘层包括层间介质层和平坦化层。
根据本申请的其中一个方面，设置于所述遮光金属层和电容金属层之间的两层绝缘层包括缓冲层和层间介质层。
根据本申请的其中一个方面，形成所述第一极板的方法包括以下步骤：
在所述基板上形成遮光金属层；
形成覆盖所述遮光金属层的缓冲层；
形成有源区，所述有源区位于所述缓冲层上，通过第一通孔与所述遮光金属层电连接，所述有源区包括沟道区和位于沟道区两侧的源漏区。
根据本申请的其中一个方面，形成所述有源区之后，所述方法还包括以下步骤：
在所述有源区上方形成覆盖所述沟道区的栅极叠层；
形成覆盖所述有源区和栅极叠层的层间介质层。
根据本申请的其中一个方面，形成所述第二极板的方法包括以下步骤：
形成位于所述层间介质层上方的源漏金属层，所述源漏金属层通过贯穿所述层间介质层的通孔与所述源漏区电连接；
形成所述电容金属层，所述电容金属层位于所述层间介质层上方，与所述源漏金属层间隔设置；
形成所述平坦化层，所述平坦化层覆盖所述源漏金属层和电容金属层；
形成所述阳极，所述阳极位于所述平坦化层上，通过通孔与所述源漏金属层和电容金属层分别电连接；
形成所述发光结构，所述发光结构位于所述阳极上。
根据本申请的其中一个方面，所述电容金属层在所述基板上的投影与所述有源区在基板上的投影不重叠。
根据本申请的其中一个方面，所述遮光金属层在所述基板上的投影覆盖所述电容金属层在基板上的投影。
根据本申请的其中一个方面，所述阳极在所述基板上的投影覆盖所述有源区在基板上的投影。
 有益效果
本申请改变了现有技术中的显示面板的电容结构的两个极板的构成方式。本申请中的显示面板的阳极与电容金属层电连接，构成电容结构的第一极板；同时有源区和遮光金属层电连接，构成电容结构的第二极板。由于阳极和有源区之间间隔了至少两层绝缘层，遮光金属和电容金属层之间同样间隔了至少两层绝缘层，本申请的显示面板能够有效的避免电容短路，从而提高了显示面板的可靠性和使用寿命。
 附图说明
图1为现有技术中的显示面板的结构示意图；
图2为本申请的一个具体实施例中的显示面板制作过程中的结构示意图；
图3为在图2中的显示面板上制作有源区之后的结构示意图；
图4为在图3中的显示面板上制作栅极叠层之后的结构示意图；
图5为在图4中的显示面板上制作源漏区之后的结构示意图；
图6为在图5中的显示面板上制作源漏金属层之后的结构示意图；
图7为在图6中的显示面板上制作阳极之后的结构示意图；
图8为本申请的一个具体实施例中的显示面板的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
首先对现有技术进行简要说明。参见图1，图1为现有技术中的显示面板的结构示意图。所述显示面板包括基板010、遮光层020、缓冲层030、有源区040、栅极叠层050、层间介质层060、源漏金属层070、电容金属层072、平坦化层074以及位于平坦化层074上的发光结构。所述发光结构包括阳极080、像素定义层090、发光材料092以及阴极094。
在图1的显示面板中，电容结构为形成上下交叠的平板电容结构。为了缩短两个电容结构的两个极板之间的距离，通常采用有源区040和阳极080通过通孔电连接构成电容结构的一个极板，源漏金属层构成电容结构的另一个极板。由于两个极板之间仅仅通过一层绝缘层隔离，当层间介质层或者平坦化层中存在异物或缺陷时，往往会造成电容短路。一旦发生短路，像素就因为电容失效而不能正常发光。如果为了增大两个极板之间的距离采用遮光层和阳极作为电容结构的两个极板，又会导致两个极板之间的距离过大，导致电容值严重偏小，同样会影响显示面板的显示功能。
因此，本申请提供了一种显示面板及其制作方法，以解决现有技术中的显示面板容易由于电容短路而失效的技术问题。
参见图8，图8为本申请的一个具体实施例中的显示面板的结构示意图。所述显示面板包括：基板10、遮光金属层20、缓冲层30、有源区40、栅极叠层50、层间介质层60、源漏金属层70、电容金属层72、平坦化层74、阳极80 和发光结构。所述发光结构位于所述阳极80上。
所述电容结构的第一极板包括电连接的有源区40和遮光金属层20，第二极板包括电连接的阳极80和电容金属层72。所述阳极80和有源区40对应设置，所述阳极80和有源区40之间设置有至少两层绝缘层。所述遮光金属层20和电容金属层72对应设置，所述遮光金属层20和电容金属层72之间设置有至少两层绝缘层。
本实施例中，设置于所述阳极80和有源区40之间的两层绝缘层包括层间介质层60和平坦化层74。设置于所述遮光金属层20和电容金属层72之间的两层绝缘层包括缓冲层30和层间介质层60。
本实施例中，所述显示面板为液晶面板或有机发光二极管显示面板。所述基板10可以为硬质基板，例如玻璃；也可以是柔性基板，例如聚酰亚胺薄膜。
所述遮光金属层20位于所述基板10上。所述遮光金属层20用于遮挡从外界进入有源区的光线，避免有源区的载流子迁移率受到光照的影响。因此，所述遮光金属层20与所述栅极叠层50对应设置。所述遮光金属层20在所述基板10上的投影完全覆盖所述栅极叠层50在所述基板10上的投影。
所述缓冲层30覆盖所述遮光金属层20。所述缓冲层30上具有至少一个第一通孔，所述第一通孔暴露出所述遮光金属层20。
所述有源区40位于所述缓冲层30上，通过第一通孔与所述遮光金属层20电连接，所述有源区40包括沟道区和位于沟道区两侧的源漏区。
所述栅极叠层50位于所述有源区40上方，并覆盖所述沟道区。通常，所述栅极叠层50包括栅极介质层和栅极金属层。所述层间介质层60覆盖所述有源区40和栅极叠层50。所述层间介质层60具有至少一个暴露出所述有源区40的第二通孔。
所述源漏金属层70位于所述层间介质层60上方，通过贯穿所述层间介质层60的第二通孔与所述源漏区电连接。所述电容金属层72位于所述层间介质层60上方，与所述源漏金属层70间隔设置。所述平坦化层74覆盖所述源漏金属层70和电容金属层72。所述平坦化层74具有至少一个暴露出所述源漏金属层70和电容金属层72的第三通孔。
所述阳极80位于所述平坦化层74上，通过所述第三通孔与所述源漏金属层70和电容金属层72分别电连接，所述发光结构位于所述阳极80上。具体的，参见图8，所述发光结构包括像素定义层90、发光材料92和阴极94。所述像素定义层90具有暴露出所述阳极80的通孔。所述发光材料92位于所述阳极80上，所述阴极94覆盖所述发光材料92。
参见图8，在本实施例中，所述阳极80和所述电容金属层72连接相同的电位，构成电容结构的第一极板。所述有源区40和遮光金属20连接相同的电位，构成电容结构的第二极板。根据所述显示面板的结构，所述电容结构的两个极板之间的最小距离为所述有源区40和所述电容金属层72之间的距离。为了增加电容结构的两个极板之间的最小距离，所述电容金属层72在所述基板10上的投影与所述有源区40在基板10上的投影不重叠或部分重叠。
在本实施例中，为了增强电容结构的有效面积，所述遮光金属层20在所述基板10上的投影覆盖所述电容金属层72在基板10上的投影。所述阳极80在所述基板10上的投影覆盖所述有源区40层在基板10上的投影。这样设置使得所述电容结构的两个极板能够尽可能的彼此对应，增强了该像素点的电容值。
在本申请的另一个实施例中，所述显示面板还包括位于层间介质层60和平坦化层74之间的第二栅极叠层和第二层间介质层。所述第二栅极叠层位于所述栅极叠层50正上方。所述第二栅极介质层覆盖所述第二栅极叠层和所述层间介质层60。所述源漏金属层70位于所述第二层间介质层上方，通过通孔与所述源漏区电连接。第二栅极结构的设置一方面能够增加薄膜晶体管的栅控能力，同时能够增加电容结构的两个极板之间的距离，降低电容结构的两个极板发生短路的风险。
相应的，参见图2至图7，本申请还提供了一种显示面板的制作方法。该方法包括以下步骤：
提供基板10；
在所述基板10上形成遮光金属层20和有源区30，构成电容结构的第一极板；
形成覆盖所述第一极板的至少两层绝缘层；
在所述至少两层绝缘层上形成阳极80和电容金属层72，构成电容结构的第二极板；其中，
所述阳极80和有源区40对应设置，所述阳极80和有源区40之间设置有至少两层绝缘层；
所述遮光金属层20和电容金属层72对应设置，所述遮光金属层20和电容金属层72之间设置有至少两层绝缘层；
在所述第二极板上形成发光结构。
参见图2，在本实施例中，首先提供基板10，并在所述基板10上形成遮光金属层20，之后形成覆盖所述遮光金属层20层缓冲层30。所述基板10可以为硬质基板，例如玻璃；也可以是柔性基板，例如聚酰亚胺薄膜。所述遮光金属层20位于所述基板10上。所述遮光金属层20用于遮挡从外界进入有源区的光线，避免有源区的载流子迁移率受到光照的影响。因此，所述遮光金属层20与所述栅极叠层50对应设置。所述遮光金属层20在所述基板10上的投影完全覆盖所述栅极叠层50在所述基板10上的投影。所述缓冲层30覆盖所述遮光金属层20。所述缓冲层30上具有至少一个第一通孔，所述第一通孔暴露出所述遮光金属层20。
之后，参见图3，形成有源区40，所述有源区40位于所述缓冲层30上，通过第一通孔与所述遮光金属层20电连接，所述有源区40包括沟道区。
之后，参见图4，在所述有源区40上方形成覆盖所述沟道区的栅极叠层50。通常，所述栅极叠层50包括栅极介质层和栅极金属层。
之后，参见图5，以所述栅极叠层为掩膜板对所述有源区40进行导体化，形成沟道区和位于沟道区两侧的源漏区。通常，导体化的方法为离子注入。
之后，参见图6，形成覆盖所述有源区40和栅极叠层的层间介质层60和位于所述层间介质层60上方的源漏金属层70和电容金属层72。所述层间介质层60覆盖所述有源区40和栅极叠层50。所述层间介质层60具有至少一个暴露出所述有源区40的第二通孔。所述源漏金属层70通过贯穿所述层间介质层60的通孔与所述源漏区电连接。所述电容金属层72位于所述层间介质层60上方，与所述源漏金属层70间隔设置。所述源漏金属层70位于所述层间介质层60上方，通过贯穿所述层间介质层60的第二通孔与所述源漏区电连接。所述电容金属层72位于所述层间介质层60上方，与所述源漏金属层70间隔设置。
之后，参见图7，形成平坦化层74和位于所述平坦化层74上的阳极80。所述平坦化层74覆盖所述源漏金属层70和电容金属层72。所述平坦化层74具有至少一个暴露出所述源漏金属层70和电容金属层72的第三通孔。所述阳极80位于所述平坦化层74上，通过通孔与所述源漏金属层70和电容金属层72分别电连接。
最后，参见图8，形成位于所述阳极80上的发光结构。所述发光结构包括像素定义层90、发光材料92和阴极94。所述像素定义层90具有暴露出所述阳极80的通孔。所述发光材料92位于所述阳极80上，所述阴极94覆盖所述发光材料92。
在本实施例中，所述阳极80和所述电容金属层72连接相同的电位，构成电容结构的第一极板。所述有源区40和遮光金属20连接相同的电位，构成电容结构的第二极板。根据所述显示面板的结构，所述电容结构的两个极板之间的最小距离为所述有源区40和所述电容金属层72之间的距离。为了增加电容结构的两个极板之间的最小距离，所述电容金属层72在所述基板10上的投影与所述有源区40在基板10上的投影不重叠或部分重叠。
在本实施例中，为了增强电容结构的有效面积，所述遮光金属层20在所述基板10上的投影覆盖所述电容金属层72在基板10上的投影。所述阳极80在所述基板10上的投影覆盖所述有源区40层在基板10上的投影。这样设置使得所述电容结构的两个极板能够尽可能的彼此对应，增强了该像素点的电容值。
在本申请的另一个实施例中，形成覆盖所述有源区40和栅极叠层的层间介质层60之后，还包括：在所述层间介质层60上形成位于所述栅极叠层50正上方的所述第二栅极叠层；以及形成覆盖所述第二栅极叠层和所述层间介质层60第二栅极介质层。第二栅极结构的设置一方面能够增加薄膜晶体管的栅控能力，同时能够增加电容结构的两个极板之间的距离，降低电容结构的两个极板发生短路的风险。
本申请改变了现有技术中的显示面板的电容结构的两个极板的构成方式。本申请中的显示面板的阳极与电容金属层电连接，构成电容结构的第一极板；同时有源区和遮光金属层电连接，构成电容结构的第二极板。由于阳极和有源区之间间隔了至少两层绝缘层，遮光金属和电容金属层之间同样间隔了至少两层绝缘层，本申请的显示面板能够有效的避免电容短路，从而提高了显示面板的可靠性和使用寿命。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种显示面板，其中，所述显示面板包括电容结构，所述电容结构的第一极板包括电连接的有源区和遮光金属层，第二极板包括电连接的阳极和电容金属层；其中，
    所述阳极和有源区对应设置，所述阳极和有源区之间设置有至少两层绝缘层；
    所述遮光金属层和电容金属层对应设置，所述遮光金属层和电容金属层之间设置有至少两层绝缘层。
  2. 根据权利要求1所述的显示面板，其中，设置于所述阳极和有源区之间的两层绝缘层包括层间介质层和平坦化层。
  3. 根据权利要求2所述的显示面板，其中，设置于所述遮光金属层和电容金属层之间的两层绝缘层包括缓冲层和层间介质层。
  4. 根据权利要求3所述的显示面板，其中，所述显示面板包括：
    基板；
    所述遮光金属层位于所述基板上，所述缓冲层覆盖所述遮光金属层；所述有源区位于所述缓冲层上，通过第一通孔与所述遮光金属层电连接，所述有源区包括沟道区和位于沟道区两侧的源漏区；
    栅极叠层，所述栅极叠层位于所述有源区上方，并覆盖所述沟道区，所述层间介质层覆盖所述有源区和栅极叠层；
    源漏金属层，所述源漏金属层位于所述层间介质层上方，通过贯穿所述层间介质层的第二通孔与所述源漏区电连接；所述电容金属层位于所述层间介质层上方，与所述源漏金属层间隔设置；所述平坦化层覆盖所述源漏金属层和电容金属层；所述阳极位于所述平坦化层上，通过第三通孔与所述源漏金属层和电容金属层分别电连接；
    发光结构，所述发光结构位于所述阳极上。
  5. 根据权利要求4所述的显示面板，其中，所述电容金属层在所述基板上的投影与所述有源区在基板上的投影不重叠。
  6. 根据权利要求4所述的显示面板，其中，所述遮光金属层在所述基板上的投影覆盖所述电容金属层在基板上的投影。
  7. 根据权利要求4所述的显示面板，其中，所述阳极在所述基板上的投影覆盖所述有源区在基板上的投影。
  8. 一种显示面板的制作方法，其中，该方法包括以下步骤：
    提供基板；
    在所述基板上形成遮光金属层和有源区，构成电容结构的第一极板；
    形成覆盖所述第一极板的至少两层绝缘层；
    在所述至少两层绝缘层上形成阳极和电容金属层，构成电容结构的第二极板；其中，
    所述阳极和有源区对应设置，所述阳极和有源区之间设置有至少两层绝缘层；
    所述遮光金属层和电容金属层对应设置，所述遮光金属层和电容金属层之间设置有至少两层绝缘层；
    在所述第二极板上形成发光结构。
  9. 根据权利要求8所述的显示面板的制作方法，其中，设置于所述阳极和有源区之间的至少两层绝缘层包括层间介质层和平坦化层。
  10. 根据权利要求9所述的显示面板的制作方法，其中，设置于所述遮光金属层和电容金属层之间的两层绝缘层包括缓冲层和层间介质层。
  11. 根据权利要求10所述的显示面板的制作方法，其中，形成所述第一极板的方法包括以下步骤：
    在所述基板上形成遮光金属层；
    形成覆盖所述遮光金属层的缓冲层；
    形成有源区，所述有源区位于所述缓冲层上，通过第一通孔与所述遮光金属层电连接，所述有源区包括沟道区和位于沟道区两侧的源漏区。
  12. 根据权利要求11所述的显示面板的制作方法，其中，形成所述有源区之后，所述方法还包括以下步骤：
    在所述有源区上方形成覆盖所述沟道区的栅极叠层；
    形成覆盖所述有源区和栅极叠层的层间介质层。
  13. 根据权利要求12所述的显示面板的制作方法，其中，形成所述第二极板的方法包括以下步骤：
    形成位于所述层间介质层上方的源漏金属层，所述源漏金属层通过贯穿所述层间介质层的通孔与所述源漏区电连接；
    形成所述电容金属层，所述电容金属层位于所述层间介质层上方，与所述源漏金属层间隔设置；
    形成所述平坦化层，所述平坦化层覆盖所述源漏金属层和电容金属层；
    形成所述阳极，所述阳极位于所述平坦化层上，通过通孔与所述源漏金属层和电容金属层分别电连接；
    形成所述发光结构，所述发光结构位于所述阳极上。
  14. 根据权利要求8所述的显示面板的制作方法，其中，所述电容金属层在所述基板上的投影与所述有源区在基板上的投影不重叠。
  15. 根据权利要求8所述的显示面板的制作方法，其中，所述遮光金属层在所述基板上的投影覆盖所述电容金属层在基板上的投影。
  16. 根据权利要求8所述的显示面板的制作方法，其中，所述阳极在所述基板上的投影覆盖所述有源区在基板上的投影。
PCT/CN2019/099263 2019-05-15 2019-08-05 显示面板及其制作方法 Ceased WO2020228149A1 (zh)

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