WO2020215208A1 - 时钟展频电路、电子设备和时钟展频方法 - Google Patents

时钟展频电路、电子设备和时钟展频方法 Download PDF

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Publication number
WO2020215208A1
WO2020215208A1 PCT/CN2019/083901 CN2019083901W WO2020215208A1 WO 2020215208 A1 WO2020215208 A1 WO 2020215208A1 CN 2019083901 W CN2019083901 W CN 2019083901W WO 2020215208 A1 WO2020215208 A1 WO 2020215208A1
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WIPO (PCT)
Prior art keywords
frequency
spreading
circuit
control word
modulation
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PCT/CN2019/083901
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English (en)
French (fr)
Inventor
魏祥野
修黎明
马玉海
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/083901 priority Critical patent/WO2020215208A1/zh
Priority to CN201980000525.6A priority patent/CN110199477B/zh
Priority to US16/980,930 priority patent/US11381229B2/en
Publication of WO2020215208A1 publication Critical patent/WO2020215208A1/zh
Priority to US17/836,419 priority patent/US11916557B2/en
Priority to US17/837,214 priority patent/US11949420B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

Definitions

  • the embodiments of the present disclosure relate to a clock spreading circuit, an electronic device, and a clock spreading method.
  • Electromagnetic interference refers to the impact of the circuit system on the surrounding circuit system through conduction or radiation. Electromagnetic interference will cause the performance of the circuit to decrease, and may even cause the entire circuit system to fail.
  • the clock signal is often the signal with the highest frequency and the steepest edge in the circuit system. Most electromagnetic interference problems are related to the high-frequency clock signal.
  • Methods to reduce electromagnetic interference include shielding, filtering, isolation, signal edge control, and printed circuit board (Printed Circuit Board, PCB) layout (for example, adding power and ground (GND) layers in the PCB).
  • PCB printed circuit board layout
  • Clock Spread Spectrum is another effective method to reduce EMI.
  • Clock Spread Spectrum uses frequency modulation to disperse the energy concentrated in a narrow frequency range to a predetermined wide frequency range.
  • the amplitude (energy) of the subharmonic frequency achieves the purpose of reducing the peak value of the electromagnetic radiation of the system.
  • At least one embodiment of the present disclosure provides a clock spreading circuit, including: a control circuit configured to generate a frequency control word according to a modulation parameter, wherein the frequency control word varies discretely with time; a signal generation circuit is configured to receive And according to the frequency control word, a spread spectrum output signal after spreading is generated and output, wherein the spread spectrum output signal corresponds to the frequency control word.
  • the modulation parameters include a spreading depth coefficient, a spreading reference value, a modulation rate, a reference frequency, and a modulation mode corresponding to the spreading output signal.
  • the control circuit includes: a decimal generating sub-circuit configured to generate the decimal part according to the spreading depth coefficient, the spreading reference value, the modulation mode, and the modulation rate; and an integer generating sub-circuit, It is configured to generate the integer part according to the reference frequency; a synthesis sub-circuit is configured to receive and generate the frequency control word according to the decimal part and the integer part.
  • the decimal generation sub-circuit includes: a frequency modulation control module configured to generate a frequency modulation clock signal according to the modulation rate to control the change of the frequency control word Rate; fractional generation module, configured to generate and output the fractional part to the synthesis under the control of the frequency modulation clock signal, according to the modulation mode, the spreading depth coefficient, and the spreading reference value Sub-circuit.
  • the decimal generation module includes a modulation mode sub-module, and the modulation mode includes a triangular modulation mode, a sawtooth modulation mode, a sinusoidal modulation mode, or a random modulation mode, so
  • the modulation mode submodule is configured to use any one of the triangular modulation mode, the sawtooth modulation mode, the sinusoidal modulation mode, and the random modulation mode to generate the fractional part.
  • the frequency modulation control module includes: a counting sub-module configured to count the reference clock signal to obtain the count value of the reference clock signal;
  • the sub-module is configured to determine a count period according to the modulation rate, and determine the frequency modulation clock signal based on the count period and the count value.
  • the signal generating circuit includes: a reference time unit generating sub-circuit configured to generate and output a reference time unit; The frequency control word and the reference time unit generate and output the spread spectrum output signal.
  • the spreading sub-circuit is a time average frequency direct period synthesizer.
  • the maximum value of the frequency control word and the minimum value of the frequency control word satisfy the following formula: 0 ⁇ Fmax-Fmin ⁇ 1, where Fmin represents The minimum value of the frequency control word, Fmax represents the maximum value of the frequency control word.
  • At least one embodiment of the present disclosure further provides an electronic device, including: the clock spreading circuit according to any one of the above.
  • At least one embodiment of the present disclosure further provides a clock spreading method, which is applied to the clock spreading circuit according to any one of the above, and the clock spreading method includes: generating the frequency control word according to the modulation parameter, wherein , The frequency control word discretely changes with time; and receiving and according to the frequency control word, generating and outputting the spread spectrum output signal after spreading, wherein the spread spectrum output signal corresponds to the frequency control word .
  • the frequency control word includes a decimal part and an integer part
  • the modulation parameter includes a spreading depth coefficient and a spreading depth coefficient corresponding to the spreading output signal.
  • Reference value, modulation mode, modulation rate, and reference frequency and generating the frequency control word according to the modulation parameter includes: generating according to the spreading depth coefficient, the spreading reference value, the modulation mode, and the modulation rate
  • the decimal part wherein the decimal part is a decimal and discretely changes with the time; the integer part is generated according to the reference frequency, wherein the integer part is an integer; according to the decimal part and the integer Part, generating the frequency control word.
  • FIG. 1 is a schematic block diagram of a clock spreading circuit provided by some embodiments of the present disclosure
  • FIG. 2 is a schematic structural diagram of a clock spreading circuit provided by some embodiments of the disclosure.
  • 3A is a schematic diagram of a decimal generation sub-circuit provided by some embodiments of the present disclosure.
  • FIG. 3B is a schematic diagram of another decimal generation sub-circuit provided by some embodiments of the present disclosure.
  • FIG. 4 is a schematic block diagram of a frequency modulation control module provided by some embodiments of the present disclosure.
  • 5A shows a schematic block diagram of a reference time unit generating sub-circuit provided by some embodiments of the present disclosure
  • FIG. 5B shows a schematic structural diagram of another reference time unit generating sub-circuit provided by some embodiments of the present disclosure
  • FIG. 6 shows a schematic diagram of K reference output signals with evenly spaced phases provided by some embodiments of the present disclosure
  • Fig. 7 shows a schematic block diagram of a spread spectrum sub-circuit provided by some embodiments of the present disclosure
  • FIG. 8 shows a schematic diagram of the working principle of a spread spectrum sub-circuit provided by some embodiments of the present disclosure
  • FIG. 9 is a schematic diagram of frequency modulation determined according to a triangular modulation mode according to some embodiments of the present disclosure.
  • 10A is a schematic structural diagram of a spread spectrum sub-circuit provided by some embodiments of the present disclosure.
  • 10B is a schematic structural diagram of another spreading sub-circuit provided by some embodiments of the present disclosure.
  • FIG. 11 is a schematic diagram of a spectrum comparison result before and after spreading provided by some embodiments of the present disclosure.
  • FIG. 12 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure.
  • FIG. 13 is a screenshot of an electronic device provided by some embodiments of the present disclosure when it is working normally;
  • FIG. 14 is a schematic flowchart of a clock spreading method provided by some embodiments of the present disclosure.
  • the frequency of the clock signal is getting higher and higher, and the high-frequency clock signal has strong electromagnetic interference.
  • periodic jitter jitter
  • this method makes each cycle of the clock signal different. If such a clock is used to drive the digital circuit, the setup time and hold time of the digital circuit cannot be determined, so it is difficult Determine the parameters of clock spreading.
  • the clock spreading circuit includes a control circuit and a signal generation circuit.
  • the control circuit is configured to generate a frequency control word according to a modulation parameter. The word discretely changes with time; the signal generating circuit is configured to receive and according to the frequency control word, generate and output a spread frequency output signal after spreading, and the spread frequency output signal corresponds to the frequency control word.
  • the clock spreading circuit is based on Time-Average-Frequency Direct-Period-Synthesis (TAF-DPS) technology, using TAF-DPS to generate the clock spreading signal, which can realize various modulations through the same circuit Mode (such as triangle wave modulation mode, sawtooth modulation mode) spread spectrum function, and can not introduce additional noise when the spread spectrum function is turned on, that is, effectively reduce electromagnetic interference without affecting the normal operation of the circuit system.
  • TAF-DPS Time-Average-Frequency Direct-Period-Synthesis
  • the clock spreading circuit is an all-digital circuit with low power consumption, small size, programmable, and easy to integrate in various chips.
  • FIG. 1 is a schematic block diagram of a clock spreading circuit provided by some embodiments of the present disclosure.
  • the clock spreading circuit 10 may include a control circuit 11 and a signal generating circuit 12.
  • the control circuit 11 is configured to generate a frequency control word according to the modulation parameter;
  • the signal generation circuit 12 is configured to receive and according to the frequency control word, generate and output a spread frequency output signal after spreading.
  • the frequency control word changes discretely with time
  • the spread spectrum output signal corresponds to the frequency control word
  • the spread spectrum output signal corresponds to the frequency control word means that the frequency of the spread spectrum output signal corresponds to the frequency control word, and the frequency of the spread spectrum output signal can be adjusted by the frequency control word. Since the frequency control word discretely changes with time, the frequency of the spread-spectrum output signal also changes discretely with time.
  • the frequency spectrum of the spread-spectrum output signal is a wide-band spectrum, thereby realizing clock spreading.
  • the normal operation of the circuit system is not affected when the spreading function is turned on and off, thereby ensuring the performance of the circuit system while achieving In order to reduce electromagnetic radiation.
  • the frequency control word can be expressed as:
  • F(t) is the frequency control word
  • I is the integer part of the frequency control word
  • r(t) is the decimal part of the frequency control word
  • r(t) changes discretely with time
  • t represents time.
  • the range of r(t) is [0,1), that is, r(t) varies from 0 to 1, and r(t) can be 0 but cannot be 1. Therefore, in some examples, when the integer part I of the frequency control word is unchanged, the maximum value of the frequency control word and the minimum value of the frequency control word can satisfy the following formula: 0 ⁇ Fmax-Fmin ⁇ 1, where, Fmin represents the minimum value of the frequency control word, and Fmax represents the maximum value of the frequency control word.
  • the integer part I of the frequency control word can be changed.
  • the frequency control word F(t) still oscillates between two integers.
  • the modulation parameters may include a reference frequency corresponding to the spread spectrum output signal, a spread depth coefficient, a spread reference value, a modulation rate, and a modulation mode.
  • the reference frequency is the operating frequency of the circuit system, so the reference frequency is determined based on the operating requirements of the circuit system.
  • the present disclosure does not limit the specific value of the reference frequency.
  • the spreading depth coefficient can be determined according to the spreading depth of the frequency of the spreading output signal. For example, in some embodiments, if the reference frequency of the spreading output signal is 100MHz, the spreading depth of the spreading output signal is 20MHz. , That is, the frequency range of the spread spectrum output signal is 90MHz to 110MHz, and the spread depth coefficient can be ⁇ 0.1 (that is, ⁇ (spread depth/2)/reference frequency).
  • the spread spectrum reference value can be set by the user according to actual needs, for example, the spread spectrum reference value can be 0.5.
  • the spread spectrum reference value may also be determined by the operating frequency (ie, reference frequency) of the circuit system, that is, the reference frequency corresponds to the reference frequency control word, and the fractional part of the reference frequency control word is the spread spectrum reference value.
  • the modulation rate represents the speed at which the frequency control word changes over time.
  • the modulation mode may include triangular modulation mode, sawtooth modulation mode, sinusoidal modulation mode, random modulation mode, and other custom modes. Users can select the corresponding modulation mode according to actual application requirements.
  • different clock spreading circuits can correspond to different modulation modes. But not limited to this, different clock spreading circuits can also correspond to the same modulation mode.
  • the same clock spreading circuit can also correspond to different modulation modes, and different modulation modes can respectively correspond to different application scenarios of the clock spreading circuit.
  • the present disclosure does not impose specific restrictions on the type and selection method of the modulation mode.
  • the integer part I of the frequency control word is determined by the reference frequency.
  • the fractional part r(t) of the frequency control word is determined by the spreading depth coefficient, spreading reference value, modulation rate and modulation mode.
  • the spreading depth coefficient, modulation mode, and modulation rate can all be set by the user according to actual needs.
  • FIG. 2 is a schematic structural diagram of a clock spreading circuit provided by some embodiments of the disclosure.
  • control circuit 11 can be implemented in hardware; or, the control circuit 11 can also be implemented in a combination of hardware and software. In some embodiments, the control circuit 11 may be implemented in hardware or a combination of hardware and software.
  • the control circuit 11 may include a decimal generation sub-circuit 110, an integer generation sub-circuit 111 and a synthesis sub-circuit 112.
  • the decimal generating sub-circuit 110 is configured to generate the fractional part r(t) of the frequency control word F(t) according to the spreading depth coefficient D, the spreading reference value Cr, the modulation mode Am, and the modulation rate V F ;
  • the integer generator circuit 111 is configured to generate a frequency control word F (t) according to the reference frequency f w of the integer part I;
  • combiner sub-circuit 112 is configured to receive and in accordance with the fractional part of r (t) frequency control word and the frequency control word F (t The integer part I of) generates the frequency control word F(t).
  • the decimal generation sub-circuit 110 is further configured to store the value of the fractional part r(t) of the frequency control word F(t).
  • the integer generation sub-circuit 111 is also configured to store the value of the integer part I of the frequency control word F(t).
  • FIG. 3A is a schematic diagram of a decimal generating sub-circuit provided by some embodiments of the disclosure
  • FIG. 3B is a schematic diagram of another decimal generating sub-circuit provided by some embodiments of the disclosure.
  • the decimal generation sub-circuit 110 may include a frequency modulation control module (or frequency modulation control sub-circuit) 1101 and a decimal generation module (or generation sub-circuit) 1102.
  • the frequency modulation control module 1101 is configured to generate a frequency modulation clock signal CLK_AF according to the modulation rate V F to control the rate of change of the fractional part r(t) of the frequency control word F(t), and finally control the rate of change of the frequency control word F(t);
  • the decimal generation module 1102 is configured to generate and output the fractional part r(t) to the synthesis sub-circuit 112 under the control of the frequency modulation clock signal CLK_AF, according to the modulation mode Am, the spreading depth coefficient D and the spreading reference value Cr.
  • the spread mode of the spread spectrum output signal is center spread, and the range of fractional part r(t) is: Cr–D/2 ⁇ r(t) ⁇ Cr+D/2, then the frequency control word F(t)
  • the range of is: I+Cr–D/2 ⁇ F(t) ⁇ I+Cr+D/2, at this time, the maximum value of the frequency control word Fmax is I+Cr+(D/2), the minimum of the frequency control word
  • the value Fmin is I+Cr-(D/2).
  • the spread mode of the spread spectrum output signal is upward spread, and the range of the fractional part is: Cr–D ⁇ r(t) ⁇ Cr, then the range of the frequency control word F(t) is: I+Cr–D ⁇ F(t) ⁇ I+Cr, at this time, the maximum value of the frequency control word Fmax is I+Cr, and the minimum value of the frequency control word Fmin is I+Cr-D.
  • the spread mode of the spread spectrum output signal is downward spread, and the range of the fractional part is: Cr ⁇ r(t) ⁇ Cr+D, then the range of the frequency control word F(t) is: I+Cr ⁇ F(t) ⁇ I+Cr+D, at this time, the maximum value of the frequency control word Fmax is I+Cr+D, and the minimum value of the frequency control word Fmin is I+Cr.
  • the decimal generating module 1102 may include a modulation mode sub-module, and the modulation mode sub-module is used to control the spreading mode of the fractional part r(t).
  • the modulation mode sub-module is configured to generate the fractional part r(t) using any of the modulation modes such as triangular modulation mode, sawtooth modulation mode, sinusoidal modulation mode, and random modulation mode.
  • the decimal generating module 1102 may include a selection sub-module and multiple modulation mode sub-modules corresponding to multiple modulation modes one-to-one. As shown in FIG. 3B, the decimal generation module 1102 may include a triangular modulation mode submodule 1102a, a sawtooth modulation mode submodule 1102b, a sinusoidal modulation mode submodule 1102c, a random modulation mode submodule 1102d, and a selection submodule 1102e.
  • the triangular modulation mode sub-module 1102a is configured to generate the first intermediate fraction corresponding to the triangular modulation mode according to the triangular modulation mode, the spreading depth coefficient D and the spreading reference value Cr;
  • the sawtooth modulation mode submodule 1102b is configured to generate the first intermediate fraction corresponding to the triangular modulation mode;
  • the modulation mode, the spreading depth coefficient D and the spreading reference value Cr generate the second middle decimal part corresponding to the sawtooth modulation mode;
  • the sine modulation mode sub-module 1102c is configured according to the sine modulation mode, the spreading depth coefficient D and the spreading
  • the reference value Cr generates the third middle decimal part corresponding to the sinusoidal modulation mode;
  • the random modulation mode sub-module 1102d is configured to generate the corresponding random modulation mode according to the random modulation mode, the spreading depth coefficient D and the spreading reference value Cr The fourth middle decimal part.
  • the selection submodule 1102e is configured to select one of the first middle decimal part, the second middle decimal part, the third middle decimal part, and the fourth middle decimal part as the decimal part of the frequency control word F(t) according to the modulation mode Am. (t). For example, in one example, when the modulation mode Am set by the user is the triangular modulation mode, the selection submodule 1102e selects the first middle decimal part as the decimal part r(t) of the frequency control word F(t).
  • the selection sub-module 1102e may include a multiplexer, and the multiplexer may be, for example, a 4-to-1 multiplexer.
  • the selection sub-module 1102e selects the middle decimal part corresponding to the modulation mode Am from a plurality of middle decimal parts according to the modulation mode Am and outputs the corresponding middle decimal part.
  • the present disclosure is not limited to this.
  • the selection sub-module 1102e may select the mode control signal corresponding to the modulation mode Am from the mode control signal group according to the modulation mode Am, and the mode control signal group includes triangular mode control. Signal, sawtooth mode control signal, sinusoidal mode control signal, random mode control signal.
  • the mode control signal can be output to the triangular modulation mode submodule 1102a, the sawtooth modulation mode submodule 1102b, the sinusoidal modulation mode submodule 1102c, and the random modulation mode submodule 1102d.
  • the modulation mode submodule corresponding to the modulation mode Am can be controlled in the mode
  • the intermediate fraction corresponding to the modulation mode Am is generated and output under the control of the signal.
  • the selection submodule 1102e can select a sawtooth mode control signal from the mode control signal group, and then the sawtooth mode control signal is output to the triangular modulation mode submodule 1102a, Modulation mode submodule 1102b, sinusoidal modulation mode submodule 1102c, random modulation mode submodule 1102d, but only sawtooth modulation mode submodule 1102b can generate and output the second intermediate decimal corresponding to the sawtooth modulation mode under the control of the sawtooth mode control signal
  • the triangular modulation mode submodule 1102a, the sinusoidal modulation mode submodule 1102c, and the random modulation mode submodule 1102d cannot generate signals.
  • the decimal generation module 1102 may include multiple modulation mode sub-modules that only correspond to multiple modulation modes in a one-to-one manner.
  • the modulation mode sub-module corresponding to the modulation mode Am set by the user can generate the middle decimal part, and the middle decimal part is output to the synthesis as the decimal part r(t) of the final frequency control word F(t)
  • the sub-circuit 112, that is, the modulation mode Am can control the modulation mode sub-module corresponding to the modulation mode Am among the multiple modulation mode sub-modules according to the corresponding modulation mode, the spreading depth coefficient D, and the spreading reference value Cr to generate the corresponding The middle decimal part corresponding to the modulation mode.
  • the decimal generation module 1102 may include a triangular modulation mode submodule 1102a, a sawtooth modulation mode submodule 1102b, a sinusoidal modulation mode submodule 1102c, and a random modulation mode submodule 1102d, and a triangular modulation mode submodule 1102a and triangular modulation Mode correspondence: the sawtooth modulation mode submodule 1102b corresponds to the sawtooth modulation mode, the sinusoidal modulation mode submodule 1102c corresponds to the sinusoidal modulation mode, and the random modulation mode submodule 1102d corresponds to the random modulation mode.
  • the sine modulation mode sub-module 1102c can generate the third intermediate corresponding to the sine modulation mode according to the sine modulation mode, the spreading depth coefficient D and the spreading reference value Cr.
  • the fractional part, and then the third intermediate fractional part can be output to the synthesis sub-circuit 112 as the fractional part r(t) of the frequency control word F(t).
  • the decimal generation module 1102 may not include the selection sub-module 1102e.
  • each of the triangular modulation mode submodule 1102a, the sawtooth modulation mode submodule 1102b, and the sinusoidal modulation mode submodule 1102c may include an adder, a memory, a subtractor, a comparator, and so on.
  • the working principle of the modulation mode submodule is described in detail below by taking the triangular modulation mode submodule 1102a as an example.
  • the memory in the triangular modulation mode sub-module 1102a is used to store the change step length of the fractional part r(t).
  • the range of the fractional part r(t) is 0.25-0.75, that is, 0.5 (spreading Frequency reference value Cr) ⁇ (0.5(Spreading depth coefficient D)/2), the change step length of the triangular modulation mode can be 0.01.
  • the first value of the fractional part r(t) can be the spread-spectrum reference value Cr, that is, 0.5.
  • the value of t) is 0.75 (that is, the maximum value of the fractional part)
  • the Nth value of 0.74 then use the adder to subtract 0.01 from the Nth value to get the N+1th value of the fractional part r(t) 0.73, and so on, until the value of
  • the initial value and the final value of a cycle period are the same, and the value of the fractional part r(t) reaches a maximum value and a minimum value in the cycle period.
  • the fractional part r(t) can be generated.
  • the memory in the triangular modulation mode submodule 1102a can also be used to store the generated fractional part r(t), the spread reference value Cr, and the spread depth coefficient D.
  • the rate of change of the value of the fractional part r(t) is controlled by the frequency-modulated clock signal CLK_AF, that is, the frequency-modulated clock signal CLK_AF can control, for example, the operation of increasing 0.01 to the first value and the operation of increasing 0.01 to the second value.
  • CLK_AF can control, for example, the operation of increasing 0.01 to the first value and the operation of increasing 0.01 to the second value. The time interval between.
  • the fractional part r(t) is composed of a series of irregularly changing random values.
  • the random modulation mode submodule 1102d can be implemented by PRBS (Pseudo-Random Binary Sequence) circuit.
  • PRBS Physical-Random Binary Sequence
  • the pseudo-random value generated by the PRBS circuit has a large cycle period, so that the pseudo-random value can be approximated as an irregular change.
  • the PRBS circuit may include a set of registers.
  • each modulation mode sub-module in the decimal generation module 1102 is based on the corresponding modulation mode, spreading depth coefficient D, and spreading reference
  • the value Cr generates the middle decimal part corresponding to the corresponding modulation mode; that is, the decimal generating module 1102 can generate multiple middle decimal parts, and then the selection submodule 1102e selects the middle decimal part from the multiple middle decimal parts according to the modulation mode Am.
  • the middle decimal part corresponding to the modulation mode Am is based on the corresponding modulation mode, spreading depth coefficient D, and spreading reference
  • the value Cr generates the middle decimal part corresponding to the corresponding modulation mode; that is, the decimal generating module 1102 can generate multiple middle decimal parts, and then the selection submodule 1102e selects the middle decimal part from the multiple middle decimal parts according to the modulation mode Am.
  • the middle decimal part corresponding to the modulation mode Am is based on the corresponding modulation mode, spreading depth coefficient D, and spreading reference
  • the value Cr
  • the decimal generating sub-circuit 110 may further include a spread spectrum depth control module and a reference value control module.
  • the spreading depth control module is configured to determine the spreading depth coefficient D, and transmit the spreading depth coefficient D to the decimal generating module 1102;
  • the reference value control module is configured to determine the spreading reference value Cr, and set the spreading reference value Cr Transmitted to the decimal generating module 110.
  • the spreading depth control module can directly acquire the spreading depth coefficient D input by the user, and the reference value control module can directly acquire the spreading reference value Cr input by the user.
  • the spread-spectrum depth control module may include a first storage circuit, the first storage circuit is used to store the spread-spectrum depth coefficient D (for example, the spread-spectrum depth coefficient D is 0.5), and the first storage circuit may include various types of storage media or registers Wait.
  • the reference value control module may also include a second storage circuit, the second storage circuit is used to store the spread-spectrum reference value Cr (for example, the spread-spectrum reference value Cr is 0.5), and the second storage circuit may include various types of storage media or registers Wait.
  • the spreading depth coefficient D and the spreading reference value Cr jointly determine the spreading range of the spreading output signal, that is, the spreading depth.
  • the user can input the reference frequency and the spread depth
  • the spread depth control module can obtain the reference frequency and the spread depth, and determine the spread depth coefficient D according to the reference frequency and the spread depth
  • the reference value control module obtains the reference frequency.
  • the spread spectrum depth control module may include a first storage circuit and a first calculation circuit
  • the reference value control module may also include a second storage circuit and a second calculation circuit.
  • the first calculation circuit in the spreading depth control module is used to calculate the spreading depth coefficient D according to the reference frequency and the spreading depth
  • the first storage circuit in the spreading depth control module is used to store the spreading depth coefficient D.
  • the second calculation circuit in the reference value control module is used to calculate the spread spectrum reference value Cr according to the reference frequency
  • the second storage circuit in the reference value control module is used to store the spread spectrum reference value Cr.
  • both the first calculation circuit in the spread spectrum depth control module and the second calculation circuit in the reference value control module can be composed of transistors, resistors, triggers, capacitors, and operational amplifiers.
  • the spreading depth coefficient D and the spreading reference value Cr can be directly input to the decimal generating module 1102 by a user through an input device (eg, keyboard, touch screen, touch panel, mouse, knob, etc.) through a data interface.
  • the decimal generation sub-circuit 110 may not include the spread spectrum depth control module and the reference value control module.
  • the modulation mode Am can also be directly input to the decimal generation module 1102 by the user through the input device through the data interface.
  • Fig. 4 is a schematic block diagram of a frequency modulation control module provided by some embodiments of the present disclosure.
  • the frequency modulation control module 1101 includes a timing sub-module 1101a and a counting sub-module 1101b.
  • the counting sub-module 1101b is configured to count the reference clock signal Sys_clk to obtain the count value of the reference clock signal Sys_clk;
  • the timing sub-module 1101a is configured to determine the count period according to the modulation rate V F , and determine the frequency modulation based on the count period and the count value The clock signal CLK_AF.
  • the modulation rate V F can be directly input to the timing sub-module 1101a by the user through the input device through the data interface.
  • the counting period can represent the duration of each frequency control word.
  • the timing submodule 1101a can output a binary number 0, that is, the value of the FM clock signal CLK_AF is 0 at this time; when the count value output by the counting sub-module 1101b is 150 to 300, the timing sub-module 1101a can output the binary number 1, that is, the value of the FM clock signal CLK_AF is 1 at this time .
  • the timing sub-module 1101a can control the count sub-module 1101b to reset the count value to 0 to restart counting. In this way, the frequency modulation clock signal CLK_AF with a period of 500 nanoseconds can be obtained.
  • the frequency of the frequency modulation clock signal CLK_AF is lower than the frequency of the reference clock signal Sys_clk.
  • the reference clock signal Sys_clk may be the clock signal of the system.
  • the timing sub-module 1101a and the counting sub-module 1101b can be implemented by hardware circuits.
  • the timing sub-module 1101a and the counting sub-module 1101b can be composed of, for example, transistors, diodes, resistors, flip-flops, capacitors, and operational amplifiers.
  • the counting sub-module 1101b may include an addition counter and the like.
  • the function of the counting sub-module 1101b can also be realized by software.
  • the frequency modulation control module 1101 may further include a storage sub-module for storing computer instructions and data, and the processor may execute the computer instructions and data stored in the storage sub-module to realize the function of the counting sub-module 1101b.
  • the reference frequency f w can be inputted through a data interface to the input means generating an integer sub-circuit 111 by the user.
  • an integer of generating sub-circuit 111 may include a calculation module and a storage module, means for calculating a control word in accordance with the reference frequency f w is calculated with the reference frequency f w corresponding to the reference frequency, the integer portion of the reference frequency is the frequency of the control word
  • the value of the integer part I of the control word F(t) and the storage module is used to store the value of the integer part I.
  • the storage module can be various types of storage media or registers.
  • the calculation module can be composed of elements such as transistors, resistors, flip-flops, capacitors, and operational amplifiers.
  • the spread spectrum clock circuit 10 may be connected to a calculator, the calculator can be used to obtain the value of the integer part I of the reference frequency f w calculated integer sub-circuit 111 may be directly generated from the calculator Get the value of the integer part I.
  • the integer generation sub-circuit 111 may only include a storage module for storing the value of the integer part I.
  • the synthesis sub-circuit 112 is used to integrate the integer part I and the decimal part r(t) together to obtain the frequency control word F(t).
  • the synthesis sub-circuit 112 may include logic circuits, registers, and the like.
  • the signal generation circuit 12 includes a reference time unit generation sub-circuit 120 and a spread spectrum sub-circuit 121.
  • the reference time unit generation sub-circuit 120 is configured to generate and output a reference time unit;
  • the spread spectrum sub-circuit 121 is configured to generate and output a spread spectrum output signal according to the frequency control word and the reference time unit ⁇ .
  • the reference time unit generation sub-circuit 120 is configured to output the reference time unit ⁇ to the integer generation sub-circuit 111.
  • the reference frequency control word can be expressed as:
  • F w represents the reference frequency control word
  • I w represents the integer part of the reference frequency control word
  • r w represents the decimal part of the reference frequency control word.
  • the integer part I of the frequency control word F(t) is the integer part I w of the reference frequency control word.
  • the spread spectrum reference value Cr may be the fractional part r w of the reference frequency control word.
  • the reference time unit generation sub-circuit 120 is further configured to output the reference time unit ⁇ to the spread spectrum sub-circuit 121.
  • FIG. 5A shows a schematic block diagram of a reference time unit generation sub-circuit provided by some embodiments of the present disclosure
  • FIG. 5B shows a schematic structure diagram of another reference time unit generation sub-circuit provided by some embodiments of the present disclosure
  • FIG. 6 shows a schematic diagram of K reference output signals with evenly spaced phases provided by some embodiments of the present disclosure.
  • the reference time unit generation sub-circuit 120 is configured to generate and output K reference output signals with evenly spaced phases and a reference time unit ⁇ .
  • the reference time unit generation sub-circuit 120 can use a phase locked loop (Phase Locked Loop, PLL), a delay locked loop (Delay Locked Loop, DLL), or a Johnson counter (Johnson Counter) to generate K reference output signals with evenly spaced phases.
  • PLL Phase Locked Loop
  • DLL delay locked loop
  • Johnson counter Johnson Counter
  • the reference time unit generation sub-circuit 120 may include a voltage controlled oscillator (VCO) 1201, a phase locked loop circuit 1202, and K output terminals 1203.
  • the voltage controlled oscillator 1201 is configured to oscillate at a predetermined oscillation frequency.
  • the phase locked loop circuit 1202 is configured to lock the output frequency of the voltage controlled oscillator 1201 to the reference output frequency.
  • the reference time unit can be expressed as ⁇ , and the reference output frequency can be expressed as f d .
  • the reference time unit ⁇ is the time span between any two adjacent output signals output by the K output terminals 1203.
  • the reference time unit ⁇ is usually generated by the multi-stage voltage controlled oscillator 1201.
  • the reference time unit ⁇ can be calculated using the following formula:
  • T d represents the period of the signal generated by the multi-stage voltage controlled oscillator 1201.
  • the phase locked loop circuit 1202 includes a phase detector PFD, a loop filter LPF, and a frequency divider FN.
  • a reference signal with a reference frequency may be input to the phase detector PFD, then enter the loop filter LPF, then enter the voltage-controlled oscillator, and finally the voltage-controlled oscillator generates
  • the signal of the predetermined oscillation frequency f vco can be divided by the frequency divider FN to obtain the frequency division frequency f vco /N 0 of the frequency division signal, where N 0 represents the frequency division coefficient of the frequency divider, and N 0 is a real number, and N 0 is greater than or equal to 1.
  • the frequency division frequency f vco /N 0 is fed back to the phase detector PFD, which is used to compare the reference frequency of the reference signal with the frequency division frequency f vco /N 0 , when the frequency of the reference frequency and the frequency division frequency f vco /N When the sum phases are equal, the error between the two is zero. At this time, the phase-locked loop circuit 1202 is in the locked state.
  • the loop filter LPF may be a low-pass filter.
  • circuit structure shown in FIG. 5B is only an exemplary implementation of the reference time unit generating sub-circuit 120.
  • the specific structure of the reference time unit generating sub-circuit 120 is not limited to this, it can also be constructed by other circuit structures, and the present disclosure is not limited herein.
  • K and ⁇ can be preset according to actual needs, and are fixed.
  • Fig. 7 shows a schematic block diagram of a frequency spreading sub-circuit provided by some embodiments of the present disclosure
  • Fig. 8 shows a schematic diagram of the working principle of a frequency spreading sub-circuit provided by some embodiments of the present disclosure.
  • the spread spectrum sub-circuit 121 includes a first input module 1211, a second input module 1212, and an output module 1213.
  • the first input module 1211 is configured to receive K uniformly spaced reference output signals and reference time units from the reference time unit generation sub-circuit 120.
  • the second input module 1212 is configured to receive the frequency control word F(t) from the control circuit 11.
  • the output module 1213 is used to generate a first period and a second period, generate a spread spectrum output signal according to the first period and the second period, and output the spread spectrum output signal. The probability of occurrence of the first cycle and the second cycle is controlled by the value of the fractional part r(t) of the frequency control word F(t).
  • the spread spectrum sub-circuit 121 may include a time average frequency direct period (TAF-DPS) synthesizer.
  • TAF-DPS technology is an emerging frequency synthesis technology, which can generate pulse signals of any frequency based on the new time average frequency concept.
  • the TAF-DPS synthesizer can achieve fine frequency adjustment with small frequency granularity.
  • the output frequency of the TAF-DPS synthesizer can be changed instantly, that is, it has the rapidity of frequency switching.
  • the frequency granularity of the TAF-DPS synthesizer can reach several ppb (parts per billion). More importantly, the frequency switching speed of TAF-DPS is quantifiable.
  • the response time from the time when the frequency control word update is received to the time when the frequency is switched can be calculated according to the clock cycle.
  • the TAF-DPS synthesizer can be used as a specific implementation of the spread spectrum sub-circuit 121 in the embodiment of the present disclosure.
  • the TAF-DPS synthesizer can be implemented using an application specific integrated circuit (for example, ASIC) or a programmable logic device (for example, FPGA).
  • the TAF-DPS synthesizer can be implemented using traditional analog circuit devices. The present disclosure is not limited here.
  • the spread spectrum sub-circuit 121 based on the TAF-DPS synthesizer 510 has two inputs: a reference time unit 520 and a frequency control word 530.
  • the TAF-DPS synthesizer 510 has an output CLK 550.
  • the output CLK 550 is a synthesized time average frequency clock signal.
  • the output CLK 550 is the spread spectrum output signal.
  • the spread spectrum output signal CLK 550 is a clock pulse train 540, and the clock pulse train 540 is composed of a first period T A 541 and a second period T B 542 in an interleaved manner.
  • the score r(t) is used to control the occurrence probability of the second period T B. Therefore, r(t) can also determine the occurrence probability of the first period T A.
  • the period T TAF of the spread spectrum output signal CLK 550 can be expressed by the following formula:
  • T TAF (1-r(t)) ⁇ T A +r(t) ⁇ T B
  • the frequency f css of the spread spectrum output signal CLK 550 can be expressed as:
  • the period T TAF of the spread spectrum output signal CLK 550 output by the TAF-DPS synthesizer 510 is linearly proportional to the frequency control word 530, and the frequency of the spread spectrum output signal CLK550 f css It is inversely proportional to the frequency control word 530 and has a small linear shape.
  • the frequency control word 530 changes, the period T TAF of the spread spectrum output signal CLK 550 output by the TAF-DPS synthesizer 510 will also change in the same form, and the frequency of the spread spectrum output signal CLK 550 will also change accordingly.
  • FIG. 9 is a schematic diagram of frequency modulation determined according to a triangular modulation mode according to some embodiments of the present disclosure.
  • the frequency control word F(t) is also approximated as a triangular wave curve, as shown in formula (2 )
  • the frequency f css of the spread spectrum output signal generated based on TAF-DPS and the frequency control word 530 are in the corresponding reciprocal form, which has a small amount of linearity.
  • the spread spectrum output signal The frequency f css is also approximated as a triangular wave curve varying with time.
  • the frequency of the spreading output signal can be controlled.
  • the control frequency control word F(t) has Waveforms in different modulation modes can achieve the spreading effect of the corresponding modulation mode, that is, in the frequency domain, it is displayed as a sweep in a certain frequency range. If the maximum and minimum values of the frequency control word have a larger frequency difference , The wider the range of spread spectrum, that is, the better the effect of reducing electromagnetic interference.
  • FIG. 10A is a schematic structural diagram of a frequency spreading sub-circuit provided by some embodiments of the present disclosure
  • FIG. 10B is a schematic structural diagram of another frequency spreading sub-circuit provided by some embodiments of the disclosure.
  • the first input module 1211 includes a K ⁇ 1 multiplexer 711.
  • the K ⁇ 1 multiplexer 711 has a plurality of input terminals, a control input terminal, and an output terminal for receiving K reference output signals uniformly spaced in phase.
  • the output module 1213 includes a trigger circuit 730.
  • the trigger circuit 730 is used to generate a pulse train.
  • the pulse train is composed of a pulse signal of the first period T A and a pulse signal of the second period T B in an interleaved manner.
  • the trigger circuit 730 includes a D flip-flop 7301, an inverter 7302, and an output terminal 7303.
  • the D flip-flop 7301 includes a data input terminal, a clock input terminal for receiving the output from the output terminal of the K ⁇ 1 multiplexer 711, and an output terminal for outputting the first clock signal CLK1.
  • the inverter 7302 includes an inverter input terminal for receiving the first clock signal CLK1 and an inverter output terminal for outputting the second clock signal CLK2, the inverter output terminal is connected to the data input terminal of the D flip-flop 7301 , To output the second clock signal CLK2 to the data input terminal of the D flip-flop 7301.
  • the output terminal 7303 of the trigger circuit 730 is used to output the first clock signal CLK1 as the spread spectrum output signal S out .
  • the first clock signal CLK1 includes a pulse train.
  • the second input module 1212 includes a logic control circuit 740.
  • the logic control circuit 740 includes an input terminal for receiving the frequency control word F(t) output by the control circuit 11, a clock input terminal for receiving the first clock signal CLK1, and a K ⁇ 1 multiplexer connected to the first input module 1211 The output terminal of the control input terminal of the multiplexer.
  • the first input module 1211 includes a first K ⁇ 1 multiplexer 721, a second K ⁇ 1 multiplexer 723, and a 2 ⁇ 1 multiplexer.
  • Multiplexer 725 Each of the first K ⁇ 1 multiplexer 721 and the second K ⁇ 1 multiplexer 723 includes a plurality of input terminals, a control input terminal, and an output terminal for receiving K signals with evenly spaced phases.
  • the 2 ⁇ 1 multiplexer 725 includes a control input terminal, an output terminal, a first input terminal for receiving the output of the first K ⁇ 1 multiplexer 721, and a first input terminal for receiving the second K ⁇ 1 multiplexer.
  • the output module 1213 includes a trigger circuit.
  • the trigger circuit is used to generate pulse trains.
  • the trigger circuit includes a D flip-flop 761, an inverter 763, and an output terminal 762.
  • the D flip-flop 761 includes a data input terminal, a clock input terminal for receiving the output from the output terminal of the 2 ⁇ 1 multiplexer 725, and an output terminal for outputting the first clock signal CLK1.
  • the inverter 763 includes an input terminal for receiving the first clock signal CLK1 and an output terminal for outputting the second clock signal CLK2.
  • the output terminal of the inverter 763 is connected to the data input terminal of the D flip-flop 761 to connect the The second clock signal CLK2 is output to the data input terminal of the D flip-flop 761.
  • the output terminal 762 of the trigger circuit is used to output the first clock signal CLK1 as the spread spectrum output signal S out .
  • the first clock signal CLK1 is connected to the control input terminal of the 2 ⁇ 1 multiplexer 725.
  • the second input module 1212 includes a first logic control circuit 70 and a second logic control circuit 74.
  • the first logic control circuit 70 includes a first adder 701, a first register 703, and a second register 705.
  • the second logic control circuit 74 includes a second adder 741, a third register 743, and a fourth register 745.
  • the first adder 701 adds the frequency control word (F(t)) and the most significant bits (for example, 5 bits) stored in the first register 703, and then adds up on the rising edge of the second clock signal CLK2 The result of the addition is stored in the first register 703; or, the first adder 701 adds the frequency control word (F(t)) and all the information stored in the first register 703, and then the second clock signal CLK2 rising edge At this time, the addition result is stored in the first register 703.
  • the most significant bit stored in the first register 703 will be stored in the second register 705 and used as the selection signal of the first K ⁇ 1 multiplexer 721
  • One signal is selected from K multi-phase input signals as the first output signal of the first K ⁇ 1 multiplexer 721.
  • the second adder 741 adds the frequency control word (F(t)) and the most significant bit stored in the first register 703, and then saves the addition result in the third register 743 at the rising edge of the second clock signal CLK2 .
  • the information stored in the third register 743 will be stored in the fourth register 745 and used as the selection signal of the second K ⁇ 1 multiplexer 723 for slave K
  • One of the two multi-phase input signals is selected as the second output signal of the second K ⁇ 1 multiplexer 723.
  • the 2 ⁇ 1 multiplexer 725 selects the first output signal from the first K ⁇ 1 multiplexer 721 and the second K ⁇ 1 multiplexer at the rising edge of the first clock signal CLK1
  • One of the second output signals of 723 is used as the output signal of the 2 ⁇ 1 multiplexer 725 and used as the input clock signal of the D flip-flop 761.
  • the period (T TAF ) of the spread spectrum output signal S out output by the TAF-DPS synthesizer shown in FIG. 10A and FIG. 10B can be calculated by the above formula (1).
  • FIG. 11 is a schematic diagram of a spectrum comparison result before and after spreading provided by some embodiments of the present disclosure.
  • the reference frequency is represented by curve 500
  • the first spread frequency after spreading according to the triangular modulation mode is represented by curve 501
  • the second spreading frequency after spreading according to the sawtooth modulation mode is represented by curve 502
  • the third spreading frequency after spreading according to the random modulation mode is represented by curve 503.
  • the modulation rate (modulation rate) corresponding to the first, second, and third spreading frequencies are all 30kHz
  • the resolution bandwidth of the spectrum analyzer is 120kHz.
  • the first spreading frequency, the second spreading frequency, and the third spreading frequency are all frequencies of the spreading output signal generated by the same clock spreading circuit provided by the embodiment of the present disclosure based on different modulation modes. As shown in Figure 11, for the reference frequency without spreading, the peak energy of the reference frequency is -16.1306dB, the energy of the first spreading frequency is -29.275dB, and the energy of the second spreading frequency is -32.3926dB. The energy of the third spreading frequency is -27.7686dB. It can be seen from the experimental results that the spread frequency based on any modulation mode can effectively reduce the EMI spike noise.
  • FIG. 12 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure
  • FIG. 13 is a screenshot of an electronic device provided by some embodiments of the present disclosure during normal operation.
  • the electronic device 1 provided by the embodiment of the present disclosure may include the clock spreading circuit 10 described in any one of the above.
  • the electronic device 1 may be a liquid crystal display device or the like, and the clock spreading circuit 10 may be applied to the logic board (TCON) of the liquid crystal display device. As shown in FIG. 13, when the liquid crystal display device is displaying, the spread spectrum function of the liquid crystal display device is turned on, and the display effect of the liquid crystal display device is not affected.
  • TCON logic board
  • clock spreading circuit 10 can refer to the relevant description in the embodiment of the clock spreading circuit, which will not be repeated here.
  • FIG. 14 is a schematic flowchart of a clock spreading method provided by some embodiments of the present disclosure.
  • the clock spreading method provided in the embodiments of the present disclosure may be implemented based on the clock spreading circuit described in any embodiment of the present disclosure.
  • the clock spreading method provided by the embodiment of the present disclosure may include the following operations:
  • S11 Generate a frequency control word according to the modulation parameters, where the frequency control word changes discretely with time;
  • S12 Receive and generate and output a spread-spectrum output signal after spreading according to the frequency control word, where the spread-spectrum output signal corresponds to the frequency control word.
  • the clock spreading method provided by the embodiments of the present disclosure can realize the spreading function of enabling various modulation modes (such as triangular wave modulation mode, sawtooth modulation mode), and can not introduce additional noise when the spreading function is turned on, that is, when the spreading function is not Without affecting the normal operation of the circuit system, electromagnetic interference can be effectively reduced.
  • various modulation modes such as triangular wave modulation mode, sawtooth modulation mode
  • the frequency control word may include a fractional part and an integer part, the integer part is an integer, the fractional part changes discretely with time, and the fractional part is a decimal, and its range is [0,1).
  • the modulation parameters include the spreading depth coefficient, spreading reference value, modulation mode, modulation rate, and reference frequency corresponding to the spreading output signal.
  • Step S11 may include: generating a fractional part according to the spreading depth coefficient, spreading reference value, modulation mode and modulation rate; generating an integer part according to the reference frequency; generating a frequency control word according to the fractional part and the integer part.
  • the spread spectrum output signal may be generated by a TAF-DPS synthesizer.
  • the clock spreading method shown in FIG. 14 can be implemented by the clock spreading circuit according to any embodiment of the present disclosure.
  • step S11 can be implemented by the control circuit in the clock spreading circuit according to any embodiment of the present disclosure.
  • Step S12 can be implemented by the signal generating circuit in the clock spreading circuit described in any embodiment of the present disclosure, and similar operations or steps will not be repeated here.

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Abstract

一种时钟展频电路、电子设备和时钟展频方法。时钟展频电路(10)包括控制电路(11)和信号生成电路(12)。控制电路(11)被配置为根据调制参数生成频率控制字，其中，频率控制字随时间离散变化；信号生成电路(12)被配置为接收并根据频率控制字，生成并输出展频后的展频输出信号，其中，展频输出信号与频率控制字对应。

Description

时钟展频电路、电子设备和时钟展频方法 技术领域
本公开的实施例涉及一种时钟展频电路、电子设备和时钟展频方法。
背景技术
电磁干扰(EMI)是指电路系统通过传导或者辐射的方式，对于周边电路系统产生的影响，电磁干扰会引起电路性能的降低，甚至可能导致整个电路系统失效。时钟信号常常是电路系统中频率最高和边沿最陡的信号，多数电磁干扰问题的产生与高频的时钟信号有关。降低电磁干扰的方法包括屏蔽、滤波、隔离、信号边沿控制以及印刷电路板(Printed Circuit Board，PCB)的布局布线(例如，在PCB中增加电源和接地(GND)层)等。然而，这些方法成本较高、效率低，同时对电路系统的性能也有一定负面影响。
时钟展频(Clock Spread Spectrum)是另一种有效降低EMI的方法，时钟展频通过频率调制的手段将集中在窄频带范围内的能量分散到预定宽频带范围，通过降低时钟在基频和奇次谐波频率的幅度(能量)，达到降低系统电磁辐射峰值的目的。
发明内容
本公开至少一实施例提供一种时钟展频电路，包括：控制电路，被配置为根据调制参数生成频率控制字，其中，所述频率控制字随时间离散变化；信号生成电路，被配置为接收并根据所述频率控制字，生成并输出展频后的展频输出信号，其中，所述展频输出信号与所述频率控制字对应。
例如，在本公开至少一实施例提供的时钟展频电路中，所述频率控制字表示为：F(t)＝I+r(t)，其中，F(t)为所述频率控制字，I为所述频率控制字的整数部分，I为常数且为整数，r(t)为所述频率控制字的小数部分，r(t)为小数且随所述时间离散变化，t表示所述时间。
例如，在本公开至少一实施例提供的时钟展频电路中，所述调制参数包括与所述展频输出信号对应的展频深度系数、展频参考值、调制速率、参考频率和调制模式，所述控制电路包括：小数生成子电路，被配置为根据所述展频深度系数、所述展频参考值、所述调制模式和所述调制速率生成所述小数部分； 整数生成子电路，被配置为根据所述参考频率生成所述整数部分；合成子电路，被配置为接收并根据所述小数部分和所述整数部分，生成所述频率控制字。
例如，在本公开至少一实施例提供的时钟展频电路中，所述小数生成子电路包括：调频控制模块，被配置为根据所述调制速率生成调频时钟信号以控制所述频率控制字的变化速率；小数生成模块，被配置为在所述调频时钟信号的控制下，根据所述调制模式、所述展频深度系数和所述展频参考值，生成并输出所述小数部分至所述合成子电路。
例如，在本公开至少一实施例提供的时钟展频电路中，所述小数生成模块包括调制模式子模块，所述调制模式包括三角调制模式、锯齿调制模式、正弦调制模式或随机调制模式，所述调制模式子模块被配置为采用所述三角调制模式、所述锯齿调制模式、所述正弦调制模式和所述随机调制模式中的任一种调制模式生成所述小数部分。
例如，在本公开至少一实施例提供的时钟展频电路中，所述调频控制模块包括：计数子模块，被配置为对参考时钟信号进行计数，以得到所述参考时钟信号的计数值；计时子模块，被配置为根据所述调制速率确定计数周期，基于所述计数周期和所述计数值确定所述调频时钟信号。
例如，在本公开至少一实施例提供的时钟展频电路中，所述信号生成电路包括：基准时间单位生成子电路，被配置生成并输出基准时间单位；展频子电路，被配置为根据所述频率控制字和所述基准时间单位生成并输出所述展频输出信号。
例如，在本公开至少一实施例提供的时钟展频电路中，所述基准时间单位生成子电路包括：压控振荡器，被配置为以预定振荡频率振荡；锁相环回路电路，被配置为将所述压控振荡器的输出频率锁定为基准输出频率；K个输出端，被配置为输出K个相位均匀间隔的基准输出信号，其中，K为大于1的正整数，其中，所述基准输出频率表示为f d，所述基准时间单位是所述K个输出端输出的任意两个相邻的基准输出信号之间的时间跨度，所述基准时间单位表示为△，并且△＝1/(K·f d)。
例如，在本公开至少一实施例提供的时钟展频电路中，所述展频子电路为时间平均频率直接周期合成器。
例如，在本公开至少一实施例提供的时钟展频电路中，所述频率控制字的最大值和所述频率控制字的最小值满足以下公式：0≤Fmax-Fmin＜1，其中， Fmin表示所述频率控制字的最小值，Fmax表示所述频率控制字的最大值。
本公开至少一实施例还提供一种电子设备，包括：根据上述任一项所述的时钟展频电路。
本公开至少一实施例还提供一种时钟展频方法，应用于根据上述任一所述的时钟展频电路，所述时钟展频方法包括：根据所述调制参数生成所述频率控制字，其中，所述频率控制字随时间离散变化；以及接收并根据所述频率控制字，生成并输出展频后的所述展频输出信号，其中，所述展频输出信号与所述频率控制字对应。
例如，在本公开至少一实施例提供的时钟展频方法中，所述频率控制字包括小数部分和整数部分，所述调制参数包括与所述展频输出信号对应的展频深度系数、展频参考值、调制模式、调制速率和参考频率，根据所述调制参数生成所述频率控制字包括：根据所述展频深度系数、所述展频参考值、所述调制模式和所述调制速率生成所述小数部分，其中，所述小数部分为小数且随所述时间离散变化；根据所述参考频率生成所述整数部分，其中，所述整数部分为整数；根据所述小数部分和所述整数部分，生成所述频率控制字。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种时钟展频电路的示意性框图；
图2为本公开一些实施例提供的一种时钟展频电路的结构示意图；
图3A为本公开一些实施例提供的一种小数生成子电路的示意图；
图3B为本公开一些实施例提供的另一种小数生成子电路的示意图；
图4为本公开一些实施例提供的一种调频控制模块的示意性框图；
图5A示出了本公开一些实施例提供一种基准时间单位生成子电路的示意性框图；
图5B示出了本公开一些实施例提供另一种基准时间单位生成子电路的示意性结构图；
图6示出了本公开一些实施例提供的一种K个相位均匀间隔的基准输出信号的示意图；
图7示出了本公开一些实施例提供的一种展频子电路的示意性框图；
图8示出了本公开一些实施例提供的一种展频子电路的工作原理示意图；
图9为本公开一些实施例提供的一种根据三角调制模式确定的频率调制示意图；
图10A为本公开一些实施例提供的一种展频子电路的结构示意图；
图10B为本公开一些实施例提供的另一种展频子电路的结构示意图；
图11为本公开一些实施例提供的一种展频前后频谱对比结果的示意图；
图12为本公开一些实施例提供的一种电子设备的示意性框图；
图13为本公开一些实施例提供的一种电子设备正常工作时的截图；
图14为本公开一些实施例提供的一种时钟展频方法的示意性流程图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。
随着技术的发展，时钟信号的频率越来越高，而高频的时钟信号具有较强的电磁干扰。目前，为了有效降低电磁干扰，可以在时钟信号中引入周期抖动(jitter)的方法来实现时钟展频功能以降低电磁干扰，即，使时钟信号的每个 周期都不相同，这样时钟信号的频谱将是一个宽带频谱，而不是一个特别纯净的尖峰。但是这种方法使得时钟信号的每个周期都不相同，如果用这样的时钟去驱动数字电路，那么数字电路的建立时间(setup time)和保持时间(hold time)将无法确定，因此，很难确定时钟展频的参数。
本公开至少一些实施例提供一种时钟展频电路、电子设备和时钟展频方法，该时钟展频电路包括控制电路和信号生成电路，控制电路被配置为根据调制参数生成频率控制字，频率控制字随时间离散变化；信号生成电路被配置为接收并根据频率控制字，生成并输出展频后的展频输出信号，展频输出信号与频率控制字对应。
该时钟展频电路基于时间平均频率脉冲直接合成(Time-Average-Frequency Direct-Period-Synthesis,TAF-DPS)技术，使用TAF-DPS生成时钟展频信号，能够通过相同的电路实现开启各种调制模式(比如三角波调制模式，锯齿波调制模式)的展频功能，且能够在开启展频功能时不引入额外的噪声，即在不影响电路系统正常工作的情况下，有效地降低电磁干扰。另外，该时钟展频电路为全数字电路，功耗低，体积小，可编程，易于集成在各种芯片中。
下面结合附图对本公开的实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图1为本公开一些实施例提供的一种时钟展频电路的示意性框图。
例如，如图1所示，时钟展频电路10可以包括控制电路11和信号生成电路12。控制电路11被配置为根据调制参数生成频率控制字；信号生成电路12被配置为接收并根据频率控制字，生成并输出展频后的展频输出信号。
例如，频率控制字随时间离散变化，展频输出信号与频率控制字对应。
需要说明的是，在本公开的实施例中，“展频输出信号与频率控制字对应”表示展频输出信号的频率与频率控制字对应，展频输出信号的频率可以通过频率控制字来调节，由于频率控制字随时间离散变化，则展频输出信号的频率也随时间离散变化，该展频输出信号的频谱是一个宽带频谱，从而实现时钟展频。
在包含本公开的实施例提供的时钟展频电路的电路系统中，在开启与关闭展频功能的状态下，电路系统的正常工作均不被影响，从而在保证电路系统性能的同时，又实现了降低电磁辐射的目的。
例如，频率控制字可以表示为：
F(t)＝I+r(t)，
其中，F(t)为频率控制字，I为频率控制字的整数部分，r(t)为频率控制字的小数部分，r(t)随时间离散变化，t表示时间。例如，r(t)的范围为[0，1)，也就是说，r(t)在0至1之间变化，r(t)可以为0，但不能为1。由此，在一些示例中，当频率控制字的整数部分I不变的情况下，频率控制字的最大值和频率控制字的最小值可以满足以下公式：0≤Fmax-Fmin＜1，其中，Fmin表示频率控制字的最小值，Fmax表示频率控制字的最大值。
需要说明的是，虽然r(t)不能为1，但频率控制字的整数部分I可以变化，此时，频率控制字的最大值Fmax和频率控制字Fmin的最小值可以满足以下公式：0≤Fmax-Fmin≤1，例如，在另一些示例中，Fmin＝I+r(t)，Fmax＝(I+1)+r(t)，可令r(t)为0，则Fmax-Fmin＝1，此时，频率控制字F(t)仍然在两个整数之间振荡。
例如，调制参数可以包括与展频输出信号对应的参考频率、展频深度系数、展频参考值、调制速率和调制模式等。
例如，参考频率为电路系统的工作频率，从而参考频率基于电路系统的工作需求确定。本公开对参考频率的具体值不作限定。
例如，展频深度系数可以根据该展频输出信号的频率的展频深度确定，例如，在一些实施例中，若展频输出信号的参考频率为100MHz，展频输出信号的展频深度为20MHz，即展频输出信号的频率范围为90MHz至110MHz，则展频深度系数可以为±0.1(即±(展频深度/2)/参考频率)。
例如，在一些实施例中，展频参考值可以由用户根据实际需求设置，例如，展频参考值可以为0.5。在另一些实施例中，展频参考值也可以由电路系统的工作频率(即参考频率)确定，即参考频率对应参考频率控制字，参考频率控制字的小数部分即为展频参考值。
例如，调制速率表示频率控制字随时间变化的速度。
例如，调制模式可以包括三角调制模式、锯齿调制模式、正弦调制模式、随机调制模式和其他自定义模式等。用户可以根据实际应用需求选择相应的调制模式，例如，不同时钟展频电路可以对应不同的调制模式。但不限于此，不同时钟展频电路也可以对应相同的调制模式。例如，同一个时钟展频电路也可以对应不同的调制模式，不同的调制模式可以分别与时钟展频电路的不同应用场景对应。本公开对调制模式的类型、选择方式等不作具体限制。
例如，频率控制字的整数部分I由参考频率确定。频率控制字的小数部分 r(t)由展频深度系数、展频参考值、调制速率和调制模式确定。
例如，在一些实施例中，展频深度系数、调制模式和调制速率均可以由用户根据实际需求设置。
图2为本公开一些实施例提供的一种时钟展频电路的结构示意图。
例如，控制电路11可以通过硬件的方式实现；或者，控制电路11还可以硬件和软件结合的方式实现。在一些实施例中，控制电路11可以通过硬件的方式或者硬件和软件结合的方式实现。
例如，在一些实施例中，如图2所示，控制电路11可以包括小数生成子电路110、整数生成子电路111和合成子电路112。例如，小数生成子电路110被配置为根据展频深度系数D、展频参考值Cr、调制模式Am和调制速率V F生成频率控制字F(t)的小数部分r(t)；整数生成子电路111被配置为根据参考频率f w生成频率控制字F(t)的整数部分I；合成子电路112被配置为接收并根据频率控制字的小数部分r(t)和频率控制字F(t)的整数部分I，生成频率控制字F(t)。
例如，在一些实施例中，小数生成子电路110还被配置为存储频率控制字F(t)的小数部分r(t)的值。整数生成子电路111还被配置为存储频率控制字F(t)的整数部分I的值。
图3A为本公开一些实施例提供的一种小数生成子电路的示意图，图3B为本公开一些实施例提供的另一种小数生成子电路的示意图。
例如，如图3A所示，在另一些实施例中，小数生成子电路110可以包括调频控制模块(或调频控制子电路)1101和小数生成模块(或生成子电路)1102。调频控制模块1101被配置为根据调制速率V F生成调频时钟信号CLK_AF以控制频率控制字F(t)的小数部分r(t)的变化速率，最终控制频率控制字F(t)的变化速率；小数生成模块1102被配置为在调频时钟信号CLK_AF的控制下，根据调制模式Am、展频深度系数D和展频参考值Cr，生成并输出小数部分r(t)至合成子电路112。
例如，展频输出信号的展频方式为中心展频，小数部分r(t)的范围为：Cr–D/2≤r(t)≤Cr+D/2，则频率控制字F(t)的范围为：I+Cr–D/2≤F(t)≤I+Cr+D/2，此时，频率控制字的最大值Fmax为I+Cr+(D/2)，频率控制字的最小值Fmin为I+Cr-(D/2)。又例如，展频输出信号的展频模式为向上展频，小数部分的范围为：Cr–D≤r(t)≤Cr，则频率控制字F(t)的范围为：I+Cr–D≤F(t)≤I+Cr，此时，频率控 制字的最大值Fmax为I+Cr，频率控制字的最小值Fmin为I+Cr-D。又例如，展频输出信号的展频模式为向下展频，小数部分的范围为：Cr≤r(t)≤Cr+D，则频率控制字F(t)的范围为：I+Cr≤F(t)≤I+Cr+D，此时，频率控制字的最大值Fmax为I+Cr+D，频率控制字的最小值Fmin为I+Cr。
例如，在一些实施例中，小数生成模块1102可以包括调制模式子模块，调制模式子模块用于控制小数部分r(t)的展频方式。例如，调制模式子模块被配置为采用三角调制模式、锯齿调制模式、正弦调制模式和随机调制模式等调制模式中的任一种调制模式生成小数部分r(t)。
例如，在另一些实施例中，小数生成模块1102可以包括选择子模块和与多种调制模式一一对应的多个调制模式子模块。如图3B所示，小数生成模块1102可以包括三角调制模式子模块1102a、锯齿调制模式子模块1102b、正弦调制模式子模块1102c、随机调制模式子模块1102d和选择子模块1102e。三角调制模式子模块1102a被配置为根据三角调制模式、展频深度系数D和展频参考值Cr，生成与三角调制模式对应的第一中间小数部分；锯齿调制模式子模块1102b被配置为根据锯齿调制模式、展频深度系数D和展频参考值Cr，生成与锯齿调制模式对应的第二中间小数部分；正弦调制模式子模块1102c被配置为根据正弦调制模式、展频深度系数D和展频参考值Cr，生成与正弦调制模式对应的第三中间小数部分；随机调制模式子模块1102d被配置为根据随机调制模式、展频深度系数D和展频参考值Cr，生成与随机调制模式对应的第四中间小数部分。选择子模块1102e被配置为根据调制模式Am从第一中间小数部分、第二中间小数部分、第三中间小数部分和第四中间小数部分中选择一个作为频率控制字F(t)的小数部分r(t)。例如，在一个示例中，当用户设定的调制模式Am为三角调制模式时，选择子模块1102e选择第一中间小数部分作为频率控制字F(t)的小数部分r(t)。
例如，选择子模块1102e可以为包括多路复用器，多路复用器例如可以为4选1多路复用器。
图3B所示的示例中，选择子模块1102e根据调制模式Am从多个中间小数部分中选择与该调制模式Am对应的中间小数部分并输出该对应的中间小数部分。但本公开不限于此，例如，在另一些实施例中，选择子模块1102e可以根据调制模式Am从模式控制信号组中选择该调制模式Am对应的模式控制信号，模式控制信号组包括三角模式控制信号、锯齿模式控制信号、正弦模式控 制信号、随机模式控制信号。模式控制信号可以被输出至三角调制模式子模块1102a、锯齿调制模式子模块1102b、正弦调制模式子模块1102c、随机调制模式子模块1102d，与该调制模式Am对应的调制模式子模块可以在模式控制信号的控制下生成并输出与该调制模式Am对应的中间小数部分。例如，在一些示例中，若调制模式Am为锯齿调制模式，选择子模块1102e可以从模式控制信号组中选择锯齿模式控制信号，然后该锯齿模式控制信号被输出至三角调制模式子模块1102a、锯齿调制模式子模块1102b、正弦调制模式子模块1102c、随机调制模式子模块1102d，然而只有锯齿调制模式子模块1102b可以在锯齿模式控制信号的控制下生成并输出与锯齿调制模式对应的第二中间小数部分，而在锯齿模式控制信号的控制下，三角调制模式子模块1102a、正弦调制模式子模块1102c和随机调制模式子模块1102d均无法生成信号。
例如，在又一些实施例中，小数生成模块1102可以包括仅与多种调制模式一一对应的多个调制模式子模块。此时，只有与用户设定的调制模式Am对应的调制模式子模块可以生成中间小数部分，且该中间小数部分作为最终的频率控制字F(t)的小数部分r(t)被输出至合成子电路112，即调制模式Am可以控制多个调制模式子模块中与该调制模式Am对应的调制模式子模块根据相应的调制模式、展频深度系数D和展频参考值Cr，生成与相应的调制模式对应的中间小数部分。例如，在一个示例中，小数生成模块1102可以包括三角调制模式子模块1102a、锯齿调制模式子模块1102b、正弦调制模式子模块1102c和随机调制模式子模块1102d，三角调制模式子模块1102a与三角调制模式对应，锯齿调制模式子模块1102b与锯齿调制模式对应，正弦调制模式子模块1102c与正弦调制模式对应，随机调制模式子模块1102d与随机调制模式对应。当用户设定的调制模式Am为正弦调制模式时，则只有正弦调制模式子模块1102c可以根据正弦调制模式、展频深度系数D和展频参考值Cr，生成与正弦调制模式对应的第三中间小数部分，然后该第三中间小数部分即可作为频率控制字F(t)的小数部分r(t)被输出至合成子电路112。在此种情况下，小数生成模块1102可以不包括选择子模块1102e。
例如，对于三角调制模式、锯齿调制模式和正弦调制模式，小数部分r(t)是规律变化的近似曲线。因此，三角调制模式子模块1102a、锯齿调制模式子模块1102b和正弦调制模式子模块1102c中的每一个可以包括加法器、存储器、减法器和比较器等。
下面以三角调制模式子模块1102a为例详细描述调制模式子模块的工作原理。三角调制模式子模块1102a中的存储器用于存储小数部分r(t)的变化步长。例如，当展频参考值Cr为0.5，展频深度系数D为0.5，展频输出信号的展频方式为中心展频时，小数部分r(t)的范围为0.25-0.75，即0.5(展频参考值Cr)±(0.5(展频深度系数D)/2)，三角调制模式的变化步长可以为0.01。小数部分r(t)的第一个值可以为展频参考值Cr，即0.5，利用三角调制模式子模块1102a中的加法器将第一个值(即展频参考值Cr)增加0.01，以得到小数部分r(t)的第二个值0.51，然后利用加法器将第二个值增加0.01，以得到小数部分r(t)的第三个值0.52，以此类推，直到小数部分r(t)的值为0.75(即小数部分的最大值)时，则利用加法器将最大值(即0.75)增加-0.01，即利用加法器将最大值减去0.01，以得到小数部分r(t)的第N个值0.74，然后利用加法器将第N个值减去0.01，以得到小数部分r(t)的第N+1个值0.73，以此类推，直到小数部分r(t)的值为0.25(即小数部分的最小值)时，则再次利用加法器将最小值(即0.25)增加0.01，以得到小数部分r(t)的第N+q个值0.26，然后利用加法器将第N+q个值加上0.01，以得到小数部分r(t)的第N+q+1个值0.27，以此类推，直到小数部分r(t)的值为0.5(即展频参考值Cr)时，完成一次循环周期。也就是说，一个循环周期的初始值和终值相同，且在该循环周期中小数部分r(t)的值达到一次最大值和一次最小值。不停循环上述过程，则可以生成小数部分r(t)。例如，三角调制模式子模块1102a中的存储器还可以用于存储生成的小数部分r(t)、展频参考值Cr和展频深度系数D等。
需要说明的是，小数部分r(t)的值的变化速率由调频时钟信号CLK_AF控制，即调频时钟信号CLK_AF可以控制例如对第一个值增加0.01的操作和对第二个值增加0.01的操作之间的时间间隔。
例如，对于随机调制模式，小数部分r(t)是由一系列不规则变化的随机数值组成的，随机调制模式子模块1102d可以采用PRBS(Pseudo-Random Binary Sequence，伪随机二进制序列)电路实现，PRBS电路产生的伪随机数值有一个大的循环周期，从而可以近似的认为该伪随机数值是不规则变化。例如，PRBS电路可以包括一组寄存器。
需要说明的是，如上面所述，在一些实施例中，如图3B所示，小数生成模块1102中的每个调制模式子模块均根据相应的调制模式、展频深度系数D和展频参考值Cr，生成与相应的调制模式对应的中间小数部分；也就是说，小 数生成模块1102可以生成多个中间小数部分，然后选择子模块1102e根据调制模式Am从多个中间小数部分中选择与该调制模式Am对应的中间小数部分。
例如，在一些实施例中，小数生成子电路110还可以包括展频深度控制模块和参考值控制模块。展频深度控制模块被配置为确定展频深度系数D，并将展频深度系数D传输至小数生成模块1102；参考值控制模块被配置为确定展频参考值Cr，并将展频参考值Cr传输至小数生成模块110。例如，展频深度控制模块可以直接获取用户输入的展频深度系数D，参考值控制模块可以直接获取用户输入的展频参考值Cr。展频深度控制模块可以包括第一存储电路，第一存储电路用于存储展频深度系数D(例如，展频深度系数D为0.5)，第一存储电路可以包括各种类型的存储介质或寄存器等。参考值控制模块也可以包括第二存储电路，第二存储电路用于存储展频参考值Cr(例如，展频参考值Cr为0.5)，第二存储电路可以包括各种类型的存储介质或寄存器等。展频深度系数D和展频参考值Cr共同决定了展频输出信号的展频范围，即展频深度。
又例如，用户可以输入参考频率和展频深度，展频深度控制模块可以获取参考频率和展频深度，并根据参考频率和展频深度确定展频深度系数D，参考值控制模块获取参考频率，并根据参考频率确定展频参考值Cr。此时，展频深度控制模块可以包括第一存储电路和第一计算电路，参考值控制模块也可以包括第二存储电路和第二计算电路。展频深度控制模块中的第一计算电路用于根据参考频率和展频深度计算展频深度系数D，展频深度控制模块中的第一存储电路用于存储展频深度系数D。参考值控制模块中的第二计算电路用于根据参考频率计算展频参考值Cr，参考值控制模块中的第二存储电路用于存储展频参考值Cr。需要说明的是，展频深度控制模块中的第一计算电路和参考值控制模块中的第二计算电路均可以采用晶体管、电阻、触发器、电容和运算放大器等元件构成。
例如，展频深度系数D和展频参考值Cr可以通过数据接口由用户通过输入装置(例如，键盘、触摸屏、触摸板、鼠标、旋钮等)直接输入至小数生成模块1102。此时，小数生成子电路110可以不包括展频深度控制模块和参考值控制模块。
例如，调制模式Am也可以通过数据接口由用户通过输入装置直接输入至小数生成模块1102。
图4为本公开一些实施例提供的一种调频控制模块的示意性框图。例如，如图4所示，调频控制模块1101包括计时子模块1101a和计数子模块1101b。计数子模块1101b被配置为对参考时钟信号Sys_clk进行计数，以得到参考时钟信号Sys_clk的计数值；计时子模块1101a被配置为根据调制速率V F确定计数周期，以及基于计数周期和计数值确定调频时钟信号CLK_AF。
例如，调制速率V F可以通过数据接口由用户通过输入装置直接输入至计时子模块1101a。
例如，计数周期可以表示每个频率控制字的持续时间。例如，对于三角调制模式，若频率控制字的调频为31.25kHz，该调频对应的调制周期为0.000032s(即1/31250＝0.000032)，调制周期表示频率控制字的变化周期，若在一个调制周期中需要改变频率控制字64次，那么每个频率控制字的持续时间为0.0000032s/64＝500纳秒(ns)，即当每个频率控制字的持续时间为500ns时，则能够满足调频31.25kHz的要求。也就是说，计数周期为500ns。例如，假设当计数周期为500ns时，在该计数周期内，参考时钟信号Sys_clk的脉冲数量为300，则当计数子模块1101b输出的计数值为1至150时，计时子模块1101a可以输出二进制数0，即此时调频时钟信号CLK_AF的值为0；当计数子模块1101b输出的计数值为150至300时，计时子模块1101a可以输出二进制数1，即此时调频时钟信号CLK_AF的值为1。当计数值达到300时，计时子模块1101a可以控制计数子模块1101b将计数值重置为0，以重新开始计数。如此循环，则可以得到周期为500纳秒的调频时钟信号CLK_AF。调频时钟信号CLK_AF的频率低于参考时钟信号Sys_clk的频率。
例如，如图4所示，参考时钟信号Sys_clk可以为系统的时钟信号。
例如，计时子模块1101a和计数子模块1101b可以利用硬件电路实现。计时子模块1101a和计数子模块1101b例如可以采用晶体管、二极管、电阻、触发器、电容和运算放大器等元件构成。例如，计数子模块1101b可以包括加法计数器等。当然，计数子模块1101b的功能也可以通过软件实现。例如，调频控制模块1101还可以包括存储子模块，以用于存储计算机指令和数据，处理器可以执行存储子模块中存储的计算机指令和数据以实现计数子模块1101b的功能。
例如，如图2所示，在一些实施例中，参考频率f w可以通过数据接口由用户通过输入装置输入至整数生成子电路111。此时，整数生成子电路111可以 包括计算模块和存储模块，计算模块用于根据参考频率f w计算与该参考频率f w对应的参考频率控制字，该参考频率控制字的整数部分即为频率控制字F(t)的整数部分I的值，存储模块用于存储该整数部分I的值。存储模块可以为各种类型的存储介质或寄存器等。计算模块例如可以采用晶体管、电阻、触发器、电容和运算放大器等元件构成。
又例如，在另一些实施例中，时钟展频电路10可以连接一计算器，可以利用该计算器根据参考频率f w计算得到整数部分I的值，整数生成子电路111可以直接从计算器中获取该整数部分I的值。此时，整数生成子电路111可以仅包括存储模块，以用于存储整数部分I的值。
例如，如图2所示，合成子电路112用于将整数部分I和小数部分r(t)整合在一起，以得到频率控制字F(t)。合成子电路112可以包括逻辑电路和寄存器等。
例如，如图2所示，信号生成电路12包括基准时间单位生成子电路120和展频子电路121。基准时间单位生成子电路120被配置生成并输出基准时间单位；展频子电路121被配置为根据频率控制字和基准时间单位△生成并输出展频输出信号。
例如，如图2所示，基准时间单位生成子电路120被配置为将基准时间单位△输出至整数生成子电路111。整数生成子电路111可以根据参考频率f w和基准时间单位△，计算与该参考频率f w对应的参考频率控制字，从而确定频率控制字F(t)的整数部分I的值。例如，参考频率控制字可以表示为：
F w＝1/(f w*△)＝I w+r w
其中，F w表示参考频率控制字，I w表示参考频率控制字的整数部分，r w表示参考频率控制字的小数部分。频率控制字F(t)的整数部分I即为该参考频率控制字的整数部分I w。例如，在一些示例中，展频参考值Cr可以为该参考频率控制字的小数部分r w。
例如，如图2所示，基准时间单位生成子电路120还被配置为将基准时间单位△输出至展频子电路121。
图5A示出了本公开一些实施例提供一种基准时间单位生成子电路的示意性框图；图5B示出了本公开一些实施例提供另一种基准时间单位生成子电路的示意性结构图；图6示出了本公开一些实施例提供的一种K个相位均匀间隔的基准输出信号的示意图。
例如，基准时间单位生成子电路120被配置为生成并输出K个相位均匀间隔的基准输出信号以及基准时间单位△。基准时间单位生成子电路120可以利用锁相环(Phase Locked Loop，PLL)、延迟锁相环(Delay locked Loop，DLL)或约翰逊计数器(Johnson Counter)等来产生K个相位均匀间隔的基准输出信号。如图5A所示，在一些实施例中，基准时间单位生成子电路120可以包括压控振荡器(VCO)1201、锁相环回路电路1202和K个输出端1203。压控振荡器1201被配置为以预定振荡频率振荡。锁相环回路电路1202被配置为将压控振荡器1201的输出频率锁定为基准输出频率。K个输出端1203被配置为输出K个相位均匀间隔的基准输出信号，其中，K为大于1的正整数。例如，K＝16、32、128或其他数值。
例如，基准时间单位可以表示为△，基准输出频率可以表示为f d。如图6所示，基准时间单位△是K个输出端1203输出的任意两个相邻的输出信号之间的时间跨度(time span)。基准时间单位△通常由多级压控振荡器1201生成。压控振荡器1201生成的信号的频率f vco可以通过锁相环回路电路1202锁定到已知的基准输出频率f d，即f d＝f vco。
例如，基准时间单位△可以使用以下公式计算：
Δ＝T d/K＝1/(K·f d)
其中，T d表示多级压控振荡器1201生成的信号的周期。f Δ表示基准时间单位的频率的值，即f Δ＝1/Δ＝K·f d。
例如，如图5B所示，锁相环回路电路1202包括相位检测器PFD、环路滤波器LPF和分频器FN。例如，在本公开实施例中，首先，例如具有参考频率的参考信号可以被输入到相位检测器PFD，然后进入环路滤波器LPF，接着进入压控振荡器，最后压控振荡器生成的具有预定振荡频率f vco的信号可以通过分频器FN进行分频以得到分频信号的分频频率f vco/N 0，其中，N 0表示分频器的分频系数，N 0为实数，且N 0大于或等于1。分频频率f vco/N 0反馈到相位检测器PFD，相位检测器PFD用于比较参考信号的参考频率与分频频率f vco/N 0，当参考频率与分频频率f vco/N的频率和相位均相等时，两者之间的误差为零，此时，锁相环回路电路1202处于锁定状态。
例如，环路滤波器LPF可以为低通滤波器。
值得注意的是，图5B所示的电路结构仅是基准时间单位生成子电路120的一种示例性的实现方式。基准时间单位生成子电路120的具体结构并不限于 此，其还可以由其他电路结构构建而成，本公开在此不作限制。例如，K和△可以根据实际需求预先设置，且固定不变。
图7示出了本公开一些实施例提供的一种展频子电路的示意性框图；图8示出了本公开一些实施例提供的一种展频子电路的工作原理示意图。
例如，如图7所示，展频子电路121包括第一输入模块1211、第二输入模块1212和输出模块1213。第一输入模块1211被配置为接收来自基准时间单位生成子电路120的K个相位均匀间隔的基准输出信号和基准时间单位。第二输入模块1212被配置为接收来自控制电路11的频率控制字F(t)。输出模块1213用于生成第一周期和第二周期，根据第一周期和第二周期生成展频输出信号，以及输出该展频输出信号。第一周期和第二周期的出现可能性由频率控制字F(t)的小数部分r(t)的值控制。
例如，展频子电路121可以包括时间平均频率直接周期(TAF-DPS)合成器。TAF-DPS技术是一种新兴的频率合成技术，其基于新的时间平均频率概念可以生成任何频率的脉冲信号。也就是说，TAF-DPS合成器能够实现小频率粒度的精细频率调整。此外，因为每个单个脉冲是直接构建的，所以TAF-DPS合成器的输出频率可以瞬间改变，也即具有频率切换的迅速性。实验证明，TAF-DPS合成器的频率粒度可以达到几个ppb(parts per billion)。更重要的是，TAF-DPS的频率切换速度是可量化的。也就是说，从接收频率控制字更新的时刻到频率切换的时刻的响应时间可以根据时钟周期来计算。TAF-DPS合成器可以作为本公开实施例中的展频子电路121的一种具体实现方式。
例如，TAF-DPS合成器可以使用专用集成电路(例如，ASIC)或者可编程逻辑器件(例如，FPGA)来实现。或者，TAF-DPS合成器可以使用传统的模拟电路器件来实现。本公开在此不作限定。
下面，将参考图8描述基于TAF-DPS合成器的展频子电路121的工作原理。
例如，如图8所示，基于TAF-DPS合成器510的展频子电路121具有两个输入：基准时间单位520和频率控制字530。频率控制字530表示为F(t)，F(t)＝I+r(t)，且I是大于1的整数，r(t)是分数，且随时间离散变化。
例如，TAF-DPS合成器510具有一个输出CLK 550。该输出CLK 550是合成的时间平均频率时钟信号。在本公开的实施例中，输出CLK 550即为展频输出信号。根据基准时间单位520，TAF-DPS合成器510可以产生两种类型的 周期，即第一周期T A＝I·Δ和第二周期T B＝(I+1)·Δ。展频输出信号CLK 550是时钟脉冲串540，且该时钟脉冲串540由第一周期T A 541和第二周期T B 542以交织的方式构成。分数r(t)用于控制第二周期T B的出现概率，因此，r(t)也可以确定第一周期T A的出现概率。
例如，如图8所示，展频输出信号CLK 550的周期T TAF可以用下面的公式表示：
T TAF＝(1-r(t))·T A+r(t)·T B
＝T A+r(t)·(T B-T A)＝T A+r(t)·△＝I·△+r(t)·△＝(I+r(t))·△
因此，当频率控制字530为F(t)＝I+r(t)时，可以得到：
T TAF＝F(t)·△      (1)
例如，基于上述公式(1)，展频输出信号CLK 550的频率f css可以表示为：
f css＝1/T TAF＝1/(F(t)·△)      (2)
由上面的公式(1)和公式(2)可知，TAF-DPS合成器510输出的展频输出信号CLK 550的周期T TAF与频率控制字530呈线性比例，展频输出信号CLK550的频率f css与频率控制字530呈反比例，具有小量线性的形状。当频率控制字530发生变化时，TAF-DPS合成器510输出的展频输出信号CLK 550的周期T TAF也将以相同的形式发生变化，展频输出信号CLK 550的频率也相应变化。
图9为本公开一些实施例提供的一种根据三角调制模式确定的频率调制示意图。例如，当小数部分r(t)随时间变化的时间间隔较短时，小数部分r(t)近似为三角波曲线，由此，频率控制字F(t)也近似为三角波曲线，如公式(2)所示，基于TAF-DPS生成的展频输出信号的频率f css与频率控制字530为对应的倒数形式，其具有小量线性的性质，从而，如图9所示，展频输出信号的频率f css也近似为一条随时间变化的三角波曲线。
由此，在本公开实施例提供的时钟展频电路中，仅通过控制频率控制字F(t)，即可以实现对展频输出信号的频率的控制，当控制频率控制字F(t)具有不同调制模式下的波形，则可以实现相应调制模式的展频效果，即在频域上表现为在某个频段范围内扫频，如果频率控制字的最大值和最小值对应的频率差越大，则展频的范围就越宽，即降低电磁干扰的效果就越好。同时，当电路系统开启展频功能时，该电路系统的基本功能并不受影响，从而在电路系统正常工作时，可以一直开启展频功能，既保证了电路系统的安全性，又降低了电路系统的电 磁干扰。
另外，当F(t)在两个整数之间变化时，展频输出信号CLK 550的周期只有两种类型，一种长周期TB，一种短周期TA。由此，在设计数字电路时，只需使用短周期来约束建立时间即可，保持时间与周期无关，只与边缘有关。对于包含该时钟展频电路的电路系统，当电路系统开启展频功能和不开启展频功能时，TAF-DPS合成器510输出的信号的周期都只存在两周周期类型，不影响电路系统的正常功能，既保证了电路系统的正常工作，又降低了电磁干扰。
例如，根据公式(2)可知，展频输出信号的频率与频率控制字呈反比例关系，从而展频输出信号的频率的最大值为1/(Fmin*Δ)，展频输出信号的频率的最小值为1/(Fmax*Δ)，展频输出信号的频率的展频深度表示为：FD＝1/(Fmin*Δ)-1/(Fmax*Δ)，其中，FD表示展频深度。
图10A为本公开一些实施例提供的一种展频子电路的结构示意图；图10B为本公开一些实施例提供的另一种展频子电路的结构示意图。
下面，将参考图10A和10B描述TAF-DPS合成器的电路结构。
例如，如图10A所示，在一个实施例中，第一输入模块1211包括K→1多路复用器711。K→1多路复用器711具有用于接收K个相位均匀间隔的基准输出信号的多个输入端、控制输入端和输出端。
例如，输出模块1213包括触发电路730。触发电路730用于生成脉冲串。脉冲串由第一周期T A的脉冲信号和第二周期T B的脉冲信号以交织方式构成。触发电路730包括D触发器7301、反相器7302和输出端7303。D触发器7301包括数据输入端、用于接收来自K→1多路复用器711的输出端的输出的时钟输入端和用于输出第一时钟信号CLK1的输出端。反相器7302包括用于接收第一时钟信号CLK1的反相器输入端和用于输出第二时钟信号CLK2的反相器输出端，反相器输出端与D触发器7301的数据输入端连接，以将第二时钟信号CLK2输出至D触发器7301的数据输入端。触发电路730的输出端7303用于输出第一时钟信号CLK1作为展频输出信号S out。
例如，第一时钟信号CLK1包括脉冲串。
例如，第二输入模块1212包括逻辑控制电路740。逻辑控制电路740包括用于接收控制电路11输出的频率控制字F(t)的输入端、用于接收第一时钟信号CLK1的时钟输入端和连接到第一输入模块1211的K→1多路复用器的控制输入端的输出端。
例如，如图10B所示，在另一个实施例中，第一输入模块1211包括第一K→1多路复用器721、第二K→1多路复用器723和2→1多路复用器725。第一K→1多路复用器721和第二K→1多路复用器723均包括用于接收K个相位均匀间隔的信号的多个输入端、控制输入端和输出端。2→1多路复用器725包括控制输入端、输出端、用于接收第一K→1多路复用器721的输出的第一输入端和用于接收第二K→1多路复用器723的输出的第二输入端。
例如，如图10B所示，输出模块1213包括触发电路。触发电路用于生成脉冲串。触发电路包括D触发器761、反相器763和输出端762。D触发器761包括数据输入端、用于接收来自2→1多路复用器725的输出端的输出的时钟输入端和用于输出第一时钟信号CLK1的输出端。反相器763包括用于接收第一时钟信号CLK1的输入端和用于输出第二时钟信号CLK2的输出端，反相器763的输出端与D触发器761的数据输入端连接，以将第二时钟信号CLK2输出至D触发器761的数据输入端。触发电路的输出端762用于输出第一时钟信号CLK1作为展频输出信号S out。
例如，第一时钟信号CLK1连接到2→1多路复用器725的控制输入端。
例如，如图10B所示，第二输入模块1212包括第一逻辑控制电路70和第二逻辑控制电路74。第一逻辑控制电路70包括第一加法器701、第一寄存器703和第二寄存器705。第二逻辑控制电路74包括第二加法器741、第三寄存器743和第四寄存器745。
第一加法器701将频率控制字(F(t))和第一寄存器703存储的最高有效位(most significant bits，例如，5比特)相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第一寄存器703中；或者，第一加法器701将频率控制字(F(t))和第一寄存器703存储的所有信息相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第一寄存器703中。在下一个第二时钟信号CLK2的上升沿时，第一寄存器703存储的最高有效位将被存储到第二寄存器705中，并作为第一K→1多路复用器721的选择信号，用于从K个多相位输入信号中选择一个信号作为第一K→1多路复用器721的第一输出信号。
第二加法器741将频率控制字(F(t))和第一寄存器703存储的最高有效位相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第三寄存器743中。在下一个第一时钟信号CLK1的上升沿时，第三寄存器743存储的信息将被存储到第四寄存器745中，并作为第二K→1多路复用器723的选择信 号，用于从K个多相位输入信号中选择一个信号作为第二K→1多路复用器723的第二输出信号。
2→1多路复用器725在第一时钟信号CLK1的上升沿时，选择来自第一K→1多路复用器721的第一输出信号和来自第二K→1多路复用器723的第二输出信号中的一个作为2→1多路复用器725的输出信号，以作为D触发器761的输入时钟信号。
例如，图10A和图10B所示的TAF-DPS合成器输出的展频输出信号S out的周期(T TAF)可以由上面的公式(1)计算得到。例如，频率控制字以F(t)＝I+r(t)的形式设置，其中，I是整数，r(t)是在[0,1)的范围内的小数。
图11为本公开一些实施例提供的一种展频前后频谱对比结果的示意图。如图11所示，参考频率由曲线500表示，根据三角调制模式进行展频后的第一展频频率由曲线501表示，根据锯齿调制模式进行展频后的第二展频频率由曲线502表示，根据随机调制模式进行展频后的第三展频频率由曲线503表示。第一展频频率、第二展频频率和第三展频频率对应的调制速率(modulation rate)均为30kHz，第一展频频率、第二展频频率和第三展频频率对应的测试设备频谱仪的分辨率带宽(resolution bandwidth)均为120kHz。第一展频频率、第二展频频率和第三展频频率均是由本公开实施例提供的同一个时钟展频电路基于不同的调制模式而生成的展频输出信号的频率。如图11所示，对于没有进行展频的参考频率，参考频率的尖峰的能量为-16.1306dB，第一展频频率的能量为-29.275dB，第二展频频率的能量为-32.3926dB，第三展频频率的能量为-27.7686dB。从实验结果可以看出，基于任意的调制模式下的展频频率都能够有效的降低EMI尖峰噪声。
本公开至少一实施例还提供一种电子设备。图12为本公开一些实施例提供的一种电子设备的示意性框图，图13为本公开一些实施例提供的一种电子设备正常工作时的截图。
例如，如图12所示，本公开实施例提供的电子设备1可以包括上述任一项所述的时钟展频电路10。
例如，该电子设备1可以为液晶显示装置等，时钟展频电路10可以应用于液晶显示装置的逻辑板(TCON)中。如图13所示，当该液晶显示装置显示时，开启液晶显示装置的展频功能，该液晶显示装置的显示效果并不受影响。
需要说明的是，关于时钟展频电路10的详细说明可以参考上述时钟展频 电路的实施例中的相关描述，在此不再赘述。
本公开至少一实施例还提供一种时钟展频方法。图14为本公开一些实施例提供的一种时钟展频方法的示意性流程图。本公开实施例提供的时钟展频方法可以基于本公开任一实施例所述的时钟展频电路实现。
例如，如图14所示，本公开实施例提供的时钟展频方法可以包括以下操作：
S11：根据调制参数生成频率控制字，其中，频率控制字随时间离散变化；
S12：接收并根据频率控制字，生成并输出展频后的展频输出信号，其中，展频输出信号与频率控制字对应。
本公开实施例提供的时钟展频方法能够实现开启各种调制模式(比如三角波调制模式，锯齿波调制模式)的展频功能，且能够在开启展频功能时不引入额外的噪声，即在不不影响电路系统正常工作的情况下，有效地降低电磁干扰。
例如，频率控制字可以包括小数部分和整数部分，整数部分为整数，小数部分随时间离散变化，且小数部分为小数，其范围为[0,1)。
例如，调制参数包括与展频输出信号对应的展频深度系数、展频参考值、调制模式、调制速率和参考频率。步骤S11可以包括：根据展频深度系数、展频参考值、调制模式和调制速率生成小数部分；根据参考频率生成整数部分；根据小数部分和整数部分，生成频率控制字。
例如，在步骤S12中，展频输出信号可以由TAF-DPS合成器生成。
需要说明的是，对所述时钟展频方法的描述，可以参考上文中对时钟展频电路的描述。图14所示的时钟展频方法可以由本公开任一实施例所述的时钟展频电路来实现，例如，步骤S11可以由本公开任一实施例所述的时钟展频电路中的控制电路来实现，步骤S12可以由本公开任一实施例所述的时钟展频电路中的信号生成电路来实现，在此不再赘述类似的操作或步骤。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种时钟展频电路，包括：
    控制电路，被配置为根据调制参数生成频率控制字，其中，所述频率控制字随时间离散变化；
    信号生成电路，被配置为接收并根据所述频率控制字，生成并输出展频后的展频输出信号，其中，所述展频输出信号与所述频率控制字对应。
  2. 根据权利要求1所述的时钟展频电路，其中，所述频率控制字表示为：
    F(t)＝I+r(t)，
    其中，F(t)为所述频率控制字，I为所述频率控制字的整数部分，I为常数且为整数，r(t)为所述频率控制字的小数部分，r(t)为小数且随所述时间离散变化，t表示所述时间。
  3. 根据权利要求2所述的时钟展频电路，其中，所述调制参数包括与所述展频输出信号对应的展频深度系数、展频参考值、调制速率、参考频率和调制模式，
    所述控制电路包括：
    小数生成子电路，被配置为根据所述展频深度系数、所述展频参考值、所述调制模式和所述调制速率生成所述小数部分；
    整数生成子电路，被配置为根据所述参考频率生成所述整数部分；
    合成子电路，被配置为接收并根据所述小数部分和所述整数部分，生成所述频率控制字。
  4. 根据权利要求3所述的时钟展频电路，其中，所述小数生成子电路包括：
    调频控制模块，被配置为根据所述调制速率生成调频时钟信号以控制所述频率控制字的变化速率；
    小数生成模块，被配置为在所述调频时钟信号的控制下，根据所述调制模式、所述展频深度系数和所述展频参考值，生成并输出所述小数部分至所述合成子电路。
  5. 根据权利要求4所述的时钟展频电路，其中，所述小数生成模块包括调制模式子模块，
    所述调制模式包括三角调制模式、锯齿调制模式、正弦调制模式或随机调 制模式，
    所述调制模式子模块被配置为采用所述三角调制模式、所述锯齿调制模式、所述正弦调制模式和所述随机调制模式中的任一种调制模式生成所述小数部分。
  6. 根据权利要求4或5所述的时钟展频电路，其中，所述调频控制模块包括：
    计数子模块，被配置为对参考时钟信号进行计数，以得到所述参考时钟信号的计数值；
    计时子模块，被配置为根据所述调制速率确定计数周期，基于所述计数周期和所述计数值确定所述调频时钟信号。
  7. 根据权利要求1-6任一项所述的时钟展频电路，其中，所述信号生成电路包括：
    基准时间单位生成子电路，被配置生成并输出基准时间单位；
    展频子电路，被配置为根据所述频率控制字和所述基准时间单位生成并输出所述展频输出信号。
  8. 根据权利要求7所述的时钟展频电路，其中，所述基准时间单位生成子电路包括：
    压控振荡器，被配置为以预定振荡频率振荡；
    锁相环回路电路，被配置为将所述压控振荡器的输出频率锁定为基准输出频率；
    K个输出端，被配置为输出K个相位均匀间隔的基准输出信号，其中，K为大于1的正整数，
    其中，所述基准输出频率表示为f d，所述基准时间单位是所述K个输出端输出的任意两个相邻的基准输出信号之间的时间跨度，所述基准时间单位表示为△，并且△＝1/(K·f d)。
  9. 根据权利要求7或8所述的时钟展频电路，其中，所述展频子电路为时间平均频率直接周期合成器。
  10. 根据权利要求1-9任一项所述的时钟展频电路，其中，所述频率控制字的最大值和所述频率控制字的最小值满足以下公式：0≤Fmax-Fmin＜1，
    其中，Fmin表示所述频率控制字的最小值，Fmax表示所述频率控制字的最大值。
  11. 一种电子设备，包括：根据权利要1-10任一项所述的时钟展频电路。
  12. 一种时钟展频方法，应用于根据权利要求1-10的任一所述的时钟展频电路，所述时钟展频方法包括：
    根据所述调制参数生成所述频率控制字，其中，所述频率控制字随时间离散变化；以及
    接收并根据所述频率控制字，生成并输出展频后的所述展频输出信号，其中，所述展频输出信号与所述频率控制字对应。
  13. 根据权利要求12所述的时钟展频方法，其中，所述频率控制字包括小数部分和整数部分，所述调制参数包括与所述展频输出信号对应的展频深度系数、展频参考值、调制模式、调制速率和参考频率，
    根据所述调制参数生成所述频率控制字包括：
    根据所述展频深度系数、所述展频参考值、所述调制模式和所述调制速率生成所述小数部分，其中，所述小数部分为小数且随所述时间离散变化；
    根据所述参考频率生成所述整数部分，其中，所述整数部分为整数；
    根据所述小数部分和所述整数部分，生成所述频率控制字。
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