WO2020211349A1 - Substrat de réseau et son procédé de préparation - Google Patents

Substrat de réseau et son procédé de préparation Download PDF

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Publication number
WO2020211349A1
WO2020211349A1 PCT/CN2019/117677 CN2019117677W WO2020211349A1 WO 2020211349 A1 WO2020211349 A1 WO 2020211349A1 CN 2019117677 W CN2019117677 W CN 2019117677W WO 2020211349 A1 WO2020211349 A1 WO 2020211349A1
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WO
WIPO (PCT)
Prior art keywords
layer
insulating layer
decomposable
array substrate
gate metal
Prior art date
Application number
PCT/CN2019/117677
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English (en)
Chinese (zh)
Inventor
刘国和
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Publication of WO2020211349A1 publication Critical patent/WO2020211349A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • This application relates to the field of display technology, in particular to an array substrate and a preparation method thereof.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the demand for high-resolution panels such as 4K/8K and large-size 65’/75’/85’ panels is increasing.
  • the current transmission distance becomes larger, which eventually causes the resistance and capacitance load of the liquid crystal panel to increase.
  • the current common practice in the industry is to increase the thickness of conductive metals such as aluminum (Al) and copper (Cu).
  • the wet etching time needs to be extended.
  • the pattern formed has a higher taper angle.
  • a higher taper angle will produce a series of negative effects such as stress concentration.
  • the gate insulating film Gate Insulator, referred to as GI
  • GI Gate Insulator
  • Cu conductive metal copper
  • ESD electrostatic discharge
  • the thin film transistors in the prior art have problems such as breakdown of the gate insulating film, diffusion of conductive metal copper, and electrostatic discharge.
  • the present application provides a display panel and a picture display method to solve the problems of gate insulation film breakdown, conductive metal copper diffusion, electrostatic discharge, and the like in thin film transistors in the prior art.
  • an embodiment of the present application provides a method for manufacturing an array substrate, and the method includes the following steps:
  • the first insulating layer is an organic insulating film layer, and the material of the organic insulating film layer is one or more of array organic insulating film, acrylic resin, and siloxane resin; the material of the first insulating layer It includes a nitrogen-silicon compound, and the thickness of the first insulating layer is 100-500 ⁇ .
  • the step of heating the substrate after the ultraviolet treatment includes: using 230° C. as a heating temperature and 20-30 minutes as a heating time for all the ultraviolet treatments. The substrate is heated.
  • the heating the substrate after the ultraviolet treatment includes: heating the substrate after the ultraviolet treatment at a heating temperature greater than or equal to 100°C.
  • the manufacturing method of the array substrate before the source and drain electrodes are formed on the first insulating layer, the manufacturing method of the array substrate further includes:
  • the second insulating layer is made of a silicon nitride compound, and the thickness of the silicon nitride compound is 3000-5000 ⁇ ;
  • the forming a source electrode and a drain electrode above the first insulating layer includes:
  • a source electrode and a drain electrode are formed above the second insulating layer.
  • the decomposable material of the decomposable layer includes one of polymethylethylene carbonate, photoacid generator, solvent, additives, and surfactant, or Many kinds.
  • forming a decomposable layer on the gate metal layer includes:
  • the yellow light process is performed on the decomposable material to obtain a decomposable layer, and the exposure amount used in the yellow light process is between 100-1000 millijoules.
  • This application also provides a method for manufacturing an array substrate, the method including the following steps:
  • a source electrode and a drain electrode are formed above the first insulating layer.
  • the first insulating layer is an organic insulating film layer
  • the material of the organic insulating film layer is one of array organic insulating film, acrylic resin, and siloxane resin Or multiple
  • the step of heating the substrate after the ultraviolet treatment includes heating the substrate after the ultraviolet treatment with 230° C. as a heating temperature and 20-30 minutes as a heating time.
  • the material of the first insulating layer includes a silicon nitride compound, and the thickness of the first insulating layer is 100-500 ⁇ ;
  • the heating the substrate after the ultraviolet treatment includes: heating the substrate after the ultraviolet treatment at a heating temperature greater than or equal to 100°C.
  • the manufacturing method of the array substrate before the source and drain electrodes are formed on the first insulating layer, the manufacturing method of the array substrate further includes:
  • the second insulating layer is made of a silicon nitride compound, and the thickness of the silicon nitride compound is 3000-5000 ⁇ ;
  • the forming a source electrode and a drain electrode above the first insulating layer includes:
  • a source electrode and a drain electrode are formed on the second insulating layer.
  • the decomposable material of the decomposable layer includes one of polymethylethylene carbonate, photoacid generator, solvent, additives, and surfactant, or Many kinds.
  • the step of forming a decomposable layer on the gate metal layer includes:
  • the yellow light process is performed on the decomposable material to obtain a decomposable layer, and the exposure amount used in the yellow light process is between 100-1000 megajoules.
  • the conductive material of the gate metal layer is one or more of molybdenum aluminum alloy, molybdenum copper alloy, or copper-titanium alloy.
  • the conductive material of the gate metal layer is one or more of molybdenum aluminum alloy, molybdenum copper alloy, or copper-titanium alloy.
  • the present application also provides an array substrate manufactured by the method for preparing the array substrate.
  • the array substrate includes a substrate and a gate metal layer prepared above the substrate; and an intermediate insulating layer is provided on the gate Above the metal layer, a hollow cavity is formed between the intermediate insulating layer and the gate metal layer;
  • the source and drain layer is arranged above the intermediate insulating layer.
  • the hollow cavity separates the intermediate insulating layer and the gate metal layer.
  • the hollow cavity has a partially disconnected structure, so that there is a contact area between the intermediate insulating layer and the gate metal layer.
  • the hollow chamber is a vacuum chamber.
  • an active layer is further provided between the source drain layer and the intermediate insulating layer.
  • a passivation layer is further provided above the source and drain electrodes.
  • the conductive material of the gate metal layer is one or more of molybdenum aluminum alloy, molybdenum copper alloy, or copper titanium alloy.
  • the conductive material of the gate metal layer is one or more of molybdenum aluminum alloy, molybdenum copper alloy or copper titanium alloy .
  • the array substrate method and array substrate provided by the present application adopt a new thin film transistor structure, which effectively reduces the gate insulating film (Gate Insulator, referred to as GI) breakdown, effectively improve the conductive metal copper (Cu) diffusion, electrostatic discharge (Electro-Static discharge, referred to as ESD) and other issues, improve the voltage retention rate.
  • GI gate Insulator
  • ESD electrostatic discharge
  • FIG. 1 is a schematic flowchart of a method for manufacturing an array substrate provided by an embodiment of the application.
  • FIGS 2a-2f are schematic diagrams of the process preparation process of the embodiment of the application.
  • FIG. 3 is a schematic diagram of another process of a method for manufacturing an array substrate provided by an embodiment of the application.
  • 4a to 4i are another schematic diagrams of the preparation process structure provided by the embodiment of the application.
  • Figures 5a-5h are schematic diagrams of the preparation process structure of an embodiment of the application.
  • FIG. 6 is a schematic side view of an array substrate according to an embodiment of the application.
  • FIG. 7 is a schematic diagram of another side view of the array substrate according to an embodiment of the application.
  • the method for manufacturing an array substrate includes:
  • the array substrate prepared by this method effectively reduces the breakdown of the gate insulating film in the array substrate, effectively improves the problems of conductive metal copper diffusion and electrostatic discharge, and improves the voltage retention rate.
  • a substrate 201 is included, and a gate metal layer 202 is prepared on the substrate 201.
  • the conductive material of the gate metal layer 202 includes one or more of molybdenum aluminum alloy (Mo/Al/Mo), molybdenum copper alloy (Cu/Mo), or copper titanium alloy (Cu/Ti) .
  • a decomposable layer 203 is formed on the gate metal layer 202.
  • the decomposable layer 203 is a positive photoresist material, so it can also be formed as required by a normal yellow light process. Its main composition is: polymethylethylene carbonate (Poly Propylene carbonate, PPC for short), Photo Acid Generator (PAG for short), solvents, additives, surfactants, etc.
  • the decomposable layer material has another property: when it is not irradiated with ultraviolet light (UV), the thermal decomposition temperature of the decomposable layer material is between 150-250°C. However, after being irradiated with ultraviolet light (UV), the decomposable layer material 203 can be decomposed from 50°C, and is almost completely decomposed at 100°C.
  • a first insulating layer 204 is formed on the substrate 201 on which the decomposable layer 203 is formed, and the first insulating layer 204 covers the decomposable layer 203.
  • the first insulating layer 204 is an organic insulating film layer
  • the material of the organic insulating film layer is an array organic insulating film (Polymer One or more of Film on Array, PFA for short), Polymethyl Methacrylate (PMMA for short), and siloxane resin.
  • the substrate including the first insulating layer 204 is irradiated with ultraviolet light 205;
  • the ultraviolet light 205 plays a role on the first insulating layer 204: performing a bleaching treatment on the first insulating layer 204 to increase the transmittance of the first insulating layer 204, and performing a decomposable layer 203 Ultraviolet 205 treatment.
  • the used ultraviolet light 205 has an accumulated light quantity greater than or equal to 800 millijoules (Milli Joule, MJ);
  • the substrate after the ultraviolet 204 treatment is heated, wherein the decomposable layer 203 is decomposed during the heating process, so that there is formed between the first insulating layer 204 and the gate metal layer 202
  • the hollow cavity 206 has the same shape as the decomposable layer 203.
  • the hollow cavity 206 covers the gate metal layer 202, so that the gate metal layer 202 and the first The insulating layer 204 is separated.
  • the heating temperature is 230°C, and the heating time is 20-30 minutes.
  • the decomposable layer 203 is decomposed and deposited through the first insulating layer 204 to form the hollow cavity 206.
  • an active layer 207, a source and drain 208, and a passivation layer 209 are formed on the first insulating layer.
  • FIG. 3 is a schematic diagram of a specific process of an array substrate method provided by an embodiment of the application, as follows:
  • Fig. 4 is a preparation flow chart of the array substrate provided by the embodiment of the application:
  • a gate metal layer 402 is formed on the substrate 401.
  • the conductive material of the gate metal layer 402 is one or more of molybdenum aluminum alloy, molybdenum copper alloy, or copper-titanium alloy.
  • the gate metal layer 401 is coated with a layer of the decomposable material 203.
  • the decomposable material 403 is subjected to a yellowing process to obtain a decomposable layer 403.
  • the exposure amount of the yellow light manufacturing process is between 100-1000 millijoules.
  • the decomposable material 403 is subjected to the yellow light manufacturing process using a mask. There is a hollow area on the top, so that the decomposable material 403 forms the structure shown in FIG. 4c; at this time, the decomposable layer 403 covers the gate metal layer 402, and the area where the decomposable layer 403 covers the substrate 401 is made of yellow Light process peeling.
  • a first insulating layer 404 is formed on the substrate on which the decomposable layer 403 is formed, and the first insulating layer 404 covers the decomposable layer 403 and the substrate 401.
  • the material of the first insulating layer 404 includes silicon nitride (SiNx).
  • the substrate on which the first insulating layer 403 is formed is subjected to ultraviolet 405 treatment, and the exposure amount of the ultraviolet 405 is greater than or equal to 800 millijoules (mj).
  • the substrate 401 on which the first insulating layer is formed is heated.
  • the heating temperature is greater than or equal to 100°C.
  • a second insulating layer 4041 is formed on the first insulating layer 404.
  • the first insulating layer 404 includes the second insulating layer 4041.
  • the material of the second insulating layer includes silicon nitride (SiNx).
  • an active layer 407 is formed by depositing on the substrate 401 after the heat treatment.
  • the substrate 401 on which the active layer 407 is deposited is subjected to deposition, yellowing and etching processes to form a source and drain layer 408 and a passivation layer 409.
  • Figures 5a-5h are flow charts of the preparation of the array substrate provided by the embodiments of the application:
  • a gate metal layer 502 is formed on the substrate 501.
  • the conductive material of the gate metal layer 502 includes one or more of molybdenum aluminum alloy, molybdenum copper alloy, or copper-titanium alloy.
  • a layer of the decomposable material 503 is coated on the gate metal layer 501.
  • the decomposable material 503 is subjected to a yellowing process to obtain a decomposable layer 503.
  • the exposure amount of the yellow light process is between 100-1000 millijoules.
  • the decomposable material 503 is subjected to the yellow light process by using a mask. There is a hollow area on it, so that the decomposable material 503 forms a structure as shown in FIG. 5c, and the decomposable material 503 forms a decomposable layer 503 that includes the hollow area and partially covers the gate metal layer 501. During the yellowing process, the gate metal layer 502 is exposed.
  • a first insulating layer 504 is formed on the substrate on which the decomposable layer 503 is formed.
  • the first insulating layer 504 covers the decomposable layer 503.
  • the first insulating layer The layer 504 is connected to the gate metal layer 502.
  • the material of the first insulating layer 504 includes silicon nitride (SiNx).
  • the substrate on which the first insulating layer 503 is formed is subjected to ultraviolet 505 treatment, and the exposure of the ultraviolet 505 is greater than or equal to 800 millijoules (mj).
  • the substrate on which the first insulating layer 504 is formed is heated to form a hollow cavity 506, and there is a contact area between the first insulating layer 504 and the upper surface of the gate metal layer 502.
  • the hollow cavity 506 has a partially disconnected structure, so that the gate metal layer 502 is connected to the first insulating layer 504.
  • the heating temperature is greater than or equal to 100°C.
  • a second insulating layer 5041 is formed on the first insulating layer 504.
  • the first insulating layer 504 includes the second insulating layer 5041.
  • the material of the second insulating layer 5041 includes silicon nitride (SiNx).
  • the first insulating layer 504 includes a second insulating layer 5041.
  • a source layer 507 is formed by depositing on the substrate after the heat treatment.
  • the substrate on which the active layer 507 is deposited is subjected to deposition, yellowing, and etching processes to form a source and drain layer 508 and a passivation layer 509.
  • FIG. 6 is a side cross-sectional view of an array substrate provided by an embodiment of the application.
  • an array substrate is manufactured by any method for preparing an array substrate provided by an embodiment of the application.
  • the array substrate includes a substrate 601 And the gate metal layer 602 prepared above the substrate; and,
  • the intermediate insulating layer 604 is disposed above the gate metal layer 602, and a hollow cavity 606 is formed between the intermediate insulating layer 604 and the gate metal layer 602;
  • the source and drain layer 608 is disposed above the intermediate insulating layer 604.
  • an active layer 607 is further provided between the source drain layer 608 and the intermediate insulating layer 604.
  • a passivation layer 609 is also provided above the source and drain electrodes 608.
  • the array substrate provided by the embodiment of the present application is formed by the preparation method of the array substrate provided by the embodiment of the present invention as shown in FIG. 6, and a hollow cavity is formed between the intermediate insulating layer 604 and the gate metal layer 602
  • the chamber 606 avoids contact between the intermediate insulating layer and the gate metal layer, thereby avoiding the breakdown of the gate insulating layer and the diffusion of copper (Cu).
  • Fig. 7 is a side view of another array substrate provided by an embodiment of the application.
  • the array substrate is made by the method for preparing an array substrate provided by the embodiment of the present invention.
  • the array substrate includes a substrate 701 and a substrate 701 prepared above the substrate.
  • a gate metal layer 702; and an intermediate insulating layer 704 is disposed above the gate metal layer 702, and a hollow cavity 706 is formed between the intermediate insulating layer 704 and the gate metal layer 702;
  • the hollow cavity 706 has a partially disconnected structure, so that the intermediate insulating layer 703 and the gate metal layer 702 are connected.
  • the source and drain layer 708 is disposed above the intermediate insulating layer 704.
  • an active layer 707 is further provided between the source drain layer 708 and the intermediate insulating layer 704.
  • a passivation layer 709 is also provided above the source and drain electrodes 708.
  • the array substrate provided by the embodiment of the present application is similar to the array substrate provided in FIG. 6.
  • the hollow cavity 706 has a partially disconnected structure, and the upper surface of the intermediate insulating layer 704 and the gate metal layer 702 There is a contact area.
  • the purpose of the array substrate provided in this embodiment is: considering that the diffusion of metal copper (Cu) mainly occurs at the edge of the gate metal layer 702 and the intermediate insulating layer 704, the design of this structure is not only willing to give up the intermediate insulating layer 704 It is in contact with the gate metal layer 702.
  • the partially disconnected structure of the hollow chamber 706 due to the partially disconnected structure of the hollow chamber 706, the breakdown of the gate insulating film and the diffusion of conductive metal copper that originally occurred in the hollow chamber 706 area are also avoided. problem.
  • the method and device for manufacturing the array substrate may be applied to organic light-emitting diodes (Organic Light-Emitting Diode, referred to as OLED) Thin Film Transistor (TFT) technology development, or Quantum Dot Light Emitting Diodes (QLED) TFT technology development, or micro diode TFT technology development in.
  • OLED Organic Light-Emitting Diode
  • TFT Thin Film Transistor
  • QLED Quantum Dot Light Emitting Diodes
  • the beneficial effects are: the array substrate preparation method is adopted.
  • the array substrate structure effectively reduces the breakdown of the gate insulating film, effectively improves the conductive metal copper diffusion, electrostatic discharge and other problems, and improves the voltage retention rate.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un substrat de réseau et son procédé de préparation. Le procédé consiste à : former une couche métallique de grille sur un substrat de verre et former une couche décomposable, la couche décomposable ayant différentes températures de décomposition thermique avant et après exposition aux UV ; former une première couche isolante recouvrant la couche décomposable ; effectuer un traitement UV sur le substrat de verre ; chauffer le substrat de verre pour décomposer la couche décomposable ; former une cavité creuse entre la première couche isolante et la couche métallique de grille ; et former une électrode source et une électrode drain sur la première couche isolante.
PCT/CN2019/117677 2019-04-17 2019-11-12 Substrat de réseau et son procédé de préparation WO2020211349A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910307251.7A CN110137083B (zh) 2019-04-17 2019-04-17 阵列基板及其制备方法
CN201910307251.7 2019-04-17

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WO2020211349A1 true WO2020211349A1 (fr) 2020-10-22

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WO (1) WO2020211349A1 (fr)

Families Citing this family (3)

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Publication number Priority date Publication date Assignee Title
CN110137083B (zh) * 2019-04-17 2020-12-08 深圳市华星光电技术有限公司 阵列基板及其制备方法
CN111124176B (zh) * 2019-12-06 2023-10-13 深圳市华星光电半导体显示技术有限公司 一种触控面板制程方法及触控面板
CN111863903B (zh) * 2020-07-23 2023-04-18 武汉天马微电子有限公司 显示面板及其制作方法、显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7211520B2 (en) * 2004-02-27 2007-05-01 Infineon Technologies Ag Method for fabricating a field effect transistor
US20090227076A1 (en) * 2008-03-07 2009-09-10 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, manufacturing method thereof, display device, and manufacturing method thereof
TW201205810A (en) * 2010-06-21 2012-02-01 Imec Method of manufacturing thin film transistors and transistor circuits
CN110137083A (zh) * 2019-04-17 2019-08-16 深圳市华星光电技术有限公司 阵列基板及其制备方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007022509B4 (de) * 2007-05-14 2015-10-22 Robert Bosch Gmbh Mikromechanisches Bauteil mit Dünnschichtverkappung und Herstellungsverfahrung
US8633055B2 (en) * 2011-12-13 2014-01-21 International Business Machines Corporation Graphene field effect transistor
CN104362179B (zh) * 2014-10-13 2017-04-26 京东方科技集团股份有限公司 一种薄膜晶体管、其制作方法、阵列基板及显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7211520B2 (en) * 2004-02-27 2007-05-01 Infineon Technologies Ag Method for fabricating a field effect transistor
US20090227076A1 (en) * 2008-03-07 2009-09-10 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, manufacturing method thereof, display device, and manufacturing method thereof
TW201205810A (en) * 2010-06-21 2012-02-01 Imec Method of manufacturing thin film transistors and transistor circuits
CN110137083A (zh) * 2019-04-17 2019-08-16 深圳市华星光电技术有限公司 阵列基板及其制备方法

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