WO2020206880A1 - Procédé et dispositif de conception de plan de référence de condensateurs de blocage de courant continu - Google Patents

Procédé et dispositif de conception de plan de référence de condensateurs de blocage de courant continu Download PDF

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Publication number
WO2020206880A1
WO2020206880A1 PCT/CN2019/098500 CN2019098500W WO2020206880A1 WO 2020206880 A1 WO2020206880 A1 WO 2020206880A1 CN 2019098500 W CN2019098500 W CN 2019098500W WO 2020206880 A1 WO2020206880 A1 WO 2020206880A1
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WIPO (PCT)
Prior art keywords
blocking capacitor
pcb model
reference plane
rectangular hole
blocking
Prior art date
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PCT/CN2019/098500
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English (en)
Chinese (zh)
Inventor
解文军
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苏州浪潮智能科技有限公司
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Publication of WO2020206880A1 publication Critical patent/WO2020206880A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer

Definitions

  • the present invention relates to the field of PCIE links, and more specifically, to a method and device for designing a reference plane of a DC blocking capacitor.
  • PCIE interface links are widely used in servers. At present, PCIE3.0 with a rate of 8Gbps has been widely used, PCIE4.0 with a rate of 16Gbps has begun to be applied, and the PCIE5.0 protocol with a rate of 32Gbps is also being improved. As the speed increases, the signal integrity problem becomes more and more prominent. And impedance continuity is becoming more and more important as a key factor affecting signal integrity.
  • PCIE signal transmission generally uses differential wiring with an impedance of 85 Ohm. The entire transmission path is usually composed of multiple parts such as a DC blocking capacitor, a motherboard, a backplane, and a connector. Each part usually needs to maintain the same impedance, that is, 85 Ohm. As a part of the link, the DC blocking capacitor usually cannot maintain impedance continuity because the pad size is larger than the trace width.
  • the adjacent reference plane layer of the DC blocking capacitor is usually hollowed out directly below the capacitor pad, as shown in Figure 1.
  • the current practice has improved the problem of impedance continuity to a certain extent, but the degree of improvement is limited, and it is greatly affected by the plate and PCB stack.
  • the purpose of the embodiments of the present invention is to propose a wiring method in which the whole under a pair of DC blocking capacitors is hollowed out or the two capacitors are hollowed out separately to reduce the parasitic capacitance of the pad, thereby further improving the impedance.
  • one aspect of the embodiments of the present invention provides a method for designing a reference plane of DC blocking capacitors, which includes the following steps: constructing a PCB model; setting a pair of DC blocking capacitors in the PCB model to make the isolation between the pair of DC blocking capacitors
  • the DC capacitors are arranged side by side; the adjacent reference plane layer of the DC blocking capacitor pair of the PCB model is drilled so that the pad of each DC blocking capacitor pair is included in a rectangular hole, where the welding of the DC blocking capacitor pair
  • the discs are located at the corners of the rectangular holes.
  • the method further includes: performing impedance simulation or testing on the PCB model.
  • performing impedance simulation or testing on the PCB model includes: extracting S parameters of the PCB model, and performing impedance simulation or testing on the PCB model according to the S parameters.
  • the width of the rectangular hole is equal to the sum of the width of the two pads and the distance between the two pads along the side of the width of the rectangular hole.
  • the length of the rectangular hole is equal to the sum of the length of the two pads and the distance between the two pads along the side of the rectangular hole.
  • a method for designing a reference plane of a DC blocking capacitor including: constructing a PCB model; setting a pair of DC blocking capacitors in the PCB model so that the DC blocking capacitors in the pair of DC blocking capacitors are arranged side by side Arrangement; the adjacent reference plane layers of the DC blocking capacitor pair of the PCB model are respectively drilled so that the pad of each DC blocking capacitor is included in a rectangular hole, wherein the rectangular hole is the same width as the pad.
  • the method further includes: performing impedance simulation or testing on the PCB model.
  • performing impedance simulation or testing on the PCB model includes: extracting S parameters of the PCB model, and performing impedance simulation or testing on the PCB model according to the S parameters.
  • the length of each rectangular hole is equal to the sum of the length of the two pads and the distance between the two pads along the side of the rectangular hole.
  • the relative dielectric constant of the laminate of the PCB model is between 2.9 and 4.2.
  • the invention has the following beneficial technical effects: the parasitic capacitance of the pad can be reduced, thereby further improving the impedance continuity.
  • Figure 1 shows the wiring method of the existing DC blocking capacitor
  • Fig. 2 is an impedance simulation result diagram of the existing wiring method of the blocking capacitor
  • FIG. 3 is a schematic flowchart of an embodiment of a method for designing a reference plane of a DC blocking capacitor provided by the present invention
  • FIG. 4 is an embodiment of a reference plane of a DC blocking capacitor designed according to the method shown in FIG. 3;
  • FIG. 5 is a diagram of impedance simulation results of the embodiment shown in FIG. 4;
  • FIG. 6 is a schematic flowchart of an embodiment of another method for designing a reference plane of a DC blocking capacitor provided by the present invention.
  • FIG. 7 is an embodiment of a reference plane of a DC blocking capacitor designed according to the method shown in FIG. 6;
  • FIG. 8 is an impedance simulation result diagram of the embodiment shown in FIG. 7.
  • the PCIE link adopts the "end-to-end data transmission mode", and both the sending end and the receiving end contain TX (transmitting logic) and RX (receiving logic).
  • TX transmitting logic
  • RX receiving logic
  • a data path (Lane) of the physical link of the PCIE bus it is composed of two sets of differential signals, a total of 4 signal lines.
  • the TX part of the transmitting end and the RX part of the receiving end are connected by a set of differential signals.
  • This link is also called the transmitting link of the transmitting end and also the receiving link of the receiving end; the RX part of the transmitting end and the TX part of the receiving end use another Group differential signal connection, this link is also called the receiving link of the sending end, and also the sending link of the receiving end.
  • the electrical specifications for high-speed differential signals require a capacitor to be connected in series at the transmitting end for AC coupling.
  • An ideal coupling capacitor will completely filter out the DC component of the signal.
  • the capacitor has parasitic inductance.
  • the capacitor itself, the fan-out lead of the capacitor, and the layer-changing via are all impedance discontinuities. Impedance mismatch will bring reflection, affect the insertion loss (IL), return loss (RL), jitter (Jitter) and bit error rate (BER) of the entire link, and ultimately affect the performance of the entire link.
  • Figure 1 shows the wiring method of the existing DC blocking capacitor.
  • the existing wiring method of the DC blocking capacitor is to only hollow out the adjacent reference plane layer of the DC blocking capacitor directly below the capacitor pad, and no operation is performed in other places.
  • the simulation is performed, and the result obtained when the thickness of the medium is 2.5mil and the relative dielectric constant is 2.96 is shown in Figure 2.
  • the lowest impedance in Figure 2 is about 79.8ohm, which is 5.2ohm different from the 85ohm standard.
  • FIG. 3 shows a flowchart of an embodiment of a method for designing a reference plane of a DC blocking capacitor.
  • the embodiment of the present invention includes the following steps:
  • the PCB model may further include: performing impedance simulation or testing on the PCB model.
  • the S parameters of the PCB model can be extracted, and the PCB model can be subjected to impedance simulation or testing according to the S parameters.
  • FIG. 4 shows an embodiment of the reference plane of the DC blocking capacitor designed according to the method shown in FIG. 3.
  • the shape of the hole is rectangular, which just completely contains four pads, that is, the length of the rectangular hole is equal to the length of the two pads and the distance between the sides of the two pads along the length of the rectangular hole.
  • the width of the rectangular hole is equal to the sum of the width of the two pads and the distance between the two pads along the side of the width of the rectangular hole.
  • Fig. 5 shows the simulation result diagram of the above-mentioned embodiment.
  • the simulation result is also obtained when the thickness of the medium is 2.5 mils and the relative dielectric constant is 2.96.
  • the lowest impedance is about 84ohm, and the distance from 85ohm is only 1ohm, which greatly reduces the impedance fluctuation, that is, improves the continuity of impedance.
  • FIG. 6 shows a flowchart of an embodiment of another method for designing a reference plane of a DC blocking capacitor. As shown in FIG. 6, the embodiment of the present invention includes the following steps:
  • the PCB model may further include: performing impedance simulation or testing on the PCB model.
  • the S parameters of the PCB model can be extracted, and the PCB model can be subjected to impedance simulation or testing according to the S parameters.
  • the length of the rectangular hole is equal to the sum of the length of the two pads and the distance between the two pads along the side of the rectangular hole.
  • the relative dielectric constant of the laminate of the PCB model is between 2.9 and 4.2.
  • the number of laminated layers there is no restriction here.
  • FIG. 7 is an embodiment of the reference plane of the DC blocking capacitor designed according to the method shown in FIG. 6.
  • the hole includes two rectangular areas, and the two rectangular areas are of equal size. Of course, in other embodiments, the size may also be different.
  • the width of each rectangular hole is equal to the width of the pad, and the length of each rectangular hole is equal to the sum of the length of the two pads and the distance between the two pads along the side of the rectangular hole.
  • FIG. 8 shows the simulation result diagram of the above-mentioned embodiment.
  • the simulation result is also obtained when the thickness of the medium is 2.5 mils and the relative dielectric constant is 2.96.
  • the lowest impedance is about 81.2ohm, which is 3.8ohm different from 85ohm.
  • An embodiment of a computer device for designing a reference plane of a DC blocking capacitor.
  • An embodiment of a computer device includes: at least one processor; and a memory.
  • the memory stores computer instructions that can be run on the processor, and the instructions execute the above-mentioned method when run by the processor.
  • the above embodiment of the computer device for designing the reference plane of the DC blocking capacitor adopts the embodiment of the method for designing the reference plane of the DC blocking capacitor to specifically describe the working process of each module.
  • Those skilled in the art can easily think of , Apply these modules to other embodiments of the above-mentioned method for designing a reference plane of a DC blocking capacitor.
  • the various steps in the above method for designing the reference plane of the DC blocking capacitor can be crossed, replaced, added, or deleted. Therefore, these reasonable permutations and combinations should also belong to the above-mentioned device for building a parallel file system.
  • the protection scope of the present invention should not be limited to the above-mentioned embodiments.
  • all of the above-mentioned modules can be connected in communication.
  • the fourth aspect of the embodiments of the present invention proposes a computer-readable storage medium.
  • the computer-readable storage medium stores computer-executable instructions.
  • the computer-executable instructions can execute any of the foregoing method embodiments.
  • the foregoing embodiment of the computer-readable storage medium can achieve the same or similar effects as any of the foregoing corresponding method and device/system embodiments.
  • the devices, devices, etc. disclosed in the embodiments of the present invention can be various electronic terminal devices, such as mobile phones, personal digital assistants (PDA), tablet computers (PAD), smart TVs, etc., or large-scale terminal devices.
  • PDA personal digital assistants
  • PAD tablet computers
  • smart TVs etc.
  • large-scale terminal devices Such as servers, etc., therefore, the protection scope disclosed in the embodiments of the present invention should not be limited to a specific type of device or equipment.
  • the client disclosed in the embodiment of the present invention may be applied to any of the above electronic terminal devices in the form of electronic hardware, computer software, or a combination of both.
  • the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium.
  • the computer program executes the above-mentioned functions defined in the method disclosed in the embodiment of the present invention.
  • the above method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the above steps or unit functions.
  • non-volatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash Memory.
  • Volatile memory can include random access memory (RAM), which can act as external cache memory.
  • RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM).
  • DRAM synchronous RAM
  • DRAM dynamic RAM
  • SDRAM synchronous DRAM
  • DDR SDRAM double data rate SDRAM
  • ESDRAM enhanced SDRAM
  • SLDRAM Synchronous link DRAM
  • DRRAM direct Rambus RAM
  • the storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.
  • DSP digital signal processors
  • ASIC application-specific integrated circuits
  • FPGA Field Programmable Gate Array
  • a general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
  • the processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP, and/or any other such configuration.
  • the steps of the method or algorithm described in combination with the disclosure herein may be directly included in hardware, a software module executed by a processor, or a combination of the two.
  • the software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from or write information to the storage medium.
  • the storage medium may be integrated with the processor.
  • the processor and the storage medium may reside in the ASIC.
  • the ASIC can reside in the user terminal.
  • the processor and the storage medium may reside as discrete components in the user terminal.
  • functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted through the computer-readable medium.
  • Computer-readable media include computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another.
  • a storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.
  • the computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or may be used for carrying or storing instructions in the form of Or any other medium that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium.
  • coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave to send software from a website, server, or other remote source
  • coaxial cable Cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio, and microwave are all included in the definition of media.
  • magnetic disks and optical disks include compact disks (CD), laser disks, optical disks, digital versatile disks (DVD), floppy disks, blu-ray disks, where disks usually reproduce data magnetically, while optical disks use lasers to optically reproduce data .
  • CD compact disks
  • DVD digital versatile disks
  • floppy disks blu-ray disks
  • the program can be stored in a computer-readable storage medium.
  • the storage medium can be read-only memory, magnetic disk or optical disk, etc.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un procédé de conception d'un plan de référence de condensateurs de blocage de courant continu comprenant les étapes suivantes consistant : à construire un modèle de PCB ; à agencer des paires de condensateurs de blocage de courant continu dans le modèle de PCB, de telle sorte que les condensateurs de blocage de courant continu dans les paires de condensateurs de blocage de courant continu sont disposés côte à côte ; à faire des trous dans des couches de plan de référence adjacentes des paires de condensateurs de blocage de courant continu du modèle de PCB de telle sorte qu'un plot de chaque paire de condensateurs de blocage de courant continu est inclus dans un trou rectangulaire, les plots de paires de condensateurs de blocage de courant continu étant tous agencés au niveau d'un coin du trou rectangulaire. L'invention concerne en outre un autre procédé de conception du plan de référence de condensateurs de blocage de courant continu. Le procédé et le dispositif de conception du plan de référence de condensateurs de blocage de courant continu, grâce à différents procédés de câblage, peuvent améliorer la continuité d'impédance d'une liaison et les performances de l'ensemble de la liaison.
PCT/CN2019/098500 2019-04-10 2019-07-31 Procédé et dispositif de conception de plan de référence de condensateurs de blocage de courant continu WO2020206880A1 (fr)

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CN201910284075.XA CN109992917A (zh) 2019-04-10 2019-04-10 一种设计隔直电容参考平面的方法及装置
CN201910284075.X 2019-04-10

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CN113408093B (zh) * 2021-06-29 2022-04-29 西南交通大学 一种基于遗传算法的电容隔直装置配置优化方法

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CN101675519A (zh) * 2007-05-22 2010-03-17 国际商业机器公司 具有改善的传输线完整性与增加的布线密度的多层电路基板和方法
US20100326716A1 (en) * 2009-06-26 2010-12-30 Zhichao Zhang Core via for chip package and interconnect
CN103987191A (zh) * 2014-05-16 2014-08-13 浪潮电子信息产业股份有限公司 一种减小ac耦合电容pad对高速串行信号传输影响的方法
CN105323966A (zh) * 2015-09-24 2016-02-10 浪潮电子信息产业股份有限公司 一种优化电容与差分过孔互连时的阻抗连续性设计方法
CN106529077A (zh) * 2016-11-29 2017-03-22 郑州云海信息技术有限公司 一种ac耦合电容参考平面的仿真设计方法
CN107729280A (zh) * 2017-11-15 2018-02-23 无锡军安电子科技有限公司 一种高速差分信号端口阻抗与传输线阻抗一致性控制方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101675519A (zh) * 2007-05-22 2010-03-17 国际商业机器公司 具有改善的传输线完整性与增加的布线密度的多层电路基板和方法
US20100326716A1 (en) * 2009-06-26 2010-12-30 Zhichao Zhang Core via for chip package and interconnect
CN103987191A (zh) * 2014-05-16 2014-08-13 浪潮电子信息产业股份有限公司 一种减小ac耦合电容pad对高速串行信号传输影响的方法
CN105323966A (zh) * 2015-09-24 2016-02-10 浪潮电子信息产业股份有限公司 一种优化电容与差分过孔互连时的阻抗连续性设计方法
CN106529077A (zh) * 2016-11-29 2017-03-22 郑州云海信息技术有限公司 一种ac耦合电容参考平面的仿真设计方法
CN107729280A (zh) * 2017-11-15 2018-02-23 无锡军安电子科技有限公司 一种高速差分信号端口阻抗与传输线阻抗一致性控制方法

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