WO2020206880A1

WO2020206880A1 - Method and device for designing dc blocking capacitor reference plane

Info

Publication number: WO2020206880A1
Application number: PCT/CN2019/098500
Authority: WO
Inventors: 解文军
Original assignee: 苏州浪潮智能科技有限公司
Priority date: 2019-04-10
Filing date: 2019-07-31
Publication date: 2020-10-15
Also published as: CN109992917A

Abstract

A method for designing a DC blocking capacitor reference plane, comprising the following steps: constructing a PCB model; arranging DC blocking capacitor pairs in the PCB model, so that the DC blocking capacitors in the DC blocking capacitor pairs are arranged side by side; making holes in adjacent reference plane layers of the DC blocking capacitor pairs of the PCB model so that a pad of each DC blocking capacitor pair is included in a rectangular hole, wherein the pads of DC blocking capacitor pairs are all arranged at a corner of the rectangular hole. Further comprised is another method for designing the DC blocking capacitor reference plane. The method and device for designing the DC blocking capacitor reference plane, through different wiring methods, can improve the impedance continuity of a link and the performance of the whole link.

Description

Method and device for designing reference plane of DC blocking capacitor

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on April 10, 2019, the application number is 201910284075.X, and the invention title is "A method and device for designing a reference plane for DC blocking capacitors", and its entire contents Incorporated in this application by reference.

Technical field

The present invention relates to the field of PCIE links, and more specifically, to a method and device for designing a reference plane of a DC blocking capacitor.

Background technique

PCIE interface links are widely used in servers. At present, PCIE3.0 with a rate of 8Gbps has been widely used, PCIE4.0 with a rate of 16Gbps has begun to be applied, and the PCIE5.0 protocol with a rate of 32Gbps is also being improved. As the speed increases, the signal integrity problem becomes more and more prominent. And impedance continuity is becoming more and more important as a key factor affecting signal integrity. PCIE signal transmission generally uses differential wiring with an impedance of 85 Ohm. The entire transmission path is usually composed of multiple parts such as a DC blocking capacitor, a motherboard, a backplane, and a connector. Each part usually needs to maintain the same impedance, that is, 85 Ohm. As a part of the link, the DC blocking capacitor usually cannot maintain impedance continuity because the pad size is larger than the trace width.

In the current PCB PCIE traces, in order to maintain impedance continuity, the adjacent reference plane layer of the DC blocking capacitor is usually hollowed out directly below the capacitor pad, as shown in Figure 1. The current practice has improved the problem of impedance continuity to a certain extent, but the degree of improvement is limited, and it is greatly affected by the plate and PCB stack.

Summary of the invention

In view of this, the purpose of the embodiments of the present invention is to propose a wiring method in which the whole under a pair of DC blocking capacitors is hollowed out or the two capacitors are hollowed out separately to reduce the parasitic capacitance of the pad, thereby further improving the impedance. Continuity.

Based on the foregoing objectives, one aspect of the embodiments of the present invention provides a method for designing a reference plane of DC blocking capacitors, which includes the following steps: constructing a PCB model; setting a pair of DC blocking capacitors in the PCB model to make the isolation between the pair of DC blocking capacitors The DC capacitors are arranged side by side; the adjacent reference plane layer of the DC blocking capacitor pair of the PCB model is drilled so that the pad of each DC blocking capacitor pair is included in a rectangular hole, where the welding of the DC blocking capacitor pair The discs are located at the corners of the rectangular holes.

In some embodiments, the method further includes: performing impedance simulation or testing on the PCB model.

In some embodiments, performing impedance simulation or testing on the PCB model includes: extracting S parameters of the PCB model, and performing impedance simulation or testing on the PCB model according to the S parameters.

In some embodiments, the width of the rectangular hole is equal to the sum of the width of the two pads and the distance between the two pads along the side of the width of the rectangular hole.

In some embodiments, the length of the rectangular hole is equal to the sum of the length of the two pads and the distance between the two pads along the side of the rectangular hole.

In another aspect of the embodiments of the present invention, a method for designing a reference plane of a DC blocking capacitor is also provided, including: constructing a PCB model; setting a pair of DC blocking capacitors in the PCB model so that the DC blocking capacitors in the pair of DC blocking capacitors are arranged side by side Arrangement; the adjacent reference plane layers of the DC blocking capacitor pair of the PCB model are respectively drilled so that the pad of each DC blocking capacitor is included in a rectangular hole, wherein the rectangular hole is the same width as the pad.

In some embodiments, the length of each rectangular hole is equal to the sum of the length of the two pads and the distance between the two pads along the side of the rectangular hole.

In some embodiments, the relative dielectric constant of the laminate of the PCB model is between 2.9 and 4.2.

The invention has the following beneficial technical effects: the parasitic capacitance of the pad can be reduced, thereby further improving the impedance continuity.

Description of the drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other embodiments can be obtained according to the drawings without creative work.

Figure 1 shows the wiring method of the existing DC blocking capacitor;

Fig. 2 is an impedance simulation result diagram of the existing wiring method of the blocking capacitor;

3 is a schematic flowchart of an embodiment of a method for designing a reference plane of a DC blocking capacitor provided by the present invention;

FIG. 4 is an embodiment of a reference plane of a DC blocking capacitor designed according to the method shown in FIG. 3;

FIG. 5 is a diagram of impedance simulation results of the embodiment shown in FIG. 4;

6 is a schematic flowchart of an embodiment of another method for designing a reference plane of a DC blocking capacitor provided by the present invention;

FIG. 7 is an embodiment of a reference plane of a DC blocking capacitor designed according to the method shown in FIG. 6;

FIG. 8 is an impedance simulation result diagram of the embodiment shown in FIG. 7.

detailed description

In order to make the objectives, technical solutions, and advantages of the present invention clearer, the following describes the embodiments of the present invention in detail in conjunction with specific embodiments and with reference to the accompanying drawings.

It should be noted that all the expressions using "first" and "second" in the embodiments of the present invention are used to distinguish two entities with the same name but not the same or parameters that are not the same, as shown in "first" and "second" Only for the convenience of presentation, it should not be understood as a limitation to the embodiments of the present invention, and subsequent embodiments will not describe this one by one.

The PCIE link adopts the "end-to-end data transmission mode", and both the sending end and the receiving end contain TX (transmitting logic) and RX (receiving logic). In a data path (Lane) of the physical link of the PCIE bus, it is composed of two sets of differential signals, a total of 4 signal lines. The TX part of the transmitting end and the RX part of the receiving end are connected by a set of differential signals. This link is also called the transmitting link of the transmitting end and also the receiving link of the receiving end; the RX part of the transmitting end and the TX part of the receiving end use another Group differential signal connection, this link is also called the receiving link of the sending end, and also the sending link of the receiving end.

The electrical specifications for high-speed differential signals require a capacitor to be connected in series at the transmitting end for AC coupling. An ideal coupling capacitor will completely filter out the DC component of the signal. However, in actual circuit operation, the capacitor has parasitic inductance. The capacitor itself, the fan-out lead of the capacitor, and the layer-changing via are all impedance discontinuities. Impedance mismatch will bring reflection, affect the insertion loss (IL), return loss (RL), jitter (Jitter) and bit error rate (BER) of the entire link, and ultimately affect the performance of the entire link.

Figure 1 shows the wiring method of the existing DC blocking capacitor. As shown in Figure 1, the existing wiring method of the DC blocking capacitor is to only hollow out the adjacent reference plane layer of the DC blocking capacitor directly below the capacitor pad, and no operation is performed in other places. According to this wiring method, the simulation is performed, and the result obtained when the thickness of the medium is 2.5mil and the relative dielectric constant is 2.96 is shown in Figure 2. The lowest impedance in Figure 2 is about 79.8ohm, which is 5.2ohm different from the 85ohm standard.

Based on the foregoing objective, the first aspect of the embodiments of the present invention proposes an embodiment of a method for designing a reference plane of a DC blocking capacitor. FIG. 3 shows a flowchart of an embodiment of a method for designing a reference plane of a DC blocking capacitor. As shown in FIG. 3, the embodiment of the present invention includes the following steps:

S1, build PCB model;

S2. Set a pair of DC blocking capacitors in the PCB model, so that the DC blocking capacitors in the pair of DC blocking capacitors are arranged side by side;

S3. Drill holes for the adjacent reference plane layers of the DC blocking capacitor pairs of the PCB model so that the pads of each DC blocking capacitor pair are included in a rectangular hole, wherein The pads are all located at the corners of the rectangular hole.

After performing the above steps, it may further include: performing impedance simulation or testing on the PCB model. According to a preferred embodiment, the S parameters of the PCB model can be extracted, and the PCB model can be subjected to impedance simulation or testing according to the S parameters.

FIG. 4 shows an embodiment of the reference plane of the DC blocking capacitor designed according to the method shown in FIG. 3. As shown in Figure 4, the shape of the hole is rectangular, which just completely contains four pads, that is, the length of the rectangular hole is equal to the length of the two pads and the distance between the sides of the two pads along the length of the rectangular hole. The width of the rectangular hole is equal to the sum of the width of the two pads and the distance between the two pads along the side of the width of the rectangular hole.

Fig. 5 shows the simulation result diagram of the above-mentioned embodiment. The simulation result is also obtained when the thickness of the medium is 2.5 mils and the relative dielectric constant is 2.96. As shown in Figure 5, the lowest impedance is about 84ohm, and the distance from 85ohm is only 1ohm, which greatly reduces the impedance fluctuation, that is, improves the continuity of impedance.

In the second aspect of the embodiments of the present invention, an embodiment of another method for designing a reference plane of a DC blocking capacitor is proposed. FIG. 6 shows a flowchart of an embodiment of another method for designing a reference plane of a DC blocking capacitor. As shown in FIG. 6, the embodiment of the present invention includes the following steps:

Sa, build PCB model;

Sb. Setting a pair of DC blocking capacitors in the PCB model so that the DC blocking capacitors in the pair of DC blocking capacitors are arranged side by side;

Sc. Dig holes for the adjacent reference plane layers of the DC blocking capacitor pair of the PCB model so that the pad of each DC blocking capacitor is included in a rectangular hole, wherein the rectangular hole and the solder The disk is of equal width.

The length of the rectangular hole is equal to the sum of the length of the two pads and the distance between the two pads along the side of the rectangular hole.

According to a preferred embodiment, the relative dielectric constant of the laminate of the PCB model is between 2.9 and 4.2. As for the number of laminated layers, there is no restriction here.

FIG. 7 is an embodiment of the reference plane of the DC blocking capacitor designed according to the method shown in FIG. 6. As shown in FIG. 7, the hole includes two rectangular areas, and the two rectangular areas are of equal size. Of course, in other embodiments, the size may also be different. The width of each rectangular hole is equal to the width of the pad, and the length of each rectangular hole is equal to the sum of the length of the two pads and the distance between the two pads along the side of the rectangular hole.

FIG. 8 shows the simulation result diagram of the above-mentioned embodiment. The simulation result is also obtained when the thickness of the medium is 2.5 mils and the relative dielectric constant is 2.96. As shown in Figure 8, the lowest impedance is about 81.2ohm, which is 3.8ohm different from 85ohm. Although the continuity of impedance improvement in this embodiment is not as obvious as in the previous embodiment, it can still produce good technical effects compared to the prior art.

It should be particularly pointed out that the steps in the various embodiments of the above method for designing the reference plane of DC blocking capacitors can be crossed, replaced, added, or deleted. Therefore, these reasonable permutations and combinations are useful for designing DC blocking capacitors. The planar method should also belong to the protection scope of the present invention, and the protection scope of the present invention should not be limited to the embodiments.

Based on the foregoing objective, the third aspect of the embodiments of the present invention proposes an embodiment of a computer device for designing a reference plane of a DC blocking capacitor. An embodiment of a computer device includes: at least one processor; and a memory. The memory stores computer instructions that can be run on the processor, and the instructions execute the above-mentioned method when run by the processor.

It should be particularly pointed out that the above embodiment of the computer device for designing the reference plane of the DC blocking capacitor adopts the embodiment of the method for designing the reference plane of the DC blocking capacitor to specifically describe the working process of each module. Those skilled in the art can easily think of , Apply these modules to other embodiments of the above-mentioned method for designing a reference plane of a DC blocking capacitor. Of course, since the various steps in the above method for designing the reference plane of the DC blocking capacitor can be crossed, replaced, added, or deleted. Therefore, these reasonable permutations and combinations should also belong to the above-mentioned device for building a parallel file system. The protection scope of the present invention should not be limited to the above-mentioned embodiments. In addition, all of the above-mentioned modules can be connected in communication.

Based on the foregoing objective, the fourth aspect of the embodiments of the present invention proposes a computer-readable storage medium. The computer-readable storage medium stores computer-executable instructions. The computer-executable instructions can execute any of the foregoing method embodiments. The method for designing the reference plane of the DC blocking capacitor and the device/system for building a parallel file system in any of the above-mentioned device/system embodiments. The foregoing embodiment of the computer-readable storage medium can achieve the same or similar effects as any of the foregoing corresponding method and device/system embodiments.

Finally, it should be noted that those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by computer programs to instruct relevant hardware. The programs can be stored in a computer readable storage medium. When the program is executed, it may include the processes of the above-mentioned method embodiments. Among them, the storage medium can be a magnetic disk, an optical disc, a read-only memory (ROM) or a random access memory (RAM), etc. The foregoing computer program embodiment can achieve the same or similar effects as any of the foregoing corresponding method embodiments.

In addition, typically, the devices, devices, etc. disclosed in the embodiments of the present invention can be various electronic terminal devices, such as mobile phones, personal digital assistants (PDA), tablet computers (PAD), smart TVs, etc., or large-scale terminal devices. Such as servers, etc., therefore, the protection scope disclosed in the embodiments of the present invention should not be limited to a specific type of device or equipment. The client disclosed in the embodiment of the present invention may be applied to any of the above electronic terminal devices in the form of electronic hardware, computer software, or a combination of both.

In addition, the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. When the computer program is executed by the CPU, it executes the above-mentioned functions defined in the method disclosed in the embodiment of the present invention.

In addition, the above method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the above steps or unit functions.

In addition, it should be understood that the computer-readable storage medium (eg, memory) herein may be volatile memory or non-volatile memory, or may include both volatile memory and non-volatile memory. By way of example and not limitation, non-volatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash Memory. Volatile memory can include random access memory (RAM), which can act as external cache memory. As an example and not limitation, RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.

Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and functions have been described in general terms. Whether this function is implemented as software or hardware depends on specific applications and design constraints imposed on the entire system. Those skilled in the art can implement the functions in various ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosure of the embodiments of the present invention.

The various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure herein can be implemented or executed using the following components designed to perform the functions herein: general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP, and/or any other such configuration.

The steps of the method or algorithm described in combination with the disclosure herein may be directly included in hardware, a software module executed by a processor, or a combination of the two. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from or write information to the storage medium. In an alternative, the storage medium may be integrated with the processor. The processor and the storage medium may reside in the ASIC. The ASIC can reside in the user terminal. In an alternative, the processor and the storage medium may reside as discrete components in the user terminal.

In one or more exemplary designs, functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted through the computer-readable medium. Computer-readable media include computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. A storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, the computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or may be used for carrying or storing instructions in the form of Or any other medium that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if you use coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave to send software from a website, server, or other remote source, the above-mentioned coaxial cable Cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio, and microwave are all included in the definition of media. As used herein, magnetic disks and optical disks include compact disks (CD), laser disks, optical disks, digital versatile disks (DVD), floppy disks, blu-ray disks, where disks usually reproduce data magnetically, while optical disks use lasers to optically reproduce data . The combination of the above content should also be included in the scope of computer-readable media.

The above are exemplary embodiments disclosed by the present invention, but it should be noted that various changes and modifications can be made without departing from the scope of the disclosure of the embodiments of the present invention defined by the claims. The functions, steps and/or actions of the method claims according to the disclosed embodiments described herein do not need to be executed in any specific order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual forms, they may also be understood as plural unless explicitly limited to a singular number.

It should be understood that as used herein, unless the context clearly supports an exception, the singular form "a" is intended to also include the plural form. It should also be understood that the "and/or" used herein refers to any and all possible combinations including one or more items listed in association.

The serial numbers of the disclosed embodiments of the foregoing embodiments of the present invention are only for description, and do not represent the superiority of the embodiments.

A person of ordinary skill in the art can understand that all or part of the steps in the above embodiments can be implemented by hardware, or by a program to instruct relevant hardware to complete. The program can be stored in a computer-readable storage medium. The storage medium can be read-only memory, magnetic disk or optical disk, etc.

Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is only exemplary, and is not intended to imply that the scope of disclosure (including the claims) of the embodiments of the present invention is limited to these examples; under the idea of the embodiments of the present invention The above embodiments or the technical features in different embodiments can also be combined, and there are many other changes in different aspects of the above embodiments of the present invention, which are not provided in the details for brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

A method for designing a reference plane of a DC blocking capacitor, which is characterized in that it includes:

Build PCB model;

Setting a pair of DC blocking capacitors in the PCB model so that the DC blocking capacitors in the pair of DC blocking capacitors are arranged side by side;

Holes are drilled on the adjacent reference plane layer of the DC blocking capacitor pair of the PCB model so that the pads of each DC blocking capacitor pair are included in a rectangular hole. The pads are all located at the corners of the rectangular hole.
The method according to claim 1, further comprising: performing impedance simulation or testing on the PCB model.
The method according to claim 2, wherein performing impedance simulation or testing on the PCB model comprises: extracting S parameters of the PCB model, and performing impedance simulation or testing on the PCB model according to the S parameters.
The method according to claim 1, wherein the width of the rectangular hole is equal to the sum of the width of the two pads and the distance between the two pads along the side of the width of the rectangular hole.
The method according to claim 1, wherein the length of the rectangular hole is equal to the sum of the length of the two pads and the distance between the two pads along the side of the rectangular hole.
A method for designing a reference plane of a DC blocking capacitor, which is characterized in that it includes:

Build PCB model;

Setting a pair of DC blocking capacitors in the PCB model so that the DC blocking capacitors in the pair of DC blocking capacitors are arranged side by side;

The adjacent reference plane layers of the pair of DC blocking capacitors of the PCB model are respectively drilled so that the pad of each DC blocking capacitor is included in a rectangular hole, wherein the rectangular hole and the pad are similar width.
The method according to claim 6, further comprising: performing impedance simulation or testing on the PCB model.
The method according to claim 7, wherein performing impedance simulation or testing on the PCB model comprises: extracting S parameters of the PCB model, and performing impedance simulation or testing on the PCB model according to the S parameters.
8. The method according to claim 8, wherein the length of each rectangular hole is equal to the sum of the length of the two pads and the distance between the two pads along the side of the rectangular hole.
The method of claim 1, wherein the relative dielectric constant of the laminate of the PCB model is between 2.9 and 4.2.