CN109992917A - A kind of method and device designing capacitance reference planes - Google Patents
A kind of method and device designing capacitance reference planes Download PDFInfo
- Publication number
- CN109992917A CN109992917A CN201910284075.XA CN201910284075A CN109992917A CN 109992917 A CN109992917 A CN 109992917A CN 201910284075 A CN201910284075 A CN 201910284075A CN 109992917 A CN109992917 A CN 109992917A
- Authority
- CN
- China
- Prior art keywords
- capacitance
- pcb model
- rectangular opening
- pad
- pcb
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Architecture (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of method for designing capacitance reference planes, include the following steps: to construct PCB model；Capacitance pair is set in PCB model, the capacitance of capacitance centering is made to be arranged side by side；Borehole is carried out so that the pad of each capacitance pair is included in a rectangular opening to the neighboring reference plane layer of the capacitance pair of PCB model, wherein the pad of capacitance pair is respectively positioned on the corner of rectangular opening.The invention also discloses the methods of another design capacitance reference planes.The method and device of design capacitance reference planes proposed by the present invention can be improved the impedance continuity of link, promote the performance of entire link by different wiring methods.
Description
Technical field
The present invention relates to PCIE link fields, more specifically, particularly relating to a kind of side for designing capacitance reference planes
Method and device.
Background technique
PCIE interface link is widely used in server.Rate is that the PCIE3.0 of 8Gbps has been widely applied at present,
The PCIE4.0 of 16Gbps has begun application, and the PCIE5.0 agreement that rate is 32Gbps is also in improving.With mentioning for rate
Height, problems of Signal Integrity are more and more prominent.And impedance continuity is also increasingly heavier as signal integrity key factor is influenced
It wants.PCIE signal transmission generally uses the difference cabling of impedance 85Ohm, and entire transmission path is usually by capacitance, mainboard, back
The multi-sections such as plate and connector are grouped as, and various pieces usually require to keep identical impedance i.e. 85Ohm.Capacitance is as link
Middle a part usually cannot keep impedance continuity since pad size is bigger than trace width.
In the PCIE cabling of current PCB, in order to keep impedance continuity, usually to blocking immediately below capacitor pad
Capacitor neighboring reference plane layer hollows out, as shown in Figure 1.Current way improves asking for impedance continuity to a certain extent
Topic, but improved limitation, and be affected by plate and PCB lamination.
Summary of the invention
In view of this, the purpose of the embodiment of the present invention is that proposing that one kind is whole below a pair of of capacitance all hollows out
Or the wire laying mode hollowed out respectively immediately below two capacitors, the parasitic capacitance of pad is reduced, to further improve impedance
Continuity.
Based on above-mentioned purpose, the one side of the embodiment of the present invention provides a kind of side for designing capacitance reference planes
Method includes the following steps: to construct PCB model；Capacitance pair is set in PCB model, makes the blocking electricity of capacitance centering
Appearance is arranged side by side；Borehole is carried out to the neighboring reference plane layer of the capacitance pair of PCB model so that each capacitance pair
Pad is included in a rectangular opening, wherein the pad of capacitance pair is respectively positioned on the corner of rectangular opening.
In some embodiments, method further include: impedance emulation or test are carried out to PCB model.
In some embodiments, impedance emulation is carried out to PCB model or test includes: to extract the S parameter of PCB model,
Impedance emulation or test are carried out to PCB model according to S parameter.
In some embodiments, the width of rectangular opening be equal to two pads width and two pads along rectangular opening width
The sum of the spacing on the side where spending.
In some embodiments, the length of rectangular opening is equal to length of the length of two pads with two pads along rectangular opening
The sum of the spacing on the side where spending.
The another aspect of the embodiment of the present invention additionally provides a kind of method for designing capacitance reference planes, comprising: structure
Build PCB model；Capacitance pair is set in PCB model, the capacitance of capacitance centering is made to be arranged side by side；To PCB mould
The neighboring reference plane layer of the capacitance pair of type carries out borehole respectively so that the pad of each capacitance is included in one
In rectangular opening, wherein rectangular opening is wide with pad.
In some embodiments, method further include: impedance emulation or test are carried out to PCB model.
In some embodiments, impedance emulation is carried out to PCB model or test includes: to extract the S parameter of PCB model,
And impedance emulation or test are carried out to PCB model according to S parameter.
In some embodiments, the length of each rectangular opening is equal to the length of two pads and two pads along rectangular opening
Length where side spacing sum.
In some embodiments, the relative dielectric constant of the lamination of PCB model is between 2.9 to 4.2.
The present invention has following advantageous effects: the parasitic capacitance of pad can be reduced, to further improve impedance
Continuity.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Other embodiments are obtained according to these attached drawings.
Fig. 1 is the wire laying mode of existing capacitance；
Fig. 2 is the impedance simulation result diagram of the wire laying mode of existing capacitance；
Fig. 3 is the flow diagram of the embodiment of a method of design capacitance reference planes provided by the invention；
Fig. 4 is the embodiment of the capacitance reference planes of the design of the method according to Fig. 3；
Fig. 5 is the impedance simulation result diagram of embodiment shown in Fig. 4；
Fig. 6 is the process signal of the embodiment of another method of design capacitance reference planes provided by the invention
Figure；
Fig. 7 is the embodiment of the capacitance reference planes of the design of the method according to Fig. 6；
Fig. 8 is the impedance simulation result diagram of embodiment shown in Fig. 7.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
The embodiment of the present invention is further described in attached drawing.
It should be noted that all statements for using " first " and " second " are for differentiation two in the embodiment of the present invention
The non-equal entity of a same names or non-equal parameter, it is seen that " first " " second " only for the convenience of statement, does not answer
It is interpreted as the restriction to the embodiment of the present invention, subsequent embodiment no longer illustrates this one by one.
PCIE link uses " data mode end to end ", all contains TX (sending logic) in transmitting terminal and receiving end
With RX (receiving logic).In a data path (Lane) of the physical link of PCIE bus, by two groups of differential signals, totally 4
Root signal line group at.Wherein the TX component of transmitting terminal and the RX component of receiving end are connected using one group of differential signal, the link
The referred to as transmission link of transmitting terminal and the receives link of receiving end；And the RX component of transmitting terminal and the TX component of receiving end
It is connected using another group of differential signal, which is also referred to as the receives link of transmitting terminal and the transmission link of receiving end.
Its transmitting terminal of high-speed differential signal electrical specifications concatenates a capacitor, ideal to couple to carry out AC coupling
Capacitor can filter out completely the DC component of signal, but in the work of actual circuit, capacitor is to have existing for parasitic inductance,
Each capacitor itself, capacitor are fanned out to lead, and layer-exchange hole-through is all impedance discontinuity point.Impedance mismatch will bring reflection,
Insertion Loss (IL), return loss (RL), shake (Jitter) and the bit error rate (BER) for influencing entire link, finally influence entire link
Performance.
Shown in fig. 1 is the wire laying mode of existing capacitance.As shown in Figure 1, the wiring side of existing capacitance
Formula is only to hollow out immediately below capacitor pad to capacitance neighboring reference plane layer, elsewhere without behaviour
Make.It is emulated according to the wire laying mode, in the knot of medium obtained when being 2.96 with a thickness of 2.5mil, relative dielectric constant
Fruit is as shown in Figure 2.Lowest impedance is about 79.8ohm in Fig. 2, differs 5.2ohm with the standard of 85ohm.
Based on above-mentioned purpose, the first aspect of the embodiment of the present invention proposes a kind of design capacitance reference planes
Method embodiment.Fig. 3 shows the flow chart of the embodiment of a method of design capacitance reference planes, such as schemes
Shown in 3, the embodiment of the present invention includes following steps:
S1, building PCB model；
S2, capacitance pair is set in the PCB model, arranges the capacitance of the capacitance centering side by side
Column；
S3, borehole is carried out so that each capacitance to the neighboring reference plane layer of the capacitance pair of the PCB model
Pair pad be included in a rectangular opening, wherein the pad of the capacitance pair is respectively positioned on the turning of the rectangular opening
Place.
It can also include: that impedance emulation or test are carried out to PCB model after having carried out above-mentioned steps.According to preferred
Embodiment can extract the S parameter of PCB model, carry out impedance emulation or test to PCB model according to S parameter.
Fig. 4 shows the embodiment of the capacitance reference planes of method design according to Fig.3,.As shown in figure 4, hole
Shape be rectangle, just completely included four pads, that is to say rectangular opening length be equal to two pads length and two
The sum of the spacing on the side where length of a pad along rectangular opening, the width of rectangular opening is equal to the width of two pads and two are welded
The sum of the spacing on the side where width of the disk along rectangular opening.
Fig. 5 shows the simulation result diagram of above-described embodiment.Also in medium with a thickness of 2.5mil, opposite dielectric
Constant obtains the simulation result when being 2.96.As shown in figure 5, lowest impedance is about 84ohm, distance 85ohm only poor 1ohm, substantially
The fluctuation for reducing impedance that is to say the continuity for improving impedance.
The second aspect of the embodiment of the present invention proposes the implementation of the method for another design capacitance reference planes
Example.Fig. 6 shows the flow chart of the embodiment of another method of design capacitance reference planes, as shown in fig. 6, this hair
Bright embodiment includes the following steps:
Sa, building PCB model；
Sb, capacitance pair is set in the PCB model, arranges the capacitance of the capacitance centering side by side
Column；
Sc, borehole is carried out respectively so that each blocking to the neighboring reference plane layer of the capacitance pair of the PCB model
The pad of capacitor is included in a rectangular opening, wherein the rectangular opening and the pad are wide.
It can also include: that impedance emulation or test are carried out to PCB model after having carried out above-mentioned steps.According to preferred
Embodiment can extract the S parameter of PCB model, carry out impedance emulation or test to PCB model according to S parameter.
The length of rectangular opening is equal to the length and the spacing on the side where two length of the pad along rectangular opening of two pads
Sum.
According to preferred embodiment, the relative dielectric constant of the lamination of PCB model is between 2.9 to 4.2.As for lamination
The number of plies, this then with no restrictions.
Fig. 7 is the embodiment of the capacitance reference planes of the design of the method according to Fig. 6.As shown in fig. 7, hole includes two
A rectangular area, and two rectangular areas etc. are big, certainly, can not also wait in other examples big.Each rectangular opening
Width is equal to the width of pad, and the length of each rectangular opening is equal to length of the length of two pads with two pads along rectangular opening
The sum of the spacing on the side at place.
Fig. 8 shows the simulation result diagram of above-described embodiment.Also in medium with a thickness of 2.5mil, opposite dielectric
Constant obtains the simulation result when being 2.96.As shown in figure 8, lowest impedance is about 81.2ohm, 3.8ohm is differed with 85ohm.Though
The continuity that the not upper one embodiment of right the present embodiment promotes impedance is obvious, but compared with the prior art, still it can produce
Raw good technical effect.
It is important to note that each step in each embodiment of the method for above-mentioned design capacitance reference planes
Suddenly it can intersect, replace, increase, deleting, therefore, these reasonable permutation and combination transformation are joined in design capacitance
The method for examining plane should also be as belonging to the scope of protection of the present invention, and protection scope of the present invention should not be confined to embodiment
On.
Based on above-mentioned purpose, the third aspect of the embodiment of the present invention proposes a kind of design capacitance reference planes
Computer equipment embodiment.The embodiment of computer equipment includes: at least one processor；And memory, memory
It is stored with the computer instruction that can be run on a processor, instruction executes above-mentioned method when being run by processor.
It is important to note that the embodiment of the computer equipment of above-mentioned design capacitance reference planes is using upper
The embodiment of the method for design capacitance reference planes is stated to illustrate the course of work of each module, those skilled in the art
It can be it is readily conceivable that by the other embodiments of the method for these module applications to above-mentioned design capacitance reference planes.
Certainly, due to each step in the embodiment of the method for above-mentioned design capacitance reference planes can intersect, replace,
Increase, delete, therefore, these reasonable permutation and combination transformation should also be as belonging in the above-mentioned device for building parallel file system
Protection scope of the present invention, and protection scope of the present invention should not be confined on above-described embodiment.In addition, above-mentioned each
It can be communicated to connect between module.
Based on above-mentioned purpose, the 4th aspect of the embodiment of the present invention proposes a kind of computer readable storage medium, should
Computer-readable recording medium storage has computer executable instructions, which can be performed above-mentioned any means
Building in the method and the above-mentioned any device/system embodiment of realization of the design capacitance reference planes in embodiment is parallel
The device/system of file system.The embodiment of above-mentioned computer readable storage medium can achieve corresponding aforementioned any
The identical or similar effect of method and apparatus/system embodiment.
Finally, it should be noted that those of ordinary skill in the art will appreciate that realizing the whole in above-described embodiment method
Or part process, related hardware can be instructed to complete by computer program, it is computer-readable that program can be stored in one
In storage medium, the program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, storage medium can
For magnetic disk, CD, read-only memory (ROM) or random access memory (RAM) etc..The implementation of above-mentioned computer program
Example, can achieve the identical or similar effect of corresponding aforementioned any means embodiment.
In addition, typically, device disclosed by the embodiments of the present invention, equipment etc. can be various electric terminal equipments, such as hand
Machine, personal digital assistant (PDA), tablet computer (PAD), smart television etc., are also possible to large-scale terminal device, such as server
Deng, therefore protection scope disclosed by the embodiments of the present invention should not limit as certain certain types of device, equipment.The present invention is implemented
Client disclosed in example, which can be, is applied to any one of the above electricity with the combining form of electronic hardware, computer software or both
In sub- terminal device.
In addition, disclosed method is also implemented as the computer program executed by CPU according to embodiments of the present invention, it should
Computer program may be stored in a computer readable storage medium.When the computer program is executed by CPU, the present invention is executed
The above-mentioned function of being limited in method disclosed in embodiment.
In addition, above method step and system unit also can use controller and for storing so that controller is real
The computer readable storage medium of the computer program of existing above-mentioned steps or Elementary Function is realized.
In addition, it should be appreciated that the computer readable storage medium (for example, memory) of this paper can be volatibility and deposit
Reservoir or nonvolatile memory, or may include both volatile memory and nonvolatile memory.As an example and
Unrestricted, nonvolatile memory may include read-only memory (ROM), programming ROM (PROM), electrically programmable ROM
(EPROM), electrically erasable programmable ROM (EEPROM) or flash memory.Volatile memory may include that arbitrary access is deposited
Reservoir (RAM), the RAM can serve as external cache.As an example and not restrictive, RAM can be with a variety of
Form obtains, such as synchronous random access memory (DRAM), dynamic ram (DRAM), synchronous dram (SDRAM), double data rate SDRAM (DDR
SDRAM), enhance SDRAM (ESDRAM), synchronization link DRAM (SLDRAM) and directly Rambus RAM (DRRAM).Institute is public
The storage equipment for the aspect opened is intended to the memory of including but not limited to these and other suitable type.
Those skilled in the art will also understand is that, various illustrative logical blocks, mould in conjunction with described in disclosure herein
Block, circuit and algorithm steps may be implemented as the combination of electronic hardware, computer software or both.It is hard in order to clearly demonstrate
This interchangeability of part and software, with regard to various exemplary components, square, module, circuit and step function to its into
General description is gone.This function is implemented as software and is also implemented as hardware depending on concrete application and application
To the design constraint of whole system.The function that those skilled in the art can realize in various ways for every kind of concrete application
Can, but this realization decision should not be interpreted as causing a departure from range disclosed by the embodiments of the present invention.
Various illustrative logical blocks, module and circuit, which can use, in conjunction with described in disclosure herein is designed to
The following component of function here is executed to realize or execute: general processor, digital signal processor (DSP), dedicated integrated electricity
It is road (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete
Any combination of hardware component or these components.General processor can be microprocessor, but alternatively, processor can
To be any conventional processors, controller, microcontroller or state machine.Processor also may be implemented as calculating the group of equipment
Close, for example, the combination of DSP and microprocessor, multi-microprocessor, one or more microprocessors combination DSP and/or it is any its
Its this configuration.
The step of method in conjunction with described in disclosure herein or algorithm, can be directly contained in hardware, be held by processor
In capable software module or in combination of the two.Software module may reside within RAM memory, flash memory, ROM storage
Device, eprom memory, eeprom memory, register, hard disk, removable disk, CD-ROM or known in the art it is any its
In the storage medium of its form.Illustrative storage medium is coupled to processor, enables a processor to from the storage medium
Information is written to the storage medium in middle reading information.In an alternative, storage medium can be integral to the processor
Together.Pocessor and storage media may reside in ASIC.ASIC may reside in user terminal.In an alternative
In, it is resident in the user terminal that pocessor and storage media can be used as discrete assembly.
In one or more exemplary designs, function can be realized in hardware, software, firmware or any combination thereof.
If realized in software, can using function as one or more instruction or code may be stored on the computer-readable medium or
It is transmitted by computer-readable medium.Computer-readable medium includes computer storage media and communication media, which is situated between
Matter includes any medium for helping for computer program to be transmitted to another position from a position.Storage medium can be energy
Any usable medium being enough accessed by a general purpose or special purpose computer.As an example and not restrictive, the computer-readable medium
It may include that RAM, ROM, EEPROM, CD-ROM or other optical disc memory apparatus, disk storage equipment or other magnetic storages are set
It is standby, or can be used for carrying or storage form be instruct or the required program code of data structure and can by general or
Special purpose computer or any other medium of general or specialized processor access.In addition, any connection can suitably claim
For computer-readable medium.For example, if using coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or all
It is if the wireless technology of infrared ray, radio and microwave to send software from website, server or other remote sources, then above-mentioned coaxial
Cable, fiber optic cable, twisted pair, DSL or such as wireless technology of infrared ray, radio and microwave are included in determining for medium
Justice.As used herein, disk and CD include compact disk (CD), it is laser disk, CD, digital versatile disc (DVD), soft
Disk, Blu-ray disc, wherein disk usually magnetically reproduce data, and CD using laser optics reproduce data.Above content
Combination should also be as being included in the range of computer-readable medium.
It is exemplary embodiment disclosed by the invention above, it should be noted that in the sheet limited without departing substantially from claim
Under the premise of inventive embodiments scope of disclosure, it may be many modifications and modify.According to open embodiment described herein
The function of claim to a method, step and/or movement be not required to the execution of any particular order.In addition, although the present invention is implemented
Element disclosed in example can be described or be required in the form of individual, but be unless explicitly limited odd number, it is understood that be multiple.
It should be understood that it is used in the present context, unless the context clearly supports exceptions, singular " one
It is a " it is intended to also include plural form.It is to be further understood that "and/or" used herein refers to including one or one
Any and all possible combinations of a above project listed in association.
It is for illustration only that the embodiments of the present invention disclose embodiment sequence number, does not represent the advantages or disadvantages of the embodiments.
Those of ordinary skill in the art will appreciate that realizing that all or part of the steps of above-described embodiment can pass through hardware
Complete, relevant hardware can also be instructed to complete by program, program can store in a kind of computer-readable storage
In medium, storage medium mentioned above can be read-only memory, disk or CD etc..
It should be understood by those ordinary skilled in the art that: the discussion of any of the above embodiment is exemplary only, not
It is intended to imply that range disclosed by the embodiments of the present invention (including claim) is limited to these examples；In the think of of the embodiment of the present invention
Under road, it can also be combined between the technical characteristic in above embodiments or different embodiments, and there is this hair as above
Many other variations of the different aspect of bright embodiment, for simplicity, they are not provided in details.Therefore, all in the present invention
Within the spirit and principle of embodiment, any omission, modification, equivalent replacement, improvement for being made etc. be should be included in of the invention real
It applies within the protection scope of example.
Claims (10)
1. a kind of method for designing capacitance reference planes characterized by comprising
Construct PCB model；
Capacitance pair is set in the PCB model, the capacitance of the capacitance centering is made to be arranged side by side；
Borehole is carried out to the neighboring reference plane layer of the capacitance pair of the PCB model so that each capacitance pair
Pad is included in a rectangular opening, wherein the pad of the capacitance pair is respectively positioned on the corner of the rectangular opening.
2. the method according to claim 1, wherein further include: impedance emulation or survey are carried out to the PCB model
Examination.
3. according to the method described in claim 2, it is characterized in that, including: to PCB model progress impedance emulation or test
The S parameter of the PCB model is extracted, and impedance emulation or test are carried out to PCB model according to the S parameter.
4. the method according to claim 1, wherein the width of the rectangular opening be equal to two pads width with
The sum of the spacing on the side where two width of the pad along rectangular opening.
5. the method according to claim 1, wherein the length of the rectangular opening be equal to two pads length with
The sum of the spacing on the side where two length of the pad along rectangular opening.
6. a kind of method for designing capacitance reference planes characterized by comprising
Construct PCB model；
Capacitance pair is set in the PCB model, the capacitance of the capacitance centering is made to be arranged side by side；
Borehole is carried out respectively to the neighboring reference plane layer of the capacitance pair of the PCB model so that each capacitance weldering
Disk is included in a rectangular opening, wherein the rectangular opening and the pad are wide.
7. according to the method described in claim 6, it is characterized by further comprising: carrying out impedance emulation or survey to the PCB model
Examination.
8. the method according to the description of claim 7 is characterized in that including: to PCB model progress impedance emulation or test
The S parameter of the PCB model is extracted, and impedance emulation or test are carried out to PCB model according to the S parameter.
9. according to the method described in claim 8, it is characterized in that, the length of each rectangular opening be equal to two pads length with
The sum of the spacing on the side where two length of the pad along rectangular opening.
10. the method according to claim 1, wherein the relative dielectric constant of the lamination of the PCB model exists
Between 2.9 to 4.2.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910284075.XA CN109992917A (en) | 2019-04-10 | 2019-04-10 | A kind of method and device designing capacitance reference planes |
| PCT/CN2019/098500 WO2020206880A1 (en) | 2019-04-10 | 2019-07-31 | Method and device for designing dc blocking capacitor reference plane |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910284075.XA CN109992917A (en) | 2019-04-10 | 2019-04-10 | A kind of method and device designing capacitance reference planes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109992917A true CN109992917A (en) | 2019-07-09 |
Family
ID=67132854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910284075.XA Pending CN109992917A (en) | 2019-04-10 | 2019-04-10 | A kind of method and device designing capacitance reference planes |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109992917A (en) |
| WO (1) | WO2020206880A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113408093A (en) * | 2021-06-29 | 2021-09-17 | 西南交通大学 | Capacitive blocking device configuration optimization method based on genetic algorithm |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101675519A (en) * | 2007-05-22 | 2010-03-17 | 国际商业机器公司 | Multi-layer circuit substrate and method having improved transmission line integrity and increased routing density |
| US20100326716A1 (en) * | 2009-06-26 | 2010-12-30 | Zhichao Zhang | Core via for chip package and interconnect |
| CN103987191A (en) * | 2014-05-16 | 2014-08-13 | 浪潮电子信息产业股份有限公司 | Method for reducing influence of AC coupling capacitor PAD on transmission of high-speed serial signals |
| CN106529077A (en) * | 2016-11-29 | 2017-03-22 | 郑州云海信息技术有限公司 | Simulation design method for AC coupling capacitor reference plane |
| CN107729280A (en) * | 2017-11-15 | 2018-02-23 | 无锡军安电子科技有限公司 | A kind of high-speed differential signal port Impedance and transmission line impedance uniformity control method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105323966A (en) * | 2015-09-24 | 2016-02-10 | 浪潮电子信息产业股份有限公司 | Design method for optimizing impedance continuity in interconnection of capacitors and differential through holes |
-
2019
- 2019-04-10 CN CN201910284075.XA patent/CN109992917A/en active Pending
- 2019-07-31 WO PCT/CN2019/098500 patent/WO2020206880A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101675519A (en) * | 2007-05-22 | 2010-03-17 | 国际商业机器公司 | Multi-layer circuit substrate and method having improved transmission line integrity and increased routing density |
| US20100326716A1 (en) * | 2009-06-26 | 2010-12-30 | Zhichao Zhang | Core via for chip package and interconnect |
| CN103987191A (en) * | 2014-05-16 | 2014-08-13 | 浪潮电子信息产业股份有限公司 | Method for reducing influence of AC coupling capacitor PAD on transmission of high-speed serial signals |
| CN106529077A (en) * | 2016-11-29 | 2017-03-22 | 郑州云海信息技术有限公司 | Simulation design method for AC coupling capacitor reference plane |
| CN107729280A (en) * | 2017-11-15 | 2018-02-23 | 无锡军安电子科技有限公司 | A kind of high-speed differential signal port Impedance and transmission line impedance uniformity control method |
Non-Patent Citations (1)
| Title |
|---|
| QW5588816QW: "AC耦合电容pad优化分析（精品）", 《道客巴巴在线公开：HTTPS://WWW.DOC88.COM/P-4334416571350.HTML》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113408093A (en) * | 2021-06-29 | 2021-09-17 | 西南交通大学 | Capacitive blocking device configuration optimization method based on genetic algorithm |
| CN113408093B (en) * | 2021-06-29 | 2022-04-29 | 西南交通大学 | Capacitive blocking device configuration optimization method based on genetic algorithm |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020206880A1 (en) | 2020-10-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107423387A (en) | The method and apparatus of table is divided in a kind of point storehouse based on middleware | |
| US11126776B2 (en) | Coherent placement of slotline mode suppression structures in coplanar waveguides for quantum devices | |
| US20100122011A1 (en) | Method and Apparatus for Supporting Multiple High Bandwidth I/O Controllers on a Single Chip | |
| CN102780574B (en) | The collocation method of the office data of service-oriented, device and check method, device | |
| CN102147726B (en) | Script-based method for implementing service configuration | |
| CN109992917A (en) | A kind of method and device designing capacitance reference planes | |
| CN102739320A (en) | Method, system and device for transmitting audio data and electronic signature tool | |
| CN105930178B (en) | A kind of configurable dynamic state of parameters stowage and system | |
| CN115116530A (en) | Method, device and equipment for processing check pin of memory and storage medium | |
| US11189980B2 (en) | Optimization analysis method and system for high-speed signal connector | |
| CN110413354A (en) | It is a kind of to realize the method, equipment and storage medium interacted with third-party platform | |
| CN109800199A (en) | A kind of method and device based on M.2 connector extension SATA hard disc | |
| CN108874714A (en) | A kind of secure communication device based on chip | |
| CN109561032A (en) | A kind of switch module and the interchanger including it | |
| CN107911427A (en) | A kind of cluster control method and device based on ICE middlewares | |
| US11120189B2 (en) | Single-ended-mode to mixed-mode transformer spice circuit model for high-speed system signal integrity simulations | |
| US10360970B1 (en) | Standing and resonant wave clocking in DDR RCD and data buffer | |
| Packianathan et al. | Performance analysis of microstriplines interconnect structure with novel guard trace as parallel links for high speed dram interfaces | |
| CN110266546A (en) | A kind of method, equipment and readable medium configuring switch port | |
| Wilson et al. | Active crosstalk cancellation for next-generation single-ended memory interfaces | |
| Stumpf | Time-Domain Electromagnetic Reciprocity in Antenna Modeling | |
| CN103470248B (en) | The collocation method of signal the spread of the rumours cable transmission channel balanced device | |
| Bland | Directional coupling and its use for memory noise reduction | |
| Lü | Existence and multiplicity results for critical growth polyharmonic elliptic systems | |
| Singamsetty et al. | EMI Control of GDDR6 Design with Drive strength control and On-Die Termination Methods |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190709 |