WO2020206752A1 - 一种阵列基板及其制作方法、以及显示面板 - Google Patents

一种阵列基板及其制作方法、以及显示面板 Download PDF

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Publication number
WO2020206752A1
WO2020206752A1 PCT/CN2019/084260 CN2019084260W WO2020206752A1 WO 2020206752 A1 WO2020206752 A1 WO 2020206752A1 CN 2019084260 W CN2019084260 W CN 2019084260W WO 2020206752 A1 WO2020206752 A1 WO 2020206752A1
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Prior art keywords
fan
area
display area
wires
substrate
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PCT/CN2019/084260
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English (en)
French (fr)
Inventor
胡建平
杨文萍
Original Assignee
深圳市华星光电技术有限公司
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Publication of WO2020206752A1 publication Critical patent/WO2020206752A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a manufacturing method thereof, and a display panel.
  • an "inverted V-shaped" pattern is adopted at the junction of the "fan-shaped” pattern and the "fan-shaped” pattern in the fan-out area.
  • the display area of the array substrate is too close to the fan-out area.
  • the diffusion of the alignment liquid at the edge of the display area is blocked by the "inverted V-shaped" pattern of the fan-out area, which causes the alignment liquid to accumulate at the edge of the display area, causing uneven brightness at the edge of the display area, affecting the display panel Quality.
  • the purpose of the present application is to provide an array substrate, a manufacturing method thereof, and a display panel, by redesigning the "inverted V-shaped" pattern of the fan-out area in the existing design to avoid alignment due to the "inverted V-shaped” pattern
  • the embodiments of the present application provide an array substrate, the array substrate includes: a base, the base includes a display area, a fan-out area, and a binding area connected in sequence; a plurality of wires, the plurality of wires are arranged on the base body On the upper side, and a plurality of spaced gathering patterns are formed in the fan-out area.
  • the wires in the gathering patterns extend from the connection between the display area and the fan-out area to the binding area, and the longer the extending distance, the greater the distance between each other. Small; multiple diversion lines, multiple diversion lines are arranged between two adjacent gathering patterns, and extend to the direction away from the display area.
  • a plurality of diversion lines are arranged axially symmetrically, and the diversion line at the symmetry axis is perpendicular to the contact boundary between the display area and the fan-out area.
  • the angle between the diversion lines on both sides of the symmetry axis and the contact boundary is less than 90 degrees.
  • a plurality of diversion lines are arranged in parallel and spaced apart and perpendicular to the contact boundary between the display area and the fan-out area.
  • the extension path of the diversion line is a straight line or a curve.
  • the material of the diversion wire is different from the material of the wire.
  • an embodiment of the present application also provides a manufacturing method of an array substrate.
  • the method includes: providing a base, the base including a display area, a fan-out area, and a binding area connected in sequence; and forming a plurality of strips on the base.
  • Conductors and a plurality of diversion lines wherein the plurality of conductors form a plurality of gathered patterns arranged at intervals in the fan-out area, and the conductors in the gathered pattern extend from the connection between the display area and the fan-out area to the binding area, and extend The longer the distance, the smaller the interval between each other, and the multiple diversion lines are located between two adjacent gathering patterns and extend away from the display area.
  • the step of forming a plurality of wires and a plurality of guide wires on the substrate specifically includes: using a first mask to form a plurality of wires on the substrate; forming an insulating layer on the wires; and using a second mask, A plurality of guide wires are formed on the insulating layer.
  • the step of forming a plurality of wires and a plurality of guide wires on the substrate specifically includes: forming a plurality of wires and a plurality of guide wires on the substrate, and forming pixels on the array substrate on the display area, and the pixels are connected to the wires .
  • a plurality of diversion lines are arranged axially symmetrically, and the diversion line at the symmetry axis is perpendicular to the contact boundary between the display area and the fan-out area.
  • the angle between the diversion lines on both sides of the symmetry axis and the contact boundary is less than 90 degrees.
  • a plurality of diversion lines are arranged in parallel and spaced apart and perpendicular to the contact boundary between the display area and the fan-out area.
  • the extension path of the diversion line is a straight line or a curve.
  • the material of the diversion wire is different from the material of the wire.
  • embodiments of the present application also provide a display panel, the display panel comprising: a first substrate, a second substrate, and a liquid crystal layer, the liquid crystal layer is located between the first substrate and the second substrate;
  • a substrate and/or a second substrate include: a base, the base includes a display area, a fan-out area, and a binding area that are sequentially connected; a plurality of wires, the plurality of wires are arranged on the base, and a plurality of spaces are formed in the fan-out area Set the gathering pattern, the wires in the gathering pattern extend from the connection between the display area and the fan-out area to the binding area, and the longer the extension distance, the smaller the distance between each other; multiple diversion lines, multiple guides
  • the streamline is arranged between two adjacent gathering patterns and extends in a direction away from the display area.
  • a plurality of diversion lines are arranged axially symmetrically, and the diversion line at the symmetry axis is perpendicular to the contact boundary between the display area and the fan-out area.
  • the angle between the diversion lines on both sides of the symmetry axis and the contact boundary is less than 90 degrees.
  • a plurality of diversion lines are arranged in parallel and spaced apart and perpendicular to the contact boundary between the display area and the fan-out area.
  • the extension path of the diversion line is a straight line or a curve.
  • the material of the diversion wire is different from the material of the wire.
  • the array substrate provided by the present application includes a base, a plurality of wires, and a plurality of flow lines, wherein the base includes a display area and a fan-out area connected in sequence , And the binding area, a plurality of wires are arranged on the substrate, and a plurality of spaced gathering patterns are formed in the fan-out area, and the wires in the gathering patterns extend from the connection between the display area and the fan-out area to the binding area, and The longer the extension, the smaller the distance between each other. Multiple diversion lines are arranged between two adjacent gathering patterns and extend away from the display area.
  • the original "inverted V-shaped" pattern design can avoid the problem of uneven brightness at the edge of the display area caused by the "inverted V-shaped” pattern blocking the diffusion of the alignment liquid, thereby improving the quality of the display panel.
  • FIG. 1 is a schematic diagram of the structure of an array substrate provided by the prior art
  • FIG. 2 is a schematic diagram of the structure of an array substrate provided by an embodiment of the present application.
  • FIG. 3 is another schematic diagram of the structure of the array substrate provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of another structure of an array substrate provided by an embodiment of the present application.
  • FIG. 5 is another schematic diagram of the structure of the array substrate provided by the embodiment of the present application.
  • FIG. 6 is a schematic flowchart of a manufacturing method of an array substrate provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by the prior art.
  • the array substrate 10 includes a display area A, a fan-out area B, and a binding area C that are sequentially connected.
  • the "fan-shaped" pattern 111 and the "fan-shaped” pattern in the fan-out area B The 111 junction adopts the "inverted V-shaped" pattern 112.
  • the diffusion of the alignment liquid at the edge of the display area A is blocked by the "inverted V-shaped" pattern 112 in the fan-out area B, which causes the alignment liquid to accumulate at the edge of the display area A, and the edge brightness of the display area A appears.
  • the unevenness affects the quality of the display panel 10.
  • this application uses multiple diversion line designs to replace the original "inverted V-shaped" pattern design, which can avoid the brightness at the edge of the display area due to the "inverted V-shaped” pattern blocking the diffusion of the alignment liquid.
  • the unevenness problem further improves the quality of the display panel.
  • FIG. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • the array substrate 20 includes a base 21, a plurality of wires 22, and a plurality of guide wires 23, wherein the base 21 includes a display area A, a fan-out area B, and a binding area C that are sequentially connected.
  • the wires 22 are arranged on the substrate 21, and a plurality of gathering patterns 22B are formed at intervals in the fan-out area B.
  • the wires 22 in the gathering patterns 22B extend from the connection between the display area A and the fan-out area B to the binding area C , And the longer the extending distance, the smaller the distance between each other.
  • a plurality of guide wires 23 are arranged between two adjacent gathering patterns 22B and extend in a direction away from the display area A.
  • the base 21 may be a glass substrate or a hard resin substrate, and may also be a flexible substrate for preparing a flexible array substrate.
  • the material of the wire 22 may be a material with low resistivity such as aluminum, copper, or silver.
  • the material of the guide wire 23 may be the same as or different from the material of the wire 22, and the material of the guide wire 23 may be conductive materials such as aluminum, copper, and silver, or insulating materials such as epoxy resin and acrylic resin.
  • the array substrate 20 further includes pixels (not shown in the figure) arranged in the display area A, and the pixels include thin film transistors and organic light emitting devices arranged on the substrate 21 in sequence.
  • the wires 22 are arranged in parallel and spaced along the row direction or the column direction in the display area A, and are electrically connected to the pixels.
  • the wire 22 After the wire 22 extends from the display area A to the junction of the display area A and the fan-out area B, it is divided into several wire groups and continues to extend from the junction of the display area A and the fan-out area B to the binding area C, and The closer to the binding area C, the smaller the distance between the wires 22 and the wires 22 in the wire group, so as to form a plurality of gathering patterns 22B in the fan-out area B.
  • the wire 22 can continue to extend in the binding area C and interface with the driver located in the binding area C (not shown in the figure) Connected to transmit driving signals to the pixels. In this way, after the wires 22 are gathered in the fan-out area B, and then connected to the driver interface of the binding area C, the space occupied by the driver can be reduced, and the driving signal of the input wire 22 can be better controlled.
  • a plurality of guide lines 23 are provided in the area between two adjacent gathering patterns 22B.
  • a plurality of guide wires 23 are arranged in parallel and spaced apart and perpendicular to the contact boundary of the display area A and the fan-out area B, so as to facilitate the diffusion of the alignment liquid at the edge of the display area A in the subsequent alignment film manufacturing process.
  • the distribution density of the guide wire 23 in the area between two adjacent gathering patterns 22B is the same as the distribution density of the wires 22 in the gathering pattern 22B or can meet the requirement of pattern density consistency in the fan-out area B. Further, as shown in FIG. 3, after the wires 22 in the gathering pattern 22B extend to the junction between the binding area C and the fan-out area B, they can continue to extend in the binding area C to form a rectangular pattern 22C correspondingly.
  • An "inverted V-shaped" pattern 24 may be formed between two adjacent rectangular patterns 22C to ensure the consistency of the pattern density of the binding area C.
  • a plurality of guide wires 23 are arranged axially symmetrically, and the guide wires 23 at the symmetry axis Z are perpendicular to the boundary of the display area A.
  • the angle between the diversion wires 23 on both sides of the symmetry axis Z and the boundary of the display area A is less than 90 degrees.
  • the plurality of diversion wires 23 in FIG. 4 are arranged in a tree shape, which facilitates subsequent alignment. The alignment liquid diffuses at the edge of the display area A during the film manufacturing process.
  • the extension path of the guide wire 23 in the fan-out area B may be a straight line or a curve.
  • the guide wire 23 and the wire 22 may be arranged in the same layer or not in the same layer.
  • the wire 22 is arranged on the base 21, an insulating layer (not shown) is arranged on the wire 22, the insulating layer covers the wire 22 and its surrounding area, and the guide wire 23 is arranged on the insulating layer.
  • the array substrate in this embodiment adopts multiple diversion line designs in the fan-out area to replace the original "inverted V-shaped" pattern design, which can avoid the impact of the "inverted V-shaped” pattern on the alignment liquid.
  • FIG. 6 is a schematic flowchart of a manufacturing method of an array substrate provided by an embodiment of the present application.
  • the manufacturing method of the array substrate includes the following steps:
  • S61 Provide a substrate, which includes a display area, a fan-out area, and a binding area connected in sequence.
  • the substrate may be a glass substrate or a rigid resin substrate, or may be a flexible substrate used to prepare a flexible array substrate.
  • a plurality of wires and a plurality of diversion wires are formed on the substrate, wherein the plurality of wires form a plurality of gathered patterns arranged at intervals in the fan-out area, and the wires in the gathered pattern are directed from the connection between the display area and the fan-out area.
  • the binding area extends, and the longer the extending distance, the smaller the distance between each other.
  • a plurality of guide lines are located between two adjacent gathering patterns and extend away from the display area.
  • the material of the wire may be a material with low resistivity such as aluminum, copper, silver, etc.
  • the material of the guide wire can be the same as or different from the material of the wire.
  • the material of the guide wire can be conductive materials such as aluminum, copper, silver, etc., or insulating materials such as epoxy resin and acrylic resin.
  • S62 may be:
  • a plurality of wires and a plurality of flow lines are formed on the substrate, and pixels of the array substrate are formed on the display area, and the pixels are connected with the wires.
  • the wires are arranged in parallel and spaced along the row direction or the column direction in the display area. After the wires extend from the display area to the junction of the display area and the fan-out area, the wires will be divided into several wire groups and continue from the display area to the fan-out area. The junction of the fan-out area extends to the binding area, and the closer to the binding area, the smaller the distance between the wires in the wire group, so as to form multiple gathering patterns in the fan-out area. After the wire extends to the junction between the bonding area and the fan-out area, the wire can continue to extend in the bonding area and interface with the driver located in the bonding area to transmit the driving signal to the pixel. In this way, after the wires are gathered in the fan-out area and then connected to the driver interface of the binding area, the space occupied by the driver can be reduced, and the driving signal of the input wire can be better controlled.
  • a plurality of guide lines are arranged in parallel and spaced between two adjacent gathering patterns, and perpendicular to the contact boundary between the display area and the fan-out area, so as to facilitate the diffusion of the alignment liquid at the edge of the display area in the subsequent alignment film manufacturing process .
  • the distribution density of the guide wire in the area between two adjacent gathering patterns is the same as the distribution density of the wires in the gathering pattern or can meet the requirement of pattern density consistency in the fan-out area.
  • the plurality of guide lines are arranged in axial symmetry, and the guide line at the axis of symmetry is perpendicular to the boundary of the display area.
  • the angle between the diversion lines on both sides of the symmetry axis and the border of the display area is less than 90 degrees.
  • multiple diversion lines are arranged in a tree shape, which is beneficial to the alignment liquid in the display area in the subsequent alignment film manufacturing process. Diffusion at the edge.
  • the diversion line extends in a direction away from the display area, and its extension path may be a straight line or a curve.
  • S62 may specifically be:
  • conductive lines and diversion lines are formed on the substrate.
  • S62 may specifically include the following steps:
  • multiple wires are formed on the substrate through processes such as deposition, exposure, and etching;
  • An insulating layer is formed on the wire, wherein the insulating layer covers the wire and its surrounding area;
  • a plurality of guide lines are formed on the insulating layer through processes such as deposition, exposure, and etching.
  • the manufacturing method of the array substrate in this embodiment replaces the original "inverted V-shaped" pattern design with multiple diversion lines in the fan-out area, which can avoid the "inverted V-shaped” pattern design.
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 70 includes a first substrate 71, a second substrate 72, and a liquid crystal layer 73.
  • the liquid crystal layer 73 is located between the first substrate 71 and the second substrate 72.
  • the first substrate 71 and/or the second substrate 72 are the array substrates of any one of the above embodiments, and include a base, a plurality of wires, and a plurality of flow lines, wherein the base includes a display area, a fan-out area, and In the binding area, a plurality of wires are arranged on the substrate, and a plurality of gathering patterns arranged at intervals are formed in the fan-out area.
  • the wires in the gathering pattern extend from the connection between the display area and the fan-out area to the binding area, and extend The longer the distance, the smaller the distance between each other, and the multiple diversion lines are arranged between two adjacent gathering patterns and extend in a direction away from the display area.
  • the display panel in this embodiment adopts multiple diversion line designs in the fan-out area to replace the original "inverted V-shaped" pattern design, which can avoid the effect of the "inverted V-shaped” pattern on the alignment liquid.

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Abstract

一种阵列基板，其包括：基体（21），基体（21）包括依次连接的显示区（A）、扇出区（B）以及绑定区（C）；设置于基体（21）上且在扇出区（B）形成多个间隔设置的聚拢图案（22B）的多条导线（22），聚拢图案（22B）内的导线（22）从显示区（A）与扇出区（B）的连接处向绑定区（C）延伸，且延伸的距离越长，相互之间的间隔越小；设置于相邻两个聚拢图案（22B）之间且向远离显示区（A）的方向延伸的多条导流线（23）。

Description

一种阵列基板及其制作方法、以及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及其制作方法、以及显示面板。
 背景技术
在阵列基板中，为保证图案密度一致，扇出区“扇形”图案与“扇形”图案交接处采用“倒V字形”图案。
但，由于薄膜晶体管液晶显示面板（TFT LCD）窄边框的设计，阵列基板显示区距离扇出区线路过近。在配向膜制程中，配向液在显示区边缘的扩散受到扇出区“倒V字形”图案的阻挡，导致配向液在显示区边缘处堆积，出现显示区边缘亮度不均匀的现象，影响显示面板的品质。
 技术问题
本申请的目的在于提供一种阵列基板及其制作方法、以及显示面板，通过对现有设计中扇出区的“倒V字形”图案进行重新设计，以避免由于“倒V字形”图案对配向液扩散的阻挡而导致的显示区边缘处亮度不均匀问题，进而提高显示面板的品质。
 技术解决方案
为了解决上述问题，本申请实施例提供了一种阵列基板，该阵列基板包括：基体，基体包括依次连接的显示区、扇出区、以及绑定区；多条导线，多条导线设置于基体上，且在扇出区形成多个间隔设置的聚拢图案，聚拢图案内的导线从显示区与扇出区的连接处向绑定区延伸，且延伸的距离越长，相互之间的间隔越小；多条导流线，多条导流线设置于相邻两个聚拢图案之间，且向远离显示区的方向延伸。
其中，多条导流线呈轴对称排布，且位于对称轴处的导流线垂直于显示区与扇出区的接触边界。
其中，位于对称轴两侧的导流线与接触边界之间的夹角小于90度。
其中，多条导流线平行间隔设置，且垂直于显示区与扇出区的接触边界。
其中，导流线的延伸路径为直线或曲线。
其中，导流线的材质与导线的材质不相同。
为了解决上述问题，本申请实施例还提供了一种阵列基板的制作方法，该方法包括：提供基体，基体包括依次连接的显示区、扇出区、以及绑定区；在基体上形成多条导线和多条导流线，其中，多条导线在扇出区形成多个间隔设置的聚拢图案，聚拢图案内的导线从显示区与扇出区的连接处向绑定区延伸，且延伸的距离越长，相互之间的间隔越小，多条导流线位于相邻两个聚拢图案之间，且向远离显示区的方向延伸。
其中，在基体上形成多条导线和多条导流线的步骤，具体包括：利用第一掩膜版，在基体上形成多条导线；在导线上形成绝缘层；利用第二掩膜板，在绝缘层上形成多条导流线。
其中，在基体上形成多条导线和多条导流线的步骤，具体包括：在基体上形成多条导线和多条导流线，并在显示区上形成阵列基板的像素，像素与导线连接。
其中，多条导流线呈轴对称排布，且位于对称轴处的导流线垂直于显示区与扇出区的接触边界。
其中，位于对称轴两侧的导流线与接触边界之间的夹角小于90度。
其中，多条导流线平行间隔设置，且垂直于显示区与扇出区的接触边界。
其中，导流线的延伸路径为直线或曲线。
其中，导流线的材质与导线的材质不相同。
为了解决上述问题，本申请实施例还提供了一种显示面板，该显示面板包括：第一基板、第二基板、以及液晶层，液晶层位于第一基板及第二基板之间；其中，第一基板和/或第二基板包括：基体，基体包括依次连接的显示区、扇出区、以及绑定区；多条导线，多条导线设置于基体上，且在扇出区形成多个间隔设置的聚拢图案，聚拢图案内的导线从显示区与扇出区的连接处向绑定区延伸，且延伸的距离越长，相互之间的间隔越小；多条导流线，多条导流线设置于相邻两个聚拢图案之间，且向远离显示区的方向延伸。
其中，多条导流线呈轴对称排布，且位于对称轴处的导流线垂直于显示区与扇出区的接触边界。
其中，位于对称轴两侧的导流线与接触边界之间的夹角小于90度。
其中，多条导流线平行间隔设置，且垂直于显示区与扇出区的接触边界。
其中，导流线的延伸路径为直线或曲线。
其中，导流线的材质与导线的材质不相同。
 有益效果
本申请的有益效果是：区别于现有技术，本申请提供的阵列基板，该阵列基板包括基体、多条导线、以及多条导流线，其中，基体包括依次连接的显示区、扇出区、以及绑定区，多条导线设置于基体上，且在扇出区形成多个间隔设置的聚拢图案，聚拢图案内的导线从显示区与扇出区的连接处向绑定区延伸，且延伸的距离越长，相互之间的间隔越小，多条导流线设置于相邻两个聚拢图案之间，且向远离显示区的方向延伸，如此，通过采用多条导流线设计替代原有的“倒V字形”图案设计，能够避免由于“倒V字形”图案对配向液扩散的阻挡而导致的显示区边缘处亮度不均匀问题，进而提高显示面板的品质。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术提供的阵列基板的结构示意图；
图2是本申请实施例提供的阵列基板的结构示意图；
图3是本申请实施例提供的阵列基板的另一结构示意图；
图4是本申请实施例提供的阵列基板的另一结构示意图；
图5是本申请实施例提供的阵列基板的另一结构示意图；
图6是本申请实施例提供的阵列基板的制作方法的流程示意图；
图7是本申请实施例提供的显示面板的结构示意图。
本申请的实施方式
下面结合附图和实施例，对本申请作进一步的详细描述。特别指出的是，以下实施例仅用于说明本申请，但不对本申请的范围进行限定。同样的，以下实施例仅为本申请的部分实施例而非全部实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
请参阅图1，图1是现有技术提供的阵列基板的结构示意图。如图1所示，阵列基板10包括依次连接的显示区A、扇出区B、以及绑定区C，为保证图案密度一致，在扇出区B的“扇形”图案111与“扇形”图案111交接处采用“倒V字形”图案112。但在后续的配向膜制程中，配向液在显示区A边缘的扩散受到扇出区B“倒V字形”图案112的阻挡，导致配向液在显示区A边缘处堆积，出现显示区A边缘亮度不均匀的现象，影响显示面板10的品质。为解决上述技术问题，本申请采用多条导流线设计替代原有的“倒V字形”图案设计，能够避免由于“倒V字形”图案对配向液扩散的阻挡而导致的显示区边缘处亮度不均匀问题，进而提高显示面板的品质。
请参阅图2，图2是本申请实施例提供的阵列基板的结构示意图。如图2所示，阵列基板20包括基体21、多条导线22、以及多条导流线23，其中，基体21包括依次连接的显示区A、扇出区B、以及绑定区C，多条导线22设置于基体21上，且在扇出区B形成多个间隔设置的聚拢图案22B，聚拢图案22B内的导线22从显示区A与扇出区B的连接处向绑定区C延伸，且延伸的距离越长，相互之间的间隔越小，多条导流线23设置于相邻两个聚拢图案22B之间，且向远离显示区A的方向延伸。
其中，基体21可以为玻璃基板或者硬质的树脂基板，也可以为用于制备柔性阵列基板的柔性基板。导线22的材质可以为铝、铜、银等具有低电阻率的材料。导流线23的材质可以与导线22的材质相同也可以不相同，导流线23的材质可以为铝、铜、银等导电材料也可以环氧树脂、丙烯醛基树脂等绝缘材料。
在一个具体实施例中，阵列基板20还包括设置于显示区A的像素（图中未示出），像素包括在基底21上依次设置的薄膜晶体管、有机发光器件。其中，导线22在显示区A内沿行方向或列方向平行间隔排布，且与像素电连接。导线22从显示区A内延伸至显示区A与扇出区B的交接处后，会分为若干个导线组继续由显示区A与扇出区B的交接处向绑定区C延伸，且越靠近绑定区C，导线组内导线22与导线22之间的距离越小，以在扇出区B形成多个聚拢图案22B。在导线22延伸至绑定区C与扇出区B之间的交接处后，导线22可以继续在绑定区C内延伸，并与位于绑定区C的驱动器接口（图中未示出）连接，以将驱动信号传送至所述像素。如此，导线22经过在扇出区B聚拢后，再与绑定区C的驱动器接口连接，可以减小驱动器的占用空间，以及更好地对输入导线22的驱动信号进行控制。
进一步地，为了保证扇出区B图案密度的一致性，在相邻两个聚拢图案22B之间的区域上设有多条导流线23。其中，多条导流线23平行间隔设置，且垂直于显示区A与扇出区B的接触边界，以便于后续配向膜制程中配向液在显示区A边缘处的扩散。
具体地，导流线23在相邻两个聚拢图案22B之间区域内的分布密度与导线22在聚拢图案22B内的分布密度相同或可以满足扇出区B图案密度一致性的要求。进一步地，如图3所示，聚拢图案22B中的导线22延伸至绑定区C与扇出区B之间的交接处后，可以继续在绑定区C内延伸，对应形成矩形图案22C，相邻两个矩形图案22C之间可以形成“倒V字形”图案24，以保证绑定区C图案密度的一致性。
在一个替代实施例中，如图4所示，多条导流线23呈轴对称排布，且位于对称轴Z处的导流线23垂直于显示区A的边界。其中，位于对称轴Z两侧的导流线23与显示区A的边界之间的夹角小于90度，例如，图4中的多条导流线23呈树状排布，有利于后续配向膜制程中配向液在显示区A边缘处的扩散。
在其他替代实施例中，如图5所示，导流线23的在扇出区B内的延伸路径可以为直线或曲线。并且，导流线23与导线22可以是同层设置也可以不是同层设置。例如，导线22设置于基体21上，导线22上设置有绝缘层（未图示），绝缘层覆盖导线22及其四周区域，导流线23设置于绝缘层上。
区别于现有技术，本实施例中的阵列基板，通过在扇出区采用多条导流线设计替代原有的“倒V字形”图案设计，能够避免由于“倒V字形”图案对配向液扩散的阻挡而导致的显示区边缘处亮度不均匀问题，进而提高显示面板的品质。
请参阅图6，图6是本申请实施例提供的阵列基板的制作方法的流程示意图。该阵列基板的制作方法包括以下步骤：
S61：提供基体，基体包括依次连接的显示区、扇出区、以及绑定区。
其中，基体可以为玻璃基板或者硬质的树脂基板，也可以为用于制备柔性阵列基板的柔性基板。
S62：在基体上形成多条导线和多条导流线，其中，多条导线在扇出区形成多个间隔设置的聚拢图案，聚拢图案内的导线从显示区与扇出区的连接处向绑定区延伸，且延伸的距离越长，相互之间的间隔越小，多条导流线位于相邻两个聚拢图案之间，且向远离显示区的方向延伸。
其中，导线的材质可以为铝、铜、银等具有低电阻率的材料。导流线的材质可以与导线的材质相同也可以不相同，导流线的材质可以为铝、铜、银等导电材料也可以环氧树脂、丙烯醛基树脂等绝缘材料。
在一个实施例中，S62可以为：
在基体上形成多条导线和多条导流线，并在显示区上形成阵列基板的像素，像素与导线连接。
具体地，导线在显示区沿行方向或列方向平行间隔排布，在导线从显示区内延伸至显示区与扇出区的交接处后，导线会分为若干个导线组继续由显示区与扇出区的交接处向绑定区延伸，且越靠近绑定区，导线组内导线与导线之间的距离越小，以在扇出区形成多个聚拢图案。在导线延伸至绑定区与扇出区之间的交接处后，导线可以继续在绑定区内延伸，并与位于绑定区的驱动器接口连接，以将驱动信号传送至所述像素。如此，导线经过在扇出区聚拢后，再与绑定区的驱动器接口连接，可以减小驱动器的占用空间，以及更好地对输入导线的驱动信号进行控制。
进一步地，多条导流线平行间隔设置于相邻两个聚拢图案之间，且垂直于显示区与扇出区的接触边界，以便于后续配向膜制程中配向液在显示区边缘处的扩散。具体地，导流线在相邻两个聚拢图案之间区域内的分布密度与导线在聚拢图案内的分布密度相同或可以满足扇出区图案密度一致性的要求。
在一个替代实施例中，多条导流线呈轴对称排布，且位于对称轴处的导流线垂直于显示区的边界。其中，位于对称轴两侧的导流线与显示区的边界之间的夹角小于90度，例如，多条导流线呈树状排布，有利于后续配向膜制程中配向液在显示区边缘处的扩散。
在其他替代实施例中，导流线向远离显示区的方向延伸，且其延伸路径可以为直线或曲线。
在另一个实施例中，S62可以具体为：
利用同一掩膜版，经过沉积、曝光、以及蚀刻等工艺在基体上形成导线、以及导流线。
在又一个实施例中，S62可以具体包括以下步骤：
利用第一掩膜版，经过沉积、曝光、以及蚀刻等工艺在基体上形成多条导线；
在导线上形成绝缘层，其中，绝缘层覆盖导线及其四周区域；
利用第二掩膜板，经过沉积、曝光、以及蚀刻等工艺在绝缘层上形成多条导流线。
区别于现有技术，本实施例中的阵列基板的制作方法，通过在扇出区采用多条导流线设计替代原有的“倒V字形”图案设计，能够避免由于“倒V字形”图案对配向液扩散的阻挡而导致的显示区边缘处亮度不均匀问题，进而提高显示面板的品质。
请参阅图7，图7是本申请实施例提供的显示面板的结构示意图。该显示面板70包括：第一基板71、第二基板72、以及液晶层73，其中，液晶层73位于第一基板71及第二基板72之间。
第一基板71和/或第二基板72为上述任一实施例的阵列基板，包括基体、多条导线、以及多条导流线，其中，基体包括依次连接的显示区、扇出区、以及绑定区，多条导线设置于基体上，且在扇出区形成多个间隔设置的聚拢图案，聚拢图案内的导线从显示区与扇出区的连接处向绑定区延伸，且延伸的距离越长，相互之间的间隔越小，多条导流线设置于相邻两个聚拢图案之间，且向远离显示区的方向延伸。
区别于现有技术，本实施例中的显示面板，通过在扇出区采用多条导流线设计替代原有的“倒V字形”图案设计，能够避免由于“倒V字形”图案对配向液扩散的阻挡而导致的显示区边缘处亮度不均匀问题，进而提高显示面板的品质。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种阵列基板，其包括：
    基体，所述基体包括依次连接的显示区、扇出区、以及绑定区；
    多条导线，所述多条导线设置于所述基体上，且在所述扇出区形成多个间隔设置的聚拢图案，所述聚拢图案内的所述导线从所述显示区与所述扇出区的连接处向所述绑定区延伸，且延伸的距离越长，相互之间的间隔越小；
    多条导流线，所述多条导流线设置于相邻两个所述聚拢图案之间，且向远离所述显示区的方向延伸。
  2. 根据权利要求1所述的阵列基板，其中，所述多条导流线呈轴对称排布，且位于对称轴处的所述导流线垂直于所述显示区与所述扇出区的接触边界。
  3. 根据权利要求2所述的阵列基板，其中，位于所述对称轴两侧的所述导流线与所述接触边界之间的夹角小于90度。
  4. 根据权利要求1所述的阵列基板，其中，所述多条导流线平行间隔设置，且垂直于所述显示区与所述扇出区的接触边界。
  5. 根据权利要求1所述的阵列基板，其中，所述导流线的延伸路径为直线或曲线。
  6. 根据权利要求1所述的阵列基板，其中，所述导流线的材质与所述导线的材质不相同。
  7. 一种阵列基板的制作方法，其包括：
    提供基体，所述基体包括依次连接的显示区、扇出区、以及绑定区；
    在所述基体上形成多条导线和多条导流线，其中，所述多条导线在所述扇出区形成多个间隔设置的聚拢图案，所述聚拢图案内的所述导线从所述显示区与所述扇出区的连接处向所述绑定区延伸，且延伸的距离越长，相互之间的间隔越小，所述多条导流线位于相邻两个所述聚拢图案之间，且向远离所述显示区的方向延伸。
  8. 根据权利要求7所述的制作方法，其中，所述在所述基体上形成多条导线和多条导流线的步骤，具体包括：
    利用第一掩膜版，在所述基体上形成所述多条导线；
    在所述导线上形成绝缘层；
    利用第二掩膜板，在所述绝缘层上形成所述多条导流线。
  9. 根据权利要求7所述的阵列基板的制作方法，其中，所述在所述基体上形成多条导线和多条导流线的步骤，具体包括：
    在所述基体上形成所述多条导线和所述多条导流线，并在所述显示区上形成所述阵列基板的像素，所述像素与所述导线连接。
  10. 根据权利要求7所述的制作方法，其中，所述多条导流线平行间隔设置，且垂直于所述显示区与所述扇出区的接触边界。
  11. 根据权利要求7所述的制作方法，其中，所述导流线的延伸路径为直线或曲线。
  12. 根据权利要求7所述的制作方法，其中，所述导流线的材质与所述导线的材质不相同。
  13. 根据权利要求7所述的制作方法，其中，所述多条导流线呈轴对称排布，且位于对称轴处的所述导流线垂直于所述显示区与所述扇出区的接触边界。
  14. 根据权利要求13所述的制作方法，其中，位于所述对称轴两侧的所述导流线与所述接触边界之间的夹角小于90度。
  15. 一种显示面板，其包括：
    第一基板、第二基板、以及液晶层，所述液晶层位于所述第一基板及所述第二基板之间；
    其中，所述第一基板和/或第二基板包括：
    基体，所述基体包括依次连接的显示区、扇出区、以及绑定区；
    多条导线，所述多条导线设置于所述基体上，且在所述扇出区形成多个间隔设置的聚拢图案，所述聚拢图案内的所述导线从所述显示区与所述扇出区的连接处向所述绑定区延伸，且延伸的距离越长，相互之间的间隔越小；
    多条导流线，所述多条导流线设置于相邻两个所述聚拢图案之间，且向远离所述显示区的方向延伸。
  16. 根据权利要求15所述的显示面板，其中，所述多条导流线呈轴对称排布，且位于对称轴处的所述导流线垂直于所述显示区与所述扇出区的接触边界。
  17. 根据权利要求16所述的显示面板，其中，位于所述对称轴两侧的所述导流线与所述接触边界之间的夹角小于90度。
  18. 根据权利要求15所述的显示面板，其中，所述多条导流线平行间隔设置，且垂直于所述显示区与所述扇出区的接触边界。
  19. 根据权利要求15所述的显示面板，其中，所述导流线的延伸路径为直线或曲线。
  20. 根据权利要求15所述的显示面板，其中，所述导流线的材质与所述导线的材质不相同。
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