WO2020202840A1

WO2020202840A1 - Method for manufacturing solar cell and solar cell

Info

Publication number: WO2020202840A1
Application number: PCT/JP2020/006030
Authority: WO
Inventors: 中野邦裕
Original assignee: 株式会社カネカ
Priority date: 2019-03-29
Filing date: 2020-02-17
Publication date: 2020-10-08
Also published as: JP7459059B2; JPWO2020202840A1

Abstract

Provided is a method for manufacturing a solar cell (1) such that performance reduction and reliability reduction caused by an outer peripheral edge region of a main surface of a semiconductor substrate (11) being exposed can be suppressed. The method for manufacturing a solar cell (1) includes: a step of forming a first conductivity type semiconductor layer material film in a first region (7) and a second region (8) on a rear side of the semiconductor substrate (11) with an outer peripheral edge region (R) of the rear side of the semiconductor substrate (11) being masked; a step of covering the first region (7) and the outer peripheral edge region (R) of the rear side of the semiconductor substrate (11) with a resist and forming a patterned semiconductor layer (25) of a first conductivity type in the first region (7); a step of forming a second conductivity type semiconductor layer material film on the entire surface including the first region (7), the second region (8), and the outer peripheral edge region (R) of the rear side of the semiconductor substrate (11); and a step of covering the second region (8) and the outer peripheral edge region (R) of the rear side of the semiconductor substrate (11) with a resist and forming a patterned semiconductor layer (35) of a second conductivity type in the second region (8) and the outer peripheral edge region (R).

Description

Manufacturing method of solar cells and solar cells

The present invention relates to a method for manufacturing a back electrode type (back contact type) solar cell and a solar cell.

Solar cells using a semiconductor substrate include a double-sided electrode type solar cell in which semiconductor layers and electrodes are formed on both the light receiving surface side and the back surface side, and a back electrode type solar cell in which the semiconductor layer and electrodes are formed only on the back surface side. There is a solar cell.

In a double-sided electrode type solar cell, if the semiconductor layer formed on one surface undesirably wraps around the side surface or the other surface of the semiconductor substrate, the characteristics deteriorate. In order to prevent this, in the solar cell described in Patent Document 1, a semiconductor layer is formed in a smaller area than the semiconductor substrate on both sides. However, in such a structure, although the deterioration of the characteristics due to the wraparound can be reduced as described above, the outer peripheral portion of the semiconductor substrate becomes an invalid portion, so that the characteristics are low by this amount.

In the solar cell described in Patent Document 2, the semiconductor layer on the front surface side is formed on substantially the entire surface of the semiconductor substrate, and the semiconductor layer on the back surface side is formed in a smaller area than the back surface of the semiconductor substrate. According to this, since the semiconductor layer on the back surface side has a smaller area than the semiconductor substrate, the semiconductor layer on the back surface side is not formed on the side surface or the end portion on the front surface side of the semiconductor substrate, and the output characteristics are less deteriorated. .. In addition, since the semiconductor on the surface side is formed on substantially the entire surface, there are few ineffective portions and the characteristics are good.

JP-A-9-129904 Japanese Unexamined Patent Publication No. 2006-222469

However, according to the knowledge of the inventor of the present application, the exposure of the outer peripheral region of the main surface of the semiconductor substrate is also one of the factors for the deterioration of the performance and reliability of the solar cell. Further, according to the findings of the inventor of the present application, in the back electrode type solar cell, the semiconductor layer formed on one surface wraps around the side surface or the other surface of the semiconductor substrate as compared with the double-sided electrode type solar cell. There is little deterioration in characteristics due to. Therefore, the inventor of the present application attempts to form a semiconductor layer up to the outer peripheral region on the back surface side of the semiconductor substrate in the back electrode type solar cell.

However, the inventor of the present application forms a good semiconductor layer in the outer peripheral region of the back surface of the semiconductor substrate and the outer peripheral region of the light receiving surface when patterning the semiconductor layer using, for example, a photoresist using a photolithography technique. It has been found that this is difficult (details will be described later).

An object of the present invention is to provide a method for manufacturing a solar cell and a solar cell that suppresses performance deterioration and reliability deterioration due to exposure of the outer peripheral region of the main surface of the semiconductor substrate.

In the method for manufacturing a solar cell according to the present invention, a first conductive semiconductor layer is sequentially laminated on a semiconductor substrate and a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate. A back electrode type sun including a first electrode layer, a second conductive semiconductor layer and a second electrode layer sequentially laminated in a second region which is a part of the other main surface side of the semiconductor substrate. A method for manufacturing a battery, in which the outer peripheral edge region on the other main surface side of the semiconductor substrate is masked, and the first region and the second region on the other main surface side of the semiconductor substrate are covered with the first region. 1 The first semiconductor layer material film forming step of forming the material film of the conductive semiconductor layer, and the first region and the outer peripheral region on the other main surface side of the semiconductor substrate are covered with a resist to cover the second region. In the first semiconductor layer forming step of forming the patterned first conductive semiconductor layer in the first region by removing the material film of the first conductive semiconductor layer in the above and removing the resist. On the entire surface including the first region, the second region, and the outer peripheral edge region on the other main surface side of the semiconductor substrate, above the first conductive semiconductor layer in the first region, and in the second region. A second semiconductor layer material film forming step of forming a material film of the second conductive semiconductor layer on the semiconductor substrate in the outer peripheral region, and the second region on the other main surface side of the semiconductor substrate. The second region and the outer peripheral region are patterned by covering the outer peripheral region with a resist and removing the material film of the second conductive semiconductor layer in the first region. It includes a second semiconductor layer forming step of forming a conductive semiconductor layer.

Another method for manufacturing a solar cell according to the present invention is a first conductive type in which a semiconductor substrate is sequentially laminated in a first region which is a part of a semiconductor substrate and a part of the other main surface side opposite to one main surface side of the semiconductor substrate. A back surface electrode type including a semiconductor layer and a first electrode layer, and a second conductive semiconductor layer and a second electrode layer laminated in this order in a second region which is another part of the other main surface side of the semiconductor substrate. In the method for manufacturing a solar cell of the above, in a state where the outer peripheral edge region on the other main surface side of the semiconductor substrate is masked, the first region and the second region on the other main surface side of the semiconductor substrate are covered. A first semiconductor layer material film forming step of forming a material film of the first conductive semiconductor layer, a lift-off layer forming step of forming a lift-off layer on the material film of the first conductive semiconductor layer, and the semiconductor. The first region and the outer peripheral peripheral region on the other main surface side of the substrate are covered with a resist to remove the material films of the lift-off layer and the first conductive semiconductor layer in the second region. A first semiconductor layer forming step of forming the patterned first conductive semiconductor layer and the lift-off layer in one region and removing the resist, and the first region on the other main surface side of the semiconductor substrate. The second conductive semiconductor on the entire surface including the second region and the outer peripheral region, on the lift-off layer in the first region, and on the semiconductor substrate in the second region and the outer peripheral region. By removing the lift-off layer and the second semiconductor layer material film forming step of forming the material film of the layer, the material film of the second conductive semiconductor layer in the first region is removed, and the second region and the second region and the material film are removed. The outer peripheral edge region includes a second semiconductor layer forming step of forming the patterned second conductive semiconductor layer.

The solar cell according to the present invention includes a semiconductor substrate, a first conductive semiconductor layer and a first conductive semiconductor layer, which are sequentially laminated in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate. A back surface electrode type solar cell including an electrode layer, a second conductive semiconductor layer and a second electrode layer sequentially laminated in a second region which is another part of the other main surface side of the semiconductor substrate. Therefore, the second conductive semiconductor layer is formed in the outer peripheral edge region on the other main surface side of the semiconductor substrate.

According to the present invention, it is possible to suppress deterioration in performance and reliability of the solar cell due to exposure of the outer peripheral region of the main surface of the semiconductor substrate.

It is the figure which looked at the solar cell which concerns on this embodiment from the back side. FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. It is a figure which shows the intrinsic semiconductor layer forming process and the optical adjustment layer forming process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the 1st semiconductor layer material film formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the 2nd semiconductor layer material film formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 1st Embodiment. It is a figure which shows the state of forming a resist on the whole surface of the back surface side and the entire surface of the light receiving surface side of a semiconductor substrate. It is a partially enlarged view which shows the ideal form of the patterning of the resist shown in FIG. 4A. It is a partially enlarged view which shows an example of the patterning of the resist shown in FIG. 4A. It is a partially enlarged view which shows an example of the patterning of the resist shown in FIG. 4A. It is a partially enlarged view which shows another example of the patterning of the resist shown in FIG. 4A. It is a partially enlarged view which shows another example of the patterning of the resist shown in FIG. 4A. It is a partially enlarged view which shows an example of the patterning of the semiconductor layer using the example of the resist shown in FIG. 5B. It is a partially enlarged view which shows an example of the patterning of the semiconductor layer using the example of the resist shown in FIG. 5B. It is a partially enlarged view which shows an example of the patterning of the semiconductor layer using the example of the resist shown in FIG. 5B. It is a partially enlarged view which shows an example of the patterning of the semiconductor layer using the example of the resist shown in FIG. 5B. It is a partially enlarged view which shows another example of the patterning of the semiconductor layer using another example of the resist shown in FIG. 6B. It is a partially enlarged view which shows another example of the patterning of the semiconductor layer using another example of the resist shown in FIG. 6B. It is a partially enlarged view which shows another example of the patterning of the semiconductor layer using another example of the resist shown in FIG. 6B. It is a partially enlarged view which shows another example of the patterning of the semiconductor layer using another example of the resist shown in FIG. 6B. It is a partially enlarged view which shows an example of the patterning of the semiconductor layer using the resist of this embodiment. It is a partially enlarged view which shows an example of the patterning of the semiconductor layer using the resist of this embodiment. It is a partially enlarged view which shows an example of the patterning of the semiconductor layer using the resist of this embodiment. It is a partially enlarged view which shows an example of the patterning of the semiconductor layer using the resist of this embodiment. It is a figure which shows the intrinsic semiconductor layer forming process and the optical adjustment layer forming process in the manufacturing method of the solar cell which concerns on 2nd Embodiment. It is a figure which shows the 1st semiconductor layer material film formation | lift-off layer formation process in the manufacturing method of the solar cell which concerns on 2nd Embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 2nd Embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 2nd Embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 2nd Embodiment. It is a figure which shows the 2nd semiconductor layer material film formation process in the manufacturing method of the solar cell which concerns on 2nd Embodiment. It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on 2nd Embodiment.

Hereinafter, an example of the embodiment of the present invention will be described with reference to the accompanying drawings. In addition, the same reference numerals are given to the same or corresponding parts in each drawing. Further, for convenience, hatching, member codes, etc. may be omitted, but in such cases, other drawings shall be referred to.

(Solar cell)
FIG. 1 is a view of the solar cell according to the present embodiment as viewed from the back surface side. The solar cell 1 shown in FIG. 1 is a back electrode type solar cell. The solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7, a second region 8, and an outer peripheral region R on the main surface of the semiconductor substrate 11.

The first region 7 has a so-called comb-shaped shape, and has a plurality of finger portions 7f corresponding to comb teeth and a bus bar portion 7b corresponding to a support portion of the comb teeth. The bus bar portion 7b extends in the first direction (X direction) along one side of the semiconductor substrate 11, and the finger portion 7f intersects the bus bar portion 7b in the first direction (X direction). It extends in the direction (Y direction).
Similarly, the second region 8 has a so-called comb-shaped shape, and has a plurality of finger portions 8f corresponding to the comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth. The bus bar portion 8b extends in the first direction (X direction) along the other side portion facing one side portion of the semiconductor substrate 11, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y). Extends in the direction).
The finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction).
The first region 7 and the second region 8 may be formed in a striped shape.

The outer peripheral edge region R is a region of the outer peripheral edge of the main surface of the semiconductor substrate 11 and surrounds the first region 7 and the second region 8. The outer peripheral edge region R is a region having a width W1 = 5 mm or less from the edge of the semiconductor substrate 11 toward the center of the semiconductor substrate 11.

FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. As shown in FIG. 2, the solar cell 1 includes a semiconductor substrate 11, an intrinsic semiconductor layer 13 and optics, which are sequentially laminated on the light receiving surface side, which is one of the main surfaces of the semiconductor substrate 11 on the light receiving side. The adjusting layer 15 is provided. Further, the solar cell 1 is a first intrinsic semiconductor layer 23 which is sequentially laminated on a part (first region 7) of the back surface side which is the other main surface of the main surface of the semiconductor substrate 11 opposite to the light receiving surface. , A first conductive semiconductor layer 25 and a first electrode layer 27 are provided. Further, the solar cell 1 includes a second intrinsic semiconductor layer 33, a second conductive semiconductor layer 35, and a second electrode layer 37, which are sequentially laminated on another part (second region 8) on the back surface side of the semiconductor substrate 11. To be equipped. The second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 are formed in the outer peripheral region R on the back surface side of the semiconductor substrate 11.

The semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. Examples of the n-type dopant include phosphorus (P).
The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate optical carriers (electrons and holes).
By using crystalline silicon as the material of the semiconductor substrate 11, a relatively high output (stable output regardless of the illuminance) can be obtained even when the dark current is relatively small and the intensity of the incident light is low.

The intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11. The first intrinsic semiconductor layer 23 is formed in the first region 7 on the back surface side of the semiconductor substrate 11. The second intrinsic semiconductor layer 33 is formed in the second region 8 and the outer peripheral region R on the back surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 13, the first intrinsic semiconductor layer 23, and the second intrinsic semiconductor layer 33 are formed of, for example, a material containing intrinsic (i-type) amorphous silicon as a main component.
The intrinsic semiconductor layer 13, the first intrinsic semiconductor layer 23, and the second intrinsic semiconductor layer 33 function as a so-called passivation layer, suppress recombination of carriers generated in the semiconductor substrate 11, and increase carrier recovery efficiency.

The optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11. The optical adjustment layer 15 functions as an antireflection layer for preventing reflection of incident light, and also functions as a protective layer for protecting the light receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13. The optical adjustment layer 15 is formed of an insulating material such as a composite thereof such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).

The first conductive semiconductor layer 25 is formed on the first intrinsic semiconductor layer 23, that is, in the first region 7 on the back surface side of the semiconductor substrate 11. The first conductive semiconductor layer 25 is formed of, for example, an amorphous silicon material. The first conductive semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant. Examples of the p-type dopant include boron (B).

The second conductive semiconductor layer 35 is formed on the second intrinsic semiconductor layer 33, that is, in the second region 8 and the outer peripheral region R on the back surface side of the semiconductor substrate 11. The second conductive semiconductor layer 35 is formed of, for example, an amorphous silicon material. The second conductive semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above).

The first conductive semiconductor layer 25 may be an n-type semiconductor layer, and the second conductive semiconductor layer 35 may be a p-type semiconductor layer.
Further, the semiconductor substrate 11 may be a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant (for example, the above-mentioned boron (B)).

The first electrode layer 27 is formed on the first conductive semiconductor layer 25, and the second electrode layer 37 is formed on the second conductive semiconductor layer 35.
The first electrode layer 27 and the second electrode layer 37 may include a transparent electrode layer and a metal electrode layer, or may include only a metal electrode layer. In the present embodiment, the first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29, which are sequentially laminated on the first conductive semiconductor layer 25. The second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39, which are sequentially laminated on the second conductive semiconductor layer 35.
The transparent electrode layers 28 and 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium tin oxide and tin oxide) and ZnO (Zinc Oxide: zinc oxide). The metal electrode layers 29 and 39 may be formed of a conductive paste material containing a metal powder such as silver.

Here, the inventor of the present application forms a good semiconductor layer in the outer peripheral region of the back surface of the semiconductor substrate and the outer peripheral region of the light receiving surface when patterning the semiconductor layer using, for example, a photoresist using a photolithography technique. We have obtained the finding that it is difficult to do so.

First, consider resist.
As shown in FIG. 4A, when the resist 40 is formed on the entire surface of the semiconductor substrate 11 on the back surface side and the entire surface on the light receiving surface side, it is actually formed on the side surface side (end surface side) of the semiconductor substrate 11.
When forming a semiconductor layer on the outer peripheral edge region R on the back surface side of the semiconductor substrate 11, it is ideally necessary to expose the outer peripheral edge region R on the back surface side of the semiconductor substrate 11 as shown in FIG. 4B.

Generally, when the back surface side of the semiconductor substrate 11 is exposed, as shown in FIGS. 5A and 5B, a mask is also arranged on the outer peripheral edge region R on the back surface side of the semiconductor substrate 11 to perform exposure and development, and the resist 40 is exposed. Patterning is performed. In this case, as shown in FIG. 5B, the resist 40 remains in the outer peripheral region R on the back surface side of the semiconductor substrate 11 (actually, due to light reflection and scattering, the influence of the developing solution, etc., the resist 40 remains larger than the mask width. Widely exposed.).

On the other hand, as shown in FIGS. 6A and 6B, in order to remove the resist 40 up to the outer peripheral edge region R on the back surface side of the semiconductor substrate 11, the mask of the outer peripheral edge region R on the back surface side of the semiconductor substrate 11 is removed. Then, the light wraps around to the light receiving surface side, and the outer peripheral edge region on the light receiving surface side is exposed.

Based on this, the patterning of the semiconductor layer will be examined.
As shown in FIG. 7A, a first conductive semiconductor layer material film 25Z (and a first intrinsic semiconductor layer material film 23Z) is formed on the entire surface of the back surface side of the semiconductor substrate 11, and the resist 40 shown in FIG. 5B is used to form a first film. When the 1 conductive semiconductor layer material film 25Z (and the 1st intrinsic semiconductor layer material film 23Z) is patterned, as shown in FIG. 7B, the 1st conductive semiconductor layer is formed in the outer peripheral region R on the back surface side of the semiconductor substrate 11. 25 (and the first intrinsic semiconductor layer 23) remains.

After that, as shown in FIG. 7C, a second conductive semiconductor layer material film 35Z (and a second intrinsic semiconductor layer material film 33Z) is formed on the entire surface of the back surface side of the semiconductor substrate 11, as shown in FIGS. 5A and 5B. When the second conductive semiconductor layer material film 35Z (and the second intrinsic semiconductor layer material film 33Z) is patterned using the formed resist 40, as shown in FIG. 7D, the outer peripheral edge on the back surface side of the semiconductor substrate 11 The first conductive semiconductor layer 25 (and the first intrinsic semiconductor layer 23) and the second conductive semiconductor layer 35 (and the second intrinsic semiconductor layer 33) remain in the region R.

As described above, when the semiconductor layer is patterned using the resist 40 shown in FIG. 5B, the semiconductor layer in the outer peripheral region R on the back surface side of the semiconductor substrate 11 cannot be obtained well.

On the other hand, as shown in FIG. 8A, the first conductive semiconductor layer material film 25Z (and the first intrinsic semiconductor layer material film 23Z) is formed on the entire surface of the back surface side of the semiconductor substrate 11, and the resist shown in FIG. 6B is formed. When the first conductive semiconductor layer material film 25Z (and the first intrinsic semiconductor layer material film 23Z) is patterned using the 40, as shown in FIG. 8B, the outer peripheral region R on the back surface side of the semiconductor substrate 11 is the first. 1 The conductive semiconductor layer 25 (and the first intrinsic semiconductor layer 23) does not remain. However, the outer peripheral edge region of the semiconductor substrate 11 on the light receiving surface side is exposed.

After that, as shown in FIG. 8C, a second conductive semiconductor layer material film 35Z (and a second intrinsic semiconductor layer material film 33Z) is formed on the entire back surface side of the semiconductor substrate 11, as shown in FIGS. 6A and 6B. When the second conductive semiconductor layer material film 35Z (and the second intrinsic semiconductor layer material film 33Z) is patterned using the formed resist 40, as shown in FIG. 8D, the outer peripheral edge on the back surface side of the semiconductor substrate 11 The second conductive semiconductor layer 35 (and the second intrinsic semiconductor layer 33) remains in the region R. However, the outer peripheral edge region of the semiconductor substrate 11 on the light receiving surface side is exposed.

When the semiconductor layer is patterned using the resist 40 shown in FIG. 6B in this way, the semiconductor layer in the outer peripheral region R on the back surface side of the semiconductor substrate 11 is satisfactorily obtained, but on the light receiving surface side of the semiconductor substrate 11. The outer peripheral area is exposed.

Therefore, the inventor of the present application has found a method for manufacturing a solar cell that masks (for example, a substrate tray) the outer peripheral region on the back surface side of the semiconductor substrate when forming the first conductive type semiconductor layer material film. In particular,
-As will be described later, for example, the first conductive semiconductor layer material film 25Z (and the first intrinsic semiconductor layer material film 23Z) in a state where the outer peripheral edge region R on the back surface side of the semiconductor substrate 11 is masked by using the substrate tray 3. (First semiconductor layer material film forming step),
As shown in FIGS. 9A and 9B, the outer peripheral region R on the back surface side of the semiconductor substrate 11 and the entire surface on the light receiving surface side are covered with a resist 40 to cover the first conductive semiconductor layer 25 (and the first intrinsic semiconductor layer 23). ) Is patterned (first semiconductor layer forming step).
As a result, the first conductive semiconductor layer 25 (and the first intrinsic semiconductor layer 23) does not remain in the outer peripheral region R on the back surface side of the semiconductor substrate 11 as shown in FIGS. 7A and 7B. Further, unlike FIGS. 8A and 8B, the outer peripheral edge region of the semiconductor substrate 11 on the light receiving surface side is not exposed.

afterwards,
As shown in FIG. 9C, on the entire surface including the first region 7, the second region 8, and the outer peripheral region R on the back surface side of the semiconductor substrate 11, on the first conductive semiconductor layer 25 in the first region 7, and on the entire surface including the outer peripheral region R. A second conductive semiconductor layer material film 35Z (and a second intrinsic semiconductor layer material film 33Z) is formed on the semiconductor substrate 11 in the second region 8 and the outer peripheral region (second semiconductor layer material film forming step).
As shown in FIG. 9D, the outer peripheral edge region R on the back surface side of the semiconductor substrate 11 and the entire surface on the light receiving surface side are covered with a resist to pattern the second conductive semiconductor layer 35 (and the second intrinsic semiconductor layer 33). (Second semiconductor layer forming step).
As a result, the second conductive semiconductor layer 35 (and the second intrinsic semiconductor layer 33) can be satisfactorily formed in the outer peripheral region R on the back surface side of the semiconductor substrate 11. That is, it is possible to avoid the formation of an unfavorable semiconductor layer in the outer peripheral region R on the back surface side of the semiconductor substrate 11 as in FIGS. 7C and 7D. Further, unlike FIGS. 8C and 8D, the outer peripheral edge region of the semiconductor substrate 11 on the light receiving surface side is not exposed.
Hereinafter, two methods for manufacturing the solar cell of the present embodiment will be described.

(Manufacturing method of the solar cell of the first embodiment)
Next, a method for manufacturing the solar cell 1 of the present embodiment shown in FIGS. 1 and 2 will be described with reference to FIGS. 3A to 3I. FIG. 3A is a diagram showing an intrinsic semiconductor layer forming step and an optical adjusting layer forming step in the method for manufacturing a solar cell according to the first embodiment. FIG. 3B is a diagram showing a first semiconductor layer material film forming step in the solar cell manufacturing method according to the first embodiment, and FIGS. 3C to 3E are diagrams in the solar cell manufacturing method according to the first embodiment. It is a figure which shows 1 semiconductor layer forming process. FIG. 3F is a diagram showing a second semiconductor layer material film forming step in the method for manufacturing a solar cell according to the first embodiment, and FIGS. 3G to 3I show a first in the method for manufacturing a solar cell according to the first embodiment. It is a figure which shows 2 semiconductor layer formation process.

First, as shown in FIG. 3A, the intrinsic semiconductor layer 13 is laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side by, for example, the CVD method (intrinsic semiconductor layer forming step). Next, for example, using a CVD method, the optical adjustment layer 15 is laminated (film-formed) on the entire surface of the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11 (optical adjustment layer forming step).

Next, as shown in FIG. 3B, for example, using the CVD method, the first intrinsic semiconductor layer material film 23Z and the first conductive type semiconductor layer material film 25Z are laminated in order on the back surface side of the semiconductor substrate 11 (film formation). To do. At this time, with the outer peripheral edge region R on the back surface side of the semiconductor substrate 11 masked by the substrate tray 3, the first intrinsic semiconductor layer material film is formed on the first region 7 and the second region 8 on the back surface side of the semiconductor substrate 11. 23Z and the first conductive type semiconductor layer material film 25Z are formed (first semiconductor layer material film forming step).

Next, as shown in FIGS. 3C to 3E, for example, using a resist 40, the first intrinsic semiconductor layer material film 23Z and the first conductive semiconductor layer material film 25Z in the second region 8 on the back surface side of the semiconductor substrate 11 By removing the above, the patterned first intrinsic semiconductor layer 23 and the first conductive semiconductor layer 25 are formed in the first region 7 on the back surface side of the semiconductor substrate 11. At this time, the first region 7 and the outer peripheral region R on the back surface side of the semiconductor substrate 11 and the entire surface on the light receiving surface side are covered with the resist 40, and the first intrinsic semiconductor layer material film 23Z and the first conductive semiconductor layer material film are covered. Patterning of 25Z is performed (first semiconductor layer forming step).

Specifically, after applying the photoresist to the entire surface of the semiconductor substrate 11 on both sides by using a photolithography method, the photoresist in the second region 8 on the back surface side is exposed and developed to be removed by using a mask. .. As a result, as shown in FIG. 3C, a resist 40 that covers the first region 7 and the outer peripheral region R on the back surface side of the semiconductor substrate 11 and the entire surface on the light receiving surface side is formed.

Then, as shown in FIG. 3D, the first intrinsic semiconductor layer material film 23Z and the first conductive semiconductor layer material film 25Z in the second region 8 on the back surface side of the semiconductor substrate 11 are etched with the resist 40 as a mask to achieve a semiconductor. A patterned first intrinsic semiconductor layer 23 and a first conductive semiconductor layer 25 are formed in the first region 7 on the back surface side of the substrate 11. As the etching solution for the first intrinsic semiconductor layer material film and the first conductive semiconductor layer material film, for example, an acidic solution such as a mixed solution of hydrofluoric acid and nitric acid is used.

After that, as shown in FIG. 3E, the resist 40 is removed. As the stripping solution for the resist 40, an organic solvent such as acetone is used depending on the type of resist.

Next, as shown in FIG. 3F, for example, by using a CVD method, the entire surface of the semiconductor substrate 11 on the back surface side, that is, the first region 7, the second region 8, and the outer peripheral region R, more specifically, The second intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z are formed on the first conductive semiconductor layer 25 in the first region 7 and on the semiconductor substrate 11 in the second region 8 and the outer peripheral region R. Laminate (film formation) in order. At this time, the second intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z are formed by the substrate tray 3 in a state of being held in the opposite direction (second semiconductor layer material film forming step).

Next, as shown in FIGS. 3G to 3I, for example, using the resist 40, the second intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z in the first region 7 on the back surface side of the semiconductor substrate 11 By removing the above, the patterned second intrinsic semiconductor layer 33 and the second conductive semiconductor layer 35 are formed in the second region 8 and the outer peripheral region R on the back surface side of the semiconductor substrate 11. At this time, the second region 8 and the outer peripheral region R on the back surface side of the semiconductor substrate 11 and the entire surface on the light receiving surface side are covered with a resist to cover the second intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z. (Second semiconductor layer forming step).

Specifically, a photoresist is applied to the entire surface of the semiconductor substrate 11 on both sides by using a photolithography method, and then the photoresist in the first region 7 on the back surface side is exposed and developed to be removed by using a mask. .. As a result, as shown in FIG. 3G, a resist 40 that covers the second region 8 and the outer peripheral region R on the back surface side of the semiconductor substrate 11 and the entire surface on the light receiving surface side is formed.

Then, as shown in FIG. 3H, the second intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z in the first region 7 on the back surface side of the semiconductor substrate 11 are etched with the resist 40 as a mask to achieve a semiconductor. A patterned second intrinsic semiconductor layer 33 and a second conductive semiconductor layer 35 are formed in the second region 8 and the outer peripheral region R on the back surface side of the substrate 11. As the etching solution for the second intrinsic semiconductor layer material film and the second conductive semiconductor layer material film, for example, an acidic solution such as a mixed solution of hydrofluoric acid and nitric acid is used.

After that, as shown in FIG. 3I, the resist 40 is removed. As the stripping solution for the resist 40, an organic solvent such as acetone is used depending on the type of resist.

Next, the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
Specifically, for example, a PVD method (physical vapor deposition method) such as a sputtering method is used to laminate (form) a transparent electrode layer material film on the entire back surface side of the semiconductor substrate 11. After that, the transparent electrode layers 28 and 38 are patterned by removing a part of the transparent electrode layer material film by, for example, an etching method using an etching paste. As the etching solution for the transparent electrode layer material film, for example, hydrochloric acid or an aqueous ferric chloride solution is used.
Then, for example, by using a pattern printing method or a coating method, a metal electrode layer 29 is formed on the transparent electrode layer 28, and a metal electrode layer 39 is formed on the transparent electrode layer 38, whereby the first electrode layer 27 and The second electrode layer 37 is formed.

Through the above steps, the back electrode type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 is completed.

As described above, according to the method for manufacturing a solar cell of the present embodiment,
-For example, the first conductive semiconductor layer material film 25Z (and the first intrinsic semiconductor layer material film 23Z) is formed in a state where the outer peripheral edge region R on the back surface side of the semiconductor substrate 11 is masked by using the substrate tray 3 (the first). 1 Semiconductor layer material film forming process),
The outer peripheral edge region R on the back surface side of the semiconductor substrate 11 and the entire surface on the light receiving surface side are covered with a resist to pattern the first conductive semiconductor layer 25 (and the first intrinsic semiconductor layer 23) (formation of the first semiconductor layer). Process).
As a result, the first conductive semiconductor layer 25 (and the first intrinsic semiconductor layer 23) is not formed in the outer peripheral region R on the back surface side of the semiconductor substrate 11 as shown in FIGS. 7A and 7B. Further, as shown in FIGS. 8A and 8B, the outer peripheral edge region of the semiconductor substrate 11 on the light receiving surface side is not exposed.

Further, according to the method for manufacturing a solar cell of the present embodiment,
On the entire surface including the first region 7, the second region 8 and the outer peripheral region R on the back surface side of the semiconductor substrate 11, the top of the first conductive semiconductor layer 25 in the first region 7 and the second region 8 and the outer peripheral edge A second conductive semiconductor layer material film 35Z (and a second intrinsic semiconductor layer material film 33Z) is formed on the semiconductor substrate 11 in the region (second semiconductor layer material film forming step).
The outer peripheral edge region R on the back surface side of the semiconductor substrate 11 and the entire surface on the light receiving surface side are covered with a resist to pattern the second conductive semiconductor layer 35 (and the second intrinsic semiconductor layer 33) (formation of the second semiconductor layer). Process).
As a result, the second conductive semiconductor layer 35 (and the second intrinsic semiconductor layer 33) can be satisfactorily formed in the outer peripheral region R on the back surface side of the semiconductor substrate 11. That is, it is possible to avoid the formation of an unfavorable semiconductor layer in the outer peripheral region R on the back surface side of the semiconductor substrate 11 as shown in FIGS. 7C and 7D. Further, unlike FIGS. 8C and 8D, the outer peripheral edge region of the semiconductor substrate 11 on the light receiving surface side is not exposed.

As described above, according to the method for manufacturing a solar cell of the present embodiment, a good second conductive semiconductor layer 35 is formed in the outer peripheral edge region R on the back surface side and the outer peripheral edge region on the light receiving surface side of the semiconductor substrate 11. Therefore, it is possible to suppress deterioration in the performance and reliability of the solar cell due to the exposure of the outer peripheral region of the main surface of the semiconductor substrate 11. Further, it is possible to suppress a decrease in the yield of the solar cell due to the exposure of the outer peripheral region of the main surface of the semiconductor substrate 11.

By the way, for example, when a solar cell is produced by integrally forming a semiconductor layer by using a CVD process, the performance is improved because it is not exposed to the atmosphere and there is no influence of dust and mechanical damage due to removal of the solar cell. However, due to the problem of the board tray, one side is always masked.
In a double-sided electrode type solar cell, since the film is formed only once on both the light receiving surface and the back surface, the once masked area is exposed and continues to be exposed. On the other hand, in the back electrode type solar cell, for example, i-layer / p-layer film formation → patterning → i-layer / n-layer film formation, so that it is after the integrated film formation of i-layer / p-layer film formation. Therefore, the outer peripheral region of the main surface of the semiconductor substrate can be covered before the integrated film formation of the i-layer / n-layer film formation.

In addition, masks such as substrate trays can be designed with a certain degree of freedom according to the design of solar cells, as compared with resists.

(Method for manufacturing the solar cell of the second embodiment)
In the second embodiment, the lift-off method using the lift-off layer is used.
Next, the method for manufacturing the solar cell 1 of the present embodiment shown in FIGS. 1 and 2 will be described with reference to FIGS. 10A to 10G. FIG. 10A is a diagram showing an intrinsic semiconductor layer forming step and an optical adjusting layer forming step in the method for manufacturing a solar cell according to the second embodiment. FIG. 10B is a diagram showing a first semiconductor layer material film forming step and a lift-off layer forming step in the method for manufacturing a solar cell according to the second embodiment, and FIGS. 10C to 10E are views of the solar cell according to the second embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of. FIG. 10F is a diagram showing a second semiconductor layer material film forming step in the method for manufacturing a solar cell according to the second embodiment, and FIG. 10G is a diagram showing a second semiconductor layer in the method for manufacturing a solar cell according to the second embodiment. It is a figure which shows the forming process.

First, as shown in FIG. 10A, the intrinsic semiconductor layer 13 is laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side by using, for example, the CVD method in the same manner as described above (intrinsic semiconductor layer forming step). Next, for example, using a CVD method, the optical adjustment layer 15 is laminated (film-formed) on the entire surface of the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11 (optical adjustment layer forming step).

Next, as shown in FIG. 10B, the first intrinsic semiconductor layer material film 23Z and the first conductive type semiconductor layer material film 25Z are laminated in order on the back surface side of the semiconductor substrate 11 by using, for example, the CVD method in the same manner as described above. Film formation). At this time, with the outer peripheral edge region R on the back surface side of the semiconductor substrate 11 masked by the substrate tray 3, the first intrinsic semiconductor layer material film is formed on the first region 7 and the second region 8 on the back surface side of the semiconductor substrate 11. 23Z and the first conductive type semiconductor layer material film 25Z are formed (first semiconductor layer material film forming step).

Next, for example, using the CVD method, the lift-off layer 50 is laminated (film-formed) on the first conductive semiconductor layer material film 25Z on the back surface side of the semiconductor substrate 11. At this time, the lift-off layer 50 is formed in the first region 7 and the second region 8 on the back surface side of the semiconductor substrate 11 in a state where the outer peripheral edge region R on the back surface side of the semiconductor substrate 11 is masked by the substrate tray 3 ( Lift-off layer forming process).
The lift-off layer 50 can be formed of, for example, an inorganic material. If formed from materials such as silicon oxide (SiO), silicon nitride (SiN), or composites thereof such as silicon oxynitride (SiON), hydrofluoric acid treatment (hydrofluoric acid, or hydrofluoric acid and other types). If lift-off proceeds with (treatment with a mixture of acids) and is formed from materials such as their composites such as ITO and ZnO, then acid treatment (hydrochloric acid, nitric acid, or theirs and other types of acids) Lift-off proceeds by treatment with a mixture with and is easily removed.
In particular, when the lift-off layer 50 is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON), the lift-off layer has two or more layers or more. Higher lift-off performance can be obtained by using a multi-layer structure. For example, in the case of a two-layer structure, a lift-off layer is formed in the order of a first lift-off layer and a second lift-off layer on the first conductive semiconductor layer material film 25Z, and these layers are etched by the first conductive semiconductor layer material film 25Z. With respect to the liquid, the etching rate of the first conductive semiconductor layer material film 25Z <the etching rate of the second lift-off layer <the etching rate of the first lift-off layer ... [Relational formula 1] is satisfied.

Next, as shown in FIGS. 10C to 10E, for example, using the resist 40, the first intrinsic semiconductor layer material film 23Z and the first conductive semiconductor layer material film 25Z in the second region 8 on the back surface side of the semiconductor substrate 11 By removing the lift-off layer 50 and the lift-off layer 50, the patterned first intrinsic semiconductor layer 23, the first conductive semiconductor layer 25, and the lift-off layer 50 are formed in the first region 7 on the back surface side of the semiconductor substrate 11. At this time, the first region 7 and the outer peripheral region R on the back surface side of the semiconductor substrate 11 and the entire surface on the light receiving surface side are covered with the resist 40, and the first intrinsic semiconductor layer material film 23Z and the first conductive semiconductor layer material film are covered. Patterning of 25Z and the lift-off layer 50 is performed (first semiconductor layer forming step).

Specifically, the photoresist is applied to the entire surface of the semiconductor substrate 11 on both sides by using the photolithography method in the same manner as described above, and then the photoresist in the second region 8 on the back surface side is exposed and developed using a mask. To remove. As a result, as shown in FIG. 10C, a resist 40 that covers the first region 7 and the outer peripheral region R on the back surface side of the semiconductor substrate 11 and the entire surface on the light receiving surface side is formed.

After that, as shown in FIG. 10D, using the resist 40 as a mask, the first intrinsic semiconductor layer material film 23Z, the first conductive semiconductor layer material film 25Z, and the lift-off layer 50 in the second region 8 on the back surface side of the semiconductor substrate 11 are formed. It is etched to form a patterned first intrinsic semiconductor layer 23, a first conductive semiconductor layer 25, and a lift-off layer 50 in the first region 7 on the back surface side of the semiconductor substrate 11. As the etching solution for the first intrinsic semiconductor layer material film, the first conductive semiconductor layer material film and the lift-off layer, an acidic solution such as a mixed solution of hydrofluoric acid and nitric acid is used as described above.

After that, as shown in FIG. 10E, the resist 40 is removed. As the stripping solution for the resist 40, an organic solvent such as acetone is used according to the type of resist as described above.

Next, as shown in FIG. 10F, in the same manner as described above, for example, the CVD method is used to cover the entire surface of the semiconductor substrate 11 on the back surface side, that is, the first region 7, the second region 8, and the outer peripheral region R. The second intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z are placed on the lift-off layer 50 in the first region 7 and on the semiconductor substrate 11 in the second region 8 and the outer peripheral region R. Laminate (film formation) in order. At this time, the second intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z are formed by the substrate tray 3 in a state of being held in the opposite direction (second semiconductor layer material film forming step).

Next, as shown in FIG. 10G, the second intrinsic semiconductor layer material film 33Z and the second conductivity in the first region 7 on the back surface side of the semiconductor substrate 11 are used by using the lift-off method using the lift-off layer (sacrificial layer). The type semiconductor layer material film 35Z is removed, and a patterned second intrinsic semiconductor layer 33 and a second conductive semiconductor layer 35 are formed in the second region 8 and the outer peripheral region R on the back surface side of the semiconductor substrate 11 ( Second semiconductor layer forming step).

Specifically, by removing the lift-off layer 50, the second intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z on the lift-off layer 50 are removed, and the second intrinsic semiconductor layer 33 and the second. The conductive semiconductor layer 35 is formed. As the removal solution for the lift-off layer 50, an acidic solution such as hydrofluoric acid or hydrochloric acid is used, depending on the configuration of the lift-off layer 50.

Then, in the same manner as described above, the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
Through the above steps, the back electrode type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 is completed.

The solar cell manufacturing method of the second embodiment can also obtain the same advantages as the solar cell manufacturing method of the first embodiment described above.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and modifications can be made. For example, in the above-described embodiment, the method for manufacturing the heterozygous solar cell 1 is illustrated as shown in FIG. 2, but the feature of the present invention is not limited to the heterozygous solar cell, but the homozygous solar cell. It can be applied to various methods for manufacturing solar cells such as batteries.

Further, in the above-described embodiment, a solar cell having a crystalline silicon substrate has been exemplified, but the present invention is not limited to this. For example, a solar cell may have a gallium arsenide (GaAs) substrate.

1 Solar cell 7

1st area

7b, 8b

Bus bar part

7f, 8f Finger part 8 2nd area 11 Semiconductor substrate 13 Intrinsic semiconductor layer 15 Optical adjustment layer 23 1st intrinsic semiconductor layer 23Z 1st intrinsic semiconductor layer Material film 25 1st conductivity Type semiconductor layer 25Z 1st conductive type semiconductor layer Material film 27 1st electrode layer 28,38

Transparent electrode layer

29,39 Metal electrode layer 33 2nd intrinsic semiconductor layer 33Z 2nd intrinsic semiconductor layer Material film 35 2nd conductive type semiconductor layer 35Z 2nd conductive semiconductor layer Material film 37 2nd electrode layer 40 Resist 50 Lift-off layer (sacrificial layer)
R outer peripheral area

Claims

A semiconductor substrate, a first conductive semiconductor layer and a first electrode layer laminated in order in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and the semiconductor substrate. A method for manufacturing a back electrode type solar cell including a second conductive semiconductor layer and a second electrode layer which are sequentially laminated in a second region which is another part on the other main surface side.
In a state where the outer peripheral edge region on the other main surface side of the semiconductor substrate is masked, the material film of the first conductive semiconductor layer is formed on the first region and the second region on the other main surface side of the semiconductor substrate. First semiconductor layer material film forming step to form
By covering the first region and the outer peripheral region on the other main surface side of the semiconductor substrate with a resist and removing the material film of the first conductive semiconductor layer in the second region, the first region In the first semiconductor layer forming step of forming the patterned first conductive semiconductor layer and removing the resist.
On the entire surface of the semiconductor substrate including the first region, the second region, and the outer peripheral region on the other main surface side, above the first conductive semiconductor layer in the first region, and in the second region and A second semiconductor layer material film forming step of forming a material film of the second conductive semiconductor layer on the semiconductor substrate in the outer peripheral region.
By covering the second region and the outer peripheral region on the other main surface side of the semiconductor substrate with a resist and removing the material film of the second conductive semiconductor layer in the first region, the second region A second semiconductor layer forming step of forming the patterned second conductive semiconductor layer in the outer peripheral region, and
Manufacturing methods for solar cells, including.
A semiconductor substrate, a first conductive semiconductor layer and a first electrode layer laminated in order in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and the semiconductor substrate. A method for manufacturing a back electrode type solar cell including a second conductive semiconductor layer and a second electrode layer which are sequentially laminated in a second region which is another part on the other main surface side.
In a state where the outer peripheral edge region on the other main surface side of the semiconductor substrate is masked, the material film of the first conductive semiconductor layer is formed on the first region and the second region on the other main surface side of the semiconductor substrate. First semiconductor layer material film forming step to form
A lift-off layer forming step of forming a lift-off layer on the material film of the first conductive semiconductor layer,
By covering the first region and the outer peripheral region on the other main surface side of the semiconductor substrate with a resist, the material films of the lift-off layer and the first conductive semiconductor layer in the second region are removed. A first semiconductor layer forming step of forming the patterned first conductive semiconductor layer and the lift-off layer in the first region and removing the resist.
On the entire surface of the semiconductor substrate including the first region, the second region, and the outer peripheral region on the other main surface side, above the lift-off layer in the first region, and on the second region and the outer peripheral region. The second semiconductor layer material film forming step of forming the material film of the second conductive type semiconductor layer on the semiconductor substrate in
By removing the lift-off layer, the material film of the second conductive semiconductor layer in the first region is removed, and the second conductive semiconductor layer patterned in the second region and the outer peripheral region. The second semiconductor layer forming step of forming
Manufacturing methods for solar cells, including.
In the first semiconductor layer forming step, the one main surface side of the semiconductor substrate is covered with a resist, and the material film of the first conductive semiconductor layer is patterned.
In the second semiconductor layer forming step, the one main surface side of the semiconductor substrate is covered with a resist to pattern the material film of the second conductive semiconductor layer.
The method for manufacturing a solar cell according to claim 1 or 2.
A semiconductor substrate, a first conductive semiconductor layer and a first electrode layer laminated in order in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and the semiconductor substrate. A back electrode type solar cell including a second conductive semiconductor layer and a second electrode layer which are sequentially laminated in a second region which is another part of the other main surface side.
A solar cell in which the second conductive semiconductor layer is formed in an outer peripheral region of the semiconductor substrate on the other main surface side.
The solar cell according to claim 4, wherein the outer peripheral edge region is a region having a width of 5 mm or less from the edge of the semiconductor substrate toward the center of the semiconductor substrate.