WO2020199283A1 - 集成电路光学芯片光圈测试方法 - Google Patents

集成电路光学芯片光圈测试方法 Download PDF

Info

Publication number
WO2020199283A1
WO2020199283A1 PCT/CN2019/084298 CN2019084298W WO2020199283A1 WO 2020199283 A1 WO2020199283 A1 WO 2020199283A1 CN 2019084298 W CN2019084298 W CN 2019084298W WO 2020199283 A1 WO2020199283 A1 WO 2020199283A1
Authority
WO
WIPO (PCT)
Prior art keywords
array
coordinates
aperture
radius
integrated circuit
Prior art date
Application number
PCT/CN2019/084298
Other languages
English (en)
French (fr)
Inventor
王�华
张志勇
邓维维
余琨
季海英
罗斌
Original Assignee
上海华岭集成电路技术股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海华岭集成电路技术股份有限公司 filed Critical 上海华岭集成电路技术股份有限公司
Priority to GB1908724.6A priority Critical patent/GB2590048B/en
Priority to US16/442,379 priority patent/US10977469B2/en
Publication of WO2020199283A1 publication Critical patent/WO2020199283A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING OF STRUCTURES OR APPARATUS, NOT OTHERWISE PROVIDED FOR
    • G01M11/00—Testing of optical apparatus; Testing structures by optical methods not otherwise provided for
    • G01M11/02—Testing optical properties
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/9501—Semiconductor wafers
    • G01N21/9505—Wafer internal defects, e.g. microcracks
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/303—Contactless testing of integrated circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N2021/9511—Optical elements other than lenses, e.g. mirrors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the technical solution is applied to under-screen fingerprint chip testing, and specifically is an integrated circuit optical chip aperture testing method.
  • Figure 1 is an image restored by the captured data from the fingerprint recognition chip under a 208*160 array screen.
  • the conventional test algorithm is to capture the data of the array, and use the current mature algorithm to calculate the image average, row/column average to find out the bad rows, bad columns, the bad pixels in the image, shading (the part with large brightness difference) and other parameters , These detection methods or algorithms are all tested based on the rows, columns, points, and blocks of the array.
  • the fingerprint chip under the screen will have an aperture phenomenon under certain specific faults or conditions.
  • the pixel unit with the aperture itself is not the maximum or minimum value in the row, column, or fixed area, so the aperture cannot be detected by the above algorithm If it fails, the method for testing the aperture of the integrated circuit optical chip provided by the solution of this application is to solve the above-mentioned problems in the aperture test.
  • the technical solution adopted by the present invention to solve the above technical problems is to provide an integrated circuit optical chip aperture test method.
  • a light source is used to illuminate the photosensitive array of the chip to be tested (for example, 208*160, a total of 33280 pixels) ,
  • Each pixel of the photosensitive array generates a weak current according to different illuminances, the current is output through the internal AD converter, and the test captures the data output by the AD converter through the ATE device, and calculates all the pixel data to obtain the corresponding chip technical parameters among them.
  • the opening of the probe card is determined according to the photosensitive area of the device under test, and the light source illuminates the photosensitive array of the device vertically through the position of the needle card opening;
  • test system digital signal generator generates the protocol vector access chip, and the digital sampling unit obtains the chip pixel output;
  • the captured image array is processed according to the concept of circle.
  • the processing method is divided by radius to obtain a circular pattern, which is reconstructed into another two-dimensional array according to the coordinates. Perform the corresponding operation on the obtained array, and finally get the required value;
  • the above-mentioned method for testing the aperture of an integrated circuit optical chip includes: 1) step.
  • each coordinate in the array can be expressed as X and Y, and the value corresponding to the coordinate is the pixel value of the point.
  • the above method for testing the aperture of an integrated circuit optical chip includes: 3) steps, forming a circle with left -80, 0, center 0, 0, right 80, 0, upper 0, 80, and lower 0, -80.
  • steps form a two-dimensional array in the following manner:
  • the present invention Compared with the prior art, the present invention has the following beneficial effects: without increasing any additional hardware cost and using the original test conditions, the present invention solves the current industry no mature coverage screen fingerprint chip aperture test method and algorithm technology problem.
  • Figure 1 is a schematic diagram of the image restored by the data captured by the fingerprint recognition chip under the 208*160 array screen.
  • Figure 2 is a schematic diagram of the aperture phenomenon of the defective chip.
  • Figure 4 is a diagram of the test system architecture.
  • ATE Automatic Test Equipment: A semiconductor integrated circuit (IC) automatic test machine used to test the integrity of integrated circuit functions.
  • Wafer The silicon wafer used in the production of silicon semiconductor integrated circuits is called a wafer because of its circular shape. Various circuit element structures can be processed on the silicon wafer to become IC products with specific electrical functions.
  • This technical solution finds out the defective chip with the aperture phenomenon by re-arranging and calculating the pixel units in the photosensitive array of the fingerprint recognition chip under the screen, as shown in FIG. 2.
  • the application plan is carried out as follows:
  • the probe card opening is determined according to the photosensitive area of the device under test, and the light source illuminates the device photosensitive array vertically through the needle card opening position;
  • the device under test is powered on, the chip is initialized and other operations, the test system digital signal generator generates the protocol vector to access the chip, and the digital sampling unit obtains the chip pixel output.
  • the automatic test system captures the output of the device under test through the test module, restores each element of the image array, and arranges each element of the image into two according to X ⁇ Y coordinates through software algorithms.
  • Dimensional array usually each coordinate in the array can be expressed as (X, Y), and the value corresponding to the coordinate is the pixel value of the point;
  • R the maximum radius of the aperture
  • the elements in the one-dimensional array M are operated according to the principle of adjacent subtraction, such as:
  • the technical solution provided by the present invention is a testing algorithm. According to the above steps, firstly, the captured image array is processed according to the concept of "circle". The processing method is to divide by radius to obtain one circle The pattern is reconstructed into another two-dimensional array according to the coordinates, and then the corresponding operation is performed on the obtained array to finally obtain the required value.
  • the present invention proposes The technical solution uses a circular pattern method to detect a specific device failure model, which makes up for the shortcomings of conventional algorithms.
  • the main innovation in the technical solution of the present invention is to design this new pattern.
  • the algorithm for obtaining the pattern And the algorithm for computing judgment is not limited.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Analytical Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Immunology (AREA)
  • Biochemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Pathology (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Input (AREA)
  • Image Analysis (AREA)
  • Collating Specific Patterns (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

一种集成电路光学芯片光圈测试方法，对抓取到的图像阵列按照圆的概念进行处理，处理的方法即是通过半径来划分，得到一个一个的圆形图案，按照坐标进行重构为另外的一个二维数组，然后对得到的数组进行相应的运算，最终得到需要的值；该测试方法在不增加任何的额外硬件成本，使用原有的测试条件下，解决了目前行业内无成熟覆盖屏幕指纹芯片光圈故障的测试方法和算法的技术问题。

Description

集成电路光学芯片光圈测试方法 技术领域
本技术方案应用于屏下指纹芯片测试，具体是一种集成电路光学芯片光圈测试方法。
背景技术
现有技术中，对于集成电路光学芯片光圈测试，通常情况下采用垂直的均匀光照射芯片感光阵列，每个像素输出是均匀分布，因为芯片本身特性，中间像素感光照度较高，边缘较低，图1为一款208*160阵列屏下指纹识别芯片通过抓取到的数据还原的图像。常规的测试算法是将阵列的数据抓取到以后，通过目前成熟的算法计算图像均值、行/列均值找出坏行坏列、图像中坏点、Shading(亮度差异较大的部分)等参数，这些检测方法或者说算法都是基于阵列的行、列、点、块进行测试。屏下指纹芯片在某些特定故障或者条件下会出现光圈的现象，出现光圈的像素单元本身在行、列、或者固定区域内都不是最大或者最小值，从而通过以上的算法无法检测出光圈的失效，本申请方案提供的集成电路光学芯片光圈测试方法，即是解决光圈测试中的上述问题。
发明内容
本发明为解决上述技术问题而采用的技术方案是提供一种集成电路光学芯片光圈测试方法，屏下指纹芯片测试中通过使用光源照射待测芯片感光阵列(比如208*160，共计33280个像素)，感光阵列每个像素根据不同的光照度产生微弱电流，电流经过内部AD转换器输出，测试通过ATE设备抓取AD转换器输出的数据，通过对所有像素数据进行运算，从而得到相应的芯片技术参数其中。
为实现上述技术效果，本发明采用的具体技术方案为：
(1)搭建测试环境，通过在探针卡背面固定LED光源，测试系统与LED光源连接，通过USB或者GPIB等方式控制调整光源亮度；
(2)探针卡开孔根据待测器件感光面积所决定，光源透过针卡开孔位置垂直照射到器件感光阵列；
(3)待测器件上电，芯片初始化等操作，测试系统数字信号发生器产生协议向量访问芯片，并由数字采样单元获取芯片像素输出；
(4)对抓取到的图像阵列按照圆的概念进行处理，处理的方法即是通过半径来划分，得到一个一个的圆形图案，按照坐标进行重构为另外的一个二维数组，然后对得到的数组进行相应的运算，最终得到需要的值；
具体如下步骤进行：
1)抓取到图像，将图像按照X、Y坐标排列成二维阵列；
2)根据待测阵列的尺寸，以阵列的行Y、列X值小的一半为光圈的最大半径R；
3)以原图像中心坐标为圆心，坐标0 0，将原图像进行转换；
4)从圆心为坐标中心，半径为1开始，查找在圆半径上的坐标；
5)根据选取的坐标以R为半径重新构成一个二维数组；
6)按照行数组求取每个数组中所有坐标对应像素的均值；
7)将得到的均值转换为一维数组，M[]＝[M1,M2,M3……MN]；
8)将一维数组M中元素按照相邻相减的原则进行运算；
X1＝M2-M1；
X2＝M3-M2；
XN-1＝MN-MN-1
通过运算后得到一维数组X[]＝[X1,X2……XN-1]；
9)求取数组X绝对值最大值；
将绝对值最大值与需要进行光圈判断的标准进行比较，超过标准值即判断为光圈测试失效，否则即为合格。
上述的集成电路光学芯片光圈测试方法，其中：1)步骤，通常情况下阵列中每个坐标可以表示为X、Y，该坐标对应的值即为该点的像素值。
上述的集成电路光学芯片光圈测试方法，其中：3)步骤，构成左-80、0，中心0、0，右80、0，上0、80，下0、-80的一个圆。
上述的集成电路光学芯片光圈测试方法，其中：4)步骤，查找方式如下：
R＝1,2,3,4……N；
R＝1时，以R为半径，X,Y坐标取最接近半径R的坐标。
上述的集成电路光学芯片光圈测试方法，其中：5)步骤构成一个二维数组，方式如下：
Array[R＝1]＝[(1,0)，(0,1)，(-1，0)，(0，-1)]
Array[R＝2]＝[(2,0)，(2,1)，(1,2)，(0,2),(-1,2)，(-2,1)，(-2,0)，(-2，-1)，(-1，-2)，(0，-2)，(1，-2)，(2，-1)]
…
Array[R＝N]＝[()，()，()…]。
本发明相对于现有技术具有如下有益效果：在不增加任何的额外硬件成本，使用原有的测试条件下，本发明解决目前行业内无成熟覆盖屏幕指纹芯片光圈故障的测试方法和算法的技术问题。
附图说明
图1为208*160阵列屏下指纹识别芯片通过抓取到的数据还原的图像示意图。
图2为故障芯片存在光圈现象的示意图。
图3为以R＝6为选取坐标，圆心为坐标中心，从半径为1开始查找在圆半径上的坐标的示意图。
图4为测试系统架构图。
具体实施方式
ATE(Automatic Test Equipment)：一种半导体集成电路(IC)自动测试机，用于检测集成电路功能之完整性。
晶圆：硅半导体集成电路制作所用的硅晶片，由于其形状为圆形，故称为晶圆；在硅晶片上可加工制作成各种电路元件结构，成为有特定电性功能之IC产品。
本技术方案通过对屏下指纹识别芯片感光阵列中像素单元从新排列和计算，从而找出存在光圈现象的故障芯片，如图2所示。
本申请方案按照如下步骤进行：
1、搭建测试环境，通过在探针卡背面固定LED光源，测试系统与LED光源连接，通过USB或者GPIB等方式控制调整光源亮度；
2、探针卡开孔根据待测器件感光面积所决定，光源透过针卡开孔位置垂直照射到器件感光阵列；
3、待测器件上电，芯片初始化等操作，测试系统数字信号发生器产生协议向量访问芯片，并由数字采样单元获取芯片像素输出。
4、自动测试系统(ATE)通过测试模块抓取待测器件的输出，并将图像阵列的每个元素进行像素点的还原，通过软件算法将图像的每个元素按照X\Y坐标排列成二维阵列，通常情况下阵列中每个坐标可以表示为(X,Y)，该坐标对应的值即为该 点的像素值；
2、根据待测阵列的尺寸，以阵列的行(Y)、列(X)值小的一半为光圈的最大半径(R)，比如208*160，以160/2＝80作为需要进行图像光圈分析的光圈最大半径；
3、以原图像中心坐标为圆心(坐标0,0)将原图像进行转换，构成左(-80,0)中心(0,0)右(80,0)上(0,80)下(0，-80)的一个圆。
4、从圆心为坐标中心，半径为1开始，查找在圆半径上的坐标，查找方式如下：
R＝1,2,3,4……N；
R＝1时，以R为半径，X,Y坐标取最接近半径R的坐标，本实施案例不限定选取的算法，如图3所示，为以R＝6选取的坐标。
5、根据选取的坐标以R为半径重新构成一个二维数组，如：
Array[R＝1]＝[(1,0)，(0,1)，(-1，0)，(0，-1)]
Array[R＝2]＝[(2,0)，(2,1)，(1,2)，(0,2),(-1,2)，(-2,1)，(-2,0)，(-2，-1)，(-1，-2)，(0，-2)，(1，-2)，(2，-1)]
…
Array[R＝N]＝[()，()，()…]
6、按照行数组求取每个数组中所有坐标对应像素的均值；
7、将得到的均值转换为一维数组，如M[]＝[M1,M2,M3……MN]；
8、将一维数组M中元素按照相邻相减的原则进行运算，如：
X1＝M2-M1；
X2＝M3-M2；
XN-1＝MN-MN-1
通过运算后得到一维数组X[]＝[X1,X2……XN-1]
9、求取数组X绝对值最大值；
将绝对值最大值与需要进行光圈判断的标准进行比较，超过标准值即判断为光圈测试失效，否则即为合格；
本发明提供的技术方案是一种测试算法，根据上述步骤，首先，对抓取到的图像阵列按照“圆”的概念进行处理，处理的方法即是通过半径来划分，得到一个一个的圆形图案，按照坐标进行重构为另外的一个二维数组，然后对得到的数组进行相应的运算，最终得到需要的值。
针对光学芯片的测试，行业中普遍的算法都是基于图形阵列的“行、列、点、块”去进行处理，这不可避免的对一些特定器件故障造成无法进行准确检测的目的，本发明提出的技术方案，通过一种圆形图案的方法去检测特定的器件故障模型，弥补了常规算法的缺陷，本发明技术方案中主要的创新性是设计出这种新型的图案，至于获取图案的算法，以及进行运算判断的算法都是不局限的。

Claims (5)

  1. 一种集成电路光学芯片光圈测试方法，搭建测试环境，通过在探针卡背面固定LED光源，测试系统与LED光源连接；探针卡开孔根据待测器件感光面积所决定，光源透过针卡开孔位置照射到器件感光阵列；待测器件上电，芯片初始化，测试系统数字信号发生器产生协议向量访问芯片，并由数字采样单元获取芯片像素输出；
    其特征在于：
    对抓取到的图像阵列按照圆的概念进行处理，处理的方法即是通过半径来划分，得到一个一个的圆形图案，按照坐标进行重构为另外的一个二维数组，然后对得到的数组进行相应的运算，最终得到需要的值；
    具体如下步骤进行：
    1)抓取到图像，将图像按照X、Y坐标排列成二维阵列；
    2)根据待测阵列的尺寸，以阵列的行Y、列X值小的一半为光圈的最大半径R；
    3)以原图像中心坐标为圆心，坐标0 0，将原图像进行转换；
    4)从圆心为坐标中心，半径为1开始，查找在圆半径上的坐标；
    5)根据选取的坐标以R为半径重新构成一个二维数组；
    6)按照行数组求取每个数组中所有坐标对应像素的均值；
    7)将得到的均值转换为一维数组，M[]＝[M1,M2,M3……MN]；
    8)将一维数组M中元素按照相邻相减的原则进行运算；
    X1＝M2-M1；
    X2＝M3-M2；
    XN-1＝MN-MN-1
    通过运算后得到一维数组X[]＝[X1,X2……XN-1]；
    9)求取数组X绝对值最大值；
    将绝对值最大值与需要进行光圈判断的标准进行比较，超过标准值即判断为光圈测试失效，否则即为合格。
  2. 如权利要求1所述的集成电路光学芯片光圈测试方法，其特征在于：1)步骤，通常情况下阵列中每个坐标可以表示为X、Y，该坐标对应的值即为该点的像素值。
  3. 如权利要求2所述的集成电路光学芯片光圈测试方法，其特征在于：3)步骤，构成左-80、0，中心0、0，右80、0，上0、80，下0、-80的一个圆。
  4. 如权利要求2所述的集成电路光学芯片光圈测试方法，其特征在于：4)步骤，查找方式如下：
    R＝1,2,3,4……N；
    R＝1时，以R为半径，X,Y坐标取最接近半径R的坐标。
  5. 如权利要求1-4中任一项所述的集成电路光学芯片光圈测试方法，其特征在于，5)步骤构成一个二维数组，方式如下：
    Array[R＝1]＝[(1,0)，(0,1)，(-1，0)，(0，-1)]
    Array[R＝2]＝[(2,0)，(2,1)，(1,2)，(0,2),(-1,2)，(-2,1)，(-2,0)，(-2，-1)，(-1，-2)，(0，-2)，(1，-2)，(2，-1)]
    …
    Array[R＝N]＝[()，()，()…]。
PCT/CN2019/084298 2019-03-29 2019-04-25 集成电路光学芯片光圈测试方法 WO2020199283A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB1908724.6A GB2590048B (en) 2019-03-29 2019-04-25 Halo test method for an optical chip in an integrated circuit
US16/442,379 US10977469B2 (en) 2019-03-29 2019-06-14 Halo test method for an optical chip in an integrated circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910251137.7A CN110031188B (zh) 2019-03-29 2019-03-29 集成电路光学芯片光圈测试方法
CN201910251137.7 2019-03-29

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/442,379 Continuation US10977469B2 (en) 2019-03-29 2019-06-14 Halo test method for an optical chip in an integrated circuit

Publications (1)

Publication Number Publication Date
WO2020199283A1 true WO2020199283A1 (zh) 2020-10-08

Family

ID=67236986

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/084298 WO2020199283A1 (zh) 2019-03-29 2019-04-25 集成电路光学芯片光圈测试方法

Country Status (2)

Country Link
CN (1) CN110031188B (zh)
WO (1) WO2020199283A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112700415A (zh) * 2020-12-31 2021-04-23 重庆宇海精密制造股份有限公司 一种笔电外壳缺陷快速检测算法
CN117058004A (zh) * 2023-10-13 2023-11-14 珠海埃克斯智能科技有限公司 晶圆的晶粒图像重构方法、电子设备及存储介质

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2590048B (en) * 2019-03-29 2023-08-30 Sino Ic Tech Co Ltd Halo test method for an optical chip in an integrated circuit
CN110031188B (zh) * 2019-03-29 2021-08-27 上海华岭集成电路技术股份有限公司 集成电路光学芯片光圈测试方法
CN110488175B (zh) * 2019-07-31 2024-04-26 广东利扬芯片测试股份有限公司 指纹芯片测试部件、方法和计算机可读存储介质
CN111341685A (zh) * 2020-03-06 2020-06-26 普迪飞半导体技术(上海)有限公司 裸芯片的异常值检测方法、装置、电子设备与存储介质

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1825421A (zh) * 2005-02-25 2006-08-30 祥硕科技股份有限公司 面板区域不均匀性补偿装置与方法
CN106033171A (zh) * 2015-03-11 2016-10-19 中芯国际集成电路制造(上海)有限公司 用于晶圆上坏点的失效分析的方法
CN106298569A (zh) * 2016-07-28 2017-01-04 深圳芯启航科技有限公司 一种图像芯片的量产测试方法及装置
CN107579028A (zh) * 2017-09-12 2018-01-12 北京中电科电子装备有限公司 一种残缺晶圆的边沿确定方法、装置及划片装置
CN108107309A (zh) * 2018-02-11 2018-06-01 苏州晶方半导体科技股份有限公司 集成电路测试系统
US10094874B1 (en) * 2011-12-01 2018-10-09 National Technology & Engineering Solutions Of Sandia, Llc Scanning method for screening of electronic devices
CN110031188A (zh) * 2019-03-29 2019-07-19 上海华岭集成电路技术股份有限公司 集成电路光学芯片光圈测试方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990018125A (ko) * 1997-08-26 1999-03-15 윤종용 Ic칩 검사용 테스터데이타 압축방법과 그 압축장치 및 ic칩용 테스터장치와 그 테스터방법
KR100466984B1 (ko) * 2002-05-15 2005-01-24 삼성전자주식회사 테스트 소자 그룹 회로를 포함하는 집적 회로 칩 및 그것의 테스트 방법
JP4136832B2 (ja) * 2003-07-15 2008-08-20 キヤノン株式会社 半導体レーザーダイオードチップの検査方法および検査装置
CN101777118A (zh) * 2010-03-16 2010-07-14 刘国传 一种基于参数化变形模板的生物芯片图像样点自动识别方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1825421A (zh) * 2005-02-25 2006-08-30 祥硕科技股份有限公司 面板区域不均匀性补偿装置与方法
US10094874B1 (en) * 2011-12-01 2018-10-09 National Technology & Engineering Solutions Of Sandia, Llc Scanning method for screening of electronic devices
CN106033171A (zh) * 2015-03-11 2016-10-19 中芯国际集成电路制造(上海)有限公司 用于晶圆上坏点的失效分析的方法
CN106298569A (zh) * 2016-07-28 2017-01-04 深圳芯启航科技有限公司 一种图像芯片的量产测试方法及装置
CN107579028A (zh) * 2017-09-12 2018-01-12 北京中电科电子装备有限公司 一种残缺晶圆的边沿确定方法、装置及划片装置
CN108107309A (zh) * 2018-02-11 2018-06-01 苏州晶方半导体科技股份有限公司 集成电路测试系统
CN110031188A (zh) * 2019-03-29 2019-07-19 上海华岭集成电路技术股份有限公司 集成电路光学芯片光圈测试方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112700415A (zh) * 2020-12-31 2021-04-23 重庆宇海精密制造股份有限公司 一种笔电外壳缺陷快速检测算法
CN112700415B (zh) * 2020-12-31 2024-05-17 重庆宇海精密制造股份有限公司 一种笔电外壳缺陷快速检测算法
CN117058004A (zh) * 2023-10-13 2023-11-14 珠海埃克斯智能科技有限公司 晶圆的晶粒图像重构方法、电子设备及存储介质
CN117058004B (zh) * 2023-10-13 2024-03-08 埃克斯工业有限公司 晶圆的晶粒图像重构方法、电子设备及存储介质

Also Published As

Publication number Publication date
CN110031188B (zh) 2021-08-27
CN110031188A (zh) 2019-07-19

Similar Documents

Publication Publication Date Title
WO2020199283A1 (zh) 集成电路光学芯片光圈测试方法
JP3668215B2 (ja) パターン検査装置
JP4776308B2 (ja) 画像欠陥検査装置、画像欠陥検査システム、欠陥分類装置及び画像欠陥検査方法
US10762621B2 (en) Semiconductor wafer measurement method and system
JPS6239815B2 (zh)
JP2004177397A (ja) 画像欠陥検査方法、画像欠陥検査装置及び外観検査装置
JPH03232250A (ja) パターン検査方法および装置
US20080260236A9 (en) Image defect inspection method, image defect inspection apparatus, and appearance inspection apparatus
KR20120014886A (ko) 검사 레시피 생성 및 검사 레시피를 기반으로 한 검사
JP2012049503A (ja) 半導体装置の検査装置及び半導体装置の検査方法
US20140002121A1 (en) System and method for electronic testing of partially processed devices
KR100814410B1 (ko) 반도체 소자가 형성된 기판의 결함 검출방법
JP2007188968A (ja) ウエーハマップデータの解析方法および解析プログラム
WO2003071298A1 (en) Pica system detector calibration
JP4111613B2 (ja) 半導体検査方法及び装置
CN103645197B (zh) 芯片缺陷的检测方法
CN113299572A (zh) 一种芯片缺陷检测方法
CN113971651A (zh) 检测方法以及检测装置、电子设备和存储介质
JP2900858B2 (ja) Ｃｍｏｓ論理回路の故障箇所特定方法
JP2008046012A (ja) 欠陥検出装置および欠陥検出方法
US20140281777A1 (en) Localizing Fault Flop in Circuit by Using Modified Test Pattern
CN116263559A (zh) 基于机器学习预测待测图形上的光学临近效应缺陷的方法
GB2590048A (en) Circular defect testing method for optical chip of integrated circuit
US11449984B2 (en) Method and system for diagnosing a semiconductor wafer
US20230334647A1 (en) Wafer inspection system

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 201908724

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20190425

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19923293

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19923293

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 23/11/2021)

122 Ep: pct application non-entry in european phase

Ref document number: 19923293

Country of ref document: EP

Kind code of ref document: A1