WO2020195748A1 - Feuille métallique pour carte à circuit imprimé, feuille métallique avec support, et stratifié plaqué de métal, et procédé de fabrication de carte à circuit imprimé l'utilisant - Google Patents

Feuille métallique pour carte à circuit imprimé, feuille métallique avec support, et stratifié plaqué de métal, et procédé de fabrication de carte à circuit imprimé l'utilisant Download PDF

Info

Publication number
WO2020195748A1
WO2020195748A1 PCT/JP2020/010017 JP2020010017W WO2020195748A1 WO 2020195748 A1 WO2020195748 A1 WO 2020195748A1 JP 2020010017 W JP2020010017 W JP 2020010017W WO 2020195748 A1 WO2020195748 A1 WO 2020195748A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
etching
sacrificial layer
etching sacrificial
metal foil
Prior art date
Application number
PCT/JP2020/010017
Other languages
English (en)
Japanese (ja)
Inventor
翼 加藤
光由 松田
Original Assignee
三井金属鉱業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三井金属鉱業株式会社 filed Critical 三井金属鉱業株式会社
Priority to JP2021508964A priority Critical patent/JP7449921B2/ja
Priority to CN202080023976.4A priority patent/CN113646469A/zh
Priority to KR1020217024157A priority patent/KR20210143727A/ko
Publication of WO2020195748A1 publication Critical patent/WO2020195748A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D1/00—Electroforming
    • C25D1/04—Wires; Strips; Foils
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/06—Wires; Strips; Foils
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/06—Wires; Strips; Foils
    • C25D7/0614—Strips or foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material

Definitions

  • the present invention relates to a metal foil for manufacturing a printed wiring board, a metal foil with a carrier, a metal-clad laminate, and a method for manufacturing a printed wiring board using them.
  • the MSAP method (modified semi-additive method) has been widely adopted as a manufacturing method for printed wiring boards suitable for circuit miniaturization.
  • the MSAP method is a method suitable for forming an extremely fine circuit, and in order to take advantage of its characteristics, it is performed using a copper foil with a carrier.
  • the ultrathin copper foil 110 is pressed and adhered to the insulating resin substrate 111 having the lower layer circuit 111b on the base material 111a by using the prepreg 112 and the primer layer 113.
  • the carrier (not shown) is peeled off, and then the via hole 114 is formed by laser perforation if necessary (step (b)).
  • step (c) After applying the chemical copper plating 115 (step (c)), masking is performed in a predetermined pattern by exposure and development using the dry film 116 (step (d)), and electroplating 117 is applied (step (e)). ). After removing the dry film 116 to form the wiring portion 117a (step (f)), unnecessary ultrathin copper foil and the like between the adjacent wiring portions 117a and 117a are removed by etching over their entire thickness (step). (G)), the wiring 118 formed in a predetermined pattern is obtained.
  • the lower layer circuit 111b on the bottom surface of the via hole is cleaned and the splash adhering to the periphery of the via hole is removed.
  • Micro-etching Cu etching
  • the thickness of the ultrathin copper foil 110 is made thinner than before, and the seed layer (ultrathin copper foil 110) at the time after the microetching is about 0.3 ⁇ m. It has become desirable to have a thickness of.
  • Patent Document 1 International Publication No. 2017/141985
  • Patent Document 1 includes a first copper layer, an etching sacrificial layer made of a Cu—Zn alloy or the like, and a second copper layer (seed layer) in this order.
  • a copper foil for manufacturing a printed wiring board in which the ratio r of the etching rate of the etching sacrificial layer to the etching rate of is higher than 1.0 is disclosed. According to such a copper foil, as conceptually shown in FIG.
  • the etching sacrificial layer 212 is sandwiched between the two copper layers 213 and 211 to form a laminate of the metal foil 210 and the insulating layer 228. Even if the etching sacrificial layer 212 is non-uniformly melted during microetching and the second copper layer (seed layer) 213 is locally exposed, the etching sacrificial layer 212 is preferentially dissolved. As a result, the thickness of the second copper layer (seed layer) 213 is generally kept uniform, and it is said that defects are less likely to occur.
  • Patent Document 1 also discloses that a copper foil provided with the etching sacrificial layer can be preferably adopted for manufacturing a printed wiring board by a coreless build-up method.
  • a wiring layer (first wiring layer) is formed on a metal layer on the surface of a support (core), a build-up layer is further formed, and then the support (core) is removed to build up.
  • This is a method of forming a wiring board with only layers. Since the printed wiring board manufactured by such a method is of a type in which a circuit pattern is embedded in an insulating layer, this method is called an ETS (Embedded Trace Substrate) method.
  • ETS embedded Trace Substrate
  • the etching sacrificial layer 212 is non-uniformly dissolved during Cu etching and / or accidentally occurs in the etching sacrificial layer 212. Even if Cu (Cu of the second copper layer 213 or the first wiring layer 226) is locally exposed due to a pinhole or the like that may exist locally, the underlying second copper layer 213 or the first is due to the local battery reaction. Melting of one wiring layer 226 (copper layer) is suppressed. As a result, the second copper layer 213 is uniformly etched in the plane, and it is said that the occurrence of local circuit dents in the first wiring layer 226 can be suppressed. Moreover, according to this method, since the etching sacrificial layer 212 is dissolved and removed by Cu etching, an additional step for removing the etching sacrificial layer 212 becomes unnecessary, and productivity is also improved.
  • the copper foil provided with the etching sacrificial layer is highly useful from the viewpoint of significantly suppressing the occurrence of the seed layer defect and the circuit dent in the production of the printed wiring board.
  • resin residue may be generated at the bottom of the via hole 114 due to the formation of the via hole 114 by laser drilling or the like (step (b)).
  • a desmear treatment using a chemical solution is performed as a treatment for removing the resin residue. This desmear treatment can also be performed when forming the build-up layer in the above-mentioned ETS method.
  • the etching sacrificial layer 212 is exposed from the side surface of the via hole 214 after drilling, as conceptually shown in FIG. ..
  • the desmear treatment is performed in this state, the etching sacrificial layer 212 is protected by the first copper layer 211 in the portion other than the side surface of the via hole 214, but the chemical solution can erode from the exposed portion of the etching sacrificial layer 212 in the side surface portion of the via hole 214. .. Therefore, there is a possibility that the etching sacrificial layer 212 has already disappeared at the start of microetching.
  • the sacrificial effect that the etching sacrificial layer 212 dissolves preferentially over the seed layer (second copper layer 213) at the time of microetching is not sufficiently exhibited, and a defect 213a may occur in the seed layer.
  • the etching sacrificial layer 212 is transferred to the copper layers 211 and 213 as conceptually shown in FIG.
  • Metals eg, Zn
  • these layers can become an alloy layer 220 having a composition similar to that of the etching sacrificial layer 212 as a whole. Therefore, at the time of micro-etching, the sacrificial effect of the etching sacrificial layer 212 may not be sufficiently exhibited, and the etching sacrificial layer 212 and the seed layer (second copper layer 213) may be removed together.
  • the present inventors have now developed a second etching rate between the seed layer (copper layer) and the first etching sacrificial layer, which is higher than Cu and lower than the first etching sacrificial layer. It was found that by using a metal foil with an etching sacrificial layer interposed, it is possible to suppress the occurrence of defects in the seed layer even when the chemical treatment is performed after drilling. Further, by interposing a second etching sacrificial layer between the seed layer (copper layer) and the first etching sacrificial layer, even when high temperature press working is performed, the first etching sacrificial layer is transferred to the seed layer. It was also found that the diffusion of metals and the like can be effectively prevented, and as a result, the sacrificial effect inherent in the etching sacrificial layer can be exhibited.
  • a first object of the present invention is to provide a metal foil for manufacturing a printed wiring board, which can suppress the occurrence of a defect in the seed layer even when a chemical treatment is performed after drilling.
  • a second object of the present invention is to effectively prevent the diffusion of metals and the like from the first etching sacrificial layer to the seed layer even when high-temperature press working is performed, and as a result, the etching sacrificial layer is originally formed. It is an object of the present invention to provide a metal foil for manufacturing a printed wiring board, which can exert a sacrificial effect.
  • a metal foil for manufacturing a printed wiring board that satisfies r 1 > r 2 > 1.0 is provided.
  • a metal foil with a carrier provided with a carrier, a release layer, and the metal foil in this order is provided.
  • a metal-clad laminate provided with the metal foil is provided.
  • a method for manufacturing a printed wiring board which comprises using the metal foil or the metal foil with a carrier.
  • FIG. 6 It is a figure which shows the process of the first half in the conventional example of the manufacturing method of the printed wiring board using the MSAP method.
  • the latter half of the process following the process shown in FIG. 6 in the conventional example of the method of manufacturing a printed wiring board using the MSAP method is shown.
  • ETS method coreless build-up method
  • FIG. 11 It is a figure which shows the process of the first half in an example of the manufacturing method of the printed wiring board by the coreless build-up method (ETS method) using the metal foil of this invention.
  • the latter half of the process following the process shown in FIG. 11 in an example of the method for manufacturing a printed wiring board by the coreless build-up method (ETS method) using the metal foil of the present invention is shown.
  • the metal foil according to the present invention is a metal foil used for manufacturing printed wiring boards.
  • FIG. 1 shows a schematic cross-sectional view of the metal foil of the present invention.
  • the metal foil 10 includes a first etching sacrificial layer 11, a second etching sacrificial layer 12, and a copper layer (seed layer) 13 in this order.
  • the metal foil 10 may further include an additional copper layer 14 on the surface of the first etching sacrificial layer 11 opposite to the second etching sacrificial layer 12.
  • the metal foil 10 may further include a diffusion prevention layer 15 between the additional copper layer 14 and the first etching sacrificial layer 11.
  • the copper layer that does not adhere to the insulating resin is the "additional copper layer 14"
  • the copper layer that adheres to the insulating resin is the “copper layer 13”.
  • the copper layer on the side where the circuit pattern is not formed is the "additional copper layer 14”
  • the copper layer on the side where the circuit pattern is formed is the “copper layer”. 13 ".
  • the "copper layer 13" is a layer exclusively used for forming a circuit pattern, the "copper layer 13" may be referred to as a "seed layer 13" by paying attention to this function.
  • the first etching sacrificial layer 11 and the second etching sacrificial layer 12 may be copper alloy layers, they are not metallic copper layers, so that the metal foil 10 contains a metal or alloy other than copper as its inner layer or outer layer. .. Therefore, in the present invention, the metal foil 10 is referred to as a "metal foil for manufacturing a printed wiring board", but the metal foil 10 has the same application as a copper foil generally recognized as a copper foil for manufacturing a printed wiring board. It can be used for.
  • the order included in the names of the "first etching sacrificial layer" and the "second etching sacrificial layer” follows the order counted from the carrier side when there is a carrier.
  • the metal foil 10 is provided in the form of a metal leaf 16 with a carrier as shown in FIG. 1, a carrier 17, a release layer 18, an additional copper layer 14 (if present), and a diffusion prevention layer 15 (exist).
  • the first etching sacrificial layer 11, the second etching sacrificial layer 12, and the copper layer 13 (seed layer) are configured in this order.
  • the ratio of the etching rate of the first etching sacrificial layer 11 to the etching rate of Cu is set to r 1
  • the second etching sacrificial layer with respect to the etching rate of Cu is set to r 1
  • the ratio of the etching rates of 12 is r 2 , it is characterized by satisfying r 1 > r 2 > 1.0.
  • the etching sacrificial layer 212 is exposed from the side surface of the via hole 214.
  • the etching sacrificial layer 212 is protected by the first copper layer 211 in the portion other than the side surface of the via hole 214, but the chemical solution can erode from the exposed portion of the etching sacrificial layer 212 in the side surface portion of the via hole 214. ..
  • the etching sacrificial layer 212 is a layer that is more easily etched than the copper layers 211 and 213, it can be said that chemical erosion is likely to occur. Therefore, there is a possibility that the etching sacrificial layer 212 has already disappeared at the start of microetching. As a result, the sacrificial effect that the etching sacrificial layer 212 dissolves preferentially over the seed layer (second copper layer 213) at the time of microetching is not sufficiently exhibited, and a defect 213a may occur in the seed layer.
  • the metal foil 10 of the present invention by using the metal foil 10 of the present invention, the above technical problem can be conveniently solved. That is, as conceptually shown in FIG. 2, the metal foil 10 (including the additional copper layer 14, the first etching sacrificial layer 11, the second etching sacrificial layer 12, and the copper layer 13) and the insulating layer 28 are laminated. In the body, the second etching sacrificial layer 12 remains on the seed layer (copper layer 13) even when the desmear treatment is performed after the via hole 54 is formed by drilling.
  • the second etching sacrificial layer 12 is subjected to a local battery reaction during chemical treatment such as desmear.
  • the 1 etching sacrificial layer 11 dissolves preferentially over the 2nd etching sacrificial layer 12 and the like. In this way, the chemical erosion of the second etching sacrificial layer 12 is suppressed, and at the start of microetching, not only the seed layer 13 but also at least the second etching sacrificial layer 12 remains in the laminate.
  • the second etching sacrificial layer 12 can be preferentially dissolved by the local battery reaction, and as a result, the underlying seed layer 13 Dissolution is suppressed and defects are less likely to occur.
  • the second etching sacrificial layer 12 between the copper layer 13 and the first etching sacrificial layer 11, for example, even when high-temperature press working at 220 ° C. or higher is performed, the seed is seeded from the first etching sacrificial layer 11. It is possible to effectively prevent the diffusion of metals and the like into the layer (copper layer 13).
  • high-temperature press working is performed using a copper foil having one etching sacrificial layer composed of a Cu—Zn alloy or the like, as conceptually shown in FIG.
  • Metals (for example, Zn) and the like diffuse from the etching sacrificial layer 212 to the copper layers 211 and 213, and as a result, these layers can become an alloy layer 220 having a composition similar to that of the etching sacrificial layer 212 as a whole. Therefore, at the time of micro-etching, the sacrificial effect of the etching sacrificial layer 212 may not be sufficiently exhibited, and the etching sacrificial layer 212 and the seed layer (second copper layer 213) may be removed together.
  • the metal foil 10 of the present invention as conceptually shown in FIG.
  • the second etching sacrificial layer 12 is interposed between the first etching sacrificial layer 11 and the copper layer 13. Further, if necessary, a diffusion prevention layer 15 may be interposed between the first etching sacrificial layer 11 and the additional copper layer 14. Therefore, diffusion of the metal from the first etching sacrificial layer 11 is prevented by the second etching sacrificial layer 12 to the diffusion prevention layer 15 (if present). As a result, the seed layer 13 and the additional copper layer 14 (if present) can be prevented from alloying, and the above technical problems can be solved.
  • a low CTE base material having a low coefficient of thermal expansion (CTE) but a high curing temperature can be used as an insulating base material, and as a result, further miniaturization of circuits can be realized in the manufacture of printed wiring boards. It will be possible.
  • diffusion does not occur means that (i) the copper layer 13 before heating the metal leaf 10 contains only 1% by weight or less (including 0% by weight), and (ii) the metal leaf 10 is heated.
  • An element contained in at least one of the previous first etching sacrificial layer 11 and the second etching sacrificial layer 12 in an amount of 1% by weight or more (hereinafter referred to as “diffusion confirmation element”) is a predetermined value of the copper layer 13 after heating the metal foil 10. It means that the content is 1% by weight or less at the measurement point of. Therefore, for example, even if the carbon contents of the copper layer 13 before and after heating are 0.5% by weight and 2% by weight, respectively, in either the first etching sacrificial layer 11 or the second etching sacrificial layer 12.
  • the "measurement point of the copper layer 13 after heating the metal foil 10" is (a) the surface of the copper layer 13 opposite to the second etching sacrificial layer 12, or (b) the second etching of the copper layer 13. This refers to a point that is 0.3 ⁇ m away from the interface with the sacrificial layer 12 in the depth direction of the copper layer 13 and is closer to the second etching sacrificial layer 12.
  • the above (a) is the measurement point
  • the above (b) is the measurement point.
  • the boundary between the copper layer 13 and the second etching sacrificial layer 12 becomes indistinguishable in the heated metal foil 10, it is considered that diffusion has occurred.
  • another member for example, a support
  • a diffusion confirmation element is adhered to the surface of the copper layer 13 opposite to the second etching sacrificial layer 12. May be good.
  • the elemental content of each layer is set to a value specified by performing elemental analysis in the depth direction of the metal foil 10 using a glow discharge emission spectrometer (GD-OES) as referred to in Examples described later. ..
  • GD-OES glow discharge emission spectrometer
  • the first etching sacrificial layer 11 is not particularly limited as long as the etching rate is higher than that of Cu and the second etching sacrificial layer 12.
  • the ratio of the etching rate of the first etching sacrificial layer 11 to the etching rate of Cu r 1 (hereinafter referred to as the etching rate ratio r 1 ) and the etching rate of the second etching sacrificial layer 12 to the etching rate of Cu.
  • the ratio r 2 (hereinafter referred to as the etching rate ratio r 2 ) satisfies r 1 > r 2 > 1.0.
  • the first etching sacrificial layer 11 can be dissolved and removed at the same time as the seed layer 13 and the like by Cu etching, and the first etching sacrificial layer 11 and the second etching sacrificial layer 12 are non-uniformly dissolved. Even if the Cu is locally exposed, the dissolution of the underlying copper layer (seed layer) is suppressed by the local battery reaction. As a result, the seed layer can be uniformly etched in the plane, and it is possible to suppress the occurrence of the seed layer defect and local circuit dents and defects.
  • the local battery is used.
  • the first etching sacrificial layer 11 is dissolved preferentially over the second etching sacrificial layer 12 and the like.
  • the second etching sacrificial layer 12 can be left in a state where dissolution is suppressed, and as a result, even when the chemical solution treatment is performed after perforation, the seed layer may be damaged. Can be suppressed.
  • the etching rate of the first etching sacrificial layer 11 is such that a foil sample made of the same material as the first etching sacrificial layer 11 and a copper foil sample as a reference sample are subjected to the same time treatment in the etching step and etched. It is calculated by dividing the change in sample thickness by the dissolution time. The change in thickness may be determined by measuring the amount of weight loss of both samples and converting the density of each metal into a thickness.
  • the preferable etching rate ratio r 1 is 1.2 or more, more preferably 1.25 or more, and further preferably 1.3 or more from the viewpoint of obtaining a high sacrificial effect.
  • the upper limit of the etching rate ratio r 1 is not particularly limited, but the dissolution rate of the first etching sacrificial layer 11 in the plane is kept uniform, and the local battery reaction with the second etching sacrificial layer 12 to the copper layer 13 is made uniform in the plane.
  • the etching rate ratio r 1 is preferably 5.0 or less, more preferably 4.5 or less, more preferably 4.0 or less, particularly preferably 3.5 or less, most It is preferably 3.0 or less.
  • the etching solution a known solution capable of dissolving copper by a redox reaction can be adopted.
  • the etching solution examples include an aqueous solution of cupric chloride (CuCl 2 ), an aqueous solution of ferric chloride (FeCl 3 ), an aqueous solution of ammonium persulfate, an aqueous solution of sodium persulfate, an aqueous solution of potassium persulfate, and an aqueous solution of sulfuric acid / hydrogen peroxide. And so on.
  • FeCl 3 ferric chloride
  • an aqueous solution of ammonium persulfate an aqueous solution of sodium persulfate
  • an aqueous solution of potassium persulfate an aqueous solution of sulfuric acid / hydrogen peroxide.
  • sodium persulfate aqueous solution, potassium persulfate aqueous solution, and sulfuric acid / hydrogen peroxide solution are suitable from the viewpoint that the etching rate of Cu can be precisely controlled
  • sulfuric acid / hydrogen peroxide solution is most preferable.
  • a spray method, a dipping method or the like can be adopted.
  • the etching temperature can be appropriately set in the range of 25 ° C. or higher and 70 ° C. or lower.
  • the etching rate in the present invention is adjusted by the combination of the etching solution, the etching method, and the like, and the selection of the material of the first etching sacrificial layer 11 shown below.
  • the material constituting the first etching sacrificial layer 11 is preferably a metal that is electrochemically lower than Cu, and examples of such a preferable metal include Cu—Zn alloy, Cu—Sn alloy, Cu—Mn alloy, and Cu. -Al alloy, Cu-Mg alloy, Fe metal, Zn metal, Co metal, Mo metal and their oxides, and combinations thereof are mentioned, and Cu—Zn alloy is particularly preferable.
  • the Cu—Zn alloy that can form the first etching sacrificial layer 11 preferably has a Zn content of 40% by weight or more, more preferably 50% by weight or more, still more preferably 60, from the viewpoint of obtaining a high sacrificial effect. By weight or more, particularly preferably 70% by weight or more.
  • the Zn content in the Cu—Zn alloy is such that the in-plane dissolution rate of the first etching sacrificial layer 11 is uniformly maintained and the in-plane reaction of the local battery reaction with the second etching sacrificial layer 12 to the copper layer 13 is uniform. From the viewpoint of action, it is preferably 98% by weight or less, more preferably 96% by weight or less, and further preferably 94% by weight or less.
  • the first etching sacrificial layer 11 preferably has a thickness d 1 of 0.1 ⁇ m or more and 5 ⁇ m or less, and a more preferable thickness d 1 is 0.1 ⁇ m or more and 4.5 ⁇ m or less, more preferably 0.2 ⁇ m or more and 4 ⁇ m or less. It is particularly preferably 0.2 ⁇ m or more and 3.5 ⁇ m or less, and most preferably 0.3 ⁇ m or more and 3 ⁇ m or less.
  • the second etching sacrificial layer 12 is not particularly limited as long as it has an etching rate higher than Cu and lower than the first etching sacrificial layer 11 (that is, satisfying the above-mentioned relationship of r 1 > r 2 > 1.0). .. With the higher etching rate than Cu can be simultaneously dissolved and removed by (etching rate ratio r 2 is higher if more 1.0) Cu etching, Cu second etching sacrificial layer 12 is dissolved unevenly localized Even if it is exposed to the surface, the local battery reaction suppresses the dissolution of the underlying copper layer (seed layer), which enables uniform etching of the seed layer in the plane, as well as chipping of the seed layer and local circuit dents.
  • the etching rate ratio r 2 is lower than the etching rate ratio r 1 , when the chemical solution treatment is performed in a state where both the first etching sacrificial layer 11 and the second etching sacrificial layer 12 are locally exposed, the local battery is used. By the reaction, the first etching sacrificial layer 11 is dissolved preferentially over the second etching sacrificial layer 12 and the like. As a result, at the start of micro-etching, the second etching sacrificial layer 12 can be left in a state where dissolution is suppressed, and as a result, even when the chemical solution treatment is performed after perforation, the seed layer may be damaged.
  • the etching rate of the second etching sacrificial layer 12 is as described above with respect to the first etching sacrificial layer 11, and preferred embodiments such as an etching solution and an etching method also apply to the second etching sacrificial layer 12 as they are.
  • the preferable etching rate ratio r 2 is 1.2 or more, more preferably 1.25 or more, from the viewpoint of obtaining a high sacrificial effect.
  • the upper limit of the etching rate ratio r 2 is not particularly limited, but in order to keep the dissolution rate of the second etching sacrificial layer 12 in the plane uniform and allow the local battery reaction with the copper layer 13 to act uniformly in the plane, etching is performed.
  • the rate ratio r 2 is preferably 5.0 or less, more preferably 4.5 or less, still more preferably 4.0 or less, still more preferably 3.5 or less, and particularly preferably 3.0 or less. Yes, most preferably 2.7 or less.
  • the material constituting the second etching sacrificial layer 12 is preferably an electrochemically base metal rather than Cu from the viewpoint of obtaining a high sacrificial effect, and examples of such a preferable metal include Cu—Zn alloy and Cu—.
  • Sn alloys, Cu—Mn alloys, Cu—Al alloys, Cu—Mg alloys, Fe metals, Zn metals, Co metals, Mo metals and their oxides, and combinations thereof are mentioned, and more preferable examples thereof are Cu—.
  • Examples thereof include Zn alloys, Fe metals, oxides thereof, and combinations thereof, and Cu—Zn alloys are particularly preferable.
  • the Cu—Zn alloy that can form the second etching sacrificial layer 12 preferably has a Zn content of 40% by weight or more, more preferably 50% by weight or more, still more preferably 60, from the viewpoint of obtaining a high sacrificial effect. Weight% or more. Further, the Zn content in the Cu—Zn alloy is preferably set from the viewpoint of uniformly maintaining the in-plane dissolution rate of the second etching sacrificial layer 12 described above and the in-plane uniform action of the local battery reaction with the copper layer 13. It is 98% by weight or less, more preferably 96% by weight or less, still more preferably 94% by weight or less, and particularly preferably 92% by weight or less.
  • the second etching sacrificial layer 12 is selected from Fe metal, Fe—W alloy, Co metal, CoW alloy, Co—Ni alloy and oxides thereof, and a combination thereof. It is preferably composed of at least one kind, and more preferable examples include Fe metal, Fe-W alloy and oxides thereof, and a combination thereof, and Fe metal is particularly preferable.
  • the second etching sacrificial layer 12 preferably has a thickness d 2 of 0.05 ⁇ m or more and 2.5 ⁇ m or less, and a more preferable thickness d 2 is 0.06 ⁇ m or more and 2.0 ⁇ m or less, more preferably 0.06 ⁇ m or more 1 It is 5.5 ⁇ m or less, particularly preferably 0.07 ⁇ m or more and 1.0 ⁇ m or less, and most preferably 0.07 ⁇ m or more and 0.5 ⁇ m or less.
  • a desired sacrificial effect can be obtained and a further excellent diffusion prevention effect can be exhibited.
  • any combination of the above-mentioned metals or alloys can be selected so as to satisfy the above-mentioned relationship of r 1 > r 2 > 1.0. ..
  • the first etching sacrificial layer 11 and the second etching sacrificial layer 12 may be the same type of alloy, or may be different types of metals or alloys.
  • the ratio of the elements constituting each alloy so as to satisfy the relationship of r 1 > r 2 > 1.0. It is preferable to adjust.
  • each of the first etching sacrificial layer 11 and the second etching sacrificial layer 12 may be made of a Cu—Zn alloy, and the Zn content of the first etching sacrificial layer 11 is x, and the second etching sacrificial layer 12
  • the Zn content of the above is y
  • the first etching sacrificial layer 11 is made of Cu—Zn alloy or Zn metal
  • the second etching sacrificial layer 12 is made of Fe metal.
  • the copper layer 13 has a known structure and is not particularly limited.
  • the copper layer 13 may be formed by a wet film forming method such as an electroless plating method and an electrolytic plating method, a dry film forming method such as sputtering and chemical vapor deposition, or a combination thereof.
  • the copper layer 13 preferably has a thickness d 3 of 0.1 ⁇ m or more and 2.5 ⁇ m or less, and a more preferable thickness d 3 is 0.1 ⁇ m or more and 2 ⁇ m or less, more preferably 0.1 ⁇ m or more and 1.5 ⁇ m or less, particularly. It is preferably 0.2 ⁇ m or more and 1 ⁇ m or less, and most preferably 0.2 ⁇ m or more and 0.8 ⁇ m or less.
  • the thickness d 3 is within such a range, it is possible to more effectively prevent defects such as defects during Cu etching, even though the thickness is sufficiently thin for circuit formation.
  • the surface of the copper layer 13 is roughened.
  • the average particle size D of the roughened particles by image analysis is preferably 0.04 ⁇ m or more and 0.53 ⁇ m or less, more preferably 0.08 ⁇ m or more and 0.13 ⁇ m or less, and further preferably 0.09 ⁇ m or more and 0.12 ⁇ m. It is as follows.
  • the roughened surface is provided with an appropriate roughness to ensure excellent adhesion to the photoresist, and the opening property of the unnecessary region of the photoresist is opened during the photoresist development. It can be satisfactorily realized, and as a result, it is possible to effectively prevent line defects of the pattern plating 22 which may occur due to difficulty in plating due to the photoresist which has not been sufficiently opened. Therefore, if it is within the above-mentioned preferable range, it can be said that the photoresist developability and the pattern plating property are excellent, and therefore, it is suitable for fine formation of the wiring pattern 24.
  • the average particle size D obtained by image analysis of the coarsened particles is obtained by taking an image at a magnification in which a predetermined number of particles (for example, 1000 or more and 3000 or less) are contained in one field of a scanning electron microscope (SEM).
  • a predetermined number of particles for example, 1000 or more and 3000 or less
  • SEM scanning electron microscope
  • the coarsened particles preferably have a particle density ⁇ of 4 / ⁇ m 2 or more and 200 / ⁇ m 2 or less, more preferably 40 / ⁇ m 2 or more and 170 / ⁇ m 2 or less, 70 / ⁇ m / ⁇ m 2 or more. ⁇ m 2 or more and 100 pieces / ⁇ m 2 or less.
  • the roughened particles on the surface of the copper layer are dense and dense, the development residue of the photoresist is likely to be generated in the ETS method, but if it is within the above preferable range, such a development residue is generated. It is difficult, and therefore, the photoresist pattern 20 is also excellent in developability.
  • the wiring pattern 24 is suitable for fine formation if it is within the above-mentioned preferable range.
  • the particle density ⁇ obtained by image analysis of the roughened particles is obtained by taking an image at a magnification at which a predetermined number of particles (for example, 1000 or more and 3000 or less) are contained in one field of a scanning electron microscope (SEM).
  • SEM scanning electron microscope
  • the surface of the copper layer 13 is preferably subjected to a rust preventive treatment such as nickel-zinc / chromate treatment and a coupling treatment with a silane coupling agent, in addition to the adhesion of roughened particles by the roughening treatment described above.
  • a rust preventive treatment such as nickel-zinc / chromate treatment
  • a coupling treatment with a silane coupling agent in addition to the adhesion of roughened particles by the roughening treatment described above.
  • the additional copper layer 14 provided as desired may have a known copper foil structure and is not particularly limited. By providing the additional copper layer 14, it is possible to control the first etching sacrificial layer 11 having a high dissolution rate so as not to be exposed in the pretreatment in the Cu etching step, and it is easy to peel off from the following peeling layer. There is an advantage that it can be made.
  • the additional copper layer 14 may be formed by a wet film forming method such as an electroless plating method and an electrolytic plating method, a dry film forming method such as sputtering and chemical vapor deposition, or a combination thereof.
  • Add copper layer 14 preferably has a thickness of less than d 3 '2.5 [mu] m or more 0.1 [mu] m, more preferably 0.1 [mu] m or more 2 ⁇ m or less, more preferably 0.2 ⁇ m or 1.5 ⁇ m or less, particularly preferably It is 0.2 ⁇ m or more and 1 ⁇ m or less, most preferably 0.3 ⁇ m or more and 0.8 ⁇ m or less.
  • the diffusion prevention layer 15 provided as desired is a layer having a function of preventing the diffusion of metals and the like from the first etching sacrificial layer 11 to the additional copper layer 14, and has a configuration similar to that of the second etching sacrificial layer 12. Can be done. Therefore, from the viewpoint of obtaining a high anti-diffusion effect, the anti-diffusion layer 15 is selected from Fe metals, Fe-W alloys, Co metals, Co-W alloys, Co-Ni alloys and oxides thereof, and combinations thereof. It is preferably composed of at least one kind, and more preferable examples include Fe metals, Fe-W alloys and oxides thereof, and combinations thereof, and Fe metal is particularly preferable.
  • Diffusion preventing layer 15 is preferably has a thickness of d 2 '2.5 [mu] m or more 0.05 .mu.m, more preferably 0.06 ⁇ m or 2.0 ⁇ m or less, more preferably 0.06 ⁇ m or 1.5 ⁇ m or less, particularly It is preferably 0.07 ⁇ m or more and 1.0 ⁇ m or less, and most preferably 0.07 ⁇ m or more and 0.5 ⁇ m or less.
  • the additional copper layer 14 and the diffusion prevention layer 15 can protect the first etching sacrificial layer 11 from dissolution by the chemical solution in a pre-etching step (for example, a chemical solution step such as desmear), or the first etching sacrificial layer. While it is possible to prevent the diffusion of metals and the like from 11, if it is excessively thick, the copper layer 13 (seed layer) after etching may be damaged.
  • the first etching sacrificial layer 11 and the second etching sacrificial layer 12 are collectively referred to as "etching sacrificial layers 11 and 12", or additional copper.
  • the layers 14, 14'and the diffusion prevention layers 15, 15' are sometimes collectively referred to as “additional copper layers 14, 14', etc.”
  • the additional copper layer 14'and the like are melted unevenly and the etching sacrificial layers 11 and 12 are exposed (FIG. 14).
  • the exposed etching sacrificial layers 11 and 12 can be immediately melted (priority over the remaining additional copper layer 14'etc.) to expose the seed layer 13 (FIG. 14 (c)).
  • the dissolution of the exposed seed layer 13 proceeds in parallel with the dissolution of the remaining additional copper layer 14'and the like (FIG. 14 (d)), and a defect 13a may occur in the seed layer 13 (FIG. FIG. 14 (e)).
  • the additional copper layer 14 and the like are moderately thin as shown in FIG.
  • the etching rate of the first etching sacrificial layer 11 is v 1
  • the etching rate of the second etching sacrificial layer 12 is v 2
  • the etching rate of the additional copper layer 14 is v 3 '
  • the etching rate of the diffusion prevention layer 15 is v 2.
  • the metal foil 10 preferably has 2 or less pinholes per unit area / mm 2 . By doing so, it is possible to further reduce defects such as defects due to chemical erosion during Cu etching.
  • the number of pinholes per unit area of the additional copper layer 14 (the first etching sacrificial layer 11 when the additional copper layer 14 does not exist) is preferably 2 pieces / mm 2 or less. This is because when the number of pinholes in the additional copper layer 14 is small as described above, the diffusion prevention layer 15, the first etching sacrificial layer 11, and the second etching sacrifice plated on the additional copper layer 14 in the manufacturing process of the metal foil 10 This is because the pinholes that can occur in the layer 12 and the copper layer 13 can also be reduced.
  • Metal foil 10 the thickness of the thickness d 1 of the first etching sacrificial layer 11, the thickness d 2 of the second etching sacrificial layer 12, the thickness d 3 of the copper layer 13, the diffusion preventing layer 15 (if present) d 2 ', and additional copper layer 14 thickness d 3 (if present)' is preferably a total thickness of d 1 + d 2 + d 3 + d 2 '+ d 3' is 3.0 ⁇ m or less, more preferably It is 0.3 ⁇ m or more and 2.8 ⁇ m or less, more preferably 0.6 ⁇ m or more and 2.8 ⁇ m or less, and particularly preferably 0.9 ⁇ m or more and 2.6 ⁇ m or less.
  • the total thickness within such a range means that the thickness of the metal foil 10 is sufficiently thin, and the direct laser perforation property of the metal foil 10 is improved.
  • the additional copper layer 14 and the anti-diffusion layer 15 between the anti-diffusion layer 15 and the first etching sacrificial layer 11, between the first etching sacrificial layer 11 and the second etching sacrificial layer 12, and /
  • another layer may be present between the second etching sacrificial layer 12 and the copper layer 13 as long as the sacrificial effects of the first etching sacrificial layer 11 and the second etching sacrificial layer 12 are not impaired.
  • Metal leaf with carrier Metal leaf 10 (ie, copper layer 13, second etching sacrificial layer 12, first etching sacrificial layer 11, diffusion prevention layer 15 if present, and additional copper layer 14 if present) ) May be provided in the form of a carrierless metal leaf, or may be provided in the form of a carrier-attached metal leaf 16, as shown in FIG. 1, but is provided in the form of a carrier-attached metal leaf 16. Is preferable.
  • the metal foil 16 with a carrier includes a carrier 17, a release layer 18, an additional copper layer 14 (if present), a diffusion prevention layer 15 (if present), a first etching sacrificial layer 11, and a second etching sacrificial layer 12.
  • a preferred metal foil with a carrier includes a carrier 17, a release layer 18, and a metal foil 10 in this order.
  • the carrier 17 is a layer (typically a foil) for supporting a metal foil and improving its handleability.
  • the carrier include an aluminum foil, a copper foil, a stainless foil, a resin film, a resin film having a metal coating on the surface, a glass plate, and the like, and a copper foil is preferable.
  • the copper foil may be either a rolled copper foil or an electrolytic copper foil.
  • the thickness of the carrier is typically 250 ⁇ m or less, preferably 12 ⁇ m or more and 200 ⁇ m or less.
  • the peeling layer 18 has a function of weakening the peeling strength of the carrier 17, ensuring the stability of the strength, and further suppressing mutual diffusion that may occur between the carrier and the metal foil during press molding at a high temperature.
  • the release layer is generally formed on one surface of the carrier, but may be formed on both sides.
  • the release layer may be either an organic release layer or an inorganic release layer.
  • the organic component used in the organic release layer include nitrogen-containing organic compounds, sulfur-containing organic compounds, and carboxylic acids.
  • the nitrogen-containing organic compound include a triazole compound and an imidazole compound, and among them, the triazole compound is preferable because the peelability is easily stable.
  • triazole compounds examples include 1,2,3-benzotriazole, carboxybenzotriazole, N', N'-bis (benzotriazolylmethyl) urea, 1H-1,2,4-triazole and 3-amino-. Examples thereof include 1H-1,2,4-triazole.
  • sulfur-containing organic compound examples include mercaptobenzothiazole, thiothianulic acid, 2-benzimidazole thiol and the like.
  • carboxylic acids include monocarboxylic acids and dicarboxylic acids.
  • examples of the inorganic component used in the inorganic release layer examples include Ni, Mo, Co, Cr, Fe, Ti, W, P, Zn, chromate-treated film, carbon layer and the like.
  • the release layer may be formed by bringing the release layer component-containing solution into contact with at least one surface of the carrier and adsorbing the release layer component on the surface of the carrier in the solution.
  • this contact may be performed by immersion in the release layer component-containing solution, spraying the release layer component-containing solution, flowing down the release layer component-containing solution, or the like.
  • a plating method such as electrolytic plating or electroless plating, or a vapor phase method such as vapor deposition or sputtering can be used to form a film of the release layer component.
  • the release layer component may be fixed to the carrier surface by drying the release layer component-containing solution, electrodeposition of the release layer component in the release layer component-containing solution, or the like.
  • the thickness of the release layer is typically 1 nm or more and 1 ⁇ m or less, preferably 5 nm or more and 500 nm or less.
  • the peel strength between the peeling layer 18 and the carrier is preferably 5 gf / cm or more and 50 gf / cm or less, more preferably 5 gf / cm or more and 40 gf / cm or less, and further preferably 6 gf / cm or more and 30 gf / cm or less. is there.
  • the metal foil of the present invention is preferably used for producing a metal-clad laminate for a printed wiring board. That is, according to a preferred embodiment of the present invention, a metal-clad laminate provided with the metal foil described above is provided.
  • the metal-clad laminate may include a metal foil in the form of a metal foil with a carrier. Further, the metal foil may be provided on one side of the resin layer or may be provided on both sides.
  • the resin layer typically comprises a resin, preferably an insulating resin.
  • the resin layer is preferably a prepreg and / or a resin sheet, more preferably a prepreg.
  • Prepreg is a general term for composite materials obtained by impregnating or laminating a base material such as a synthetic resin plate, a glass plate, a glass woven fabric, a glass non-woven fabric, or paper with a synthetic resin.
  • a base material such as a synthetic resin plate, a glass plate, a glass woven fabric, a glass non-woven fabric, or paper with a synthetic resin.
  • Preferred examples of the insulating resin impregnated in the prepreg include an epoxy resin, a cyanate resin, a bismaleimide triazine resin (BT resin), a polyphenylene ether resin, a phenol resin, a polyamide resin and the like.
  • examples of the insulating resin constituting the resin sheet include insulating resins such as epoxy resin, polyimide resin, and polyester resin (liquid crystal polymer).
  • the resin layer may contain filler particles made of various inorganic particles such as silica and alumina from the viewpoint of lowering the coefficient of thermal expansion and increasing the rigidity.
  • the thickness of the resin layer is not particularly limited, but is preferably 3 ⁇ m or more and 1000 ⁇ m or less, more preferably 5 ⁇ m or more and 400 ⁇ m or less, and further preferably 10 ⁇ m or more and 200 ⁇ m or less.
  • the resin layer may be composed of a plurality of layers.
  • a resin layer such as a prepreg and / or a resin sheet may be provided on the metal foil with a carrier via a primer resin layer previously applied to the surface of the metal foil.
  • a printed wiring board can be preferably manufactured by using the metal foil of the present invention or the metal foil with a carrier as described above.
  • Preferable examples of the method for manufacturing a printed wiring board include the MSAP method (modified semi-additive method) and the coreless build-up method (ETS method), but the method is not limited to these methods, and the metal foil of the present invention or the metal foil with a carrier is not limited to these methods.
  • MSAP method modified semi-additive method
  • ETS method coreless build-up method
  • a method of manufacturing a printed wiring board by a coreless build-up method (ETS method) using the metal foil of the present invention will be described below.
  • ETS method coreless build-up method
  • a metal leaf provided with an additional copper layer 14 (if present), a diffusion prevention layer 15 (if present), a first etching sacrificial layer 11, a second etching sacrificial layer 12, and a copper layer 13. 10 is used to obtain a support.
  • a build-up wiring layer including at least a first copper wiring layer 26 and an insulating layer 28 is formed on the copper layer 13 to obtain a laminate with a build-up wiring layer.
  • a build-up wiring layer as shown in FIG.
  • n is an integer of 2 or more
  • the additional copper layer 14 (if present), the diffusion prevention layer 15 (if present), the first etching sacrificial layer 11, the second etching sacrificial layer 12 and the copper layer 13 are removed by an etching solution to remove the first wiring layer. 26 is exposed, thereby obtaining a printed wiring board containing a build-up wiring layer.
  • FIGS. 11 and 12 are drawn so as to form the build-up wiring layer 42 by providing the metal foil 16 with a carrier on one side of the coreless support 19 for simplification of the description. It is desirable to provide the metal foil 16 with a carrier on both sides of the support 19 to form the build-up wiring layer 42 on both sides.
  • a metal foil 10 or a metal foil 16 with a carrier containing the metal foil 10 is prepared as a support.
  • the metal foil 10 additional copper layer 14 side
  • the carrier-attached metal foil 16 carrier 17 side
  • the coreless support 19 typically comprises a resin, preferably an insulating resin.
  • the coreless support 19 is preferably a prepreg and / or a resin sheet, more preferably a prepreg. That is, the coreless support 19 corresponds to the resin layer in the above-mentioned metal-clad laminate, and therefore, the above-mentioned preferred embodiment with respect to the metal-clad laminate or the resin layer applies to the coreless support 19 as it is.
  • a build-up wiring layer 42 including at least a first copper wiring layer 26 and an insulating layer 28 is formed on the copper layer 13 to form a laminate with a build-up wiring layer.
  • the insulating layer 28 may be made of the insulating resin as described above.
  • the build-up wiring layer 42 may be formed according to a known method for manufacturing a printed wiring board, and is not particularly limited. According to a preferred embodiment of the present invention, as described below, (i) a photoresist pattern is formed, (ii) electrolytic copper plating, and (iii) the photoresist pattern is peeled off to form the first wiring layer 26. After that, the (iv) build-up wiring layer 42 is formed.
  • a photoresist pattern 20 is formed on the surface of the copper layer 13.
  • the photoresist pattern 20 may be formed by either a negative resist or a positive resist, and the photoresist may be either a film type or a liquid type.
  • the developing solution may be a developing solution such as sodium carbonate, sodium hydroxide, or an amine-based aqueous solution, and is not particularly limited as long as it is carried out according to various methods and conditions generally used for producing a printed wiring board.
  • the electrolytic copper plating 22 is applied to the copper layer 13 on which the photoresist pattern 20 is formed.
  • the formation of the electrolytic copper plating 22 is not particularly limited as long as it is carried out according to various pattern plating methods and conditions generally used for producing a printed wiring board such as a copper sulfate plating solution or a copper pyrophosphate plating solution.
  • the photoresist pattern 20 is peeled off to form a wiring pattern 24.
  • the peeling of the photoresist pattern 20 is not particularly limited as long as an aqueous solution of sodium hydroxide, an amine solution or an aqueous solution thereof or the like is adopted and various peeling methods and conditions generally used for manufacturing a printed wiring board are followed. In this way, the wiring pattern 24 in which the wiring portions (lines) made of the first wiring layer 26 are arranged with the gaps (spaces) separated from each other is directly formed on the surface of the copper layer 13.
  • the line / space (L / S) is highly fine to the extent of 13 ⁇ m or less / 13 ⁇ m or less (for example, 12 ⁇ m / 12 ⁇ m, 10 ⁇ m / 10 ⁇ m, 5 ⁇ m / 5 ⁇ m, 2 ⁇ m / 2 ⁇ m). It is preferable to form a modified wiring pattern.
  • a build-up wiring layer 42 is formed on the copper layer 13 to prepare a laminate with a build-up wiring layer.
  • the insulating layer 28 and the second wiring layer 38 can be formed in this order to form the build-up wiring layer 42.
  • the insulating layer 28 and the copper foil 30 with a carrier are laminated to form the build-up wiring layer 42, and the carrier 32 is peeled off.
  • the copper foil 36 and the insulating layer 28 immediately below the copper foil 36 may be laser-processed by a carbon dioxide gas laser or the like.
  • N may be an integer of 2 or more).
  • the construction method for forming the build-up layer after the second wiring layer 38 is not limited to the above method, but is limited to the subtractive method, the MSAP (modified semi-additive process) method, the SAP (semi-additive) method, and the full additive method. Etc. can be used. For example, when a resin layer and a metal foil typified by a copper foil are simultaneously pressed together, the panel plating layer and the metal foil are etched in combination with the formation of via holes and the formation of interlayer conduction means such as panel plating. The wiring pattern can be formed. Further, when only the resin layer is bonded to the surface of the copper layer 13 by pressing or laminating, a wiring pattern can be formed on the surface by a semi-additive method.
  • a build-up wiring layer is formed in which resin layers and wiring layers including wiring patterns are alternately laminated, and a build-up wiring layer formed up to the nth wiring layer 40 (n is an integer of 2 or more) is attached. It is preferable to obtain a laminate.
  • This step may be repeated until a desired number of build-up wiring layers are formed.
  • a solder resist, bumps for mounting pillars, or the like may be formed on the outer layer surface. Further, the outermost layer surface of the build-up wiring layer may form an outer layer wiring pattern in a later outer layer processing step.
  • the laminate with build-up wiring layer is peeled off. It can be separated by such as.
  • the metal foil with a carrier includes a carrier 17, a release layer 18, an additional copper layer 14, a diffusion prevention layer 15, a first etching sacrificial layer 11, a second etching sacrificial layer 12, and a copper layer 13 in this order, the method of the present invention. It is preferable that the laminated body with the build-up wiring layer is separated by the release layer 18 to expose the additional copper layer 14 prior to the removal by the etching solution described later.
  • the method of separation is preferably physical peeling, and as the method of peeling, a method of machine or jig, manual work, or a combination thereof can be adopted.
  • the metal foil with a carrier includes a carrier 17, an additional copper layer 14, a first etching sacrificial layer 11, a second etching sacrificial layer 12, and a copper layer 13 in this order (that is, the peeling layer 18 is used as a single layer). If not), the method of the present invention adds a laminate with a build-up wiring layer between the carrier 17 and the additional copper layer 14 or inside the additional copper layer 14 prior to removal by the etching solution described later. It is preferable to expose the copper layer 14.
  • the additional copper layer 14, the diffusion prevention layer 15, the first etching sacrificial layer 11, the second etching sacrificial layer 12, and the copper layer 13 are subjected to the etching solution. It is removed to expose the first wiring layer 26, thereby obtaining a printed wiring board 46 including the build-up wiring layer 42.
  • the printed wiring board 46 is preferably a multilayer printed wiring board. In any case, due to the presence of the first etching sacrificial layer 11 and the second etching sacrificial layer 12, the removal of each layer by etching can be efficiently performed uniformly in the plane by Cu etching without requiring an additional etching step.
  • the additional copper layer 14, the diffusion prevention layer 15, the first etching sacrificial layer 11, the second etching sacrificial layer 12, and the copper layer 13 can be removed by the etching solution in one step. it can.
  • the etching solution and etching method used at this time are as described above.
  • the outer layer of the printed wiring board 46 as shown in FIG. 12 can be processed by various construction methods.
  • an insulating layer as a build-up wiring layer and a wiring layer may be further laminated on the first wiring layer 26 of the printed wiring board 46 as an arbitrary number of layers, or a solder-resist layer may be laminated on the surface of the first wiring layer 26.
  • May be formed and surface-treated as an outer layer pad such as Ni-Au plating, Ni-Pd-Au plating, and water-soluble preflux treatment.
  • columnar pillars or the like may be provided on the outer layer pad.
  • the first wiring layer 26 created by using the etching sacrificial layer in the present invention can maintain the uniformity of the circuit thickness in the plane, and the surface of the first wiring layer 26 has a local circuit recess. Will be less likely to occur. For this reason, the occurrence rate of defects such as local processing defects in the surface treatment process due to extremely thin circuit thickness or circuit dents, solder resist residue defects, and mounting defects due to unevenness of the mounting pad is low. , A printed wiring board with excellent mounting reliability can be obtained.
  • the method for manufacturing the printed wiring board described above is based on the coreless build-up method (ETS method), but the method for manufacturing the printed wiring board by the MSAP method is described in the conventional MSAP method described with reference to FIGS. 6 and 7.
  • ETS method coreless build-up method
  • the metal foil 10 of the present invention instead of the ultrathin copper foil 110, a printed wiring board can be preferably manufactured.
  • carrier A titanium electrode whose surface was polished with a # 2000 buff was prepared as a cathode.
  • DSA dimensional stability anode
  • the electrode is immersed in a copper sulfate solution having a copper concentration of 80 g / L and a sulfuric acid concentration of 260 g / L, electrolyzed at a solution temperature of 45 ° C. and a current density of 55 A / dm 2 , and an electrolytic copper foil having a thickness of 18 ⁇ m is used as a carrier.
  • a copper sulfate solution having a copper concentration of 80 g / L and a sulfuric acid concentration of 260 g / L
  • electrolyzed at a solution temperature of 45 ° C. and a current density of 55 A / dm 2
  • an electrolytic copper foil having a thickness of 18 ⁇ m is used as a carrier.
  • the pickled carrier is immersed in a CBTA solution having a CBTA (carboxybenzotriazole) concentration of 1 g / L, a sulfuric acid concentration of 150 g / L, and a copper concentration of 10 g / L at a liquid temperature of 30 ° C. for 30 seconds. Then, the CBTA component was adsorbed on the electrode surface of the carrier. In this way, the CBTA layer was formed as an organic release layer on the surface of the electrode surface of the carrier.
  • CBTA carboxybenzotriazole
  • the carrier on which the organic exfoliation layer is formed is immersed in a solution having a nickel concentration of 20 g / L prepared using nickel sulfate, and the liquid temperature is 45 ° C., pH is 3, and the current density is 5 A / dm. Under the condition of 2 , an adhering amount of nickel corresponding to a thickness of 0.001 ⁇ m was adhered on the organic release layer. In this way, a nickel layer was formed as an auxiliary metal layer on the organic exfoliation layer.
  • Example 4 Formation of Additional Copper Layer
  • the carrier on which the auxiliary metal layer was formed was immersed in a copper sulfate solution having a copper concentration of 60 g / L and a sulfuric acid concentration of 200 g / L, and the solution temperature was 50 ° C. Electrolysis was performed at a current density of 5 A / dm 2 or more and 30 A / dm 2 or less to form an additional copper layer having a thickness of 0.3 ⁇ m on the auxiliary metal layer. On the other hand, in Example 4, no additional copper layer was formed.
  • Example 3 Formation of First Etching Sacrificial Layer
  • a carrier on which a diffusion prevention layer is formed (Examples 1 and 2) or a carrier on which an additional copper layer is formed (Example 3) is immersed in the plating bath shown in Table 1.
  • the first etching sacrificial layer having the composition and thickness shown in Table 2 was formed on the anti-diffusion layer or the additional copper layer by electrolysis under the plating conditions shown in Table 1. On the other hand, in Example 4, the first etching sacrificial layer was not formed.
  • This roughening treatment comprises a burn-plating step of depositing and adhering fine copper particles on the copper layer, and a covering plating step for preventing the fine copper grains from falling off.
  • a roughening treatment was performed using an acidic copper sulfate solution containing a copper concentration of 10 g / L and a sulfuric acid concentration of 120 g / L at a liquid temperature of 25 ° C. and a current density of 15 A / dm 2 .
  • electrodeposition was performed using an acidic copper sulfate solution containing a copper concentration of 70 g / L and a sulfuric acid concentration of 120 g / L under smooth plating conditions of a liquid temperature of 40 ° C. and a current density of 15 A / dm 2 .
  • the surface subjected to the zinc-nickel alloy plating treatment was subjected to chromate treatment under the conditions of pH 10 and a current density of 5 A / dm 2 .
  • silane coupling agent Silane coupling by adsorbing an aqueous solution containing 2 g / L of 3-glycidoxypropyltrimethoxysilane on the surface of the metal foil with a carrier on the copper layer side and evaporating the water content with an electric heater. Agent treatment was performed. At this time, the silane coupling agent treatment was not performed on the carrier side.
  • Evaluation 1 etch rate ratio r 2 of the etching rate ratio diffusion preventing layer ', etching rate ratio r 1 of the first etching sacrificial layer, and the etching rate ratio r 2 of the second etching sacrificial layer was measured as follows.
  • a commercially available concentrated sulfuric acid (95% by weight) and a hydrogen peroxide solution (30% by weight) are dissolved in water to prepare an etching solution having a sulfuric acid concentration of 5.9% by weight and a hydrogen peroxide concentration of 2.1% by weight.
  • Each carrier-attached metal foil sample is masked so that the carrier side is not etched, immersed in an etching solution at 25 ° C. for a certain period of time to dissolve it, and the change in the thickness of the plating film before and after dissolution is measured by a fluorescent X-ray film thickness meter (Fisher Instruments). It was measured with a Fisherscape X-Ray XDAL-FD manufactured by the same company.
  • the etching rate of each target plating film was determined by dividing the obtained thickness change by the dissolution time.
  • the etching rate of the sample (iv) of Example 4 thus obtained is the etching rate of Cu
  • the etching rates of the samples (i), (ii) and (iii) in Examples 1 to 3 are the diffusion prevention layers and the first. It is the etching rate of 1 etching sacrificial layer and each 2nd etching sacrificial layer.
  • the diffusion preventing layer by dividing the etching rate of Cu etching rate of the first etching sacrificial layer and the second etching sacrificial layer, respectively, the etching rate ratio r 2 of the diffusion preventing layer ', etching of the first etching sacrificial layer
  • the rate ratio r 1 and the etching rate ratio r 2 of the second etching sacrificial layer were calculated. The results are as shown in Table 2.
  • Evaluation 2 Number of pinholes per unit area
  • a copper foil with a carrier that is, thickness
  • An intermediate product an intermediate product in which an additional copper layer of 0.3 ⁇ m was formed and the diffusion prevention layer was not formed and the subsequent treatment was not performed was prepared.
  • This copper foil with a carrier is laminated on an insulating resin base material (prepreg manufactured by Panasonic Corporation, R-1661, thickness 0.1 mm) so that the additional copper layer side is in contact with each other, and heat is applied at a pressure of 4.0 MPa and a temperature of 190 ° C. for 90 minutes. It was crimped.
  • the carrier was peeled off to obtain a laminated board.
  • This laminated board was observed with an optical microscope while being backlit in a dark room, and the number of pinholes was counted.
  • the number of pinholes per 1 mm 2 was measured in this way, the number of pinholes per unit area of the additional copper layer was 2 or less per mm 2 in all of Examples 1 to 3.
  • the copper layer contains only 1% by weight or less (including 0% by weight), and at least one of the first etching sacrificial layer and the second etching sacrificial layer (if present) contains 1% by weight or more.
  • the contained element was defined as a diffusion confirmation element.
  • the following points (A) The surface of the copper layer opposite to the second etching sacrificial layer (the surface of the copper layer opposite to the first etching sacrificial layer in the absence of the second etching sacrificial layer), or (b) the copper layer Of the points 0.3 ⁇ m away from the interface with the second etching sacrificial layer (the interface between the copper layer and the first etching sacrificial layer when the second etching sacrificial layer does not exist) in the depth direction of the copper layer.
  • the content of all diffusion-confirmed elements is 1% by weight or less at the point closer to the second etching sacrificial layer (the first etching sacrificial layer if the second etching sacrificial layer does not exist). was determined to be non-diffusion, and those not were determined to be diffused. It was also determined that there was diffusion even when the boundary between the copper layer and the second etching sacrificial layer could not be determined. The results are as shown in Table 2.
  • Evaluation 4 Defect of seed layer On the surface of the inner layer substrate, the metal foil with a carrier obtained in (11) above was applied to an insulating resin base material (prepreg manufactured by Mitsubishi Gas Chemicals Corporation, GHPL-830NS, thickness 0.1 mm). The copper layers were laminated so as to be close to each other, and thermocompression bonded at a pressure of 4.0 MPa and a temperature of 220 ° C. for 90 minutes. The carrier of the metal-clad laminate thus obtained is peeled off, cut into a size of 10 cm ⁇ 10 cm, and the first etching sacrificial layer and the second etching sacrificial layer (if present) are completely contained in the etching solution prepared in Evaluation 1.
  • an insulating resin base material prepreg manufactured by Mitsubishi Gas Chemicals Corporation, GHPL-830NS, thickness 0.1 mm.
  • the copper layers were laminated so as to be close to each other, and thermocompression bonded at a pressure of 4.0 MPa and a temperature of 220 ° C

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Laminated Bodies (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

L'invention concerne une feuille métallique pour la fabrication d'une carte à circuit imprimé, l'apparition de défauts de couche germe pouvant être supprimée même lorsqu'un traitement chimique est effectué après perforation. L'invention concerne également une feuille métallique pour la fabrication d'une carte à circuit imprimé, par laquelle la diffusion de métal ou analogue dans une couche germe à partir d'une première couche sacrificielle de gravure est empêchée efficacement même lorsqu'un pressage à haute température est effectué, et, en conséquence, l'effet sacrificiel inhérent à la couche sacrificielle de gravure peut être présenté. Cette feuille métallique pour la fabrication d'une carte à circuit imprimé est pourvue d'une première couche sacrificielle de gravure, d'une deuxième couche sacrificielle de gravure et d'une couche de cuivre dans cet ordre, et satisfait l'expression r1 > r2 > 1,0, où r1 est le rapport du taux de gravure de la première couche sacrificielle de gravure au taux de gravure de Cu, et r2 représente le rapport du taux de gravure de la deuxième couche sacrificielle de gravure au taux de gravure de Cu.
PCT/JP2020/010017 2019-03-27 2020-03-09 Feuille métallique pour carte à circuit imprimé, feuille métallique avec support, et stratifié plaqué de métal, et procédé de fabrication de carte à circuit imprimé l'utilisant WO2020195748A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2021508964A JP7449921B2 (ja) 2019-03-27 2020-03-09 プリント配線板用金属箔、キャリア付金属箔及び金属張積層板、並びにそれらを用いたプリント配線板の製造方法
CN202080023976.4A CN113646469A (zh) 2019-03-27 2020-03-09 印刷电路板用金属箔、带载体的金属箔和覆金属层叠板、及使用其的印刷电路板的制造方法
KR1020217024157A KR20210143727A (ko) 2019-03-27 2020-03-09 프린트 배선판용 금속박, 캐리어를 구비하는 금속박 및 금속 클래드 적층판, 그리고 그것들을 사용한 프린트 배선판의 제조 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019060651 2019-03-27
JP2019-060651 2019-03-27

Publications (1)

Publication Number Publication Date
WO2020195748A1 true WO2020195748A1 (fr) 2020-10-01

Family

ID=72610535

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2020/010017 WO2020195748A1 (fr) 2019-03-27 2020-03-09 Feuille métallique pour carte à circuit imprimé, feuille métallique avec support, et stratifié plaqué de métal, et procédé de fabrication de carte à circuit imprimé l'utilisant

Country Status (5)

Country Link
JP (1) JP7449921B2 (fr)
KR (1) KR20210143727A (fr)
CN (1) CN113646469A (fr)
TW (1) TW202041119A (fr)
WO (1) WO2020195748A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112911804A (zh) * 2021-01-13 2021-06-04 柏承科技(昆山)股份有限公司 能防除胶污染的退膜、除胶、化铜三合一工艺

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017141985A1 (fr) * 2016-02-18 2017-08-24 三井金属鉱業株式会社 Feuille de cuivre pour production de carte de circuit imprimé, feuille de cuivre avec support, et plaque stratifiée revêtue de cuivre, et procédé de production de carte de circuit imprimé utilisant une feuille de cuivre pour production de carte de circuit imprimé, une feuille de cuivre avec support et une plaque stratifiée revêtue de cuivre

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4515652A (en) * 1984-03-20 1985-05-07 Harris Corporation Plasma sculpturing with a non-planar sacrificial layer
US6242078B1 (en) * 1998-07-28 2001-06-05 Isola Laminate Systems Corp. High density printed circuit substrate and method of fabrication
TW513777B (en) * 2001-04-19 2002-12-11 Macronix Int Co Ltd Manufacture process of dual damascene
US6806204B1 (en) * 2003-06-30 2004-10-19 Intel Corporation Semiconductor etch speed modification
EP1985406A1 (fr) * 2007-04-25 2008-10-29 NV Bekaert SA Procédé pour fournir des fibres métalliques écroûtées
KR20090054120A (ko) * 2007-11-26 2009-05-29 엘에스엠트론 주식회사 에칭계수가 향상된 동박 적층판
TWI569705B (zh) 2011-03-30 2017-02-01 三井金屬礦業股份有限公司 多層印刷配線板的製造方法及以該製造方法所得之多層印刷配線板
US9338898B2 (en) * 2012-03-09 2016-05-10 Mitsui Mining & Smelting Co., Ltd. Method of producing a printed wiring board
JP5358740B1 (ja) * 2012-10-26 2013-12-04 Ｊｘ日鉱日石金属株式会社 キャリア付銅箔、それを用いた銅張積層板、プリント配線板、プリント回路板、及び、プリント配線板の製造方法
KR101762049B1 (ko) * 2013-06-13 2017-07-26 제이엑스금속주식회사 캐리어 부착 구리박, 구리 피복 적층판, 프린트 배선판, 전자 기기, 및, 프린트 배선판의 제조 방법
CN105813839B (zh) * 2013-12-27 2017-10-13 三井金属矿业株式会社 复合金属箔、带有载体的复合金属箔、用这些金属箔得到的覆金属层压板及印刷线路板
CN103904035B (zh) * 2014-03-05 2016-09-21 清华大学 Tcat结构及其形成方法
JP6546526B2 (ja) * 2015-12-25 2019-07-17 三井金属鉱業株式会社 キャリア付銅箔及びコアレス支持体用積層板、並びに配線層付コアレス支持体及びプリント配線板の製造方法
CN108464062B (zh) * 2016-02-18 2020-10-27 三井金属矿业株式会社 印刷电路板的制造方法
JP6471140B2 (ja) * 2016-11-30 2019-02-13 福田金属箔粉工業株式会社 複合金属箔及び該複合金属箔を用いた銅張積層板並びに該銅張積層板の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017141985A1 (fr) * 2016-02-18 2017-08-24 三井金属鉱業株式会社 Feuille de cuivre pour production de carte de circuit imprimé, feuille de cuivre avec support, et plaque stratifiée revêtue de cuivre, et procédé de production de carte de circuit imprimé utilisant une feuille de cuivre pour production de carte de circuit imprimé, une feuille de cuivre avec support et une plaque stratifiée revêtue de cuivre

Also Published As

Publication number Publication date
KR20210143727A (ko) 2021-11-29
TW202041119A (zh) 2020-11-01
JPWO2020195748A1 (fr) 2020-10-01
CN113646469A (zh) 2021-11-12
JP7449921B2 (ja) 2024-03-14

Similar Documents

Publication Publication Date Title
KR102480377B1 (ko) 조화 처리 구리박, 캐리어 구비 구리박, 동장 적층판 및 프린트 배선판
JP6836580B2 (ja) プリント配線板製造用銅箔、キャリア付銅箔及び銅張積層板、並びにそれらを用いたプリント配線板の製造方法
TW201722219A (zh) 附載體銅箔、積層體、印刷配線板之製造方法及電子機器之製造方法
JP2015199355A (ja) キャリア付銅箔、プリント配線板、積層体、積層板、電子機器及びプリント配線板の製造方法
WO2015030256A1 (fr) Feuille de cuivre avec support, panneau stratifié revêtu de cuivre, carte à circuits imprimés, dispositif électronique et procédé de fabrication d'une carte à circuits imprimés
WO2019188712A1 (fr) Feuille de cuivre rugueuse, feuille de cuivre pourvue d'un support, plaque multicouche cuivrée et carte de circuit imprimé
JP6836579B2 (ja) プリント配線板の製造方法
JP6131395B1 (ja) プリント配線板の製造方法
WO2020195748A1 (fr) Feuille métallique pour carte à circuit imprimé, feuille métallique avec support, et stratifié plaqué de métal, et procédé de fabrication de carte à circuit imprimé l'utilisant
JP6140480B2 (ja) キャリア付銅箔、キャリア付銅箔の製造方法、プリント配線板、プリント回路板、銅張積層板、及び、プリント配線板の製造方法
JP2014193592A (ja) キャリア付銅箔、キャリア付銅箔の製造方法、プリント配線板、プリント回路板、銅張積層板、及び、プリント配線板の製造方法
JP2014193591A (ja) キャリア付銅箔、キャリア付銅箔の製造方法、プリント配線板、プリント回路板、銅張積層板、及び、プリント配線板の製造方法
JP6329727B2 (ja) キャリア付銅箔、キャリア付銅箔の製造方法、プリント配線板、プリント回路板、銅張積層板、及び、プリント配線板の製造方法
JP6176948B2 (ja) キャリア付銅箔、キャリア付銅箔の製造方法、プリント回路板の製造方法、銅張積層板の製造方法、及び、プリント配線板の製造方法
WO2023189566A1 (fr) Feuille métallique dotée d'un support, stratifié revêtu de métal et circuit imprimé
WO2023189565A1 (fr) Feuille métallique fixée à un élément porteur, stratifié revêtu de métal, et carte de circuit imprimé
JP6336142B2 (ja) キャリア付銅箔、キャリア付銅箔の製造方法、プリント回路板の製造方法、銅張積層板の製造方法、及び、プリント配線板の製造方法
KR20230159393A (ko) 캐리어 구비 구리박, 동장 적층판 및 프린트 배선판

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20780063

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021508964

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20780063

Country of ref document: EP

Kind code of ref document: A1