WO2020192345A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2020192345A1
WO2020192345A1 PCT/CN2020/076811 CN2020076811W WO2020192345A1 WO 2020192345 A1 WO2020192345 A1 WO 2020192345A1 CN 2020076811 W CN2020076811 W CN 2020076811W WO 2020192345 A1 WO2020192345 A1 WO 2020192345A1
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WIPO (PCT)
Prior art keywords
electrode
thin film
base substrate
groove
film transistor
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PCT/CN2020/076811
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English (en)
French (fr)
Inventor
宋威
赵策
丁远奎
金憘槻
王明
刘宁
胡迎宾
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/959,114 priority Critical patent/US11404515B2/en
Publication of WO2020192345A1 publication Critical patent/WO2020192345A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light-Emitting Diode
  • the structure of this OLED display device mainly includes: a base substrate, a thin film transistor array formed on the base substrate, and a light emitting unit formed on the thin film transistor array; because the light emitting unit corresponds to the pixel unit included in the OLED display device one-to-one , And the light-emitting layer included in the light-emitting unit is generally realized by inkjet printing technology.
  • the prior art in order to accurately form the light-emitting layer in the corresponding position, the prior art generally prepares a pixel defining layer on the thin film transistor array.
  • the pixel defining layer defines the pixel opening area corresponding to the pixel unit one-to-one, so that when the light-emitting unit is made, inkjet printing technology can be used to stably and accurately drop the ink droplets used to form the light-emitting layer in the light-emitting unit Pixel opening area.
  • the above-mentioned pixel defining layer needs to go through processes such as coating, exposure, development, and curing during production, and the preparation process is complicated, and the organic materials used are likely to cause environmental pollution.
  • a first aspect of the present disclosure provides a display substrate, including:
  • a thin film transistor array disposed on the base substrate includes a plurality of thin film transistors, each of the thin film transistors includes a first electrode and a second electrode, wherein the first electrode includes a first portion having a height difference And a second part, wherein the height of the second part in a direction perpendicular to the base substrate is greater than the height of the first part.
  • each of the thin film transistors further includes a first insulation pattern disposed between the second portion of the first electrode and the second electrode, and the first insulation pattern is on the base substrate
  • the orthographic projection of is located between the orthographic projection of the second electrode on the base substrate and the orthographic projection of the second part of the first electrode on the base substrate.
  • a plurality of grooves for arranging light-emitting units are formed in the thin film transistor array, wherein the first part of the first electrode of each thin film transistor is located at the bottom of the groove, and the groove wall of the groove includes the The second part of the first electrode of the thin film transistor.
  • the wall of the groove further includes a second part of the first electrode of the thin film transistor adjacent to the thin film transistor.
  • the thin film transistor array defines a plurality of grooves for arranging light-emitting units on a side facing away from the base substrate, wherein the first part of the first electrode of each thin film transistor constitutes a groove of the groove At the bottom, the wall of the groove is formed by the second part of the first electrode of the thin film transistor.
  • the thin film transistor array defines a plurality of grooves for arranging light-emitting units on a side facing away from the base substrate, wherein the first part of the first electrode of each thin film transistor constitutes a groove of the groove At the bottom, the wall of the groove includes the second part of the first electrode of the thin film transistor adjacent to the thin film transistor.
  • the display substrate further includes:
  • a plurality of light emitting units are arranged in the grooves in one-to-one correspondence, and each light emitting unit is in contact with the groove bottom of the corresponding groove.
  • the groove corresponds to a thin film transistor
  • the thin film transistor further includes:
  • a gate provided on the side of the second insulation pattern facing away from the base substrate, and the orthographic projection of the gate on the base substrate is located on the second insulation pattern on the base substrate Inside the orthographic projection, the orthographic projection of the grid on the base substrate surrounds the orthographic projection of the first part of the first electrode on the base substrate.
  • the display substrate further includes: an insulating film layer disposed on the side of the thin film transistor array facing away from the base substrate, the insulating film layer covering the second part of the first electrode, the The source layer, the second insulating pattern and the gate, and the insulating film layer includes a plurality of openings corresponding to the plurality of grooves one-to-one, and each opening exposes a groove bottom of the corresponding groove.
  • each groove corresponds to two thin film transistors, and each thin film transistor further includes:
  • the active layer disposed on the side of the second electrode facing away from the base substrate, the active layer is respectively connected to the second electrode, the first insulating pattern and the first electrode of the first electrode Two-part contact
  • a second insulating pattern provided on the side of the active layer facing away from the base substrate;
  • a gate provided on the side of the second insulation pattern facing away from the base substrate, and the orthographic projection of the gate on the base substrate is located on the second insulation pattern on the base substrate The interior of the orthographic projection.
  • the gates of the two thin film transistors are connected, the second electrodes of the two thin film transistors are connected, and the first electrodes of the two thin film transistors are connected.
  • the height of the second electrode is the same as the height of the second part of the first electrode;
  • the height of the first insulating pattern is the same as the height of the second portion of the first electrode.
  • the first electrode and the second electrode are one of a source electrode and a drain electrode, respectively.
  • a second aspect of the present disclosure provides a display device including the above display substrate.
  • a third aspect of the present disclosure provides a manufacturing method of a display substrate, including:
  • a thin film transistor array is fabricated on the base substrate, the thin film transistor array includes a plurality of thin film transistors, each of the thin film transistors includes a first electrode and a second electrode, wherein the first electrode includes a first portion with a height difference and The second part, wherein the height of the second part in a direction perpendicular to the base substrate is greater than the height of the first part.
  • the manufacturing method further includes:
  • An insulating film layer is fabricated on the side of the thin film transistor array facing away from the base substrate, the insulating film layer includes a plurality of openings corresponding to the plurality of grooves one-to-one, and each opening exposes a corresponding groove The bottom of the groove;
  • a plurality of light-emitting units are fabricated in the plurality of grooves, and the light-emitting units are in one-to-one correspondence with the grooves, and each light-emitting unit is in contact with the groove bottom of the corresponding groove.
  • the insulating film layer includes an inorganic layer
  • the light-emitting unit includes a first pixel electrode and a second pixel electrode disposed opposite to each other, and a second pixel electrode disposed between the first pixel electrode and the second pixel electrode.
  • the steps of manufacturing the light-emitting unit specifically include:
  • the second pixel electrode is formed on the side of the organic light-emitting function layer facing away from the bottom of the groove.
  • the step of fabricating the second electrode and the first electrode in the thin film transistor specifically includes:
  • the second electrode and the first electrode are fabricated.
  • the height of the second electrode is the same as the height of the second part of the first electrode. the same.
  • Figures 1a-1g are schematic cross-sectional views of grooves in the first mode and the third mode provided by the embodiments of the disclosure;
  • FIGS. 2a-2g are schematic cross-sectional views of the groove in the second manner provided by the embodiments of the disclosure.
  • FIG. 3 is a top view of a thin film transistor provided by an embodiment of the disclosure.
  • FIG. 4 is a top view of another thin film transistor provided by an embodiment of the disclosure.
  • FIG. 5 is a top view of two thin film transistors corresponding to one groove provided by an embodiment of the disclosure.
  • FIG. 6 is a top view of a groove after forming an insulating film layer according to an embodiment of the disclosure.
  • FIG. 7 is a top view of an RGB pixel unit provided by an embodiment of the disclosure.
  • an embodiment of the present disclosure provides a display substrate, including a base substrate 10 and a thin film transistor array disposed on the base substrate 10, the thin film transistor array includes a plurality of thin film transistors, each thin film transistor Each of the first electrodes 13 includes a first portion 131 and a second portion 132 having a height difference. In the direction perpendicular to the base substrate 10, the height of the second portion 132 is higher than the height of the first portion 131.
  • the position, shape, and size of the first electrode 13 of the thin film transistor included in the thin film transistor array can be set so that the thin film transistor array can be turned back to the base substrate 10.
  • One side defines a plurality of grooves.
  • the first electrode 13 in each thin film transistor can be configured to include a first portion 131 and a second portion 132 that are connected, and are arranged in a direction perpendicular to the base substrate 10, and the second portion 132 Is higher than the height of the first part 131, so that the second part 132 of the first electrode 13 in each thin film transistor can be used as the groove wall of the groove, and the first part 131 of the first electrode 13 in each thin film transistor can be used as the groove At the bottom of the groove, on the side of the thin-film transistor array facing away from the base substrate 10, a plurality of grooves with accommodating functions are defined.
  • one thin film transistor can be used to define a groove, or through multiple adjacent thin films.
  • the transistors collectively define a groove.
  • the first part 131 of the first electrode 13 in the thin film transistor serves as the bottom of the defined groove
  • the second part 132 of the first electrode 13 in the thin film transistor serves as the bottom of the defined groove.
  • the first portion 131 of the first electrode 13 in one thin film transistor serves as the bottom of the defined groove, and the first electrode 13 in the adjacent thin film transistor
  • the two parts 132 are all used as the groove walls of the defined groove; or, the first part 131 of the first electrode 13 in the plurality of thin film transistors is used as the groove bottom of the defined groove, and the first electrode of the plurality of thin film transistors
  • the second part 132 of 13 all serves as the groove wall of the defined groove.
  • the groove defined by the thin film transistor array should have a certain depth, which can at least accommodate the light-emitting unit, so that when the light-emitting unit is formed in the groove, the groove wall of the groove can be equivalent to the pixel in the prior art
  • the bank of the delimiting layer and the space in the groove are equivalent to the pixel opening area defined by the pixel delimiting layer in the prior art.
  • the first electrode 13 in each thin film transistor included in the thin film transistor array is configured to include a first portion 131 and a second portion 132 with different heights, so that The first portion 131 and the second portion 132 of the first electrode 13 in each thin film transistor can define a plurality of grooves on the side of the thin film transistor array facing away from the base substrate 10, and the groove walls of the plurality of grooves are equivalent to the current
  • the bank of the pixel defining layer in the prior art, and the space in the groove of the groove is equivalent to the pixel opening area defined by the pixel defining layer in the prior art, so that when the light emitting layer in the light emitting unit is made, inkjet printing technology can be used directly
  • the light-emitting layer is formed in the groove, and there is no need to make an additional pixel defining layer to define the pixel area for making the light-emitting unit.
  • the display substrate provided by the embodiment of the present disclosure avoids the use of coating, exposure, development and
  • the pixel defining layer is made by curing and other processes, which simplifies the preparation process of the display substrate; at the same time, it also avoids the problem of environmental pollution caused by using organic materials to make the pixel defining layer.
  • the display substrate provided in the above embodiments further includes:
  • the insulating film layer 18 is arranged on the side of the thin film transistor array facing away from the base substrate 10.
  • the insulating film layer 18 includes a plurality of openings corresponding to the plurality of grooves one by one, and the openings expose the groove bottom of the corresponding groove (such as The first part 131) in Figure 1g;
  • a number of light-emitting units are arranged in the grooves in a one-to-one correspondence, and the light-emitting units are in contact with the groove bottom of the corresponding groove, and the thin film transistor corresponding to the groove is used to output the driving signal to the corresponding light-emitting unit through the groove bottom. To drive the light-emitting unit to emit light.
  • the insulating film layer 18 provided on the side of the thin film transistor array facing away from the base substrate 10 has various specific types.
  • it may be a passivation layer.
  • the size of the opening provided on the insulating film layer 18 can be set according to actual needs.
  • the opening only exposes the first portion 131 of the first electrode 13 and does not expose other film layers included in the thin film transistor.
  • the insulating film layer 18 can be set to completely cover the inner sidewalls of the groove, so that the light-emitting unit formed in the groove can only contact the first portion 131 of the first electrode 13 as the groove bottom, but not It is in contact with other film layers in the thin film transistor to avoid short circuit between the light-emitting unit and other film layers in the thin film transistor, thereby ensuring the stable working performance of the display substrate.
  • the orthographic projection of the insulating film layer 18 on the base substrate 10 can surround the orthographic projection of the first portion 131 of the first electrode 13 on the base substrate 10.
  • the structure of a thin film transistor generally includes a gate 17, a second electrode 12, a first electrode 13, an active layer 15 and an insulating layer, etc., and its working mode is to receive the second electrode 12 under the control of the gate 17.
  • the driving signal is output to the light-emitting unit through the first electrode 13 to drive the light-emitting unit to emit light.
  • the insulating film layer 18 is provided on the side of the thin film transistor array facing away from the base substrate 10, and the insulating film layer 18 can be formed One-to-one correspondence exposes the openings at the bottom of the groove, so that the light-emitting unit formed in the groove can only contact the bottom of the groove (that is, the first part 131 of the first electrode 13 in the corresponding thin film transistor), which not only ensures that the thin film transistor can pass through it.
  • the included first portion 131 of the first electrode 13 transmits the driving signal to the corresponding light-emitting unit, and avoids short circuit between the light-emitting unit and other film layers in the thin film transistor, and ensures the stable working performance of the display substrate.
  • the light-emitting unit provided by the above-mentioned embodiments may include two electrodes arranged oppositely and a light-emitting layer arranged between the two electrodes; the groove bottom of the groove is in contact with the light-emitting layer in the corresponding light-emitting unit, and the groove The groove bottom is multiplexed as one of the electrodes in the corresponding light-emitting unit.
  • the groove bottom of the groove corresponding to the light-emitting unit can be exposed through the opening on the insulating film layer 18, and the groove bottom of the groove can be in contact with the corresponding light-emitting unit to provide driving signals for the light-emitting unit, Therefore, the groove bottom of the groove can be directly reused as one of the electrodes in the corresponding light-emitting unit, so that when the light-emitting unit is made, the light-emitting layer can be directly formed on the groove bottom of the corresponding groove, and then the light-emitting layer
  • the other electrode of the light-emitting unit is fabricated on the side facing away from the groove bottom to complete the production of the light-emitting unit, which simplifies the production process of the light-emitting unit and reduces the production cost of the display substrate.
  • the thin film Transistors specifically include:
  • the first insulating pattern 14, the second electrode 12 and the first electrode 13 are arranged on the base substrate 10.
  • the orthographic projection of the second electrode 12 on the base substrate 10 surrounds the first insulating pattern 14 on the base substrate 10.
  • Orthographic projection, the orthographic projection of the first insulating pattern 14 on the base substrate 10 surrounds the orthographic projection of the first electrode 13 on the base substrate 10, and the second portion 132 of the first electrode 13 is on the base substrate 10
  • the projection surrounds the orthographic projection of the first portion 131 in the first electrode 13 on the base substrate 10;
  • the active layer 15 disposed on the side of the second electrode 12 facing away from the base substrate 10 is in contact with the second electrode 12, the first insulating pattern 14 and the second portion 132 of the first electrode 13, respectively,
  • the orthographic projection of the source layer 15 on the base substrate 10 encompasses the orthographic projection of the first portion 131 in the first electrode 13 on the base substrate 10;
  • the gate 17 is arranged on the side of the second insulating pattern 16 facing away from the base substrate 10.
  • the orthographic projection of the gate 17 on the base substrate 10 is located inside the orthographic projection of the second insulating pattern 16 on the base substrate 10.
  • the orthographic projection of the gate 17 on the base substrate 10 surrounds the orthographic projection of the first portion 131 in the first electrode 13 on the base substrate 10.
  • the first electrode 13 having the first portion 131 and the second portion 132 of different heights is fabricated on the base substrate 10, and the second portion 132 of the first electrode 13 is arranged on the substrate 10
  • the orthographic projection on the base substrate 10 surrounds the orthographic projection of the first portion 131 of the first electrode 13 on the base substrate 10, so that the first electrode 13 can be formed into a groove structure, and then the The pattern 14 and the second part 132 of the first electrode 13 on the side facing away from the base substrate 10 are successively fabricated to form an active layer 15, a second insulating pattern 16 and a gate 17, and an active layer 15,
  • the second insulating pattern 16 and the gate 17 are both formed around the first portion 131 of the first electrode 13, so that the sidewall of the groove formed by the second portion 132 of the first electrode 13 is high in the direction perpendicular to the base substrate 10.
  • the groove has a deeper depth in the direction perpendicular to the base substrate 10.
  • the insulating film layer 18 can expose the first portion 131 of the first electrode 13 at the bottom of the groove, and at the same time cover the second portion 132 of the first electrode 13 and The sidewalls of the groove extend to the height of the active layer 15, the second insulating pattern 16 and the gate 17.
  • the thin film transistor of the above-mentioned structure can define a closed groove, so that when the ink droplet used to form the light-emitting layer in the light-emitting unit is dropped into the groove using inkjet printing technology, the ink drop can be confined in the groove , And will not flow into other non-pixel areas, thus avoiding the spread of ink droplets in other areas and polluting adjacent pixels, causing cross-color phenomenon.
  • the second portions 132 of the two thin film transistors are respectively arranged on opposite sides of the groove, and the thin film transistor specifically includes:
  • the first insulating pattern 14, the second electrode 12, and the first electrode 13 are arranged on the base substrate 10, and the first insulating pattern 14 is arranged between the second electrode 12 and the first electrode 13;
  • the active layer 15 disposed on the side of the second electrode 12 facing away from the base substrate 10, the active layer 15 is in contact with the second electrode 12, the first insulating pattern 14 and the second portion 132 of the first electrode 13 respectively;
  • a second insulating pattern 16 provided on the side of the active layer 15 facing away from the base substrate 10;
  • the gate 17 is arranged on the side of the second insulating pattern 16 facing away from the base substrate 10.
  • the orthographic projection of the gate 17 on the base substrate 10 is located inside the orthographic projection of the second insulating pattern 16 on the base substrate 10. .
  • each groove corresponds to two thin film transistors, that is, each groove is jointly defined by the first electrodes 13 included in the two thin film transistors, and the first part 131 of one of the two thin film transistors is used as The bottom of the groove defined by the thin film transistor.
  • the second parts 132 of the two thin film transistors corresponding to the groove are respectively disposed on opposite sides of the groove, and respectively form two opposite groove walls in the groove, and the first electrode 13 in a thin film transistor
  • the first part 131 of the first electrode 13 of the thin film transistor is located between the two groove walls.
  • the first part 131 of the first electrode 13 of the thin film transistor is only electrically connected to the second part 132 of the first electrode 13 of the thin film transistor.
  • the second portion 132 of the first electrode 13 of the other thin film transistor is insulated.
  • the two thin film transistors are two independent thin film transistors that respectively control different light-emitting units.
  • the second portions 132 of the two thin film transistors corresponding to the groove are respectively disposed on opposite sides of the groove, respectively corresponding to form two opposite groove walls in the groove, and then pass in each groove.
  • the second electrode 12 corresponding to a thin film transistor, the first insulating pattern 14 and the second portion 132 of the first electrode 13 are formed on the side facing away from the base substrate 10 in order to form a laminated active layer 15, and the second insulating pattern 16 and the gate 17 so that the sidewall of the groove formed by the second portion 132 of each first electrode 13 is extended in the direction perpendicular to the base substrate 10, so that the groove is in the direction perpendicular to the base substrate 10.
  • the above has a deeper depth.
  • the insulating film layer 18 can expose the first part 131 of the first electrode 13 at the bottom of the groove, and at the same time cover the second part 132 of the first electrode 13 and The sidewalls of the groove extend to the height of the active layer 15, the second insulating pattern 16 and the gate electrode 17.
  • the structure of the groove defined by the thin film transistor of the above structure is different from the first method.
  • the groove defined by the two thin film transistors only includes opposite groove walls. However, when inkjet printing technology is used, it will be used for When the ink droplets forming the light-emitting layer in the light-emitting unit are dropped into the groove, the ink droplets can also be confined in the groove and will not flow to other areas.
  • the second parts 132 of the two thin film transistors are respectively arranged on opposite sides of the groove, and the thin film transistors specifically include:
  • the first insulating pattern 14, the second electrode 12, and the first electrode 13 are arranged on the base substrate 10, and the first insulating pattern 14 is arranged between the second electrode 12 and the first electrode 13;
  • the active layer 15 disposed on the side of the second electrode 12 facing away from the base substrate 10, the active layer 15 is in contact with the second electrode 12, the first insulating pattern 14 and the second portion 132 of the first electrode 13 respectively;
  • a second insulating pattern 16 provided on the side of the active layer 15 facing away from the base substrate 10;
  • the gate 17 is arranged on the side of the second insulating pattern 16 facing away from the base substrate 10.
  • the orthographic projection of the gate 17 on the base substrate 10 is located inside the orthographic projection of the second insulating pattern 16 on the base substrate 10. ;
  • the gates 17 of the two thin film transistors are connected, the second electrodes 12 of the two thin film transistors are connected, and the first electrodes 13 of the two thin film transistors are connected.
  • the aforementioned groove corresponds to two thin film transistors
  • the groove is jointly defined by the first electrodes 13 included in the two thin film transistors
  • the first portion 131 of the first electrode 13 in the two thin film transistors is used as The bottom of the groove defined by the two thin film transistors.
  • the second parts 132 of the two thin film transistors corresponding to the groove are respectively disposed on opposite sides of the groove, and respectively form two opposite groove walls in the groove.
  • the first portion 131 of the electrode 13 is located between the two groove walls, and the gates 17 of the two thin film transistors are connected, the second electrodes 12 of the two thin film transistors are connected, and the first electrodes 13 of the two thin film transistors are connected (also The same first electrode 13) can be shared, and the two thin film transistors are used to drive the same light-emitting unit.
  • the second parts 132 of the two thin film transistors corresponding to the groove are respectively disposed on two opposite sides of the groove, and respectively form two opposite groove walls in the groove, and then pass through
  • the first insulating pattern 14 and the second portion 132 of the first electrode 13 corresponding to each thin film transistor a stacked active layer 15 is sequentially formed on the side facing away from the base substrate 10.
  • the insulating pattern 16 and the gate 17 make the side wall of the groove formed by the second portion 132 of each first electrode 13 extend in the direction perpendicular to the base substrate 10 so that the groove is perpendicular to the base substrate 10. The direction has a deeper depth.
  • the insulating film layer 18 can expose the first portion 131 of the first electrode 13 at the bottom of the groove, and at the same time cover the second portion 132 of the first electrode 13 and The sidewalls of the groove extend to the height of the active layer 15, the second insulating pattern 16 and the gate 17.
  • the groove defined by the thin film transistor of the above structure only includes opposite groove walls. However, when ink droplets used to form the light-emitting layer in the light-emitting unit are dropped into the pixel area using inkjet printing technology, the ink droplets can also be Confined in the groove, and will not flow into other non-pixel areas.
  • the second electrode 12 in each thin film transistor may include a drain electrode, and the first electrode 13 may include a source electrode; or, the second electrode 12 may include a source electrode, and the first electrode 13 may include a drain electrode. pole.
  • the above three methods can be selected according to actual needs. More specifically, among the above three methods, the first method and the second method are both driven by a thin film transistor to drive a corresponding light-emitting unit.
  • the third method is to drive a corresponding light-emitting unit through two thin film transistors.
  • the first mode and the second mode can be selected.
  • the third mode can be selected.
  • the second electrode 12 may be arranged in a direction perpendicular to the base substrate 10, and the height of the second electrode 12 is the same as the height of the second portion 132 in the first electrode 13; and/or, in a direction perpendicular to the base substrate In the direction of 10, the height of the first insulating pattern 14 is the same as the height of the second portion 132 in the first electrode 13.
  • the second electrode 12, the second portion 132 of the first electrode 13 and/or the surface of the first insulating pattern 14 away from the base substrate 10 may have the same height, that is, at least two The surface away from the base substrate 10 may be formed as a flat surface.
  • the height of the second electrode 12 is set to be the same as the height of the second portion 132 in the first electrode 13; and/or the height of the first insulating pattern 14 is set to be the same as the height of the first insulating pattern 14
  • the height of the second portion 132 in one electrode 13 is the same, so that the active layer 15 formed above the three parts will not have a step difference, that is, the surface of the active layer 15 for forming the second insulating pattern 16 is flatter, thereby The second insulating pattern 16 and the gate 17 formed on the active layer 15 will not have a step difference, which is more conducive to the stability of the display substrate.
  • the second portion 132 provided with the second electrode 12 and the first electrode 13 has a thicker thickness in the direction perpendicular to the base substrate 10, so that the resistance of the second electrode 12 and the first electrode 13 is smaller and more suitable Large size display substrate needs.
  • the portion of the insulating film layer 18 outside the groove is hydrophobic on the surface facing away from the base substrate 10.
  • the part of the insulating film layer 18 outside the groove can be exposed by ultraviolet light, so that the part of the insulating film layer 18 outside the groove has a surface facing away from the base substrate 10. Hydrophobicity.
  • the part where the insulating film layer 18 is located outside the groove has hydrophobicity on the surface facing away from the base substrate 10.
  • the droplets used to form the light-emitting layer can be printed into the groove more stably and accurately.
  • the embodiments of the present disclosure also provide a display device, including the display substrate provided in the above-mentioned embodiments.
  • the display substrate provided by the above embodiments not only the use of coating, exposure, development, and curing processes to make the pixel defining layer is avoided, and the manufacturing process of the display substrate is simplified, but it also avoids the use of organic materials to make the pixel defining layer. It will cause environmental pollution; therefore, when the display device provided by the embodiments of the present disclosure includes the display substrate provided by the above-mentioned embodiments, it also has the advantages of simple manufacturing process, saving manufacturing cost, and no pollution to the environment.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a mobile phone, a tablet computer, etc.
  • the embodiments of the present disclosure also provide a manufacturing method of a display substrate, which is used to manufacture the display substrate provided in the above embodiment, and the manufacturing method includes:
  • a thin film transistor array is fabricated on the base substrate 10.
  • the thin film transistor array includes a plurality of thin film transistors.
  • the first electrode 13 in each thin film transistor includes a first portion 131 and a second portion 132 with a height difference, which are perpendicular to the substrate. In the direction of the substrate 10, the height of the second portion 132 is higher than the height of the first portion 131.
  • a base substrate 10 is provided first.
  • the base substrate 10 can be a glass substrate, and then a thin film transistor array can be fabricated on the base substrate 10 by using the manufacturing process of thin film transistors in the prior art.
  • the position, shape and size of the first electrode 13 of the thin film transistor included in the TFT enable the thin film transistor array to define a plurality of grooves on the side facing away from the base substrate 10.
  • the first electrode 13 in each thin film transistor may be formed to include a first portion 131 and a second portion 132 that are connected, and the second portion 132 is provided in a direction perpendicular to the base substrate 10.
  • the second portion 132 of the first electrode 13 in each thin film transistor can be used as the groove wall of the groove, and the first portion 131 of the first electrode 13 in each thin film transistor can be used as the groove
  • the bottom of the groove defines a plurality of grooves with accommodating functions on the side of the thin film transistor array facing away from the base substrate 10.
  • the first electrode 13 in each thin film transistor included in the thin film transistor array is formed to include a first portion 131 and a second portion 132 with different heights, so that the first electrode 13 in each thin film transistor
  • the first portion 131 and the second portion 132 of an electrode 13 can define a plurality of grooves on the side of the thin film transistor array facing away from the base substrate 10, and the groove walls of the plurality of grooves are equivalent to the pixel defining layer in the prior art
  • the space in the groove of the groove is equivalent to the pixel opening area defined by the pixel defining layer in the prior art, so that when the light-emitting layer in the light-emitting unit is made, the ink-jet printing technology can be directly used to form the light-emitting layer in the groove , There is no need to additionally fabricate a pixel defining layer to limit the pixel area used to fabricate the light-emitting unit.
  • the fabrication method provided by the embodiments of the present disclosure avoids the use of coating, exposure, development, and curing processes to fabricate pixels when fabricating the display substrate.
  • the defining layer simplifies the preparation process of the display substrate; at the same time, it also avoids the problem of environmental pollution caused by the use of organic materials to make the pixel defining layer.
  • the above manufacturing method further includes:
  • An insulating film layer 18 is fabricated on the side of the thin film transistor array facing away from the base substrate 10.
  • the insulating film layer 18 includes a plurality of openings corresponding to the plurality of grooves one-to-one, and the openings expose the groove bottom of the corresponding groove;
  • Multiple light-emitting units are fabricated in multiple grooves, the light-emitting units and the grooves are in one-to-one correspondence, and the light-emitting units are in contact with the groove bottom of the corresponding groove, and the thin film transistor corresponding to the groove is used to pass the driving signal through the groove bottom. Output to the corresponding light-emitting unit to drive the light-emitting unit to emit light.
  • the insulating film layer 18 can be deposited on the side of the thin film transistor array facing away from the base substrate 10, and the insulating film layer 18 can be formed on the insulating film layer 18 through a patterning process. There are a plurality of openings, and each opening exposes the bottom of the corresponding groove, and then a corresponding light-emitting unit is formed in each groove, and the light-emitting unit is in contact with the bottom of the corresponding groove.
  • the material of the insulating film layer 18 can be silicon oxide, silicon nitride, aluminum oxide, etc., and the insulating film layer 18 can be used as a passivation layer.
  • the size of the opening formed on the insulating film layer 18 can be set according to actual needs.
  • the opening only exposes the first portion 131 of the first electrode 13 and does not expose other film layers included in the thin film transistor.
  • the insulating film layer 18 can completely cover the inner side wall of the groove, so that the light-emitting unit formed in the groove can only contact the first part 131 of the first electrode 13 as the groove bottom, but not It is in contact with other film layers in the thin film transistor, which not only ensures that the thin film transistor can transmit the driving signal to the corresponding light-emitting unit through the first part 131 of the first electrode 13 included, but also avoids the light-emitting unit and the thin film transistor.
  • the other film layers are short-circuited, thereby ensuring the stable working performance of the display substrate.
  • the above-mentioned light-emitting unit may include two electrodes arranged opposite to each other and a light-emitting layer arranged between the two electrodes; the above-mentioned step of fabricating the light-emitting unit in the groove specifically includes:
  • a light-emitting layer is fabricated in the groove, and the light-emitting layer is in contact with the groove bottom of the corresponding groove.
  • the groove bottom of the groove is multiplexed as one of the electrodes in the corresponding light-emitting unit.
  • the other electrode in the light-emitting unit is fabricated on the side.
  • the bottom of the groove can be directly reused as one of the electrodes in the corresponding light-emitting unit, so that when the light-emitting unit is made, inkjet printing technology can be used to form the ink droplets of the light-emitting layer in the light-emitting unit.
  • a light-emitting layer is formed on the groove bottom, and then another electrode of the light-emitting unit is fabricated on the side of the light-emitting layer facing away from the groove bottom to complete the production of the light-emitting unit.
  • the above multiplexing the bottom of the groove as an electrode in the light-emitting unit better simplifies the manufacturing process of the light-emitting unit and reduces the manufacturing cost of the display substrate.
  • the steps of manufacturing a thin film transistor specifically include:
  • the first insulating pattern 14, the second electrode 12, and the first electrode 13 are fabricated on the base substrate 10.
  • the orthographic projection of the second electrode 12 on the base substrate 10 surrounds the front of the first insulating pattern 14 on the base substrate 10. Projection, the orthographic projection of the first insulating pattern 14 on the base substrate 10 surrounds the orthographic projection of the first electrode 13 on the base substrate 10, and the orthographic projection of the second portion 132 of the first electrode 13 on the base substrate 10 The orthographic projection of the first portion 131 in the surrounding first electrode 13 on the base substrate 10;
  • An active layer 15 is fabricated on the side of the second electrode 12 facing away from the base substrate 10.
  • the active layer 15 is in contact with the second electrode 12, the first insulating pattern 14 and the second portion 132 of the first electrode 13, respectively.
  • a second insulating pattern 16 is formed on the side of the active layer 15 facing away from the base substrate 10.
  • the orthographic projection of the second insulating pattern 16 on the base substrate 10 surrounds the first portion 131 of the first electrode 13 on the base substrate Orthographic projection on 10;
  • a grid 17 is fabricated on the side of the second insulating pattern 16 facing away from the base substrate 10.
  • the orthographic projection of the grid 17 on the base substrate 10 is located inside the orthographic projection of the second insulating pattern 16 on the base substrate 10.
  • the orthographic projection of the gate 17 on the base substrate 10 surrounds the orthographic projection of the first portion 131 in the first electrode 13 on the base substrate 10.
  • a magnetron sputtering device is first used to deposit a conductive film 11 on the base substrate 10, and the conductive film 11 is patterned.
  • a second electrode 12 is formed.
  • the first electrode 13 the material of the conductive film 11 can be Cu, Al or indium tin oxide (ITO), etc.; then the first insulating film is formed by plasma enhanced chemical vapor deposition, and the first insulating film is patterned.
  • a first insulating pattern 14 is formed.
  • the material of the first insulating film can be silicon oxide, silicon nitride, etc., or organic matter can be used to make the first insulating pattern 14.
  • the fabricated first electrode 13 includes a first portion 131 and a second portion 132, and in the direction perpendicular to the base substrate 10, the height of the second portion 132 is higher than the height of the first portion 131, and the second When the height of the portion 132 is the same as the height of the second electrode 12, a halftone mask can be used to realize the simultaneous formation of the second electrode 12, the first portion 131 and the second portion 132 of the first electrode 13 through one patterning process.
  • the active layer 15 in contact with the second portion 132 of the first electrode 13 is an orthographic projection of the active layer 15 on the base substrate 10, surrounding the first portion 131 of the first electrode 13 on the base substrate 10. Orthographic projection.
  • plasma enhanced chemical vapor deposition is continued to form a second insulating film on the side of the active layer 15 facing away from the base substrate 10, and the second insulating film is patterned to form a second insulating film.
  • the insulating pattern 16, the material of the second insulating film can be silicon oxide, silicon nitride, etc., and the second insulating pattern 16 is used as the gate insulating layer in the thin film transistor.
  • the second insulating pattern 16 is formed on the base substrate 10
  • the orthographic projection surrounds the orthographic projection of the first portion 131 of the first electrode 13 on the base substrate 10.
  • a magnetron sputtering device is finally used to deposit a conductive film on the side of the second insulating pattern 16 that faces away from the base substrate 10, and the conductive film is patterned to form a gate 17, which
  • the orthographic projection of the electrode 17 on the base substrate 10 is located inside the orthographic projection of the second insulation pattern 16 on the base substrate 10, and the orthographic projection of the gate 17 on the base substrate 10 surrounds the first portion 131 of the first electrode 13 Orthographic projection on the base substrate 10;
  • the material of the above-mentioned conductive film can be Cu, Al, or indium tin oxide (ITO).
  • the first electrode 13 having the first portion 131 and the second portion 132 of different heights is fabricated on the base substrate 10, and the second portion 132 of the first electrode 13 is arranged on the substrate 10
  • the orthographic projection on the base substrate 10 surrounds the orthographic projection of the first portion 131 of the first electrode 13 on the base substrate 10, so that the first electrode 13 can be formed into a groove structure, and then the The pattern 14 and the second part 132 of the first electrode 13 on the side facing away from the base substrate 10 are successively fabricated to form an active layer 15, a second insulating pattern 16 and a gate 17, and an active layer 15,
  • the second insulating pattern 16 and the gate 17 are both formed around the first portion 131 of the first electrode 13, so that the sidewall of the groove formed by the second portion 132 of the first electrode 13 is high in the direction perpendicular to the base substrate 10.
  • the groove has a deeper depth in the direction perpendicular to the base substrate 10.
  • the insulating film layer 18 can expose the first portion 131 of the first electrode 13 at the bottom of the groove, and at the same time cover the second portion 132 of the first electrode 13 and The sidewalls of the groove extend to the height of the active layer 15, the second insulating pattern 16 and the gate 17.
  • the thin film transistor fabricated by the above-mentioned manufacturing method can define a closed groove, so that when ink droplets used to form the light-emitting layer in the light-emitting unit are dropped into the groove using inkjet printing technology, the ink droplets can be confined in the groove. In the groove, it will not flow to other areas, thereby avoiding the spread of ink droplets in other areas and polluting adjacent pixels, causing cross-color phenomenon.
  • the steps of making a thin film transistor specifically include :
  • first insulating pattern 14 a second electrode 12, and a first electrode 13 on a base substrate 10, and the first insulating pattern 14 is disposed between the second electrode 12 and the first electrode 13;
  • An active layer 15 is formed on the side of the second electrode 12 facing away from the base substrate 10, and the active layer 15 is in contact with the second electrode 12, the first insulating pattern 14 and the second portion 132 of the first electrode 13 respectively;
  • a gate 17 is fabricated on the side of the second insulation pattern 16 facing away from the base substrate 10, and the orthographic projection of the gate 17 on the base substrate 10 is located inside the orthographic projection of the second insulation pattern 16 on the base substrate 10.
  • a magnetron sputtering device is first used to deposit a conductive film 11 on the base substrate 10, and the conductive film 11 is patterned.
  • a second electrode 12 is formed.
  • the first electrode 13 the material of the conductive film 11 can be Cu, Al or indium tin oxide (ITO), etc.; then the first insulating film is formed by plasma enhanced chemical vapor deposition, and the first insulating film is patterned.
  • the first insulating pattern 14 is formed.
  • the material of the first insulating film can be silicon oxide, silicon nitride, etc., or organic matter can be used to make the first insulating pattern 14.
  • the fabricated first electrode 13 includes a first portion 131 and a second portion 132, and in the direction perpendicular to the base substrate 10, the height of the second portion 132 is higher than the height of the first portion 131, and the second When the height of the portion 132 is the same as the height of the second electrode 12, a halftone mask can be used to realize the simultaneous formation of the second electrode 12, the first portion 131 and the second portion 132 of the first electrode 13 through one patterning process.
  • the second electrode 12 and the first insulating pattern 14 is the active layer 15 in contact with the second portion 132 of the first electrode 13.
  • plasma enhanced chemical vapor deposition is continued to form a second insulating film on the side of the active layer 15 facing away from the base substrate 10, and the second insulating film is patterned to form a second insulating film.
  • the material of the second insulating film can be silicon oxide, silicon nitride, etc., and the second insulating pattern 16 serves as the gate insulating layer in the thin film transistor.
  • a magnetron sputtering device is used to deposit a conductive film on the side of the second insulating pattern 16 facing away from the base substrate 10, and the conductive film is patterned to form a gate 17, which is The orthographic projection of the pole 17 on the base substrate 10 is located inside the orthographic projection of the second insulating pattern 16 on the base substrate 10.
  • the material of the conductive film can be Cu, Al, or indium tin oxide (ITO).
  • the above-mentioned groove corresponds to two thin film transistors, and the groove is jointly defined by the first electrodes 13 included in the two thin film transistors, and the first part 131 of the first electrode 13 in one thin film transistor serves as the groove bottom of the groove.
  • the second portions 132 of the two thin film transistors corresponding to the groove are respectively arranged on opposite sides of the groove, and respectively form two opposite groove walls in the groove, and the first electrode in one thin film transistor
  • the first part 131 of 13 is located between the two groove walls.
  • the first part 131 of the first electrode 13 of the thin film transistor is only electrically connected to the second part 132 of the first electrode 13 of the thin film transistor, and is connected to the two thin film transistors.
  • the second portion 132 of the first electrode 13 of the other thin film transistor is insulated.
  • the two thin film transistors are two independent thin film transistors that respectively control different light-emitting units.
  • the second portions 132 of the two thin film transistors corresponding to the groove are respectively arranged on two opposite sides of the groove, and two opposite groove walls in the groove are formed correspondingly.
  • the second electrode 12 corresponding to a thin film transistor, the first insulating pattern 14 and the second portion 132 of the first electrode 13 are formed on the side facing away from the base substrate 10 in order to form a laminated active layer 15, and the second insulating pattern 16 and the gate 17 so that the side wall of the groove formed by the second portion 132 of each first electrode 13 is extended in the direction perpendicular to the base substrate 10, so that the groove is in the direction perpendicular to the base substrate 10.
  • the above has a deeper depth.
  • the insulating film layer 18 can expose the first portion 131 of the first electrode 13 at the bottom of the groove, and at the same time cover the second portion 132 of the first electrode 13 and The sidewalls of the groove extend to the height of the active layer 15, the second insulating pattern 16 and the gate 17.
  • the structure of the groove defined by the thin film transistor manufactured by the above-mentioned manufacturing method is different from the first method.
  • the groove defined by the two thin film transistors only includes opposite groove walls.
  • the inkjet printing technology is used. When the ink droplet used to form the light-emitting layer in the light-emitting unit is dropped into the groove, the ink droplet can also be confined in the groove and will not flow to other areas.
  • the steps of manufacturing the thin film transistor specifically include:
  • first insulating pattern 14 a second electrode 12, and a first electrode 13 on a base substrate 10, and the first insulating pattern 14 is disposed between the second electrode 12 and the first electrode 13;
  • An active layer 15 is formed on the side of the second electrode 12 facing away from the base substrate 10, and the active layer 15 is in contact with the second electrode 12, the first insulating pattern 14 and the second portion 132 of the first electrode 13 respectively;
  • the gates 17 of the two thin film transistors are connected, the second electrodes 12 of the two thin film transistors are connected, and the first electrodes 13 of the two thin film transistors are connected.
  • a magnetron sputtering device is first used to deposit a conductive film 11 on the base substrate 10, and the conductive film 11 is patterned to form the second electrode 12 and the first electrode 13.
  • the material of the conductive film 11 Cu, Al, or indium tin oxide (ITO) can be selected; plasma-enhanced chemical vapor deposition is then used to form a first insulating film, and the first insulating film is patterned to form a first insulating pattern 14.
  • the material of the insulating film can be silicon oxide, silicon nitride, etc., or organic matter can also be used to make the first insulating pattern 14.
  • the fabricated first electrode 13 includes a first portion 131 and a second portion 132, and in the direction perpendicular to the base substrate 10, the height of the second portion 132 is higher than the height of the first portion 131, and the second When the height of the portion 132 is the same as the height of the second electrode 12, a halftone mask can be used to realize the simultaneous formation of the second electrode 12, the first portion 131 and the second portion 132 of the first electrode 13 through one patterning process.
  • the material of the two insulating films can be silicon oxide, silicon nitride, etc., and the second insulating pattern 16 serves as the gate insulating layer in the thin film transistor.
  • a magnetron sputtering device is used to deposit a conductive film 11 on the side of the second insulating pattern 16 that faces away from the base substrate 10, and the conductive film 11 is patterned to form a gate 17, which is on the lining
  • the orthographic projection on the base substrate 10 is located inside the orthographic projection of the second insulating pattern 16 on the base substrate 10, and the material of the conductive film 11 can be Cu, Al, or indium tin oxide (ITO).
  • the above-mentioned groove corresponds to two thin film transistors.
  • the groove is jointly defined by the first electrodes 13 included in the two thin film transistors, and the first portion 131 of the first electrode 13 in the two thin film transistors is used as the The bottom of the groove defined by the transistor.
  • the second parts 132 of the two thin film transistors corresponding to the groove are respectively disposed on opposite sides of the groove, and respectively form two opposite groove walls in the groove.
  • the first part 131 of the electrode 13 is located between the two groove walls, and the gates 17 of the two thin film transistors are connected, the second electrodes 12 of the two thin film transistors are connected, and the first electrodes 13 of the two thin film transistors are connected.
  • Two thin film transistors are used to drive the same light-emitting unit.
  • the second portions 132 of the two thin film transistors corresponding to the groove are respectively arranged on two opposite sides of the groove, and two opposite groove walls in the groove are formed correspondingly.
  • the second electrode 12 corresponding to a thin film transistor, the first insulating pattern 14 and the second portion 132 of the first electrode 13 are formed on the side facing away from the base substrate 10 in order to form a laminated active layer 15, and the second insulating pattern 16 and the gate 17 so that the side wall of the groove formed by the second portion 132 of each first electrode 13 is extended in the direction perpendicular to the base substrate 10, so that the groove is in the direction perpendicular to the base substrate 10.
  • the above has a deeper depth.
  • the insulating film layer 18 can expose the first portion 131 of the first electrode 13 at the bottom of the groove, and at the same time cover the second portion 132 of the first electrode 13 and The sidewalls of the groove extend to the height of the active layer 15, the second insulating pattern 16 and the gate 17.
  • the groove defined by the thin film transistor manufactured by the above-mentioned manufacturing method only includes the oppositely arranged groove walls.
  • the ink droplet used to form the light-emitting layer in the light-emitting unit is dropped into the pixel area by the inkjet printing technology, the ink droplet It can also be confined in the groove without flowing into other areas.
  • the insulating film layer 18 provided in the above embodiments includes an inorganic layer
  • the light-emitting unit includes a first pixel electrode and a second pixel electrode disposed opposite to each other, and a second pixel electrode disposed between the first pixel electrode and the second pixel electrode.
  • the bottom of the groove is multiplexed as the first pixel electrode of the corresponding light-emitting unit; the steps of manufacturing the light-emitting unit specifically include:
  • a second pixel electrode is formed on the side of the organic light-emitting function layer facing away from the bottom of the groove.
  • the specific types of the above-mentioned insulating film layer 18 are various.
  • the insulating film layer 18 is an inorganic layer. Since the first portion 131 of the first electrode 13 of the thin film transistor corresponding to the light-emitting unit can be exposed through the opening on the insulating film layer 18, and the first portion 131 of the first electrode 13 can be in contact with the light-emitting unit, it is used as a light-emitting unit.
  • the first part 131 of the first electrode 13 can be directly multiplexed as the first pixel electrode in the light-emitting unit, so that when the light-emitting unit is made, inkjet printing technology can be used to form the light-emitting unit
  • the organic solution of the organic light-emitting function layer is dropped into the groove to form an organic light-emitting function layer on the first part 131 of the first electrode 13, and then fabricated on the side of the organic light-emitting function layer facing away from the first part 131 of the first electrode 13
  • the second pixel electrode of the light-emitting unit can complete the manufacture of the light-emitting unit.
  • the above-mentioned multiplexing the first part 131 of the first electrode 13 as the first pixel electrode of the light-emitting unit better simplifies the manufacturing process of the light-emitting unit and reduces the manufacturing cost of the display substrate.
  • the top-view structure of the red light-emitting unit R, the green light-emitting unit G, and the blue light-emitting unit B manufactured by the manufacturing method provided by the above-mentioned embodiment is shown in FIG. 7, because the groove wall of the groove is equivalent to that in the prior art In the bank of the pixel defining layer, the space in the groove of the groove is equivalent to the pixel opening area defined by the pixel defining layer in the prior art, so that when the organic light-emitting functional layer in the light-emitting unit is made, inkjet printing technology can be directly used in the concave An organic light-emitting functional layer is formed in the groove, and no additional pixel defining layer is required to define the pixel area for manufacturing the light-emitting unit.
  • the step of fabricating the second electrode 12 and the first electrode 13 in the thin film transistor specifically includes:
  • the second electrode 12 and the first electrode 13 are fabricated.
  • the height of the second electrode 12 is the same as the height of the second portion 132 of the first electrode 13.
  • a conductive film can be deposited on the base substrate 10 first, and then a photoresist can be formed on the conductive film, and the photoresist can be exposed using a halftone mask to form a completely reserved area of the photoresist and the photoresist
  • the semi-reserved area and the photoresist removal area wherein the photoresist completely reserved area corresponds to the area where the second electrode 12 and the second part 132 of the first electrode 13 are located, and the photoresist semi-reserved area corresponds to the first part of the first electrode 13 131 corresponds to the area, and the photoresist removal area corresponds to other areas except the area where the second electrode 12, the first part 131 and the second part 132 of the first electrode 13 are located; the developer is used to remove the photoresist The photoresist is completely removed, and the photoresist part located in the photoresist semi-reserved area is removed, and then the conductive film 11 located in the photoresist removal area is completely
  • the second electrode 12 and the first electrode 13 are fabricated through the above-mentioned one patterning process, which effectively simplifies the process flow and reduces the fabrication cost.
  • the height of the second electrode 12 is set to be the same as the height of the second portion 132 in the first electrode 13; and/or the height of the first insulating pattern 14 is set to be the same as that of the first
  • the height of the second part 132 in the electrode 13 is the same, so that the active layer 15 formed above the three will not have a step difference, that is, the surface of the active layer 15 for forming the second insulating pattern 16 is flatter, thereby making Neither the second insulating pattern 16 nor the gate 17 formed on the active layer 15 has a step difference, which is more conducive to the stability of the display substrate.

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Abstract

本公开提供一种显示基板及其制作方法、显示装置，涉及显示技术领域。所述显示基板包括衬底基板和薄膜晶体管阵列，薄膜晶体管阵列包括多个薄膜晶体管，每个薄膜晶体管中的第一电极均包括具有高度差的第一部分和第二部分，在垂直于衬底基板的方向上，第二部分的高度高于第一部分的高度。

Description

显示基板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2019年3月27日在中国提交的中国专利申请号No.201910237989.0的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法、显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(英文：Organic Light-Emitting Diode，以下简称OLED)显示装置以其自发光、广视角、高对比度等优点逐渐受到人们的广泛关注。这种OLED显示装置的结构主要包括：衬底基板，形成在衬底基板上的薄膜晶体管阵列，以及形成在薄膜晶体管阵列上的发光单元；由于发光单元与OLED显示装置包括的像素单元一一对应，且发光单元中包括的发光层一般通过喷墨打印技术实现，因此，为了使发光层能够准确的形成在对应的位置，现有技术一般会在薄膜晶体管阵列上制备一层像素界定层，通过该像素界定层限定出与像素单元一一对应的像素开口区，这样在制作发光单元时，就能够采用喷墨打印技术，将用于形成发光单元中发光层的墨滴稳定并精确的滴入像素开口区中。
但是上述像素界定层在制作时需要经过涂覆、曝光、显影和固化等工艺，制备工艺复杂，而且所采用的有机材料容易对环境造成污染。
发明内容
本公开提供如下技术方案：
本公开的第一方面提供一种显示基板，包括：
衬底基板，
设置在所述衬底基板上的薄膜晶体管阵列，所述薄膜晶体管阵列包括多 个薄膜晶体管，每个所述薄膜晶体管包括第一电极和第二电极，其中第一电极包括具有高度差的第一部分和第二部分，其中在垂直于所述衬底基板的方向上所述第二部分的高度大于所述第一部分的高度。
可选的，每个所述薄膜晶体管还包括设置在所述第一电极的第二部分与所述第二电极之间的第一绝缘图形，所述第一绝缘图形在所述衬底基板上的正投影位于所述第二电极在所述衬底基板上的正投影与所述第一电极的第二部分在所述衬底基板上的正投影之间。
可选的，薄膜晶体管阵列中形成有多个用于设置发光单元的凹槽，其中每个薄膜晶体管的第一电极的第一部分位于凹槽的槽底，所述凹槽的槽壁包括所述薄膜晶体管的第一电极的第二部分。
可选的，凹槽的槽壁还包括与所述薄膜晶体管相邻的薄膜晶体管的第一电极的第二部分。
可选的，所述薄膜晶体管阵列在背向所述衬底基板的一侧限定出用于设置发光单元的多个凹槽，其中每个薄膜晶体管的第一电极的第一部分构成凹槽的槽底，所述凹槽的槽壁由所述薄膜晶体管的第一电极的第二部分构成。
可选的，所述薄膜晶体管阵列在背向所述衬底基板的一侧限定出用于设置发光单元的多个凹槽，其中每个薄膜晶体管的第一电极的第一部分构成凹槽的槽底，所述凹槽的槽壁包括与所述薄膜晶体管相邻的薄膜晶体管的第一电极的第二部分。
可选的，所述显示基板还包括：
设置在所述薄膜晶体管阵列背向所述衬底基板的一侧的绝缘膜层，所述绝缘膜层包括与所述多个凹槽一一对应的多个开口，每个开口暴露出对应凹槽的槽底；
一一对应设置在所述凹槽内的多个发光单元，每个发光单元与对应的所述凹槽的槽底接触。
可选的，所述凹槽与一个薄膜晶体管对应，该薄膜晶体管还包括：
设置在所述第二电极背向所述衬底基板的一侧的有源层，所述有源层分别与所述第二电极，所述第一绝缘图形和所述第一电极的第二部分接触，所 述有源层在所述衬底基板上的正投影，包围所述第一电极的第一部分在所述衬底基板上的正投影；
设置在所述有源层背向所述衬底基板的一侧的第二绝缘图形，所述第二绝缘图形在所述衬底基板上的正投影包围所述第一电极的第一部分在所述衬底基板上的正投影；
设置在所述第二绝缘图形背向所述衬底基板的一侧的栅极，所述栅极在所述衬底基板上的正投影位于所述第二绝缘图形在所述衬底基板上的正投影的内部，所述栅极在所述衬底基板上的正投影包围所述第一电极的第一部分在所述衬底基板上的正投影。
可选的，显示基板还包括：设置在所述薄膜晶体管阵列背向所述衬底基板的一侧的绝缘膜层，所述绝缘膜层覆盖所述第一电极的第二部分、所述有源层、所述第二绝缘图形和所述栅极，并且所述绝缘膜层包括与所述多个凹槽一一对应的多个开口，每个开口暴露出对应凹槽的槽底。
可选的，其中每个凹槽与两个薄膜晶体管对应，其中每个薄膜晶体管还包括：
设置在所述第二电极背向所述衬底基板的一侧的有源层，所述有源层分别与所述第二电极，所述第一绝缘图形和所述第一电极中的第二部分接触；
设置在所述有源层背向所述衬底基板的一侧的第二绝缘图形；
设置在所述第二绝缘图形背向所述衬底基板的一侧的栅极，所述栅极在所述衬底基板上的正投影位于所述第二绝缘图形在所述衬底基板上的正投影的内部。
可选的，
所述两个薄膜晶体管的栅极连接，所述两个薄膜晶体管的第二电极连接，所述两个薄膜晶体管的第一电极连接。
可选的，在垂直于所述衬底基板的方向上，所述第二电极的高度与所述第一电极中的第二部分的高度相同；和/或，
在垂直于所述衬底基板的方向上，所述第一绝缘图形的高度与所述第一电极中的第二部分的高度相同。
可选的，所述第一电极和所述第二电极分别为源极和漏极之一。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示基板。
基于上述显示基板的技术方案，本公开的第三方面提供一种显示基板的制作方法，包括：
提供一衬底基板；
在所述衬底基板上制作薄膜晶体管阵列，所述薄膜晶体管阵列包括多个薄膜晶体管，每个所述薄膜晶体管包括第一电极和第二电极，其中第一电极包括具有高度差的第一部分和第二部分，其中在垂直于所述衬底基板的方向上所述第二部分的高度大于所述第一部分的高度。
可选的，所述制作方法还包括：
在所述薄膜晶体管阵列背向所述衬底基板的一侧制作绝缘膜层，所述绝缘膜层包括与所述多个凹槽一一对应的多个开口，每个开口暴露出对应凹槽的槽底；
在所述多个凹槽内制作多个发光单元，所述发光单元与所述凹槽一一对应，每个发光单元与对应的所述凹槽的槽底接触。
可选的，所述绝缘膜层包括无机层，所述发光单元包括相对设置的第一像素电极和第二像素电极，以及设置在所述第一像素电极和所述第二像素电极之间的有机发光功能层，所述凹槽的槽底复用为对应的所述发光单元的第一像素电极；
制作所述发光单元的步骤具体包括：
采用喷墨打印技术，将有机溶液打印在所述凹槽中，以形成所述有机发光功能层；
在所述有机发光功能层背向所述凹槽的槽底的一侧形成所述第二像素电极。
可选的，制作所述薄膜晶体管中的第二电极和第一电极的步骤具体包括：
通过一次构图工艺，制作所述第二电极和所述第一电极，在垂直于所述衬底基板的方向上，所述第二电极的高度与所述第一电极中的第二部分的高度相同。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1a-图1g为本公开实施例提供的第一种方式和第三种方式下凹槽的截面示意图；
图2a-图2g为本公开实施例提供的第二种方式下凹槽的截面示意图；
图3为本公开实施例提供的一种薄膜晶体管的俯视图；
图4为本公开实施例提供的另一种薄膜晶体管的俯视图；
图5为本公开实施例提供的与一个凹槽对应的两个薄膜晶体管的俯视图；
图6为本公开实施例提供的形成绝缘膜层后凹槽的俯视图；
图7为本公开实施例提供的RGB像素单元的俯视图。
附图标记：
10-衬底基板，                11-导电薄膜，
12-第二电极，                13-第一电极，
131-第一部分，               132-第二部分，
14-第一绝缘图形，            15-有源层，
16-第二绝缘图形，            17-栅极，
18-绝缘膜层。
具体实施方式
为了进一步说明本公开实施例提供的显示基板及其制作方法、显示装置，下面结合说明书附图进行详细描述。
请参阅图1g，本公开实施例提供了一种显示基板，包括衬底基板10和设置在衬底基板10上的薄膜晶体管阵列，所述薄膜晶体管阵列包括多个薄膜晶体管，每个薄膜晶体管中的第一电极13均包括具有高度差的第一部分131和第二部分132，在垂直于衬底基板10的方向上，第二部分132的高度高于第一部分131的高度。
具体地，在衬底基板10上制作薄膜晶体管阵列时，可通过设置薄膜晶体 管阵列中包括的薄膜晶体管的第一电极13的位置、形状和尺寸，使得薄膜晶体管阵列能够在背向衬底基板10的一侧限定出多个凹槽。更详细地说，可将每个薄膜晶体管中的第一电极13均设置为包括相连接的第一部分131和第二部分132，并设置在垂直于衬底基板10的方向上，第二部分132的高度高于第一部分131的高度，这样就可通过将各薄膜晶体管中第一电极13的第二部分132作为凹槽的槽壁，各薄膜晶体管中第一电极13的第一部分131作为凹槽的槽底，在薄膜晶体管阵列背向衬底基板10的一侧限定出多个具有容纳作用的凹槽。
值得注意，由于薄膜晶体管阵列中多个薄膜晶体管呈阵列分布，因此通过设置薄膜晶体管中第一电极13的具体结构，可实现通过一个薄膜晶体管限定出一个凹槽，或通过相邻的多个薄膜晶体管共同限定出一个凹槽。
当通过一个薄膜晶体管限定出一个凹槽时，该薄膜晶体管中第一电极13的第一部分131作为所限定的凹槽的槽底，该薄膜晶体管中第一电极13的第二部分132作为所限定的凹槽的槽壁；
当通过多个薄膜晶体管限定出一个凹槽时，示例性的，一个薄膜晶体管中第一电极13的第一部分131作为所限定的凹槽的槽底，相邻薄膜晶体管中第一电极13的第二部分132全部作为所限定的凹槽的槽壁；或者，该多个薄膜晶体管中第一电极13的第一部分131均作为所限定的凹槽的槽底，该多个薄膜晶体管中第一电极13的第二部分132全部作为所限定的凹槽的槽壁。
需要说明，由薄膜晶体管阵列限定出的凹槽应具有一定的深度，该深度至少能够容纳发光单元，这样当在凹槽中形成发光单元时，凹槽的槽壁能够相当于现有技术中像素界定层的挡墙(bank)，凹槽的槽内空间相当于现有技术中像素界定层限定的像素开口区，在制作发光单元中的发光层时，就可以采用喷墨打印技术，将用于形成发光单元中发光层的墨滴稳定并精确的滴入凹槽中，形成对应的发光层。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，将薄膜晶体管阵列包括的各薄膜晶体管中的第一电极13设置为包括高度不同的第一部分131和第二部分132，使得通过各薄膜晶体管中第一电极13的第一部分131和第二部分132能够在薄膜晶体管阵列背向衬底基板10的一侧 限定出多个凹槽，该多个凹槽的槽壁相当于现有技术中像素界定层的bank，凹槽的槽内空间相当于现有技术中像素界定层限定的像素开口区，从而使得在制作发光单元中的发光层时，可直接采用喷墨打印技术在凹槽内形成发光层，而不需要额外制作像素界定层来限定用于制作发光单元的像素区域，因此，本公开实施例提供的显示基板在制作时，避免了采用涂覆、曝光、显影和固化等工艺制作像素界定层，简化了显示基板的制备工艺；同时，还避免了由于采用有机材料制作像素界定层导致的会对环境造成污染的问题。
在一些实施例中，上述实施例提供的显示基板还包括：
设置在薄膜晶体管阵列背向衬底基板10的一侧的绝缘膜层18，绝缘膜层18包括与多个凹槽一一对应的多个开口，开口暴露出对应的凹槽的槽底(如图1g中的第一部分131)；
一一对应设置在凹槽内的多个发光单元，发光单元与对应的凹槽的槽底接触，与该凹槽对应的薄膜晶体管用于将驱动信号经该槽底输出至对应的发光单元，以驱动发光单元发光。
具体地，在薄膜晶体管阵列背向衬底基板10的一侧设置的绝缘膜层18的具体类型多种多样，示例性的，可选为钝化层。在绝缘膜层18上设置的开口的大小可根据实际需要设置，示例性的，该开口仅暴露第一电极13的第一部分131，而不会暴露薄膜晶体管中包括的其它膜层。更详细地说，可设置绝缘膜层18完全覆盖凹槽的内侧壁，这样就使得形成在凹槽中的发光单元仅能够与作为槽底的第一电极13的第一部分131接触，而不会与薄膜晶体管中的其它膜层接触，避免了发光单元与薄膜晶体管中的其它膜层发生短路，从而很好的保证了显示基板稳定的工作性能。
另外，如图6所示，绝缘膜层18在衬底基板10上的正投影，能够包围第一电极13的第一部分131在衬底基板10上的正投影。
由于薄膜晶体管的结构一般包括栅极17、第二电极12、第一电极13、有源层15和绝缘层等，且其工作方式为在栅极17的控制下，将第二电极12接收到的驱动信号经第一电极13输出至发光单元，以驱动发光单元发光，因此，上述在薄膜晶体管阵列背向衬底基板10的一侧设置绝缘膜层18，通过在绝缘膜层18上形成能够一一对应暴露槽底的开口，使得形成在凹槽内的发 光单元仅能够与槽底(即对应的薄膜晶体管中第一电极13的第一部分131)接触，这样不仅保证了薄膜晶体管能够通过其包括的第一电极13的第一部分131将驱动信号传输至对应的发光单元，而且，避免了发光单元与薄膜晶体管中的其它膜层发生短路，保证了显示基板稳定的工作性能。
进一步地，上述实施例提供的发光单元可包括相对设置的两个电极和设置在两个电极之间的发光层；凹槽的槽底与对应的发光单元中的发光层接触，该凹槽的槽底复用为对应的发光单元中的其中一个电极。
具体地，由于与发光单元对应的凹槽的槽底能够通过绝缘膜层18上的开口暴露出来，且该凹槽的槽底能够与对应的发光单元接触，用于为发光单元提供驱动信号，因此，可直接将凹槽的槽底复用为对应的发光单元中的其中一个电极，这样在制作发光单元时，可直接将发光层形成在对应的凹槽的槽底上，然后在发光层背向槽底的一侧制作发光单元的另一个电极，即可完成发光单元的制作，更好的简化了发光单元的制作工艺流程，降低了显示基板的制作成本。
上述通过各薄膜晶体管的第一电极13的第一部分131和第二部分132限定出凹槽的方式多种多样，下面给出几种具体的限定方式。
第一种方式，如图1g和图3所示，当凹槽与一个薄膜晶体管对应时(即每个凹槽均由一一对应的一个薄膜晶体管的第一电极13限定出时)，该薄膜晶体管具体包括：
设置在衬底基板10上的第一绝缘图形14、第二电极12和第一电极13，第二电极12在衬底基板10上的正投影包围第一绝缘图形14在衬底基板10上的正投影，第一绝缘图形14在衬底基板10上的正投影包围第一电极13在衬底基板10上的正投影，第一电极13中的第二部分132在衬底基板10上的正投影包围第一电极13中的第一部分131在衬底基板10上的正投影；
设置在第二电极12背向衬底基板10的一侧的有源层15，有源层15分别与第二电极12，第一绝缘图形14和第一电极13的第二部分132接触，有源层15在衬底基板10上的正投影，包围第一电极13中的第一部分131在衬底基板10上的正投影；
设置在有源层15背向衬底基板10的一侧的第二绝缘图形16，第二绝缘 图形16在衬底基板10上的正投影，包围第一电极13中的第一部分131在衬底基板10上的正投影；
设置在第二绝缘图形16背向衬底基板10的一侧的栅极17，栅极17在衬底基板10上的正投影位于第二绝缘图形16在衬底基板10上的正投影的内部，栅极17在衬底基板10上的正投影，包围第一电极13中的第一部分131在衬底基板10上的正投影。
具体地，上述结构的薄膜晶体管中，通过在衬底基板10上制作具有不同高度的第一部分131和第二部分132的第一电极13，并设置第一电极13中的第二部分132在衬底基板10上的正投影包围第一电极13中的第一部分131在衬底基板10上的正投影，使得第一电极13能够形成为凹槽结构，然后通过在第二电极12，第一绝缘图形14和第一电极13的第二部分132三者背向衬底基板10的一侧依次制作层叠设置的有源层15，第二绝缘图形16和栅极17，并设置有源层15、第二绝缘图形16和栅极17均是环绕第一电极13的第一部分131形成，使得由第一电极13的第二部分132构成的凹槽侧壁在垂直于衬底基板10的方向上高度得到延伸，使凹槽在垂直于衬底基板10的方向上具有更深的深度。在这种结构的薄膜晶体管上形成绝缘膜层18时，绝缘膜层18能够将位于槽底的第一电极13的第一部分131暴露，并同时覆盖第一电极13的第二部分132，以及位于凹槽侧壁延伸高度上的有源层15，第二绝缘图形16和栅极17。
上述结构的薄膜晶体管能够限定出四周封闭的凹槽，这样当采用喷墨打印技术，将用于形成发光单元中发光层的墨滴滴入凹槽中时，墨滴能够被限定在凹槽内，而不会流到其它非像素区域中，从而很好的避免了墨滴在其它区域铺展污染相邻的像素，造成串色现象。
第二种方式，如图2g和图4所示所示，当凹槽与两个薄膜晶体管对应，两个薄膜晶体管的第二部分132分别设置在凹槽相对的两侧，薄膜晶体管具体包括：
设置在衬底基板10上的第一绝缘图形14、第二电极12和第一电极13，第一绝缘图形14设置在第二电极12和第一电极13之间；
设置在第二电极12背向衬底基板10的一侧的有源层15，有源层15分 别与第二电极12，第一绝缘图形14和第一电极13中的第二部分132接触；
设置在有源层15背向衬底基板10的一侧的第二绝缘图形16；
设置在第二绝缘图形16背向衬底基板10的一侧的栅极17，栅极17在衬底基板10上的正投影位于第二绝缘图形16在衬底基板10上的正投影的内部。
具体地，上述凹槽与两个薄膜晶体管对应，即每个凹槽由两个薄膜晶体管中包括的第一电极13共同限定出来，且这两个薄膜晶体管中的一个薄膜晶体管的第一部分131作为由该薄膜晶体管限定的凹槽的槽底。
对于第二种方式，凹槽对应的两个薄膜晶体管的第二部分132分别设置在凹槽相对的两侧，分别对应形成凹槽中相对的两个槽壁，一个薄膜晶体管中第一电极13的第一部分131位于该两个槽壁之间，该薄膜晶体管中第一电极13的第一部分131仅与该薄膜晶体管中第一电极13的第二部分132电连接，而与两个薄膜晶体管中另一个薄膜晶体管的第一电极13的第二部分132绝缘。另外，两个薄膜晶体管为两个相互独立的薄膜晶体管，分别对应控制不同的发光单元。
具体地，上述结构的薄膜晶体管中，凹槽对应的两个薄膜晶体管的第二部分132分别设置在凹槽相对的两侧，分别对应形成凹槽中相对的两个槽壁，然后通过在每一个薄膜晶体管对应的第二电极12，第一绝缘图形14和第一电极13的第二部分132三者背向衬底基板10的一侧依次制作层叠设置的有源层15，第二绝缘图形16和栅极17，使得由各第一电极13的第二部分132构成的凹槽侧壁在垂直于衬底基板10的方向上高度得到延伸，使凹槽在垂直于衬底基板10的方向上具有更深的深度。在这种结构的薄膜晶体管上形成绝缘膜层18时，绝缘膜层18能够将位于槽底的第一电极13的第一部分131暴露，并同时覆盖第一电极13的第二部分132，以及位于凹槽侧壁延伸高度上的有源层15，第二绝缘图形16和栅极17。
上述结构的薄膜晶体管限定出的凹槽的结构与第一种方式不同，这种通过两个薄膜晶体管限定出的凹槽仅包括相对设置的槽壁，但是在采用喷墨打印技术，将用于形成发光单元中发光层的墨滴滴入凹槽中时，墨滴同样能够被限定在凹槽内，而不会流到其它区域。
第三种方式，如图1g和图5所示，当凹槽与两个薄膜晶体管对应时，两个薄膜晶体管的第二部分132分别设置在凹槽相对的两侧，薄膜晶体管具体包括：
设置在衬底基板10上的第一绝缘图形14、第二电极12和第一电极13，第一绝缘图形14设置在第二电极12和第一电极13之间；
设置在第二电极12背向衬底基板10的一侧的有源层15，有源层15分别与第二电极12，第一绝缘图形14和第一电极13中的第二部分132接触；
设置在有源层15背向衬底基板10的一侧的第二绝缘图形16；
设置在第二绝缘图形16背向衬底基板10的一侧的栅极17，栅极17在衬底基板10上的正投影位于第二绝缘图形16在衬底基板10上的正投影的内部；
两个薄膜晶体管的栅极17连接，两个薄膜晶体管的第二电极12连接，两个薄膜晶体管的第一电极13连接。
可选地，上述凹槽与两个薄膜晶体管对应，凹槽由两个薄膜晶体管中包括的第一电极13共同限定出来，且这两个薄膜晶体管中第一电极13的第一部分131均作为由这两个薄膜晶体管限定的凹槽的槽底。
对于第三种方式，凹槽对应的两个薄膜晶体管的第二部分132分别设置在凹槽相对的两侧，分别对应形成凹槽中相对的两个槽壁，两个薄膜晶体管中的第一电极13的第一部分131均位于该两个槽壁之间，且两个薄膜晶体管的栅极17连接，两个薄膜晶体管的第二电极12连接，两个薄膜晶体管的第一电极13连接(也可以共用同一个第一电极13)，该两个薄膜晶体管用于驱动相同的发光单元。
更详细地说，上述结构的薄膜晶体管中，凹槽对应的两个薄膜晶体管的第二部分132分别设置在凹槽相对的两侧，分别对应形成凹槽中相对的两个槽壁，然后通过在每一个薄膜晶体管对应的第二电极12，第一绝缘图形14和第一电极13的第二部分132三者背向衬底基板10的一侧依次制作层叠设置的有源层15，第二绝缘图形16和栅极17，使得由各第一电极13的第二部分132构成的凹槽侧壁在垂直于衬底基板10的方向上高度得到延伸，使凹槽在垂直于衬底基板10的方向上具有更深的深度。在这种结构的薄膜晶体管上 形成绝缘膜层18时，绝缘膜层18能够将位于槽底的第一电极13的第一部分131暴露，并同时覆盖第一电极13的第二部分132，以及位于凹槽侧壁延伸高度上的有源层15，第二绝缘图形16和栅极17。
上述结构的薄膜晶体管限定出的凹槽仅包括相对设置的槽壁，但是在采用喷墨打印技术，将用于形成发光单元中发光层的墨滴滴入像素区域中时，墨滴同样能够被限定在凹槽内，而不会流到其它非像素区域中。
需要说明，上述三种方式中，各薄膜晶体管中的第二电极12可包括漏电极，第一电极13可包括源电极；或者，第二电极12可包括源电极，第一电极13可包括漏电极。
另外，在实际应用中，可根据实际需要选择上述三种方式，更详细地说，上述三种方式中，第一种方式和第二种方式均为通过一个薄膜晶体管驱动对应的一个发光单元，第三种方式为通过两个薄膜晶体管驱动对应的一个发光单元。当需要发光单元的发光亮度较小时，可选择第一种方式和第二种方式，当需要较强的驱动能力，使得发光单元的发光亮度较大时，可选择第三种方式。
在一些实施例中，可设置在垂直于衬底基板10的方向上，第二电极12的高度与第一电极13中的第二部分132的高度相同；和/或，在垂直于衬底基板10的方向上，第一绝缘图形14的高度与第一电极13中的第二部分132的高度相同。换言之，根据本公开的一些实施例，第二电极12、第一电极13的第二部分132和/或第一绝缘图形14的远离衬底基板10的表面可以具有相同的高度，也即至少二者远离衬底基板10的表面可以形成为平坦表面。
具体地，在垂直于衬底基板10的方向上，设置第二电极12的高度与第一电极13中的第二部分132的高度相同；和/或，设置第一绝缘图形14的高度与第一电极13中的第二部分132的高度相同，能够使形成在三者上方的有源层15不会产生段差，即使得有源层15用于形成第二绝缘图形16的表面更加平坦，从而使形成在有源层15上方的第二绝缘图形16以及栅极17均不会存在段差，更有利于显示基板的稳定性。
另外，设置第二电极12和第一电极13的第二部分132在垂直于衬底基板10的方向上具有较厚的厚度，使得第二电极12和第一电极13的电阻更小， 更适合大尺寸显示基板的需要。
在一些实施例中，可设置上述绝缘膜层18位于凹槽外的部分在背向衬底基板10的表面具有疏水性。
具体地，在制作完绝缘膜层18后，可利用紫外线对绝缘膜层18位于凹槽外的部分进行曝光，使绝缘膜层18位于凹槽外的部分在背向衬底基板10的表面具有疏水性。
由于发光单元中的发光层一般采用喷墨打印技术制作，因此，设置绝缘膜层18位于凹槽外的部分在背向衬底基板10的表面具有疏水性，能够使得在采用喷墨打印技术形成发光层时，用于形成发光层的液滴能够更稳定、更精确的被打印到凹槽内。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
由于上述实施例提供的显示基板，不仅避免了采用涂覆、曝光、显影和固化等工艺制作像素界定层，简化了显示基板的制备工艺，而且还避免了由于采用有机材料制作像素界定层导致的会对环境造成污染的问题；因此，本公开实施例提供的显示装置在包括上述实施例提供的显示基板时，同样具有制作工艺简单、节约制作成本，以及不会对环境产生污染等优点。
需要说明的是，所述显示装置可以为：电视、显示器、手机、平板电脑等任何具有显示功能的产品或部件。
本公开实施例还提供了一种显示基板的制作方法，用于制作上述实施例提供的显示基板，所述制作方法包括：
提供一衬底基板10；
在衬底基板10上制作薄膜晶体管阵列，薄膜晶体管阵列包括多个薄膜晶体管，每个薄膜晶体管中的第一电极13均包括具有高度差的第一部分131和第二部分132，在垂直于衬底基板10的方向上，第二部分132的高度高于第一部分131的高度。
具体地，先提供一衬底基板10，该衬底基板10可选用玻璃基板，然后可采用现有技术中制作薄膜晶体管的制作工艺在衬底基板10上制作薄膜晶体管阵列，通过设置薄膜晶体管阵列中包括的薄膜晶体管的第一电极13的位置、形状和尺寸，使得薄膜晶体管阵列能够在背向衬底基板10的一侧限定出 多个凹槽。更详细地说，可将每个薄膜晶体管中的第一电极13均形成为包括相连接的第一部分131和第二部分132，并在垂直于衬底基板10的方向上，设置第二部分132的高度高于第一部分131的高度，这样就可通过将各薄膜晶体管中第一电极13的第二部分132作为凹槽的槽壁，各薄膜晶体管中第一电极13的第一部分131作为凹槽的槽底，在薄膜晶体管阵列背向衬底基板10的一侧限定出多个具有容纳作用的凹槽。
本公开实施例提供的显示基板的制作方法中，将薄膜晶体管阵列包括的各薄膜晶体管中的第一电极13形成为包括高度不同的第一部分131和第二部分132，使得通过各薄膜晶体管中第一电极13的第一部分131和第二部分132能够在薄膜晶体管阵列背向衬底基板10的一侧限定出多个凹槽，该多个凹槽的槽壁相当于现有技术中像素界定层的bank，凹槽的槽内空间相当于现有技术中像素界定层限定的像素开口区，从而使得在制作发光单元中的发光层时，可直接采用喷墨打印技术在凹槽内形成发光层，而不需要额外制作像素界定层来限定用于制作发光单元的像素区域，因此，本公开实施例提供的制作方法制作显示基板时，避免了采用涂覆、曝光、显影和固化等工艺制作像素界定层，简化了显示基板的制备工艺；同时，还避免了由于采用有机材料制作像素界定层导致的会对环境造成污染的问题。
在一些实施例中，上述制作方法还包括：
在薄膜晶体管阵列背向衬底基板10的一侧制作绝缘膜层18，绝缘膜层18包括与多个凹槽一一对应的多个开口，开口暴露出对应的凹槽的槽底；
在多个凹槽内制作多个发光单元，发光单元与凹槽一一对应，发光单元与对应的凹槽的槽底接触，与该凹槽对应的薄膜晶体管用于将驱动信号经该槽底输出至对应的发光单元，以驱动发光单元发光。
具体地，在制作完薄膜晶体管阵列后，可在薄膜晶体管阵列背向衬底基板10的一侧沉积形成绝缘膜层18，并通过构图工艺在绝缘膜层18上形成与凹槽一一对应的多个开口，各开口均暴露出对应的凹槽的槽底，然后在各凹槽内形成对应的发光单元，并使发光单元与对应的凹槽的槽底接触。
需要说明，上述绝缘膜层18的材料可选为氧化硅、氮化硅或氧化铝等，该绝缘膜层18可作为钝化层。
另外，在绝缘膜层18上形成的开口的大小可根据实际需要设置，示例性的，该开口仅暴露第一电极13的第一部分131，而不会暴露薄膜晶体管中包括的其它膜层。更详细地说，可使绝缘膜层18完全覆盖凹槽的内侧壁，这样就使得形成在凹槽中的发光单元仅能够与作为槽底的第一电极13的第一部分131接触，而不会与薄膜晶体管中的其它膜层接触，这样不仅保证了薄膜晶体管能够通过其包括的第一电极13的第一部分131将驱动信号传输至对应的发光单元，而且，避免了发光单元与薄膜晶体管中的其它膜层发生短路，从而很好的保证了显示基板稳定的工作性能。
在一些实施例中，上述发光单元可以包括相对设置的两个电极和设置在两个电极之间的发光层；上述在凹槽内制作发光单元的步骤具体包括：
在凹槽内制作发光层，发光层与对应的凹槽的槽底接触，该凹槽的槽底复用为对应的发光单元中的其中一个电极，在发光层背向衬底基板10的一侧制作发光单元中的另一个电极。
具体地，由于与发光单元对应的凹槽的槽底能够通过绝缘膜层18上的开口暴露出来，且该凹槽的槽底能够与对应的发光单元接触，用于为发光单元提供驱动信号，因此，可直接将凹槽的槽底复用为对应的发光单元中的其中一个电极，这样在制作发光单元时，可以采用喷墨打印技术，将用于形成发光单元中发光层的墨滴滴入凹槽中暴露的槽底上，在槽底上形成发光层，然后在发光层背向槽底的一侧制作发光单元的另一个电极，即可完成发光单元的制作。
上述将槽底复用为发光单元中的一个电极，更好的简化了发光单元的制作工艺流程，降低了显示基板的制作成本。
通过各薄膜晶体管的第一电极13的第一部分131和第二部分132限定出凹槽的方式多种多样，下面给出几种具体的限定方式下薄膜晶体管的制作过程。
第一种方式，当凹槽与一个薄膜晶体管对应时，如图1a-1g所示，制作薄膜晶体管的步骤具体包括：
在衬底基板10上制作第一绝缘图形14、第二电极12和第一电极13，第二电极12在衬底基板10上的正投影包围第一绝缘图形14在衬底基板10上 的正投影，第一绝缘图形14在衬底基板10上的正投影包围第一电极13在衬底基板10上的正投影，第一电极13中的第二部分132在衬底基板10上的正投影包围第一电极13中的第一部分131在衬底基板10上的正投影；
在第二电极12背向衬底基板10的一侧制作有源层15，有源层15分别与第二电极12，第一绝缘图形14和第一电极13的第二部分132接触，有源层15在衬底基板10上的正投影，包围第一电极13中的第一部分131在衬底基板10上的正投影；
在有源层15背向衬底基板10的一侧制作第二绝缘图形16，第二绝缘图形16在衬底基板10上的正投影，包围第一电极13中的第一部分131在衬底基板10上的正投影；
在第二绝缘图形16背向衬底基板10的一侧制作栅极17，栅极17在衬底基板10上的正投影位于第二绝缘图形16在衬底基板10上的正投影的内部，栅极17在衬底基板10上的正投影，包围第一电极13中的第一部分131在衬底基板10上的正投影。
具体地，如图1a所示，先采用磁控溅射设备在衬底基板10上沉积一层导电薄膜11，并对该导电薄膜11进行图形化，如图1b所示，形成第二电极12和第一电极13，该导电薄膜11的材料可选用Cu、Al或氧化铟锡(ITO)等；再采用等离子体增强化学气相沉积法形成第一绝缘薄膜，并对该第一绝缘薄膜进行图形化，如图1c所示，形成第一绝缘图形14，该第一绝缘薄膜的材料可选用氧化硅、氮化硅等，或者也可以采用有机物制作该第一绝缘图形14。
更详细地说，当制作的第一电极13包括第一部分131和第二部分132，且在垂直于衬底基板10的方向上，第二部分132的高度高于第一部分131的高度，第二部分132的高度与第二电极12的高度相同时，可利用半色调掩膜板，实现通过一次构图工艺同时形成第二电极12、第一电极13的第一部分131和第二部分132。
如图1d所示，继续采用磁控溅射设备或者溶液法，并结合图形化工艺，在第二电极12背向衬底基板10的一侧制作能够分别与第二电极12，第一绝缘图形14和第一电极13的第二部分132接触的有源层15，该有源层15在 衬底基板10上的正投影，包围第一电极13中的第一部分131在衬底基板10上的正投影。
如图1e所示，继续采用等离子体增强化学气相沉积法，在有源层15背向衬底基板10的一侧形成第二绝缘薄膜，并对该第二绝缘薄膜进行图形化，形成第二绝缘图形16，该第二绝缘薄膜的材料可选用氧化硅、氮化硅等，且该第二绝缘图形16作为薄膜晶体管中的栅极绝缘层，第二绝缘图形16在衬底基板10上的正投影包围第一电极13中第一部分131在衬底基板10上的正投影。
如图1f所示，最后采用磁控溅射设备在第二绝缘图形16背向衬底基板10的一侧沉积一层导电薄膜，并对该导电薄膜进行图形化，形成栅极17，该栅极17在衬底基板10上的正投影位于第二绝缘图形16在衬底基板10上的正投影的内部，栅极17在衬底基板10上的正投影包围第一电极13的第一部分131在衬底基板10上的正投影；上述导电薄膜的材料可选用Cu、Al或氧化铟锡(ITO)等。
采用上述制作方法制作的薄膜晶体管中，通过在衬底基板10上制作具有不同高度的第一部分131和第二部分132的第一电极13，并设置第一电极13中的第二部分132在衬底基板10上的正投影包围第一电极13中的第一部分131在衬底基板10上的正投影，使得第一电极13能够形成为凹槽结构，然后通过在第二电极12，第一绝缘图形14和第一电极13的第二部分132三者背向衬底基板10的一侧依次制作层叠设置的有源层15，第二绝缘图形16和栅极17，并设置有源层15、第二绝缘图形16和栅极17均是环绕第一电极13的第一部分131形成，使得由第一电极13的第二部分132构成的凹槽侧壁在垂直于衬底基板10的方向上高度得到延伸，使凹槽在垂直于衬底基板10的方向上具有更深的深度。在这种结构的薄膜晶体管上形成绝缘膜层18时，绝缘膜层18能够将位于槽底的第一电极13的第一部分131暴露，并同时覆盖第一电极13的第二部分132，以及位于凹槽侧壁延伸高度上的有源层15，第二绝缘图形16和栅极17。
采用上述制作方法制作的薄膜晶体管能够限定出封闭的凹槽，这样当采用喷墨打印技术，将用于形成发光单元中发光层的墨滴滴入凹槽中时，墨滴 能够被限定在凹槽内，而不会流到其它区域，从而很好的避免了墨滴在其它区域铺展污染相邻的像素，造成串色现象。
第二种方式，当凹槽与两个薄膜晶体管对应时，两个薄膜晶体管的第二部分132分别设置在凹槽相对的两侧，如图2a-2g所示，制作薄膜晶体管的步骤具体包括：
在衬底基板10上制作第一绝缘图形14、第二电极12和第一电极13，第一绝缘图形14设置在第二电极12和第一电极13之间；
在第二电极12背向衬底基板10的一侧制作有源层15，有源层15分别与第二电极12，第一绝缘图形14和第一电极13中的第二部分132接触；
在有源层15背向衬底基板10的一侧制作第二绝缘图形16；
在第二绝缘图形16背向衬底基板10的一侧制作栅极17，栅极17在衬底基板10上的正投影位于第二绝缘图形16在衬底基板10上的正投影的内部。
具体地，如图2a所示，先采用磁控溅射设备在衬底基板10上沉积一层导电薄膜11，并对该导电薄膜11进行图形化，如图2b所示，形成第二电极12和第一电极13，该导电薄膜11的材料可选用Cu、Al或氧化铟锡(ITO)等；再采用等离子体增强化学气相沉积法形成第一绝缘薄膜，并对该第一绝缘薄膜进行图形化，如图2c所示，形成第一绝缘图形14，该第一绝缘薄膜的材料可选用氧化硅、氮化硅等，或者也可以采用有机物制作该第一绝缘图形14。
更详细地说，当制作的第一电极13包括第一部分131和第二部分132，且在垂直于衬底基板10的方向上，第二部分132的高度高于第一部分131的高度，第二部分132的高度与第二电极12的高度相同时，可利用半色调掩膜板，实现通过一次构图工艺同时形成第二电极12、第一电极13的第一部分131和第二部分132。
如图2d所示，继续采用磁控溅射设备或者溶液法，并结合图形化工艺，在第二电极12背向衬底基板10的一侧制作能够分别与第二电极12，第一绝缘图形14和第一电极13的第二部分132接触的有源层15。
如图2e所示，继续采用等离子体增强化学气相沉积法，在有源层15背向衬底基板10的一侧形成第二绝缘薄膜，并对该第二绝缘薄膜进行图形化， 形成第二绝缘图形16，该第二绝缘薄膜的材料可选用氧化硅、氮化硅等，且该第二绝缘图形16作为薄膜晶体管中的栅极绝缘层。
如图2f所示，最后采用磁控溅射设备在第二绝缘图形16背向衬底基板10的一侧沉积一层导电薄膜，并对该导电薄膜进行图形化，形成栅极17，该栅极17在衬底基板10上的正投影位于第二绝缘图形16在衬底基板10上的正投影的内部，上述导电薄膜的材料可选用Cu、Al或氧化铟锡(ITO)等。
上述凹槽与两个薄膜晶体管对应，凹槽由两个薄膜晶体管中包括的第一电极13共同限定出来，其中一个薄膜晶体管中第一电极13的第一部分131作为凹槽的槽底。
对于第二种方式，凹槽对应的两个薄膜晶体管的第二部分132分别设置在凹槽相对的两侧，分别对应形成凹槽中相对的两个槽壁，其中一个薄膜晶体管中第一电极13的第一部分131位于该两个槽壁之间，该薄膜晶体管中第一电极13的第一部分131仅与该薄膜晶体管中第一电极13的第二部分132电连接，而与两个薄膜晶体管中另一个薄膜晶体管的第一电极13的第二部分132绝缘。另外，两个薄膜晶体管为两个相互独立的薄膜晶体管，分别对应控制不同的发光单元。
采用上述制作方法制作的薄膜晶体管中，凹槽对应的两个薄膜晶体管的第二部分132分别设置在凹槽相对的两侧，分别对应形成凹槽中相对的两个槽壁，然后通过在每一个薄膜晶体管对应的第二电极12，第一绝缘图形14和第一电极13的第二部分132三者背向衬底基板10的一侧依次制作层叠设置的有源层15，第二绝缘图形16和栅极17，使得由各第一电极13的第二部分132构成的凹槽侧壁在垂直于衬底基板10的方向上高度得到延伸，使凹槽在垂直于衬底基板10的方向上具有更深的深度。在这种结构的薄膜晶体管上形成绝缘膜层18时，绝缘膜层18能够将位于槽底的第一电极13的第一部分131暴露，并同时覆盖第一电极13的第二部分132，以及位于凹槽侧壁延伸高度上的有源层15，第二绝缘图形16和栅极17。
采用上述制作方法制作的薄膜晶体管限定出的凹槽的结构与第一种方式不同，这种通过两个薄膜晶体管限定出的凹槽仅包括相对设置的槽壁，但是在采用喷墨打印技术，将用于形成发光单元中发光层的墨滴滴入凹槽中时， 墨滴同样能够被限定在凹槽内，而不会流到其它区域。
第三种方式，当凹槽与两个薄膜晶体管对应时，两个薄膜晶体管的第二部分132分别设置在凹槽相对的两侧，制作薄膜晶体管的步骤具体包括：
在衬底基板10上制作第一绝缘图形14、第二电极12和第一电极13，第一绝缘图形14设置在第二电极12和第一电极13之间；
在第二电极12背向衬底基板10的一侧制作有源层15，有源层15分别与第二电极12，第一绝缘图形14和第一电极13中的第二部分132接触；
在有源层15背向衬底基板10的一侧制作第二绝缘图形16；
在第二绝缘图形16背向衬底基板10的一侧制作栅极17，栅极17在衬底基板10上的正投影位于第二绝缘图形16在衬底基板10上的正投影的内部；
两个薄膜晶体管的栅极17连接，两个薄膜晶体管的第二电极12连接，两个薄膜晶体管的第一电极13连接。
具体地，先采用磁控溅射设备在衬底基板10上沉积一层导电薄膜11，并对该导电薄膜11进行图形化，形成第二电极12和第一电极13，该导电薄膜11的材料可选用Cu、Al或氧化铟锡(ITO)等；再采用等离子体增强化学气相沉积法形成第一绝缘薄膜，并对该第一绝缘薄膜进行图形化，形成第一绝缘图形14，该第一绝缘薄膜的材料可选用氧化硅、氮化硅等，或者也可以采用有机物制作该第一绝缘图形14。
更详细地说，当制作的第一电极13包括第一部分131和第二部分132，且在垂直于衬底基板10的方向上，第二部分132的高度高于第一部分131的高度，第二部分132的高度与第二电极12的高度相同时，可利用半色调掩膜板，实现通过一次构图工艺同时形成第二电极12、第一电极13的第一部分131和第二部分132。
继续采用磁控溅射设备或者溶液法，并结合图形化工艺，在第二电极12背向衬底基板10的一侧制作能够分别与第二电极12，第一绝缘图形14和第一电极13的第二部分132接触的有源层15。
继续采用等离子体增强化学气相沉积法，在有源层15背向衬底基板10的一侧形成第二绝缘薄膜，并对该第二绝缘薄膜进行图形化，形成第二绝缘图形16，该第二绝缘薄膜的材料可选用氧化硅、氮化硅等，且该第二绝缘图 形16作为薄膜晶体管中的栅极绝缘层。
最后采用磁控溅射设备在第二绝缘图形16背向衬底基板10的一侧沉积一层导电薄膜11，并对该导电薄膜11进行图形化，形成栅极17，该栅极17在衬底基板10上的正投影位于第二绝缘图形16在衬底基板10上的正投影的内部，上述导电薄膜11的材料可选用Cu、Al或氧化铟锡(ITO)等。
上述凹槽与两个薄膜晶体管对应，凹槽由两个薄膜晶体管中包括的第一电极13共同限定出来，且这两个薄膜晶体管中第一电极13的第一部分131均作为由这两个薄膜晶体管限定的凹槽的槽底。
对于第三种方式，凹槽对应的两个薄膜晶体管的第二部分132分别设置在凹槽相对的两侧，分别对应形成凹槽中相对的两个槽壁，两个薄膜晶体管中的第一电极13的第一部分131均位于该两个槽壁之间，且两个薄膜晶体管的栅极17连接，两个薄膜晶体管的第二电极12连接，两个薄膜晶体管的第一电极13连接，该两个薄膜晶体管用于驱动相同的发光单元。
采用上述制作方法制作的薄膜晶体管中，凹槽对应的两个薄膜晶体管的第二部分132分别设置在凹槽相对的两侧，分别对应形成凹槽中相对的两个槽壁，然后通过在每一个薄膜晶体管对应的第二电极12，第一绝缘图形14和第一电极13的第二部分132三者背向衬底基板10的一侧依次制作层叠设置的有源层15，第二绝缘图形16和栅极17，使得由各第一电极13的第二部分132构成的凹槽侧壁在垂直于衬底基板10的方向上高度得到延伸，使凹槽在垂直于衬底基板10的方向上具有更深的深度。在这种结构的薄膜晶体管上形成绝缘膜层18时，绝缘膜层18能够将位于槽底的第一电极13的第一部分131暴露，并同时覆盖第一电极13的第二部分132，以及位于凹槽侧壁延伸高度上的有源层15，第二绝缘图形16和栅极17。
采用上述制作方法制作的薄膜晶体管限定出的凹槽仅包括相对设置的槽壁，但是在采用喷墨打印技术，将用于形成发光单元中发光层的墨滴滴入像素区域中时，墨滴同样能够被限定在凹槽内，而不会流到其它区域中。
在一些实施例中，上述实施例提供的绝缘膜层18包括无机层，发光单元包括相对设置的第一像素电极和第二像素电极，以及设置在第一像素电极和第二像素电极之间的有机发光功能层，凹槽的槽底复用为对应的发光单元的 第一像素电极；制作发光单元的步骤具体包括：
采用喷墨打印技术，将有机溶液打印在凹槽中，以形成有机发光功能层；
在有机发光功能层背向凹槽的槽底的一侧形成第二像素电极。
具体地，上述绝缘膜层18的具体类型多种多样，示例性的，绝缘膜层18选用无机层。由于与发光单元对应的薄膜晶体管的第一电极13的第一部分131能够通过绝缘膜层18上的开口暴露出来，且该第一电极13的第一部分131能够与发光单元接触，用于为发光单元提供驱动信号，因此，可直接将该第一电极13的第一部分131复用为发光单元中的第一像素电极，这样在制作发光单元时，可以采用喷墨打印技术，将用于形成发光单元中有机发光功能层的有机溶液滴入凹槽中，在第一电极13的第一部分131上形成有机发光功能层，然后在有机发光功能层背向第一电极13的第一部分131的一侧制作发光单元的第二像素电极，即可完成发光单元的制作。
上述将第一电极13的第一部分131复用为发光单元的第一像素电极，更好的简化了发光单元的制作工艺流程，降低了显示基板的制作成本。
更具体地，采用上述实施例提供的制作方法制作的红色发光单元R、绿色发光单元G和蓝色发光单元B的俯视结构如图7所示，由于凹槽的槽壁相当于现有技术中像素界定层的bank，凹槽的槽内空间相当于现有技术中像素界定层限定的像素开口区，从而使得在制作发光单元中的有机发光功能层时，可直接采用喷墨打印技术在凹槽内形成有机发光功能层，而不需要额外制作像素界定层来限定用于制作发光单元的像素区域。
在一些实施例中，上述制作薄膜晶体管中的第二电极12和第一电极13的步骤具体包括：
通过一次构图工艺，制作第二电极12和第一电极13，在垂直于衬底基板10的方向上，第二电极12的高度与第一电极13中的第二部分132的高度相同。
具体地，可先在衬底基板10上沉积形成导电薄膜，然后在导电薄膜上形成光刻胶，利用半色调掩膜板对光刻胶进行曝光，形成光刻胶完全保留区域、光刻胶半保留区域和光刻胶去除区域，其中光刻胶完全保留区域与第二电极12和第一电极13的第二部分132所在区域对应，光刻胶半保留区域与第一 电极13的第一部分131所在区域对应，光刻胶去除区域与除第二电极12、第一电极13的第一部分131和第二部分132所在区域之外的其它区域对应；利用显影液将位于光刻胶去除区域的光刻胶完全去除，并将位于光刻胶半保留区域的光刻胶部分去除，然后通过刻蚀工艺将位于光刻胶去除区域的导电薄膜11完全去除，接着对光刻胶进行灰化工艺，将位于光刻胶半保留区域的光刻胶全部去除，并将位于光刻胶完全保留区域的光刻胶部分去除，然后通过刻蚀工艺将位于光刻胶半保留区域的导电薄膜部分去除，形成第一电极13的第一部分131，最后将位于光刻胶完全保留区域的光刻胶剥离，形成第一电极13的第二部分132和第二电极12。
上述通过一次构图工艺，制作第二电极12和第一电极13，有效的简化了工艺流程，降低了制作成本。
另外，在垂直于衬底基板10的方向上，设置第二电极12的高度与第一电极13中的第二部分132的高度相同；和/或，设置第一绝缘图形14的高度与第一电极13中的第二部分132的高度相同，能够使形成在三者上方的有源层15不会产生段差，即使得有源层15用于形成第二绝缘图形16的表面更加平坦，从而使形成在有源层15上方的第二绝缘图形16以及栅极17均不会存在段差，更有利于显示基板的稳定性。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置 改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种显示基板，包括：
    衬底基板，
    设置在所述衬底基板上的薄膜晶体管阵列，所述薄膜晶体管阵列包括多个薄膜晶体管，每个所述薄膜晶体管包括第一电极和第二电极，其中第一电极包括具有高度差的第一部分和第二部分，其中在垂直于所述衬底基板的方向上所述第二部分的高度大于所述第一部分的高度。
  2. 根据权利要求1所述的显示基板，其中每个所述薄膜晶体管还包括设置在所述第一电极的第二部分与所述第二电极之间的第一绝缘图形，所述第一绝缘图形在所述衬底基板上的正投影位于所述第二电极在所述衬底基板上的正投影与所述第一电极的第二部分在所述衬底基板上的正投影之间。
  3. 根据权利要求2所述的显示基板，其中所述薄膜晶体管阵列中形成有多个用于设置发光单元的凹槽，其中每个薄膜晶体管的第一电极的第一部分位于凹槽的槽底，所述凹槽的槽壁包括所述薄膜晶体管的第一电极的第二部分。
  4. 根据权利要求3所述的显示基板，其中所述凹槽的槽壁还包括与所述薄膜晶体管相邻的薄膜晶体管的第一电极的第二部分。
  5. 根据权利要求1所述的显示基板，还包括：
    设置在所述薄膜晶体管阵列背向所述衬底基板的一侧的绝缘膜层，所述绝缘膜层包括与所述多个凹槽一一对应的多个开口，每个开口暴露出对应凹槽的槽底；
    一一对应设置在所述凹槽内的多个发光单元，每个发光单元与对应的所述凹槽的槽底接触。
  6. 根据权利要求3所述的显示基板，其中，所述薄膜晶体管还包括：
    设置在所述第二电极背向所述衬底基板的一侧的有源层，所述有源层分别与所述第二电极，所述第一绝缘图形和所述第一电极的第二部分接触，所述有源层在所述衬底基板上的正投影包围所述第一电极的第一部分在所述衬底基板上的正投影；
    设置在所述有源层背向所述衬底基板的一侧的第二绝缘图形，所述第二绝缘图形在所述衬底基板上的正投影包围所述第一电极的第一部分在所述衬底基板上的正投影；
    设置在所述第二绝缘图形背向所述衬底基板的一侧的栅极，所述栅极在所述衬底基板上的正投影位于所述第二绝缘图形在所述衬底基板上的正投影的内部，所述栅极在所述衬底基板上的正投影包围所述第一电极的第一部分在所述衬底基板上的正投影。
  7. 根据权利要求6所述的显示基板，还包括：
    设置在所述薄膜晶体管阵列背向所述衬底基板的一侧的绝缘膜层，所述绝缘膜层覆盖所述第一电极的第二部分、所述有源层、所述第二绝缘图形和所述栅极，并且所述绝缘膜层包括与所述多个凹槽一一对应的多个开口，每个开口暴露出对应凹槽的槽底。
  8. 根据权利要求4所述的显示基板，其中每个凹槽与两个薄膜晶体管对应，所述两个薄膜晶体管的第二部分分别设置在所述凹槽相对的两侧，其中每个薄膜晶体管还包括：
    设置在所述第二电极背向所述衬底基板的一侧的有源层，所述有源层分别与所述第二电极，所述第一绝缘图形和所述第一电极中的第二部分接触；
    设置在所述有源层背向所述衬底基板的一侧的第二绝缘图形；
    设置在所述第二绝缘图形背向所述衬底基板的一侧的栅极，所述栅极在所述衬底基板上的正投影位于所述第二绝缘图形在所述衬底基板上的正投影的内部。
  9. 根据权利要求8所述的显示基板，还包括：
    设置在所述薄膜晶体管阵列背向所述衬底基板的一侧的绝缘膜层，所述绝缘膜层覆盖所述第一电极的第二部分、所述有源层、所述第二绝缘图形和所述栅极，并且所述绝缘膜层包括与所述多个凹槽一一对应的多个开口，每个开口暴露出对应凹槽的槽底。
  10. 根据权利要求8或9所述的显示基板，
    其中，所述两个薄膜晶体管的栅极连接，所述两个薄膜晶体管的第二电极连接，所述两个薄膜晶体管的第一电极连接。
  11. 根据权利要求2～10中任一项所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述第二电极的高度与所述第一电极中的第二部分的高度相同；和/或，
    在垂直于所述衬底基板的方向上，所述第一绝缘图形的高度与所述第一电极中的第二部分的高度相同。
  12. 根据权利要求1所述的显示基板，其中所述薄膜晶体管的第一电极和所述第二电极分别为源极和漏极之一。
  13. 一种显示装置，包括如权利要求1～12中任一项所述的显示基板。
  14. 一种显示基板的制作方法，包括：
    提供一衬底基板；
    在所述衬底基板上制作薄膜晶体管阵列，所述薄膜晶体管阵列包括多个薄膜晶体管，每个所述薄膜晶体管包括第一电极和第二电极，其中第一电极包括具有高度差的第一部分和第二部分，其中在垂直于所述衬底基板的方向上所述第二部分的高度大于所述第一部分的高度。
  15. 根据权利要求14所述的显示基板的制作方法，还包括：
    在所述薄膜晶体管阵列背向所述衬底基板的一侧制作绝缘膜层，所述绝缘膜层包括与所述多个凹槽一一对应的多个开口，每个开口暴露出对应凹槽的槽底；
    在所述多个凹槽内制作多个发光单元，所述发光单元与所述凹槽一一对应，每个发光单元与对应的所述凹槽的槽底接触。
  16. 根据权利要求15所述的显示基板的制作方法，其中，所述绝缘膜层包括无机层，所述发光单元包括相对设置的第一像素电极和第二像素电极，以及设置在所述第一像素电极和所述第二像素电极之间的有机发光功能层，所述凹槽的槽底复用为对应的所述发光单元的第一像素电极；
    制作所述发光单元的步骤具体包括：
    采用喷墨打印技术，将有机溶液打印在所述凹槽中，以形成所述有机发光功能层；
    在所述有机发光功能层背向所述凹槽的槽底的一侧形成所述第二像素电极。
  17. 根据权利要求14～16中任一项所述的显示基板的制作方法，其中，制作所述薄膜晶体管中的第二电极和第一电极的步骤具体包括：
    通过一次构图工艺，制作所述第二电极和所述第一电极，在垂直于所述衬底基板的方向上，所述第二电极的高度与所述第一电极中的第二部分的高度相同。
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