WO2020192284A1 - 一种显示面板和显示装置 - Google Patents

一种显示面板和显示装置 Download PDF

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Publication number
WO2020192284A1
WO2020192284A1 PCT/CN2020/074865 CN2020074865W WO2020192284A1 WO 2020192284 A1 WO2020192284 A1 WO 2020192284A1 CN 2020074865 W CN2020074865 W CN 2020074865W WO 2020192284 A1 WO2020192284 A1 WO 2020192284A1
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Prior art keywords
area
fan
voltage power
data line
power line
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Application number
PCT/CN2020/074865
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English (en)
French (fr)
Inventor
韩龙
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/958,746 priority Critical patent/US11837687B2/en
Publication of WO2020192284A1 publication Critical patent/WO2020192284A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays

Definitions

  • the embodiments of the present application relate to but are not limited to a display panel and a display device.
  • the design of the full screen is to pursue a borderless design at each frame position and pursue a screen-to-body ratio close to 100%.
  • the full screen claimed by the industry only increases the screen-to-body ratio, and cannot truly achieve 100% screen-to-body ratio. Therefore, reducing the frame size of the display panel is still an important means to increase the screen-to-body ratio.
  • an embodiment of the present application provides a display panel, including:
  • a plurality of data lines are located in the display area and extend from the display area to the first fan-out area, the plurality of data lines are electrically connected to the plurality of sub-pixels, and are configured as the plurality of sub-pixels Provide data signals;
  • the first fan-out area includes: at least two data line fan-out partitions, and the plurality of data lines respectively extend into the at least two data line fan-out partitions.
  • the display panel further includes: a high-voltage power line and a low-voltage power line;
  • the high-voltage power line is located in the non-display area, and at least part of the high-voltage power line is located in the first fan-out area, and the high-voltage power line is configured to transmit high voltage to the plurality of sub-pixels Signal, the high-voltage power line includes at least two high-voltage power line pins;
  • the low-voltage power line located in the non-display area and surrounding the display area, is configured to transmit low-voltage signals to the plurality of sub-pixels, and the low-voltage power line includes at least two low-voltage power line pins ;
  • At least one of the at least two high-voltage power line pins and the at least two low-voltage power line pins is located between the at least two data line fan-out sections.
  • the number of the at least two data line fan-out partitions is two
  • the number of the at least two high voltage power line pins is two
  • the at least two low voltage power lines The number of pins is two
  • the two high-voltage power line pins and the two low-voltage power line pins are all located between the two data line fan-out sections.
  • the number of the at least two data line fan-out partitions is three, and the at least two high-voltage power line pins and the At least one of the at least two low-voltage power line pins.
  • the number of the at least two high-voltage power line pins is two
  • the number of the at least two low-voltage power line pins is two
  • the at least two data line fans The number of out partitions is three
  • the two high-voltage power line pins are respectively located between the three data line fan-out partitions
  • the two low-voltage power line pins are respectively located on the three data lines Fan out between partitions.
  • the number of the at least two high-voltage power line pins is two
  • the number of the at least two low-voltage power line pins is two
  • the at least two data line fans The number of out partitions is five
  • the two high-voltage power line pins and the two low-voltage power line pins are respectively located between the five data line fan-out partitions.
  • one of the two high-voltage power line pins and one of the two low-voltage power line pins is arranged between every two of the five data line fan-out partitions .
  • the two high-voltage power line pins are arranged symmetrically with respect to the center line of the display panel, and the two low-voltage power line pins are arranged symmetrically with respect to the center line of the display panel.
  • the number of data lines in the two outermost data line fan-out partitions of the at least two data line fan-out partitions is the same.
  • the display panel further includes a bending area located on a side of the first fan-out area away from the display area, and the plurality of data lines extend to the The bending area, the bending area is configured to be bent to the back of the display panel.
  • it further includes: a second fan-out area, the second fan-out area is located on a side of the bending area away from the display area, and the plurality of data lines extend to the first Two fan-out areas;
  • the second fan-out area includes a resistance compensation module, and the resistance compensation module is configured to perform resistance compensation on the plurality of data lines, so that the impedance of the data lines changes gradually.
  • an embodiment of the present application further provides a display device, including the display panel as described in any one of the above.
  • FIG. 1 is a schematic diagram of the structure of a display panel
  • FIG. 2 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of another display panel provided by an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of another display panel provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of still another display panel provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of still another display panel provided by an embodiment of the application.
  • FIG. 7 is a schematic structural diagram of still another display panel provided by an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of still another display panel provided by an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of still another display panel provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of still another display panel provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of still another display panel provided by an embodiment of the application.
  • FIG. 12 is a schematic structural diagram of still another display panel provided by an embodiment of the application.
  • FIG. 1 it is a schematic structural diagram of a display panel.
  • the display panel 20 includes a display area 21, a non-display area, a plurality of sub-pixels, a plurality of data lines, a high voltage power line Vdd and a low voltage power line Vss.
  • the power line Vdd includes a Vdd pin
  • the low-voltage power line Vss includes two Vss pins.
  • the data line provides data signals for the plurality of sub-pixels
  • the high-voltage power line transmits high-voltage signals to the plurality of sub-pixels
  • the low-voltage power line transmits low-voltage signals to the plurality of sub-pixels.
  • the data line 22a Data Line
  • the Data Line Fanout area 22 is located below the display area 21, that is, the lower frame of the display panel 20 1 shows the data line fan-out area 22 with a dark gray filled area.
  • the data line fan-out area 22 includes all the data lines drawn from the bottom of the display panel 20. Since the number of data lines is in the thousands, Not all the data lines 22a are shown in the data line fan-out area 22, only the data line in the data line fan-out area 22 is connected to the position of the bending area 23, and the data line 22a is shown, and the data line shown is The number of 22a does not represent the actual number of data lines. Therefore, the size and resolution of the display panel itself and the specifications of the integrated circuit (IC) affect the overall width of the data line fan-out area 22, that is, the size of the bottom frame in the display panel. In the above display panel, the size of the lower frame cannot be further reduced to increase the screen-to-body ratio.
  • IC integrated circuit
  • an embodiment of the present application provides a display panel 100, including: a display area 110 and a non-display area 120 located at least on one side of the display area, and the non-display area 120 includes a first fan-out area 122; multiple sub-pixels 126 located in the display area 110; multiple data lines 110a located in the display area 110 and extending from the display area 110 to the first fan-out area 122, the multiple data lines Is electrically connected to the plurality of sub-pixels 126 and is configured to provide data signals for the plurality of sub-pixels 126; the first fan-out area 122 includes: at least two data line fan-out partitions, and the plurality of data lines are respectively It is located in the at least two data line fan-out partitions (the data line fan-out partitions 122a and 122b in FIG. 2).
  • dark gray filled areas indicate the data line fan-out partitions (122a and 122b in FIG. 2).
  • the data line fan-out partitions include the data line fan-out partitions drawn from under the display area 110. For all data lines, since the number of data lines is in the thousands, not all the data lines 110a are shown in the data line fan-out partition.
  • the minimum line width and minimum spacing of the data lines are related to the process level and design rules, the number and resolution of the data lines in the display panel 100 are related, and the size of the display area 110 is determined by the product design specifications and will be fixed A number of data lines are connected to the first fan-out area 122.
  • the data lines in each data line fan-out partition can be reduced by at least half, or even more, for example, reducing To 1/3, 1/4, 1/5 or 1/7 etc.
  • the data lines in the lower frame are fanned out in segments to reduce the wiring occupation
  • the space can effectively reduce the width of the first fan-out area 122, that is, reduce the size of the lower frame in the display panel 100.
  • a signal line other than the data line between at least two data line fan-out partitions includes at least one of the following: a high-voltage power line Vdd (configured to The plurality of sub-pixels transmit high-voltage signals), a low-voltage power supply line Vss (configured to transmit low-voltage signals to the plurality of sub-pixels), a clock signal line (configured to transmit clock signals to the plurality of sub-pixels), and A touch signal line (configured to transmit touch signals for the plurality of sub-pixels).
  • the data lines are distributed, which can reduce the space occupied by the wiring and reduce the width of the first fan-out area 122.
  • the display panel 100 further includes: a high-voltage power line Vdd and a low-voltage power line Vss;
  • the high-voltage power line located in the non-display area 120, is configured to transmit high-voltage signals to the plurality of sub-pixels; the high-voltage power line includes two high-voltage power line pins;
  • the low-voltage power line located in the non-display area 120, is configured to provide and transmit voltage signals for the plurality of sub-pixels; the low-voltage power line includes two low-voltage power line pins;
  • the two high-voltage power line pins and the two low-voltage power line pins are all located between the two data line fan-out sections.
  • the fan-out structure of the data line is reasonably designed, that is, the data line is fan-out segmented, and one or more of the high-voltage power line and the low-voltage power line are used as at least
  • the interval between the two data line fan-out partitions effectively reduces the overall width of the data line fan-out area (that is, the first fan-out area 122), that is, reduces the size of the lower frame in the display panel 100, thereby improving the display The screen-to-body ratio of the panel 100.
  • part of the two high-voltage power supply line pins and the two low-voltage power supply line pins may be located between the two data line fan-out partitions, and partly located in the The two data lines fan out of the partition.
  • FIG. 4 is a schematic structural diagram of another display panel provided by an embodiment of the application.
  • the data line fan-out partition may include: the left area data line fan-out partition 122L arranged in sequence, and the center data line fan-out partition 122L Partition 122C, and the right area data line fan-out partition 122R.
  • the high-voltage power line pin may be located between the left area data line fan-out partition 122L and the central data line fan-out partition 122C, and the low voltage power line pin may be located at the right area data line fan-out partition 122R Between the fan-out partition 122C and the central data line. That is, the high-voltage power line pins and the low-voltage power line pins are used as the interval for segmented fan-out of the data line.
  • the ratio of the central area data lines a-2r to the total number of data lines a can be reasonably configured by the designer according to the size and shape of the display area 110 and the design specifications of the display panel 100.
  • the display panel 100 In order to achieve uniform light emission in the display area 110, the display panel 100 usually adopts a double-side drive mode, that is, both the left and right sides of the display area 110 can be configured with a high-voltage power line Vdd and a low-voltage power line Vss.
  • a double-side drive mode that is, both the left and right sides of the display area 110 can be configured with a high-voltage power line Vdd and a low-voltage power line Vss.
  • FIG. 5 it is a schematic structural diagram of still another display panel provided in an embodiment of this application.
  • FIG. 5 is shown based on the structure shown in FIG. 4 as an example.
  • the high-voltage power supply line includes two high-voltage power supply line pins Vdd1 and Vdd2, and the low-voltage power supply line includes two low-voltage power supply lines.
  • the high-voltage power line pin Vdd1 and the low-voltage power line pin Vss1 are located between the left area data line fan-out partition 122L and the center data line fan-out partition 122C, and the high-voltage power line pin Vdd2
  • the low voltage power line pin Vss2 is located between the right area data line fan-out partition 122R and the center data line fan-out partition 122C.
  • the two high-voltage power supply line pins Vdd1 and Vdd2 are symmetrically arranged with the center line of the display panel 100, and the two low-voltage power supply line pins Vss1 and Vss2 are arranged symmetrically with respect to the display panel 100.
  • the center line of 100 is set symmetrically.
  • the center line of the display panel 100 is the center line from the first side to the second side of the display panel 100 on the plane where the display panel is located, and the first side and the second side are not the first fan On the side where the exit area 122 is located, as shown in FIGS. 5 and 6, the dotted line 127 is the center line of the display panel 100.
  • FIG. 6 it is a schematic structural diagram of still another display panel provided by an embodiment of this application.
  • Fig. 6 is based on the structure shown in Fig. 5 as an example.
  • the first fan-out area 122 has five data line fan-out partitions, and the five data line fan-out partitions are sequentially: the first data line fan-out partition 1221, the second data line fan-out partition 1222, and the third data line fan-out partition.
  • the partition 1223 and the fourth data line fan out the partition 1224.
  • any two adjacent sections of the five data line fan-out sections can be provided with high-voltage power line pins or low-voltage power line pins, or only some adjacent sections can be provided with high-voltage power lines.
  • Pins or low-voltage power line pins that is, the two high-voltage power line pins Vdd1 and Vdd2 and the two low-voltage power line pins Vss1 and Vss2 may be partially located between the five data line fan-out sections , Partly located outside the five data line fan-out partitions.
  • the two high-voltage power line pins Vdd1 and Vdd2 and the two low-voltage power line pins Vss1 and Vss2 are respectively located between the five data line fan-out sections.
  • one of the two high-voltage power line pins and one of the two low-voltage power line pins is provided between each two of the five data line fan-out partitions .
  • the low-voltage power line pin Vss1 is located between the data line fan-out partition 1221 and the data line fan-out partition 1222
  • the high-voltage power line pin Vdd1 is located between the data line fan-out partition 1222 and the data line fan-out partition.
  • the high-voltage power line pin Vdd2 is located between the data line fan-out partition 1223 and the data line fan-out partition 122C
  • the low-voltage power line pin Vss1 is located between the data line fan-out partition 1223 and the data line fan-out partition 1224. between.
  • the number of data lines in the aforementioned data line fan-out partition 1221, data line fan-out partition 1222, data line fan-out partition 1223, and data line fan-out partition 1224 are both r/2, that is, the outermost The data line fan-out partition has the same number of data lines, and the second-outer data line fan-out partition has the same number of data lines. This solution can improve the uniformity of display brightness.
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the display panel 100 provided in this embodiment may include: a display area 110 and a non-display area 120 located around the display area 110.
  • the non-display area 120 includes a bending area 121 and a data line 110a configured to connect the display area 110 to
  • the first fan-out area 122 of the bending area 121 further includes a plurality of sub-pixels 126 located in the display area 110; multiple data lines located in the display area 110 and extending from the display area 110 to the second A fan-out area 122, the plurality of data lines are electrically connected to the plurality of sub-pixels 126, and are configured to provide data signals for the plurality of sub-pixels, and the bending area 121 is configured to be bent to the display The back of the panel.
  • the first fan-out zone 122 includes: at least two data line fan-out zones (such as data line fan-out zones 122a and 122b in FIG. 7), and the data lines in the data line fan-out zone 110a is connected to the data line bending area in the bending area 121 corresponding to the data line fan-out partition one-to-one (the data line bending areas 121a and 121b in FIG. 7).
  • dark gray filled areas indicate the data line fan-out partition (122a and 122b in FIG. 7), and the data line fan-out partition includes all the data line fan-out partitions that are drawn below the display area 110.
  • Data lines since the number of data lines is in the thousands, the specific data line 110a is not shown in the data line fan-out partition, only the data lines in the data line fan-out partition are connected to the corresponding data line bending area The position of indicates the data line 110a, and the indicated number of data lines 110a does not represent the actual number of data lines.
  • the display panel 100 provided by the embodiment of the present application can further reduce the size of the fan-out portion of the data line.
  • the current structure of the display panel is arranged in order from the outside to the inside into the non-display area and the display area (Active Area, referred to as: AA).
  • the display area is the effective display area in the panel, that is, the area where the light-emitting unit is arranged in the entire panel.
  • the non-display area is the border around the display area. This part of the area can be equipped with a driving circuit.
  • the lower border of the display panel is provided with a fan-out area, a bending area and a driving IC for the data line, as shown in Figure 1 and Figure 7.
  • the left and right borders of the display panel can be reduced by using known technical means.
  • the embodiment of the present application can reduce the size of the lower border with the data line fan-out area to achieve the purpose of increasing the screen-to-body ratio.
  • the structure of the display panel 100 provided by the embodiment of the present application is as shown in FIG. 7, except for the display area 110 that can be effectively displayed, the others are all non-display areas 120.
  • the display panel 100 in the embodiment of the present application is based on the structure in which the bending area can be bent in the flexible display technology. In a way to achieve a full screen (that is, to increase the screen-to-body ratio), the bending area 121 and the display area in the non-display area 120 are reduced.
  • the size between 110 is to reduce the size of the fan-out portion of the data line (ie, the first fan-out area 122).
  • the data lines of the display area 110 are usually arranged vertically, and each data line is independently connected to the driving IC, that is, all the data lines are connected to the driving IC in parallel, and the driving IC controls these data lines to be in the display area 110
  • the light-emitting pixels provide data information for display. The higher the resolution of the display panel, the larger the number of data lines.
  • the resolution of the display panel is 1080*1920
  • the number of data lines is 1080, that is, 1080 data lines are connected from the first fan-out area 122 to the bending area 121 in parallel.
  • all the data lines 22a are connected to the middle area of the bending area 23 (ie, the data line bending area 23a).
  • the number of data lines 22a of the display panel 20 is in the thousands, and a large number of data lines 22a in the divergent area are connected to the concentrated area in the bending area 23 (ie, data lines).
  • the bending area 23a in this structure, it is difficult to further reduce the width of the data line fan-out area 22.
  • the number of data lines in the display area 110 is usually very large, in the data line fan-out area 22 of FIG. 1 and the first fan-out area 122 of FIG. 7, only the position where the fan-out area is connected to the data line bending area is shown.
  • the data lines are shown sexually, and do not represent the number of data lines in the display panel, and are only used to schematically indicate the implementation of connecting the data lines of the display area to the bending area.
  • At least two data line fan-out partitions are divided in the first fan-out area 122 (such as 122a and 122b in FIG. 7), and the area in the bending area 121 for accessing the data line (Data line bending areas 121a and 121b in FIG. 7) correspond to the aforementioned data line fan-out partitions (122a and 122b).
  • the data line bending area 121a corresponds to the data line fan-out partition.
  • the data line bending area 121b corresponds to the data line fan-out partition 122b (that is, the data line connection in the data line fan-out partition 122b To the data line bending area 121b); in addition, the number of data lines in the corresponding data line fan-out area and the data line bending area in the embodiment of the present application are the same.
  • the wires leading out from under the display area 110 and connected to the bending area 121 include the high-voltage power line Vdd (configured as the aforementioned data line 110a).
  • a plurality of sub-pixels provide high-voltage signals) and a low-voltage power line Vss (configured to provide low-voltage signals for the plurality of sub-pixels), etc.
  • the display panel can pass through the high-voltage power line Vdd and the low-voltage power line Vdd during normal display.
  • the voltage power line Vss continuously supplies power to the light-emitting unit so that the light-emitting unit is in a lightable state.
  • the TFT in the thin film transistor (Thin Film Transistor, abbreviated as: TFT) array layer can be scanned.
  • the TFT is turned on at a time sequence to light up the corresponding light-emitting unit, so a clock signal line may also be included.
  • the data lines 22a of the display panel 20 are collectively connected to the middle area of the bending area 23 (that is, the data line bending area 23a), the high voltage power line Vdd and the low voltage power line Vss are connected to both sides of the bending area 23 , As shown in Figure 1 in the power cord bending areas 23b and 23c.
  • the bending area 121 there is a certain distance between at least two data line bending areas.
  • One or more of the following bending areas may be arranged between the data line bending areas: a high voltage power line bending area 121Vdd and a low voltage power line bending area 121Vss.
  • FIG. 8 a schematic structural diagram of another display panel provided by an embodiment of the application, in which the high-voltage power line bending area 121Vdd is set to connect to the high-voltage power line Vdd of the light-emitting unit in the display area 110.
  • the voltage power line bending area 121Vss is set as a low voltage power line Vss connected to the light-emitting unit in the display area 110.
  • FIG. 8 shows an example in which a high voltage power line bending area 121Vdd and a low voltage power line bending area 121Vss are provided between two adjacent data line bending areas 121a and 121b.
  • the bending area 121 may also include: a clock signal (Clock, referred to as Clk) bending area (not shown in FIG. 8), a touch signal bending area (FIG. 8 Not shown in) etc.
  • a non-data line bending area is provided between at least two data line bending areas in the bending area, and the non-data line bending area is set to access The signal lines other than the data lines in the display area.
  • the non-data line bending area includes one or more of the following bending areas: a high voltage power line bending area, a low voltage power line bending area, a clock signal bending area, and a touch signal bending area.
  • the minimum line width and minimum spacing of the data lines are related to the process level and design rules, the number and resolution of the data lines in the display panel 100 are related, and the size of the display area 110 is determined by the product design specifications and will be fixed
  • a number of data lines are connected to the first fan-out area 122, and the segmented fan-out method provided in the embodiment of the present application is adopted.
  • the data line connected in each data line bending area and the corresponding data line fan-out area The data line can be reduced by at least half, or even more, for example, reduced to 1/3, 1/4, 1/5, or 1/7.
  • the data lines in the lower frame are fanned out in segments to reduce the wiring occupation
  • the space can effectively reduce the width of the first fan-out area 122, that is, reduce the size of the lower frame in the display panel 100.
  • the size of the first fan-out area 122 configured to connect the data line to the bending area 121 is not only related to the above-mentioned parameters, but can also consider the size of the display area 110 and the specifications of the driving IC.
  • the display panel 100 provided by the embodiment of the present application includes a display area and a non-display area 120 located at the periphery of the display area 110.
  • the non-display area 120 includes a bending area 121 and is configured to connect the data lines in the display area 110 to the bending area.
  • the first fan-out area 122 of the area 121 includes at least two data line fan-out partitions, and the data line in the data line fan-out partition is connected to the bending area 121 and the data line fan-out partition
  • One-to-one corresponding data line bending areas, and at least two data line bending areas in the bending area 121 may be provided with one or more of the following bending areas: high-voltage power line bending areas 121Vdd and 121Vss in the bending area of the low-voltage power cord.
  • the fan-out structure of the data line is reasonably designed, that is, the data line is fan-out segmented, and the high-voltage power line bending area and the low-voltage power line bending area One or more are used as the interval between at least two bending areas of the data line, and the wiring method of the lines in the bending area is reasonably planned, and the data is effectively reduced based on the bending structure of the lower frame in the flexible display technology
  • the overall width of the wiring in the line fan-out area ie, the first fan-out area 122) reduces the size of the bottom frame of the display panel 100, thereby increasing the screen-to-body ratio of the display panel 100.
  • the embodiment of the present application does not limit the data line bending area to only the two illustrated in FIGS. 7 and 8 (that is, 121a and 121b), nor does it limit the data line fan-out partition to the two illustrated in FIGS. 7 and 8.
  • Numbers ie 122a and 122b, for example, can be 2 to 7, or can be other numbers.
  • the data line fan-out partition is an odd number.
  • each data line fan-out zone or each data line bending area
  • Figures 7 and 8 show the data in the two data line bending areas. The lines are shown as an example of half of the total number. In actual applications, it can be reasonably configured according to the shape of the display area 110 and actual use requirements.
  • the partitioning manner of the bending area 121 and the first fan-out area 122 will be described in detail below through several embodiments.
  • the wires leading from under the display area 110 and connected to the bending area 121 may also include high-voltage power lines Vdd and low-voltage power lines Vss. Therefore, the first fan-out zone 122 of the embodiment of the present application may also include a high-voltage power line fan-out zone and a low-voltage power line fan-out zone, where the high-voltage power line fan-out zone is set to connect the high-voltage power line Vdd To the bending area 121, the low-voltage power line fan-out partition is configured to connect the low-voltage power line Vss to the bending area 121.
  • the high-voltage power line Vdd, the low-voltage power line Vss, and the data line are usually made in different layers, that is, the fan-out zones of different circuits are also located in the first fan-out area 122.
  • at least one of the data line fan-out partition, the high-voltage power line fan-out partition, and the low-voltage power line fan-out partition has an overlapping area in the projection on the plane where the display panel 100 is located.
  • the projection of a certain data line fan-out partition and the fan-out partition of which lines on a different layer have an overlap area, which can be performed by the designer according to the actual data line partition fan-out mode and the fan-out mode of other lines planning.
  • the embodiment of the present application also adopts the method of partitioning and bending the data line in the bending area 121, and tries to set the bending area of other lines in the interval between at least two data line bending areas to reasonably plan the bending area.
  • the wiring space in the folding area 121 is not limited to.
  • FIG. 9 is a schematic structural diagram of another display panel provided by an embodiment of the application.
  • the data line bending area of the bending area 121 can be divided into three parts, including, for example, the central area of the display area 110.
  • the left area of the display area 110 is the area near the first side of the display panel 100 in the display area 110 (the left side in FIG.
  • the right area of the display area 110 is the area near the second side of the display panel 100.
  • Area (the right side in FIG. 9) the central area of the display area 110 is the area between the left area of the display area 110 and the right area of the display area 110, and the first side and the second side are opposite sides , And adjacent to the third side where the data line fan-out partition is located.
  • the bending area 121 is divided into three sections.
  • FIG. 9 shows the above-mentioned three data line bending areas with non-uniform configuration as an example. Accordingly, since the data in the first fan-out area 122 The segmentation method of the line fan-out partition corresponds to the above-mentioned data line bending area (121C, 121L, and 121R).
  • the data line fan-out partition may include: setting the data line in the central area of the display area 110 to the center
  • the central data line fan-out partition 122C of the data line bending area 121C is set to connect the data line in the left area of the display area 110 to the left area data line fan-out partition 122L of the data line bending area 121L in the left area, and set to The data line in the right area of the display area 110 is connected to the right area data line fan-out area 122R of the right area data line bending area 121R.
  • the segmentation of the data line fan-out area and the data line bending area and the corresponding manner are, for example, assuming that the total number of data lines in the display area 110 is a, and the data lines in the left and right areas are respectively The number of data lines in the central area is r, and the number of data lines in the central area is a-2r.
  • the data lines in the central area are the largest part of the data line partition of the display area 110.
  • the a-2r data lines in this part pass through and the display area 110
  • the central data line fan-out zone 122C connected to the central area is connected to the central data line bending area 121C.
  • the left and right data lines of the display area 110 are equal and symmetrically distributed.
  • the r data lines in the left area pass through and
  • the left area data line fan-out partition 122L connected to the left area of the display area 110 is connected to the left area data line bending area 121L, and the r data lines in the right area are fanned out through the right area data lines connected to the right area of the display area 110
  • the partition 122R is connected to the right area data line bending area 121R.
  • the ratio of the central area data lines a-2r to the total number of data lines a can be reasonably configured by the designer according to the size and shape of the display area 110 and the design specifications of the display panel 100.
  • the high-voltage power line bending area 121Vdd may be located between the left area data line bending area 121L and the central data line bending area 121C, and the low voltage power line bending area 121Vss may be located at the right area data line Between the bending area 121R and the central data line bending area 121C.
  • the first fan-out area 122 may also include other wires connecting the signal line in the display area 110 to the bending area 121, for example, including a high-voltage power line Vdd and a low-voltage power line Vss, As well as the clock signal line Clk, etc., therefore, the high-voltage power line Vdd or the low-voltage power line Vss can be arranged between adjacent data line fan-out sections, that is, the high-voltage power line Vdd and the low-voltage power line Vss are used as data
  • the line segment fan-out interval accordingly, in the bending area 121, the high-voltage power line bending area 121Vdd that is connected to the high-voltage power line Vdd and the low-voltage power source that is set to be connected to the low-voltage power line Vss can be set
  • the line bending area 121Vss serves as the interval between adjacent data line bending areas.
  • a part of the structure in the display panel 100 is used as the interval between the segmented fan-out and the bending area of the data line, so that the internal structure of the display panel 100 is rationally planned and utilized without adding a new structure.
  • the display panel 100 usually adopts a double-side driving method, that is, both the left and right sides of the display area 110 can be configured with a symmetrically arranged high-voltage power line Vdd and a symmetrically arranged low-voltage power line Vss.
  • the low-voltage power line bending area 121Vss in the bending area 121 may include a first low-voltage power line bending area 121Vss1 and a second low-voltage power line bending area 121Vss2 that are symmetrically arranged about the center line of the display area 110
  • the high voltage power line bending area 121Vdd may also include a first high voltage power line bending area 121Vdd1 and a second high voltage power line bending area 121Vdd2 that are symmetrically arranged about the center line of the display area 110.
  • the symmetrically arranged Vdd and Vss are not shown in FIGS. 7 to 9 above.
  • the high-voltage power line bending area 121 Vdd and the low-voltage power line in the bending area 121 of FIGS. 7 to 9 The bending area 121Vss is configured to be symmetrically arranged, and based on the number and position of the bending area of the data line in the bending area 121 of FIG. 7 to FIG. 9, the segment interval can be reasonably configured.
  • a resistance compensation method can be used to achieve uniform light emission of the light emitting unit in the display area 110.
  • FIG. 10 it is a schematic structural diagram of still another display panel provided by the embodiment of the present application.
  • FIG. 10 is shown based on the structure shown in FIG. 9 as an example, that is, FIG. 10 also includes three data line bending areas (that is, 121C, 121L, and 121R), and the display panel 100 shown in FIG.
  • the first low voltage power line bending area 121Vss1 and the first high voltage power line bending area 121Vdd1 are located between the left area data line bending area 121L and the center data line bending area 121C, and the second low voltage The power cord bending area 121Vss2 and the second high voltage power cord bending area 121Vdd2 are located between the right data line bending area 121R and the central data line bending area 121C.
  • the interval of the segmented data lines in the bending area 121 is as follows Shown in Figure 10.
  • FIG. 11 is shown based on the structure shown in FIG. 10 as an example.
  • the central data line bending area 121C is the same as that in FIG. 10, and the data line bending area 121L in the left area includes a first data line bending area 1211 and a second data line bending area.
  • the second data line bending area 1212, the right area data line bending area 121L includes a third data line bending area 1213 and a fourth data line bending area 1214.
  • the first fan-out area 122 also has five data line fan-out partitions corresponding to each other, and a corresponding pair of data line fan-out partitions and data line bending areas
  • the number of data lines in the folding area is the same and corresponds to one to one.
  • the bending area 121 is provided with four symmetrical high-voltage power lines and low-voltage power lines. Two bending areas (ie 121Vss1, 121Vdd1, 121Vdd2 and 121Vss2).
  • a high-voltage power supply line Vdd or a low-voltage power supply line Vss may be arranged between any two adjacent partitions of the five data line fan-out partitions, that is, the structure of the bending area 121 may be arranged in order from left to right Arranged with: first data line bending area 1211, first low voltage power line bending area 121Vss1, second data line bending area 1212, first high voltage power line bending area 121Vdd1, central data line bending area 121C , The second high voltage power line bending area 121Vdd2, the third data line bending area 1213, the second low voltage power line bending area 121Vss2, and the fourth data line bending area 1214.
  • the first fan-out area 121 of the display panel 100 shown in FIG. 11 there are arranged from left to right: the first data line bending area 1211, the second data line bending area 1212, and the third subarea.
  • the first data line fan-out partition 1221, the second data line fan-out partition 1222, the third data line fan-out partition 1223, and the fourth data corresponding to the data line bending area 1213 and the fourth data line bending area 1214 one-to-one Line fan-out partition 1224.
  • the display area 110 of the display panel is usually made in a shape with four arc-shaped chamfers.
  • the display panel 100 shown in FIGS. 2 to 11 is not shown.
  • the arc-shaped chamfer but it is understandable that the left and right corners below the display area can be in the shape of an arc-shaped chamfer.
  • the area including the left corner is called the left chamfer area (or called The first chamfer area), the area including the right corner is called the right chamfer area (or second chamfer area), and it is understandable that the left chamfer area and the right chamfer area are longitudinally distributed There are a few data lines, and the data lines in these areas can be connected to the corresponding data line bending area through the corresponding left area data line fan-out partition 122L and right area data line fan-out partition 122R. Refer to Figures 9 to The segmented fan-out method in 11.
  • the data line in the left area data line fan-out partition 122L connected to the left area data line bending area 121L The number of data lines is equal to the number of data lines in the left chamfered area of the display area 110, and the number of data lines in the right area data line fan-out partition 122R connected to the right area data line bending area 121R is equal to the right chamfered area of the display area 110
  • the number of data lines in the area is equal to the number of data lines in the left chamfered area of the display area 110
  • the number of data lines in the right area data line fan-out partition 122R connected to the right area data line bending area 121R is equal to the right chamfered area of the display area 110
  • the number of data lines in the area For example, in the structure shown in FIG. 9 and FIG.
  • the shape and area of the light-emitting pixels in the chamfered area are different from the central area of the display area 110, and the above two areas (the left chamfered area and the right chamfered area)
  • the data lines in the corner area) are respectively connected to the drive IC through the corresponding left area data line bending area 121L and right area data line bending area 121R. Therefore, the drive IC can be used to connect the left chamfered area and the right area.
  • the data lines in the side chamfered area perform brightness uniformity compensation to ensure that the display brightness of the display panel 100 has better uniformity.
  • FIG. 12 is a schematic structural diagram of still another display panel provided by an embodiment of the application.
  • FIG. 12 is shown as an example based on the structure of the display panel 100 shown in FIG. 7 to FIG. 11, and the structure of the bending area 121 and the first fan-out area 122 is not shown in FIG.
  • the above-mentioned bending area 121 and the first fan-out area 122 are schematically shown.
  • the non-display area 120 of the display panel 100 provided by the embodiment of the present application may further include: a second fan-out area 123 bent to the non-display area 120 of the display panel 100 through the bending area 121, and the plurality of data lines extend to The second fan-out area 123.
  • the second fan-out area 123 in the embodiment of the present application is configured to fan out the data lines in the bending area 121 again.
  • the second fan-out area 123 includes a resistance compensation module 1231, and the resistance compensation module 1231 is configured to The data line connected to the first fan-out area 122 is subjected to resistance compensation, so that the impedance of the data line changes gradually.
  • the non-display area 120 in the embodiment of the present application may also include a cell test area (Cell Test) 124 connected to the second fan-out area 123, and a driving IC 125 connected to the cell test area 124.
  • Cell Test Cell Test
  • the implementation of this application In the example, all data lines and other wires are connected to the drive IC 125.
  • FIG. 1 illustrates a data line fan-out structure in a display panel
  • FIGS. 7 to 11 illustrate a data line in a display panel provided by an embodiment of the present application.
  • Fan-out structure It can be seen that in the display panel 20 shown in FIG. 1, a large number of scattered data lines 22a drawn from under the display area 21 are connected to the centralized data line bending area 23a, and the data line fan-out area 22 and the data line bending area There is no segmentation in 23a. Therefore, the impedance of the adjacent data line 22a changes continuously and gradually. As shown in FIG.
  • the data lines perform segmented fan-out, that is, the data lines in the first fan-out area 122 and the bending area 121 have at least two partitions, as shown in FIGS. 7 to Figure 11 shows the structure.
  • the length of the data line connected to the same data line bending area changes gradually, and its impedance also changes gradually, due to the segmented fan-out and bending area
  • the middle partition there is a sudden change in the impedance of the two adjacent data lines connected to the adjacent data line bending area.
  • 100 data lines are connected to the first data line bending area 1211, the second data line bending area 1212, the third data line bending area 1213, and the fourth data line bending area 1214, and the data
  • the lines are consecutively numbered, and there is a sudden change in impedance between the 100th data line in the first data line bending area 1211 and the 101st data line in the second data line bending area 1212, and the multiple data lines are bent
  • the data lines in the area perform secondary fan-out, and an equal resistance compensation design is performed in the second fan-out area 123, so that the impedance of all the data lines changes gradually.
  • the specifications of the display area 110 and the driving IC are fixed, and the data lines are fan-out segmented so that the overall width W from the first fan-out area 122 to the second fan-out area 123 becomes larger.
  • the wiring space of the first fan-out area 122 becomes smaller (that is, the width W1 of the 122 becomes smaller).
  • the overall wiring space of the second fan-out area 123 connected to the driving IC 125 under the bending area 121 becomes larger, this part of the wiring is finally bent to the back of the display area 110 through the bending area 121, and does not affect the lower frame of the display panel 100.
  • the width that is, the display panel 100 provided by the embodiment of the present application, by adopting the structure of segmented fan-out and partitioning in the bending area for the data line, the lower bezel can be effectively reduced to achieve the goal of narrowing the lower bezel.
  • the bent lower frame can be reduced from 2.0 millimeters (mm) to 1.5 mm, which increases the screen-to-body ratio of the display panel 100.
  • the display panel 100 includes a flexible display panel.
  • an embodiment of the present application further provides a display device, which includes the display panel 100 in any of the foregoing embodiments shown in FIGS. 2 to 12. Based on the technical effects of the display panel 100 provided by the foregoing embodiment, the display device provided by the embodiment of the present application also has a structure with a narrow lower frame and a higher screen-to-body ratio.

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Abstract

提供了一种显示面板和显示装置。显示面板包括：显示区和至少位于所述显示区一侧的非显示区，所述非显示区包括第一扇出区；多个子像素，位于所述显示区；多条数据线，位于所述显示区且从所述显示区延伸到所述第一扇出区，所述多条数据线与所述多个子像素电连接，被配置为为所述多个子像素提供数据信号；所述第一扇出区包括：至少两个数据线扇出分区，所述多条数据线分别位于所述至少两个数据线扇出分区中。

Description

一种显示面板和显示装置
本申请要求于2019年3月28日提交中国专利局、申请号为201910245586.0、发明名称为“一种柔性显示面板和显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本申请实施例涉及但不限于一种显示面板和显示装置。
背景技术
随着显示技术的发展，柔性显示面板已广泛应用于多种显示技术领域，全面屏逐渐成为显示设备的主流。
全面屏的设计是追求在每个边框位置采用无边框设计，追求接近100％的屏占比。但由于受限于目前的技术，业界宣称的全面屏只是提高屏占比，无法真正做到100％的屏占比，因此，缩小显示面板的边框尺寸仍是提高屏占比的重要手段。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本申请实施例提供一种显示面板，包括：
显示区和至少位于所述显示区一侧的非显示区，所述非显示区包括第一扇出区；
多个子像素，位于所述显示区；
多条数据线，位于所述显示区且从所述显示区延伸到所述第一扇出区，所述多条数据线与所述多个子像素电连接，被配置为为所述多个子像素提供数据信号；
所述第一扇出区包括：至少两个数据线扇出分区，所述多条数据线分别延伸到所述至少两个数据线扇出分区中。
一种示例性实施例中，所述显示面板还包括：高电压电源线和低电压电源线；
所述高电压电源线，位于所述非显示区，且至少部分所述高电压电源线位于所述第一扇出区，所述高电压电源线被配置为为所述多个子像素传输高电压信号，所述高电压电源线包括至少两个高电压电源线引脚；
所述低电压电源线，位于所述非显示区且围绕所述显示区，被配置为为所述多个子像素传输低电压信号，所述低电压电源线包括至少两个低电压电源线引脚；
所述至少两个高电压电源线引脚和所述至少两个低电压电源线引脚中的至少一个位于所述至少两个数据线扇出分区之间。
一种示例性实施例中，所述至少两个数据线扇出分区的数量为两个，所述至少两个高电压电源线引脚的数量为两个，所述至少两个低电压电源线引脚数量为两个，所述两个高电压电源线引脚和所述两个低电压电源线引脚全部位于所述两个数据线扇出分区之间。
一种示例性实施例中，所述至少两个数据线扇出分区的数量为三个，每两个所述数据线扇出分区之间设置有所述至少两个高电压电源线引脚和所述至少两个低电压电源线引脚中的至少一个。
一种示例性实施例中，所述至少两个高电压电源线引脚的数量为两个，所述至少两个低电压电源线引脚的数量为两个，所述至少两个数据线扇出分区的数量为三个，所述两个高电压电源线引脚分别位于所述三个数据线扇出分区之间，所述两个低电压电源线引脚分别位于所述三个数据线扇出分区之间。
一种示例性实施例中，所述至少两个高电压电源线引脚的数量为两个，所述至少两个低电压电源线引脚的数量为两个，所述至少两个数据线扇出分区的数量为五个，所述两个高电压电源线引脚和所述两个低电压电源线引脚分别位于所述五个数据线扇出分区之间。
一种示例性实施例中，所述五个数据线扇出分区中的每两个之间设置有所述两个高电压电源线引脚和所述两个低电压电源线引脚中的一个。
一种示例性实施例中，所述两个高电压电源线引脚相对于所述显示面板的中线对称设置，所述两个低电压电源线引脚相对于所述显示面板的中线对称设置。
一种示例性实施例中，所述至少两个数据线扇出分区中最外侧的两个数据线扇出分区中的数据线数量一致。
一种示例性实施例中，所述显示面板还包括弯折区，所述弯折区位于所述第一扇出区远离所述显示区的一侧，所述多条数据线延伸到所述弯折区，所述弯折区被配置为弯折到所述显示面板的背面。
一种示例性实施例中，还包括：第二扇出区，所述第二扇出区位于所述弯折区远离所述显示区的一侧，所述多条数据线延伸到所述第二扇出区；
所述第二扇出区中包括电阻补偿模块，所述电阻补偿模块被配置为对所述多条数据线进行电阻补偿，以使得所述数据线的阻抗呈渐进式变化。
又一方面，本申请实施例还提供一种显示装置，包括：如上述任一项所述的显示面板。
附图说明
附图用来提供对本申请实施例技术方案的进一步理解，并且构成说明书的一部分，与本申请实施例一起用于解释技术方案，并不构成对技术方案的限制。
图1为一种显示面板的结构示意图；
图2为本申请实施例提供的一种显示面板的结构示意图；
图3为本申请实施例提供的另一种显示面板的结构示意图；
图4为本申请实施例提供的又一种显示面板的结构示意图；
图5为本申请实施例提供的再一种显示面板的结构示意图；
图6为本申请实施例提供的再一种显示面板的结构示意图；
图7为本申请实施例提供的再一种显示面板的结构示意图；
图8为本申请实施例提供的再一种显示面板的结构示意图；
图9为本申请实施例提供的再一种显示面板的结构示意图；
图10为本申请实施例提供的再一种显示面板的结构示意图；
图11为本申请实施例提供的再一种显示面板的结构示意图；
图12为本申请实施例提供的再一种显示面板的结构示意图。
具体实施方式
下文中将结合附图对本申请实施例进行详细说明。在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
目前的全面屏显示设备(例如手机)在设计上追求接近100％的屏占比，采用的主要方法是缩小边框尺寸。相比于左右边框，通常显示面板的下边框尺寸更大，目前对于左右边框已具有成熟的缩小方案，由于下边框尺寸受到的限制因素较多，缩小下边框的难度更高。如图1所示，为一种显示面板的结构示意图，显示面板20包括显示区21、非显示区，多个子像素、多条数据线、高电压电源线Vdd和低电压电源线Vss，高电压电源线Vdd包括Vdd引脚，低电压电源线Vss包括两个Vss引脚。所述数据线为所述多个子像素提供数据信号，所述高电压电源线为所述多个子像素传输高电压信号，所述低电压电源线为所述多个子像素传输低电压信号。在显示面板20的结构中，数据线22a(Data Line)通常从显示区21的下方引出，即数据线扇出(Data Line Fanout)区22位于显示区21的下方，即显示面板20下边框的位置，图1中以深灰色填充区域示意出数据线扇出区22，该数据线扇出区22内部包括显示面板20下方引出的所有数据线，由于数据线的数量数以千计，在该数据线扇出区22中并未示意出全部数据线22a，仅在数据线扇出区22中的数据线连接至弯折区23的位置，示意出了数据线22a，且示意出的数据线22a的数量并不代表实际数据线的数量。因此，显示面板本身的尺寸和分辨率，以及驱动集成电路(Integrated Circuit，简称为：IC)的规格，影响数据线扇出区22布线的总体宽度，即影响显示面板中下边框的尺寸。上述显示面板中， 无法进一步缩小下边框的尺寸以提高屏占比。
以下几个实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
如图2所示，本申请一实施例提供一种显示面板100，包括：显示区110和至少位于所述显示区一侧的非显示区120，所述非显示区120包括第一扇出区122；多个子像素126，位于所述显示区110；多条数据线110a，位于所述显示区110且从所述显示区110延伸到所述第一扇出区122，所述多条数据线与所述多个子像素126电连接，被配置为为所述多个子像素126提供数据信号；所述第一扇出区122包括：至少两个数据线扇出分区，所述多条数据线分别位于所述至少两个数据线扇出分区中(如图2中的数据线扇出分区122a和122b)。
本实施例及以下实施例的附图中，均以深灰色填充区域示意出数据线扇出分区(如图2中的122a和122b)，该数据线扇出分区内部包括显示区110下方引出的所有数据线，由于数据线的数量数以千计，在该数据线扇出分区中并未示意出全部的数据线110a。
在实际应用中，数据线的最小线宽和最小间距与工艺水平和设计规则相关，显示面板100中数据线的数量和分辨率相关，显示区110的尺寸则由产品的设计规格决定，将固定数量的数据线连接至第一扇出区122，采用本申请实施例提供的分段扇出的方式，每个数据线扇出分区中的数据线至少可以减少一半，甚至减少更多，例如减少到1/3、1/4、1/5或1/7等。在数据线的设计规格、显示面板分辨率和大小均相同的情况下，本申请实施例的显示面板100中，通过对下边框中的数据线进行分段扇出的方式来减小布线占用的空间，可以有效缩小第一扇出区122的宽度，即缩小了显示面板100中下边框的尺寸。
在一示例性实施例中，至少存在两个数据线扇出分区之间存在除所述数据线外的信号线，所述信号线包括以下至少之一：高电压电源线Vdd(被配置为为所述多个子像素传输高电压信号)和低电压电源线Vss(被配置为为所述多个子像素传输低电压信号)、时钟信号线(被配置为为所述多个子像素传输时钟信号)和触控信号线(被配置为为所述多个子像素传输触控信号)。 本实施例中，数据线被分散配置，可以减小布线所占空间，缩小第一扇出区122的宽度。
在一示例性实施例中，如图3所示，所述显示面板100还包括：高电压电源线Vdd和低电压电源线Vss；
所述高电压电源线，位于所述非显示区120，被配置为为所述多个子像素传输高电压信号；所述高电压电源线包括两个高电压电源线引脚；
所述低电压电源线，位于所述非显示区120，被配置为为所述多个子像素提传输电压信号；所述低电压电源线包括两个低电压电源线引脚；
所述两个高电压电源线引脚和所述两个低电压电源线引脚全部位于所述两个数据线扇出分区之间。
本申请实施例提供的显示面板100，通过合理的设计数据线的扇出结构，即对数据线进行分段扇出，并以高电压电源线、低电压电源线中的一个或多个作为至少两个数据线扇出分区之间的间隔，有效缩小了数据线扇出区域(即第一扇出区122)布线的总体宽度，即缩小了显示面板100中下边框的尺寸，从而提高了显示面板100的屏占比。
在另一示例性实施例中，所述两个高电压电源线引脚和所述两个低电压电源线引脚中可以部分位于所述两个数据线扇出分区之间，部分位于所述两个数据线扇出分区之外。
图4为本申请实施例提供的又一种显示面板的结构示意图。在图2所示显示面板100的结构基础上，本申请实施例提供的显示面板100中，数据线扇出分区可以包括：依次排布的左区数据线扇出分区122L，中心数据线扇出分区122C，右区数据线扇出分区122R。
在本申请实施例中，高电压电源线引脚可以位于左区数据线扇出分区122L与中心数据线扇出分区122C之间，低电压电源线引脚可以位于右区数据线扇出分区122R与中心数据线扇出分区122C之间。即采用高电压电源线引脚和低电压电源线引脚作为数据线分段扇出的间隔。
假设显示区110的数据线总数为a个，则左区数据线扇出分区122L的数据线为r个，右区数据线扇出分区122R的数据线为r个，即左区数据线扇 出分区122L和右区数据线扇出分区122R的数据线的数量一致，中心数据线扇出分区122C的数据线为a-2r个。本申请实施例中，中心区数据线a-2r占数据线总数a的比值，可以由设计人员根据显示区110的大小和形状，以及显示面板100的设计规格进行合理配置。
为了实现显示区110均匀发光，显示面板100通常采用双侧驱动的方式，即显示区110的左侧和右侧均可以配置有高电压电源线Vdd和低电压电源线Vss，在本申请实施例的一种可能的实现方式中，如图5所示，为本申请实施例提供的再一种显示面板的结构示意图。图5以在图4所示结构的基础上为例予以示出，所述高电压电源线包括两个高电压电源线引脚Vdd1和Vdd2，所述低电压电源线包括两个低电压电源线引脚Vss1和Vss2，其中，高电压电源线引脚Vdd1和低电压电源线引脚Vss1位于左区数据线扇出分区122L与中心数据线扇出分区122C之间，高电压电源线引脚Vdd2和低电压电源线引脚Vss2位于右区数据线扇出分区122R与中心数据线扇出分区122C之间。
在一示例性实施例中，所述两个高电压电源线引脚Vdd1和Vdd2以所述显示面板100的中线对称设置，所述两个低电压电源线引脚Vss1和Vss2以所述显示面板100的中线对称设置。所述显示面板100的中线为在所述显示面板所在平面上，从所述显示面板100的第一侧至第二侧的中线，且所述第一侧和第二侧非所述第一扇出区122所在侧，如图5和图6所示，虚线127为显示面板100的中线。
如图6所示，为本申请实施例提供的再一种显示面板的结构示意图。图6以在图5所示结构的基础上为例予以示出。第一扇出区122具有五个数据线扇出分区，该五个数据线扇出分区依次为：第一数据线扇出分区1221、第二数据线扇出分区1222、第三数据线扇出分区1223和第四数据线扇出分区1224。基于上述结构，五个数据线扇出分区中任意相邻两个分区中间可以设置有高电压电源线引脚或低电压电源线引脚，也可以只有部分相邻分区中间设置有高电压电源线引脚或低电压电源线引脚，即所述两个高电压电源线引脚Vdd1和Vdd2和所述两个低电压电源线引脚Vss1和Vss2可以部分位于五个数据线扇出分区之间，部分位于所述五个数据线扇出分区之外。
在一示例性实施例中，所述两个高电压电源线引脚Vdd1和Vdd2、所述 两个低电压电源线引脚Vss1和Vss2分别位于所述五个数据线扇出分区之间。
在一示例性实施例中，所述五个数据线扇出分区中的每两个之间设置有所述两个高电压电源线引脚和所述两个低电压电源线引脚中的一个。如图6所示，低电压电源线引脚Vss1位于数据线扇出分区1221和数据线扇出分区1222之间，高电压电源线引脚Vdd1位于数据线扇出分区1222和数据线扇出分区122C之间，高电压电源线引脚Vdd2位于数据线扇出分区1223和数据线扇出分区122C之间，低电压电源线引脚Vss1位于数据线扇出分区1223和数据线扇出分区1224之间。
在一示例性实施例中，上述数据线扇出分区1221、数据线扇出分区1222、数据线扇出分区1223和数据线扇出分区1224中数据线数量均为r/2，即最外侧的数据线扇出分区的数据线数量相同，次外侧的数据线扇出分区的数据线数量数量相同。该方案可以提高显示亮度的均一性。
图7为本申请实施例提供的一种显示面板的结构示意图。本实施例提供的显示面板100可以包括：显示区110和位于显示区110周边的非显示区120，该非显示区120包括弯折区121和设置为将显示区110中的数据线110a连接至弯折区121的第一扇出区122，还包括，多个子像素126，位于所述显示区110；多条数据线，位于所述显示区110且从所述显示区110延伸到所述第一扇出区122，所述多条数据线与所述多个子像素126电连接，被配置为为所述多个子像素提供数据信号，所述弯折区121被配置为弯折到所述显示面板的背面。
本申请实施例的上述结构中，第一扇出区122包括：至少两个数据线扇出分区(如图7中的数据线扇出分区122a和122b)，数据线扇出分区中的数据线110a连接至弯折区121中与数据线扇出分区一一对应的数据线弯折区(如图7中的数据线弯折区121a和121b)。本申请以下各实施例的附图中，均以深灰色填充区域示意出数据线扇出分区(如图7中的122a和122b)，该数据线扇出分区内部包括显示区110下方引出的所有数据线，由于数据线的数量数以千计，在该数据线扇出分区中并未示意出具体的数据线110a，仅在数据线扇出分区中的数据线连接至对应数据线弯折区的位置，示意出了数据线110a，且示意出的数据线110a的数量并不代表实际数据线的数量。
本申请实施例提供的显示面板100，可以进一步缩小数据线扇出部分的尺寸。目前的显示面板的结构排布由外向内依次为非显示区和显示区(Active Area，简称为：AA)，显示区为面板中可有效显示的区域，即整个面板中布设发光单元的区域，非显示区即为显示区周边的边框，该部分区域可以布设驱动电路，通常显示面板的下边框设置有数据线的扇出区、弯折区以及驱动IC等，如图1和图7所示，其中示意出了显示区和非显示区之间的位置关系。对于显示面板的左右边框，可以采用已知的技术手段进行缩小，本申请实施例可以实现缩小具有数据线扇出区域的下边框的尺寸，以达到提高屏占比的目的。
本申请实施例提供的显示面板100的结构如图7所示，除可以进行有效显示的显示区110，其它都为非显示区120。本申请实施例中的显示面板100基于柔性显示技术中弯折区可弯折的结构，实现全面屏(即提高屏占比)的方式中，减少非显示区120中弯折区121与显示区110之间的尺寸，即减少数据线扇出部分(即第一扇出区122)的尺寸。显示区110的数据线，通常为纵向排列的，且每根数据线独立的与驱动IC相连接，即所有数据线并行的连接到驱动IC，由驱动IC控制这些数据线为显示区110中的发光像素提供用来显示的数据信息。显示面板的分辨率越高，其数据线的数量也越大。
举例来说，显示面板的分辨率为：1080*1920，其数据线的数量则为1080，也就是要将1080根数据线并行的从第一扇出区122连接至弯折区121。参考图1所示的显示面板20，通常地，所有数据线22a连接至弯折区23的中间区域(即数据线弯折区23a)。由于用户对显示面板20高分辨率的要求，显示面板20的数据线22a是数以千计的，将发散区域内的大量的数据线22a连接到弯折区23内的集中区域(即数据线弯折区域23a)，该结构中，难以进一步缩小数据线扇出区22的宽度。
由于显示区110中数据线的数量通常非常巨大，图1的数据线扇出区22和图7的第一扇出区122中，仅在扇出区与数据线弯折区相连接的位置示意性的表示出数据线，并不代表显示面板中数据线的数量，仅用于示意性的表示显示区的数据线连接至弯折区中的实现方式。
在本申请实施例中，通过在第一扇出区122中划分出至少两个数据线扇 出分区(如图7中的122a和122b)，且弯折区121中供接入数据线的区域(如图7中数据线弯折区121a和121b)与上述数据线扇出分区(122a和122b)为一一对应的，如图7所示，数据线弯折区121a对应数据线扇出分区122a(即数据线扇出分区122a中的数据线连接至数据线弯折区121a中)，数据线弯折区121b对应数据线扇出分区122b(即数据线扇出分区122b中的数据线连接至数据线弯折区121b中)；另外，本申请实施例中相对应的数据线扇出分区和数据线弯折区中的数据线数量是相同的。基于本申请实施例提供的上述弯折区121的结构，并非所有发散区域内的大量数据线连接到一个集中区域，而是将发散区域中的数据线分段连接到弯折区121的不同区域内。
在本申请实施例的一种实现方式中，显示区110下方引出、且连接到弯折区121的连线除上述数据线110a之外，还有高电压电源线Vdd(被配置为为所述多个子像素提供高电压信号)和低电压电源线Vss(被配置为为所述多个子像素提供低电压信号)等线路，显示面板在正常显示的过程中，可以通过高电压电源线Vdd和低电压电源线Vss持续的给发光单元供电，以使得发光单元处于可点亮的状态，这样，就可以通过薄膜晶体管(Thin Film Transistor，简称为：TFT)阵列层中的TFT进行扫描，以一定的时序开启TFT，从而点亮相应的发光单元，因此还可以包括时钟信号线。由于显示面板20的数据线22a集中连接至弯折区23的中间区域(即数据线弯折区23a)，高电压电源线Vdd、低电压电源线Vss则连接至弯折区23的两侧区域，如图1中的电源线弯折区23b和23c。
基于本申请实施例中对在第一扇出区122中对数据线进行分区的扇出方式，在弯折区121中，至少两个数据线弯折区之间存在一定的间距，该至少两个数据线弯折区之间可以设置有以下弯折区中的一个或多个：高电压电源线弯折区121Vdd和低电压电源线弯折区121Vss。如图8所示，为本申请实施例提供的另一种显示面板的结构示意图，其中，高电压电源线弯折区121Vdd设置为接入显示区110中发光单元的高电压电源线Vdd，低电压电源线弯折区121Vss设置为接入显示区110中发光单元的低电压电源线Vss。图8以在两个相邻的数据线弯折区121a和121b之间设置有高电压电源线弯折区121Vdd和低电压电源线弯折区121Vss为例予以示出。根据显示面板100 的功能或设计规格，弯折区121中还可以包括：时钟信号(Clock，简称为：Clk)弯折区(图8中未示意出)、触控信号弯折区(图8中未示意出)等。
在本申请实施例的一种实现方式中，所述弯折区中的至少两个数据线弯折区之间设置有非数据线弯折区，所述非数据线弯折区设置为接入所述显示区中除数据线外的信号线。所述非数据线弯折区包括以下弯折区中的一个或多个：高电压电源线弯折区、低电压电源线弯折区、时钟信号弯折区和触控信号弯折区。
在实际应用中，数据线的最小线宽和最小间距与工艺水平和设计规则相关，显示面板100中数据线的数量和分辨率相关，显示区110的尺寸则由产品的设计规格决定，将固定数量的数据线连接至第一扇出区122，采用本申请实施例提供的分段扇出的方式，每个数据线弯折区中接入的数据线以及对应的数据线扇出分区中的数据线至少可以减少一半，甚至减少更多，例如减少到1/3、1/4、1/5或1/7等。在数据线的设计规格、显示面板分辨率和大小均相同的情况下，本申请实施例的显示面板100中，通过对下边框中的数据线进行分段扇出的方式来减小布线占用的空间，可以有效缩小第一扇出区122的宽度，即缩小了显示面板100中下边框的尺寸。另外，设置为将数据线连接至弯折区121的第一扇出区122的尺寸不仅与上述参数相关，还可以考虑显示区110的尺寸和驱动IC的规格。
本申请实施例提供的显示面板100，包括显示区和位于显示区110周边的非显示区120，该非显示区120包括弯折区121和设置为将显示区110中的数据线连接至弯折区121的第一扇出区122，该第一扇出区122包括至少两个数据线扇出分区，数据线扇出分区中的数据线连接至弯折区121中与该数据线扇出分区一一对应的数据线弯折区，且弯折区121中的至少两个数据线弯折区之间可以设置有以下弯折区中的一个或多个：高电压电源线弯折区121Vdd和低电压电源线弯折区121Vss。本申请实施例提供的显示面板100，通过合理的设计数据线的扇出结构，即对数据线进行分段扇出，并以高电压电源线弯折区、低电压电源线弯折区中的一个或多个作为至少两个数据线弯折区之间的间隔，合理的规划了弯折区中线路的布线方式，且在柔性显示技术中下边框弯折结构的基础上，有效缩小了数据线扇出区域(即第一扇出区 122)布线的总体宽度，即缩小了显示面板100中下边框的尺寸，从而提高了显示面板100的屏占比。
本申请实施例不限制数据线弯折区仅为图7和图8中示意出的两个(即121a和121b)，也不限制数据线扇出分区为图7和图8中示意出的两个(即122a和122b)，例如可以是2个到7个，或者可以是其它数量，在一示例性实施例中，数据线扇出分区为奇数个。
另外，本申请实施例不限制每个数据线扇出分区(或每个数据线弯折区)中的数据线是相等数量的，图7和图8以两个数据线弯折区中的数据线均为总数的一半为例予以示出，实际应用中可以根据显示区110的形状和实际使用要求进行合理配置。以下通过几个实施例对弯折区121和第一扇出区122的分区方式进行详细描述。
上述实施例中已经说明，显示区110下方引出、且连接到弯折区121的连线除上述数据线110a之外，还可以有高电压电源线Vdd和低电压电源线Vss等线路。因此，本申请实施例的第一扇出区122还可以包括高电压电源线扇出分区和低电压电源线扇出分区，其中，高电压电源线扇出分区设置为将高电压电源线Vdd连接至弯折区121，低电压电源线扇出分区设置为将低电压电源线Vss连接至弯折区121。另外，由于在显示面板的制作工艺中，高电压电源线Vdd和低电压电源线Vss与数据线通常为非同层制作的，即不同线路的扇出分区在第一扇出区122中也处于不同工艺层中，因此，至少一个数据线扇出分区与高电压电源线扇出分区、低电压电源线扇出分区中的一个或多个，在显示面板100所在平面的投影具有交叠区域。实际应用中，某个数据线扇出分区与非同层的哪些线路的扇出分区的投影具有交叠区域，可以由设计人员根据实际数据线分区扇出的方式和其它线路的扇出方式进行规划。
虽然本申请实施例的第一扇出区122中数据线扇出分区与高电压电源线扇出分区122Vdd和低电压电源线扇出分区122Vss位于不同的工艺层，且投影可以存在交叠，但是上述一个或多个扇出分区中的线路接入弯折区121时，通过跳线方式接入同一工艺层，即接入弯折区121中的所有线路位于同一层中。因此，本申请实施例在弯折区121中同样采用对数据线分区弯折的方式， 并尽量在至少两个数据线弯折区的间隔区内设置其它线路的弯折区，以合理规划弯折区121内的布线空间。
图9为本申请实施例提供的又一种显示面板的结构示意图。在图7所示显示面板100的结构基础上，本申请实施例提供的显示面板100中，弯折区121的数据线弯折区可以划分为三部分，例如包括：位于显示区110中心区正下方的中心数据线弯折区121C，以及分别位于显示区110左区正下方的左区数据线弯折区121L和位于显示区110右区正下方的右区数据线弯折区121R。其中，显示区110左区为所述显示区110中靠近所述显示面板100第一侧的区域(图9中的左侧)，显示区110右区为靠近所述显示面板100第二侧的区域(图9中的右侧)，所述显示区110中心区为所述显示区110左区和显示区110右区之间的区域，所述第一侧、第二侧为相对的两侧，且与所述数据数据线扇出分区所在的第三侧相邻。
在本申请实施例中，将弯折区121分成了三段，图9以非均匀配置的上述三个数据线弯折区为例予以示出，相应地，由于第一扇出区122中数据线扇出分区的分段方式与上述数据线弯折区(121C、121L和121R)一一对应，该数据线扇出分区可以包括：设置为将显示区110中心区内的数据线连接至中心数据线弯折区121C的中心数据线扇出分区122C，设置为将显示区110左区内数据线连接至左区数据线弯折区121L的左区数据线扇出分区122L，以及设置为将显示区110右区内的数据线连接至右区数据线弯折区121R的右区数据线扇出分区122R。
在本申请实施例中，数据线扇出分区与数据线弯折区的分段及对应的方式例如为：假设显示区110的数据线总数为a个，其左区和右区的数据线分别为r个，其中心区的数据线则为a-2r个，其中，中心区的数据线为显示区110数量最大的一部分数据线分区，该部分的a-2r个数据线通过与显示区110中心区相连接的中心数据线扇出分区122C连接至中心数据线弯折区121C，显示区110的左区和右区数据线相等、且为对称分布的，左区的r个数据线通过与显示区110左区相连接的左区数据线扇出分区122L连接至左区数据线弯折区121L，右区的r个数据线通过与显示区110右区相连接的右区数据线扇出分区122R连接至右区数据线弯折区121R。本申请实施例中，中心区 数据线a-2r占数据线总数a的比值，可以由设计人员根据显示区110的大小和形状，以及显示面板100的设计规格进行合理配置。
在本申请实施例中，高电压电源线弯折区121Vdd可以位于左区数据线弯折区121L与中心数据线弯折区121C之间，低电压电源线弯折区121Vss可以位于右区数据线弯折区121R与中心数据线弯折区121C之间。
本申请实施例中，第一扇出区122中还可以包括有将显示区110中信号线连接至弯折区121中的其它导线，例如包括，高电压电源线Vdd和低电压电源线Vss，以及时钟信号线Clk等，因此，可以将高电压电源线Vdd或低电压电源线Vss设置于相邻的数据线扇出分区之间，即采用高电压电源线Vdd和低电压电源线Vss作为数据线分段扇出的间隔；相应的，弯折区121中可以将设置为接入高电压电源线Vdd的高电压电源线弯折区121Vdd和设置为接入低电压电源线Vss的低电压电源线弯折区121Vss作为相邻数据线弯折区的间隔。本申请实施例中采用显示面板100中的部分结构作为分段扇出和数据线弯折区的间隔，使得显示面板100内部的结构合理规划和利用，无需增加新的结构。
为了实现显示区110均匀发光，显示面板100通常采用双侧驱动的方式，即显示区110的左侧和右侧均可以配置有对称设置的高电压电源线Vdd和对称设置的低电压电源线Vss，相应地，弯折区121中的低电压电源线弯折区121Vss可以包括以显示区110的中线对称设置的第一低电压电源线弯折区121Vss1和第二低电压电源线弯折区121Vss2，高电压电源线弯折区121Vdd同样可以包括以显示区110的中线对称设置的第一高电压电源线弯折区121Vdd1和第二高电压电源线弯折区121Vdd2。
上述图7到图9中并未示意出对称设置的Vdd和Vss，在实际应用中，可以将图7到图9的弯折区121中的高电压电源线弯折区121Vdd和低电压电源线弯折区121Vss配置为对称设置的，并基于图7到图9的弯折区121中数据线弯折区的数量和位置可以合理配置分段间隔的方式。
另外，对于如图7到图9中非对称设置的Vdd和Vss，可以采用电阻补偿的方式实现显示区110中发光单元的均匀发光。
在本申请实施例的一种可能的实现方式中，如图10所示，为本申请实施 例提供的再一种显示面板的结构示意图。图10以在图9所示结构的基础上为例予以示出，即图10中同样包括三个数据线弯折区(即121C、121L和121R)，在图10所示显示面板100的弯折区121中，第一低电压电源线弯折区121Vss1和第一高电压电源线弯折区121Vdd1位于左区数据线弯折区121L与中心数据线弯折区之间121C，第二低电压电源线弯折区121Vss2和第二高电压电源线弯折区121Vdd2位于右区数据线弯折区121R与中心数据线弯折区121C之间，弯折区121中分段数据线的间隔方式如图10所示。
在本申请实施例的另一种可能的实现方式中，弯折区121中划分出五个数据线弯折区，如图11所示，为本申请实施例提供的再一种显示面板的结构示意图。图11以在图10所示结构的基础上为例予以示出，中心数据线弯折区121C与图10中相同，左区数据线弯折区121L包括第一数据线弯折区1211和第二数据线弯折区1212，右区数据线弯折区121L包括第三数据线弯折区1213和第四数据线弯折区1214。
针对图11中划分出的五个数据线弯折区，第一扇出区122同样具有一一对应的五个数据线扇出分区，且相对应的一对数据线扇出分区和数据线弯折区中的数据线的数量相同且一一对应。另外，基于显示区110中配置有对称设置的高电压电源线Vdd和对称设置的低电压电源线Vss，弯折区121中设置有设置为接入上述高电压电源线和低电压电源线的四个弯折区(即121Vss1、121Vdd1、121Vdd2和121Vss2)。基于上述结构，五个数据线扇出分区中任意相邻两个分区中间可以设置有高电压电源线Vdd或低电压电源线Vss，即弯折区121的结构可以为，从左到右依次排布有：第一数据线弯折区1211、第一低电压电源线弯折区121Vss1、第二数据线弯折区1212、第一高电压电源线弯折区121Vdd1、中心数据线弯折区121C、第二高电压电源线弯折区121Vdd2、第三分据线弯折区1213、第二低电压电源线弯折区121Vss2和第四分据线弯折区1214。另外，图11所示显示面板100的第一扇出区121中，从左到右依次排布有：与上述第一数据线弯折区1211、第二数据线弯折区1212、第三分据线弯折区1213和第四分据线弯折区1214一一对应的第一数据线扇出分区1221、第二数据线扇出分区1222、第三数据线扇出分区1223和第四数据线扇出分区1224。
在实际应用中，为了显示屏的美观或者用户需求等，显示面板的显示区110通常制作为四个角为圆弧形倒角的形状，图2到图11所示显示面板100并未示意出圆弧形倒角，但可以理解的，在显示区的下方的左右两个顶角，可以为圆弧形倒角的形状，包括左侧顶角的区域称为左侧倒角区域(或称第一倒角区域)，包括右侧顶角的区域称为右侧倒角区域(或称第二倒角区域)，且可以理解的，左侧倒角区域和右侧倒角区域中纵向分布有少数的数据线，可以将这些区域内的数据线通过对应的左区数据线扇出分区122L和右区数据线扇出分区122R连接至相对应的数据线弯折区，参考图9到图11中的分段扇出的方式。
基于图9到图11所示的显示面板100中数据线分段扇出和弯折区中分区的方式，连接至左区数据线弯折区121L的左区数据线扇出分区122L中数据线的数量等于显示区110的左侧倒角区域的数据线数量，连接至右区数据线弯折区121R的右区数据线扇出分区122R中数据线的数量等于显示区110的右侧倒角区域的数据线数量。举例来说，如图9和图10所示结构，左侧倒角区域、右侧倒角区域以及相对应的左区数据线弯折区121L、右区数据线弯折区121R中数据线数量均为r，中心数据线弯折区121C的数据线数量为a，数据线的整体数据量为a+2r；再举例来说，如图11所示结构，左侧倒角区域和右侧倒角区域的数据线数量均为r，左侧倒角区域的数据线分段连接至第一数据线弯折区1211和第二数据线弯折区1212，右侧倒角区域的数据线分段连接至第三数据线弯折区1213和第四数据线弯折区1214，即上述1211、1212、1213和1214中数据线数量均为r/2，中心数据线弯折区121C的数据线数量为a，数据线的整体数据量同样为a+2r。
针对上述具有倒角的显示区110的显示面板100，由于倒角区域内发光像素的形状和面积与显示区110的中心区有差别，且上述两个区域(左侧倒角区域和右侧倒角区域)中的数据线分别通过相对应的左区数据线弯折区121L和右区数据线弯折区121R与驱动IC相连接，因此，可以采用驱动IC对上述左侧倒角区域和右侧倒角区域中的数据线进行亮度均一性补偿，以保证显示面板100的显示亮度具有较好的均匀性。
图12为本申请实施例提供的再一种显示面板的结构示意图。图12以在 上述图7到图11所示显示面板100的结构基础上为例予以示出，且图12中未示意出弯折区121和第一扇出区122的结构，仅以区域标识示意性表示出上述弯折区121和第一扇出区122。本申请实施例提供的显示面板100的非显示区120还可以包括：通过弯折区121弯折到显示面板100的非显示区120的第二扇出区123，所述多条数据线延伸到所述第二扇出区123。
本申请实施例中的第二扇出区123设置为对弯折区121中的数据线进行再次扇出，第二扇出区123中包括电阻补偿模块1231，所述电阻补偿模块1231设置为对连接至第一扇出区122的数据线进行电阻补偿，以使得数据线的阻抗呈渐进式变化。另外，本申请实施例中的非显示区120还可以包括与第二扇出区123相连接的单元测试区(Cell Test)124，以及与该单元测试区124相连接的驱动IC125，本申请实施例中所有数据线和其它导线均连接至该驱动IC125中。
参考图1及图7到图11所示，图1示意出了显示面板中一种数据线扇出的结构，图7到图11示意出了本申请实施例提供的显示面板中一种数据线扇出的结构。可以看出，由于图1所示显示面板20中，显示区21下方引出的大量分散的数据线22a连接至集中的数据线弯折区23a，且数据线扇出区22和数据线弯折区23a中没有分段，因此，相邻数据线22a的阻抗是连续且呈渐进式变化的。图11所示本申请实施例提供的显示面板100中，数据线进行分段扇出，即第一扇出区122和弯折区121中的数据线都具有至少两个分区，如图7到图11所示的结构。以图11所示结构为例予以示出，连接至同一个数据线弯折区中的数据线的长短是渐进式变化的，其阻抗也是渐进式变化的，由于分段扇出和弯折区中分区的结构，连接至相邻数据线弯折区中相邻的两个数据线的阻抗存在一个突变。举例来说，第一数据线弯折区1211、第二数据线弯折区1212、第三数据线弯折区1213和第四数据线弯折区1214中都连接有100根数据线，且数据线为连续编号的，第一数据线弯折区1211中的第100根与第二数据线弯折区1212中的第101根数据线之间的阻抗存在突变，对上述多个数据线弯折区中的数据线进行二次扇出，且在该第二扇出区123做等电阻补偿设计，以使得所有数据线的阻抗呈渐进式变化。
显示面板100中，显示区110和驱动IC的规格固定，对数据线进行分段 扇出的结构，使得从第一扇出区122到第二扇出区123这部分的整体宽度W变大，第一扇出区122布线占用空间变小(即122的宽度W1变小)。虽然弯折区121下方与驱动IC125连接的第二扇出区123布线整体空间变大，但是这部分布线最终通过弯折区121弯折到显示区110的背后，不影响显示面板100下边框的宽度，即本申请实施例提供的显示面板100，通过对数据线采用分段扇出和弯折区中分区的结构，可以有效的缩小下边框以实现窄下边框的目标，在一示例性实施例中，大约可以将弯折后的下边框由2.0毫米(mm)缩小至1.5mm，提高了显示面板100的屏占比。
在一示例性实施例中，所述显示面板100包括柔性显示面板。
基于本申请上述实施例提供的显示面板100，本申请实施例还提供一种显示装置，该显示装置中包括如上述图2到图12所示任一实施例中的显示面板100。基于上述实施例提供的显示面板100的技术效果，本申请实施例提供的显示装置同样具有窄下边框的结构，且具有较高的屏占比。
虽然本申请所揭露的实施方式如上，但所述的内容仅为便于理解本申请而采用的实施方式，并非用以限定本申请。任何本申请所属领域内的技术人员，在不脱离本申请所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (12)

  1. 一种显示面板，包括：显示区和至少位于所述显示区一侧的非显示区，所述非显示区包括第一扇出区；
    多个子像素，位于所述显示区；
    多条数据线，位于所述显示区且从所述显示区延伸到所述第一扇出区，所述多条数据线与所述多个子像素电连接，被配置为为所述多个子像素提供数据信号；
    所述第一扇出区包括：至少两个数据线扇出分区，所述多条数据线分别延伸到所述至少两个数据线扇出分区中。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：高电压电源线和低电压电源线；
    所述高电压电源线，位于所述非显示区，且至少部分所述高电压电源线位于所述第一扇出区，所述高电压电源线被配置为为所述多个子像素传输高电压信号，所述高电压电源线包括至少两个高电压电源线引脚；
    所述低电压电源线，位于所述非显示区且围绕所述显示区，被配置为为所述多个子像素传输低电压信号，所述低电压电源线包括至少两个低电压电源线引脚；
    所述至少两个高电压电源线引脚和所述至少两个低电压电源线引脚中的至少一个位于所述至少两个数据线扇出分区之间。
  3. 根据权利要求2所述的显示面板，其中，所述至少两个数据线扇出分区的数量为两个，所述至少两个高电压电源线引脚的数量为两个，所述至少两个低电压电源线引脚数量为两个，所述两个高电压电源线引脚和所述两个低电压电源线引脚全部位于所述两个数据线扇出分区之间。
  4. 根据权利要求2所述的显示面板，其中，所述至少两个数据线扇出分区的数量为三个，每两个所述数据线扇出分区之间设置有所述至少两个高电压电源线引脚和所述至少两个低电压电源线引脚中的至少一个。
  5. 根据权利要求4所述的显示面板，其中，所述至少两个高电压电源线 引脚的数量为两个，所述至少两个低电压电源线引脚的数量为两个，所述至少两个数据线扇出分区的数量为三个，所述两个高电压电源线引脚分别位于所述三个数据线扇出分区之间，所述两个低电压电源线引脚分别位于所述三个数据线扇出分区之间。
  6. 根据权利要求2所述的显示面板，其中，所述至少两个高电压电源线引脚的数量为两个，所述至少两个低电压电源线引脚的数量为两个，所述至少两个数据线扇出分区的数量为五个，所述两个高电压电源线引脚和所述两个低电压电源线引脚分别位于所述五个数据线扇出分区之间。
  7. 根据权利要求6所述的显示面板，其中，所述五个数据线扇出分区中的每两个之间设置有所述两个高电压电源线引脚和所述两个低电压电源线引脚中的一个。
  8. 根据权利要求2或7所述的显示面板，其中，所述两个高电压电源线引脚相对于所述显示面板的中线对称设置，所述两个低电压电源线引脚相对于所述显示面板的中线对称设置。
  9. 根据权利要求1至7任一所述的显示面板，其中，所述至少两个数据线扇出分区中最外侧的两个数据线扇出分区中的数据线数量一致。
  10. 根据权利要求1至7任一所述的显示面板，其中，所述显示面板还包括弯折区，所述弯折区位于所述第一扇出区远离所述显示区的一侧，所述多条数据线延伸到所述弯折区，所述弯折区被配置为弯折到所述显示面板的背面。
  11. 根据权利要求10所述的显示面板，还包括，第二扇出区，所述第二扇出区位于所述弯折区远离所述显示区的一侧，所述多条数据线延伸到所述第二扇出区；
    所述第二扇出区中包括电阻补偿模块，所述电阻补偿模块被配置为对所述多条数据线进行电阻补偿，以使得所述数据线的阻抗呈渐进式变化。
  12. 一种显示装置，包括：如权利要求1～11中任一项所述的显示面板。
PCT/CN2020/074865 2019-03-28 2020-02-12 一种显示面板和显示装置 WO2020192284A1 (zh)

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