WO2020186699A1 - 场效应晶体管及其制备方法 - Google Patents

场效应晶体管及其制备方法 Download PDF

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WO2020186699A1
WO2020186699A1 PCT/CN2019/103910 CN2019103910W WO2020186699A1 WO 2020186699 A1 WO2020186699 A1 WO 2020186699A1 CN 2019103910 W CN2019103910 W CN 2019103910W WO 2020186699 A1 WO2020186699 A1 WO 2020186699A1
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type material
gallium oxide
material layer
oxide substrate
layer
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French (fr)
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于洪宇
曾凡明
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Southern University of Science and Technology
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Southern University of Science and Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices

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  • the embodiments of the present application relate to semiconductor technology, for example, to a field effect transistor and a manufacturing method thereof.
  • Gallium oxide is a wide band gap semiconductor material.
  • the band gap of ⁇ -Ga 2 O 3 is about 4.85 eV.
  • Its critical breakdown electric field is as high as 8 MV/cm.
  • Gallium oxide has better high voltage resistance characteristics than third-generation semiconductor materials such as silicon carbide.
  • BFOM Baliga's figure merit
  • gallium oxide materials Due to the deep acceptor energy level of gallium oxide and the hole self-binding effect, it is difficult to realize effective p-type doping materials, which in turn leads to the high technical difficulties and difficulties associated with the use of gallium oxide materials to prepare semiconductor devices in related technologies.
  • the problem of high cost This largely limits the use of gallium oxide materials to fabricate field effect transistors, that is, it is impossible to use gallium oxide materials to fabricate high-performance field effect transistors.
  • the present application provides a field effect transistor and a preparation method thereof, so as to realize a high performance field effect transistor by using gallium oxide material.
  • an embodiment of the present application provides a field effect transistor.
  • the field effect transistor includes: a gallium oxide substrate; a p-type material layer and a passivation layer on the gallium oxide substrate; The drain electrode and the source electrode on both sides of the p-type material layer; the gate electrode on the p-type material layer.
  • the drain electrode and the source electrode form an ohmic contact structure with the gallium oxide substrate;
  • the passivation layer covers the p-type material layer and the gallium oxide substrate, and
  • a plurality of openings are provided on the passivation layer, and the plurality of openings respectively expose the drain electrode, the source electrode and the gate electrode.
  • the gallium oxide substrate further includes an epitaxial layer; the p-type material layer and the passivation layer are located on the epitaxial layer of the gallium oxide substrate; the drain electrode and the source electrode An ohmic contact structure is formed with the gallium oxide substrate; the passivation layer covers the p-type material layer and the gallium oxide substrate, and the passivation layer is provided with a plurality of openings, the plurality of openings The drain electrode, source electrode and gate electrode are respectively exposed.
  • the thickness of the p-type material layer ranges from 20 nanometers to 500 nanometers.
  • the gallium oxide substrate is an ⁇ -Ga 2 O 3 substrate, a ⁇ -Ga 2 O 3 substrate, a ⁇ -Ga 2 O 3 substrate, a ⁇ -Ga 2 O 3 substrate or an ⁇ -Ga 2 O 3 substrate. -Ga 2 O 3 substrate.
  • an embodiment of the present application also provides a method for manufacturing a field effect transistor, including: forming a p-type material layer and a gate electrode on a gallium oxide substrate, the gate electrode being located in the p-type material layer On; forming a passivation layer on the gallium oxide substrate and the p-type material layer, the passivation layer exposing the gate electrode; forming source electrodes and on both sides of the p-type material layer The drain electrode, and the passivation layer exposes the source electrode and the drain electrode.
  • the gallium oxide substrate further includes an epitaxial layer; forming a p-type material layer on the gallium oxide substrate includes: forming a p-type material layer on the epitaxial layer.
  • forming a p-type material layer and a gate electrode on a gallium oxide substrate includes: growing a p-type material film on the gallium oxide substrate; forming a mask on the p-type material film The area of the mask is smaller than the area of the p-type material film; the part of the p-type material film that is not covered by the mask is etched to form the p-type material layer; the mask is removed , And forming the gate electrode on the p-type material layer.
  • forming a source electrode and a drain electrode on both sides of the p-type material layer, and exposing the source electrode and the drain electrode by the passivation layer includes: removing the first predetermined area and the second The passivation layer in the preset area exposes the gallium oxide substrate; the source electrode and the drain electrode are respectively fabricated on the exposed gallium oxide substrate.
  • FIG. 1 is a schematic structural diagram of a field effect transistor provided by an embodiment of the application
  • FIG. 2 is a schematic structural diagram of another field effect transistor provided by an embodiment of the application.
  • FIG. 3 is a flowchart of a method for manufacturing a field effect transistor according to an embodiment of the application
  • 4-6 are schematic diagrams of the structure of the film layer formed by the method for preparing the field effect transistor provided by the embodiment of the application.
  • FIG. 1 is a schematic structural diagram of a field effect transistor provided by an embodiment of the application.
  • the field effect transistor includes: a gallium oxide substrate 11; a p-type material layer 102 and a passivation layer on the gallium oxide substrate 11 104; the source electrode 105 and the drain electrode 106 on both sides of the p-type material layer 102; the gate electrode 103 on the p-type material layer 102.
  • the intrinsic gallium oxide crystal will show the characteristics of an n-type semiconductor.
  • the conduction band of the gallium oxide substrate 11 in contact with the p-type material layer 102 is pulled up, causing partial depletion of electrons, thereby forming a normally-off device.
  • the p-type material layer 102 can be formed by growth or the like, that is, the p-type material layer 102 is directly grown on the gallium oxide substrate 11, compared to using gallium oxide material to form a p-type semiconductor material, the structure of the p-type material layer 102 is formed It has lower technical difficulty and cost, thereby greatly reducing the difficulty and cost of using gallium oxide materials to form P-type materials to further form field effect transistors.
  • a gate electrode 103 is provided on the p-type material layer 102, and the p-type material layer
  • the source electrode 105 and the drain electrode 106 are provided on both sides of 102 to form an enhanced junction field effect transistor.
  • the difference between the source electrode 105 and the drain electrode 106 can be controlled. Turn on or off indirectly to form a high-performance field effect transistor. It is understandable that since the gallium oxide substrate is a surface current type material, the passivation layer 104 is provided to cover the gallium oxide substrate 11 and the p-type material layer 102 to insulate and protect the field effect transistor.
  • the technical solution of this embodiment adopts a field effect transistor including a gallium oxide substrate, a p-type material layer, a passivation layer, a source electrode, a drain electrode, and a gate electrode, because the gallium oxide substrate and the p-type material layer
  • the p-type material layer can deplete the electrons at its bottom to form a normally-off device, thereby avoiding the use of gallium oxide materials in the related technology to make semiconductor devices because it is difficult to achieve p-type doping
  • the field effect transistors produced can be applied to a variety of special fields, such as high-voltage power electronics, which expands the application range of field effect transistors. .
  • the drain electrode 105 and the source electrode 106 respectively form an ohmic contact structure with the gallium oxide substrate 11;
  • the passivation layer 104 covers the p-type material layer 102 and the gallium oxide substrate 11, on the passivation layer 104 A plurality of openings are provided, and the plurality of openings respectively expose the drain electrode 105, the source electrode 106 and the gate electrode 103.
  • FIG. 2 is a schematic structural diagram of another field effect transistor provided by an embodiment of the application.
  • the gallium oxide substrate 11 further includes an epitaxial layer 201; a p-type material layer 102 and a passivation layer 104 Located on the epitaxial layer 201 of the gallium oxide substrate 11; the drain electrode 105 and the source electrode 106 respectively form an ohmic contact structure with the gallium oxide substrate 11; the passivation layer 104 covers the p-type material layer 102 and the gallium oxide substrate 11 A plurality of openings are provided on the passivation layer 104, and the plurality of openings respectively expose the drain electrode 105, the source electrode 106 and the gate electrode 103.
  • the gallium oxide substrate 11 includes a substrate 101 and an epitaxial layer 201, and the p-type material layer 102 depletes electrons in the heterojunction channel formed by the p-type material layer 102 and the epitaxial layer 201, thereby forming a normally closed Type device, by providing the source electrode 105 and the drain electrode 106 on the epitaxial layer 201, a junction field effect transistor can be formed. By controlling the potential of the gate electrode 103, the source electrode 105 and the drain electrode 106 can be controlled. Turn on or off in time.
  • the heterojunction channel is formed in the epitaxial layer 201, which can further improve the performance of the field effect transistor.
  • the heterojunction channel can be formed in the epitaxial layer, which can improve the performance of the field effect transistor.
  • the gate electrode 103, the source electrode 105, and the drain electrode 106 may each include a field plate structure to increase the breakdown voltage of the field effect transistor and enhance the stability of the field effect transistor.
  • the gallium oxide substrate is an ⁇ -Ga 2 O 3 substrate, a ⁇ -Ga 2 O 3 substrate, a ⁇ -Ga 2 O 3 substrate, a ⁇ -Ga 2 O 3 substrate or an ⁇ -Ga 2 O 3 substrate.
  • it may be an ⁇ -Ga 2 O 3 substrate.
  • the substrate 101 when the gallium oxide substrate 11 includes an epitaxial layer, the substrate 101 can be an ⁇ -Ga 2 O 3 substrate, a ⁇ -Ga 2 O 3 substrate, a ⁇ -Ga 2 O 3 substrate, or a ⁇ -Ga 2 O 3 substrate or ⁇ -Ga 2 O 3 substrate, the commercial gallium oxide substrate 11 in the related art includes a modulated doped (Al x Ga 1-x ) 2 O 3 epitaxial layer 201, where if the composition of x If the content of Al 2 O 3 is too high, the crystal type of the material will change. For example, if the content of Al 2 O 3 is too high, the hexagonal crystal structure of sapphire will be produced. When the content of Al 2 O 3 is low, it will be a monoclinic crystal structure. It is 1%-80%.
  • the thickness of the p-type material layer 102 ranges from 20 nanometers to 500 nanometers. For example, it can be 100 nanometers. If the p-type material layer 102 is too thin, it cannot provide effective holes, and if the p-type material layer 102 is too thick, it will introduce more material defects, increase the body resistance and capacitance, and affect the performance of the field effect transistor. .
  • the specific material of the field effect transistor and the thickness of each film layer are set to facilitate the preparation of a field effect transistor with better performance.
  • FIG. 3 is a flow chart of a method for manufacturing a field effect transistor according to an embodiment of the application.
  • the method for manufacturing a field effect transistor includes step 501 to step 503.
  • a p-type material layer and a gate electrode are formed on a gallium oxide substrate, and the gate electrode is located on the p-type material layer.
  • the gallium oxide substrate further includes an epitaxial layer; forming a p-type material layer on the gallium oxide substrate includes: forming a p-type material layer on the gallium oxide epitaxial layer.
  • FIGS. 4-6 are schematic diagrams of the structure of the film formed by the method for preparing the field effect transistor provided by the embodiment of the application.
  • a layer of p-type material is first grown on the gallium oxide substrate 11
  • the film 301 can be grown in metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE) or Atom Layer Deposition (ALD).
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • HVPE hydride vapor phase epitaxy
  • ALD Atom Layer Deposition
  • p-type aluminum indium gallium nitride (such as p-type gallium nitride) is grown on the epitaxial layer 201 by molecular beam epitaxy.
  • the nitrogen source is a nitrogen radio frequency nitrogen plasma source
  • solid gallium is used as a gallium source
  • solid magnesium is used as a magnesium source.
  • the reaction source and carrier gas used for growth mainly include: trimethylgallium (TMGa), trimethylaluminum (TMAl), trimethylindium (TMIn) ), NH 3 , Cp 2 Mg, H 2 , N 2, etc.; the growth temperature of the material is between 900° C. -1100° C.
  • TMGa trimethylgallium
  • TMAl trimethylaluminum
  • TMIn trimethylindium
  • NH 3 NH 3
  • Magnesium provides p-type dopants, that is, magnesium element. It is understandable that the above-mentioned p-type material layer 301 is based on p-type aluminum indium gallium nitride as an example.
  • p-type material layer 301 uses p-type silicon carbide
  • hot wall CVD or low pressure chemical vapor deposition can be used.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • a mask 401 is formed on the p-type material film 301.
  • the area of the mask 401 is smaller than that of the p-type material film 301, so that the mask 401 is used to etch away
  • the p-type material film 301 outside the mask 401 forms the p-type material layer 102.
  • a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) method can be used to grow 200nm thick silicon oxide as a hard mask on the surface of the p-type material film 301.
  • the surface of 301 is coated with photoresist, and the grid pattern on the photoresist is transferred to the surface photoresist of p-type material film 301 by photolithography.
  • the image on the photoresist is transferred to the silicon oxide hard mask by dry etching. Then, dry etching is used to remove the part of the p-type material film 301 that is not covered by the mask 401, thereby forming the p-type material layer 102.
  • the mask 401 is cleaned off.
  • the photoresist can be commonly used S1818, Ruihong 304, AZ5314 and other photoresists
  • the hard mask can be made of silicon oxide, silicon nitride, metal nickel and other materials
  • the growth of the hard mask can be made by plasma enhanced vapor chemical deposition , Electron beam evaporation, magnetron sputtering, etc.
  • dry etching can be achieved by inductively coupled ion etching machine, reactive ion etching machine, etc.
  • a passivation layer is formed on the gallium oxide substrate and the p-type material layer, and the passivation layer exposes the gate electrode.
  • a silicon nitride passivation layer can be deposited on the surface of the p-type material layer and the gallium oxide substrate by vapor deposition, the thickness of the silicon nitride ranges from 100 nm to 200 nm; the material of the passivation layer It can also be silicon oxide, aluminum oxide or aluminum nitride.
  • a source electrode and a drain electrode are formed on both sides of the p-type material layer, and the source electrode and the drain electrode are exposed by the passivation layer.
  • the passivation layer in the first predetermined area and the second predetermined area is first removed to expose the gallium oxide substrate.
  • the method of removing the passivation layer may be photolithography combined with wet etching or The method of dry etching, and then using photolithography and metal evaporation methods on the exposed gallium oxide substrate, the source electrode and the drain electrode are fabricated.
  • the material of the source electrode and the drain electrode may be one of Ni, Ti, Al, Au, TiN, W, Pt, Pd, Mo and ITO, or a laminated structure composed of multiple. Evaporation methods include magnetron sputtering, electron beam evaporation, chemical plating and other programs.
  • the first way is to coat photoresist on the wafer first, remove the photoresist by photolithography exposure at the positions where the source and drain electrodes need to be made, and continue evaporation The metal, and then remove the photoresist, so that only the source and drain positions have electrodes, and the metal in other positions is removed along with the photoresist.
  • the second method is to evaporate the metal first, then coat the photoresist on the wafer, and leave the photoresist in the position where the source and drain electrodes need to be made by photolithography exposure, and then dry etching Or the etching method removes the metal at the locations not covered by the photoresist, leaving the metal at the locations covered by the photoresist as the source and drain metals.
  • the source and drain metals are thermally annealed using high-temperature rapid annealing equipment, so that the source and drain metals form ohmic contact structures with the gallium oxide substrate respectively.
  • the annealing temperature is generally 500 degrees to 900 degrees, and the annealing environment can be nitrogen or other gas environments.
  • a part of the gallium oxide epitaxial layer 201 can be removed by dry etching, and the source electrode and the drain electrode are made in the groove structure to improve the field
  • the electrical characteristics of effect transistors enhance the performance of field effect transistors.
  • the gate electrode can be fabricated after the passivation layer is fabricated.
  • the fabrication method is to first remove the passivation layer where the gate electrode needs to be fabricated, and fabricate the gate by photolithography and metal evaporation.
  • a Schottky contact structure is formed between the pole electrode, the gate electrode and the p-type material layer.
  • the material of the gate electrode can be selected from one of Ni, Ti, Al, Au, TiN, W, Pt, Pd, Mo and ITO, or a laminated structure composed of multiple.
  • the technical solution of this embodiment provides a method for preparing a field-effect transistor. Due to the difference in work function between the gallium oxide substrate and the p-type material layer, the p-type material layer can remove the electrons at the bottom of the field-effect transistor. Depleted to form a normally-off device, thereby avoiding the fact that gallium oxide materials in the related art are difficult to be used to fabricate semiconductor devices because it is difficult to achieve p-type doping. Because gallium oxide materials have excellent semiconductor characteristics, the production The field effect transistors can be applied to a variety of special fields, such as high-voltage power electronics, etc., which expands the application range of field effect transistors.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

一种场效应晶体管及其制备方法，所述场效应晶体管包括：氧化镓衬底（11）；位于所述氧化镓衬底（11）上的p型材料层（102）和钝化层（104）；位于所述p型材料层（102）两侧的漏极电极（106）和源极电极（105）；位于所述p型材料层（102）上的栅极电极（103）。因氧化镓衬底（11）与p型材料层（102）材料功函数的差别，p型材料层（102）可将其底部的电子耗尽，以形成常关型器件从而避免了相关技术中氧化镓材料由于很难实现p型掺杂而用于制作半导体器件时伴随的高技术难度和高成本的情况，且氧化镓材料具有优异的半导体特性，制作的半导体器件可适用于多种特殊的领域，如高压电力电子等，扩展了半导体器件的使用范围。

Description

场效应晶体管及其制备方法
本申请要求在2019年03月19日提交中国专利局、申请号为201910207646.X的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术，例如涉及一种场效应晶体管及其制备方法。
背景技术
氧化镓是一种宽禁带半导体材料，β-Ga 2O 3禁带宽度大约是4.85eV，其临界击穿电场高达8MV/cm，且n型掺杂可控，耐辐射，熔点高，非常适合于制作高压电力电子器件。其应用包括功率电子器件，射频电子器件，紫外探测器，气体传感器等，并在固态照明、通讯、消费电子产品，以及新能源汽车、智能电网等领域有广阔的应用前景。氧化镓具有比碳化硅等第三代半导体材料更优异的耐高压等特性，其Baliga优值(Baliga‘s figure merit，BFOM)比氮化镓高大约4倍，比碳化硅高9倍多，且同质衬底可以采用熔体方式加工，因此具有广阔的应用前景，切合国家节能减排、智能制造、通讯与信息安全的要求。
对氧化镓的研究，目前还处于起步阶段，尽管实验表明氧化镓器件的击穿电场测试值已经超过氮化镓和碳化硅的理论值，但是目前工艺条件下氧化镓器件电学特性相比于其他第三代半导体器件仍然有一定的差距。由于氧化镓受主能级较深，且存在空穴自束缚效应，因此很难实现有效的p型掺杂材料，进而导致相关技术中利用氧化镓材料制备半导体器件时所伴随的高技术难度和高成本的问题。这在很大程度上限制了利用氧化镓材料来制作场效应晶体管，即无法利用氧化镓材料制备高性能的场效应晶体管。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请提供一种场效应晶体管及其制备方法，以利用氧化镓材料实现高性能的场效应晶体管。
第一方面，本申请实施例提供了一种场效应晶体管，所述场效应晶体管包括：氧化镓衬底；位于所述氧化镓衬底上的p型材料层和钝化层；位于所述p型材料层两侧的漏极电极和源极电极；位于所述p型材料层上的栅极电极。
在一实施例中，所述漏极电极和源极电极与所述氧化镓衬底形成有欧姆接触结构；所述钝化层覆盖所述p型材料层及所述氧化镓衬底，所述钝化层上设置有多个开口，所述多个开口分别暴露出所述漏极电极、所述源极电极和所述栅极电极。
在一实施例中，所述氧化镓衬底还包括外延层；所述p型材料层和所述钝化层位于所述氧化镓衬底的外延层上；所述漏极电极和源极电极与所述氧化镓衬底形成有欧姆接触结构； 所述钝化层覆盖所述p型材料层及所述氧化镓衬底，所述钝化层上设置有多个开口，所述多个开口分别暴露出所述漏极电极、源极电极和栅极电极。
在一实施例中，所述p型材料层采用p型In xAl yGa zN单层结构、p型In xAl yGa zN多层交叠结构或p型碳化硅；其中，在所述p型In xAl yGa zN中，X+Y+Z＝1。
在一实施例中，所述p型材料层厚度范围为20纳米至500纳米。
在一实施例中，所述氧化镓衬底采用α-Ga 2O 3衬底，β-Ga 2O 3衬底，γ-Ga 2O 3衬底，δ-Ga 2O 3衬底或ε-Ga 2O 3衬底。
第二方面，本申请实施例还提供了一种场效应晶体管的制备方法，包括：在氧化镓衬底上形成p型材料层和栅极电极，所述栅极电极位于所述p型材料层上；在所述氧化镓衬底上和所述p型材料层上形成钝化层，所述钝化层暴露出所述栅极电极；在所述p型材料层两侧形成源极电极和漏极电极，所述钝化层暴露出源极电极和漏极电极。
在一实施例中，所述氧化镓衬底还包括外延层；在所述氧化镓衬底上形成p型材料层包括：在所述外延层上形成p型材料层。
在一实施例中，在氧化镓衬底上形成p型材料层和栅极电极，包括：在所述氧化镓衬底上生长一层p型材料膜；在所述p型材料膜上形成掩膜，所述掩膜的面积小于所述p型材料膜的面积；刻蚀掉所述p型材料膜未被所述掩膜覆盖的部分，形成所述p型材料层；去除所述掩膜，并在所述p型材料层上形成所述栅极电极。
在一实施例中，在所述p型材料层上两侧形成源极电极和漏极电极，所述钝化层暴露出源极电极和漏极电极包括：去除第一预设区域及第二预设区域内的钝化层，暴露出所述氧化镓衬底；在暴露出的所述氧化镓衬底上分别制作所述源极电极和所述漏极电极。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
图1为本申请实施例提供的一种场效应晶体管的结构示意图；
图2为本申请实施例提供的又一种场效应晶体管的结构示意图；
图3为本申请实施例提供的一种场效应晶体管的制备方法流程图；
图4-6为本申请实施例提供的对应场效应晶体管的制备方法形成的膜层的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的示例实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
参考图1，图1为本申请实施例提供的一种场效应晶体管的结构示意图，场效应晶体管包括：氧化镓衬底11；位于氧化镓衬底11上的p型材料层102和钝化层104；位于p型材料层102两侧的源极电极105和漏极电极106；位于p型材料层102上的栅极电极103。
在一实施例中，氧化镓晶体结构中，由于氧空位的存在，本征的氧化镓晶体即会表现出n型半导体的特性，然而由于氧化镓晶体很难实现p型掺杂，因此很难利用氧化镓材料实现同质结构的半导体器件。通过在氧化镓衬底11上设置一层p型材料层102，由于氧化镓衬底11中存在的多数载流子为电子，而p型材料层102中的多数载流子为空穴，p型材料层102与氧化镓衬底11接触后，与p型材料层102接触的氧化镓衬底11导带被拉升起来，导致电子局部耗尽，进而形成常关型器件。由于p型材料层102可通过生长等方式形成，也即直接在氧化镓衬底11上生长p型材料层102，相比利用氧化镓材料形成p型半导体材料，p型材料层102结构的形成具有更低的技术难度和成本，进而大大降低了利用氧化镓材料形成P型材料以进一步形成场效应晶体管的难度和成本，在p型材料层102上设置栅极电极103，在p型材料层102的两侧设置源极电极105和漏极电极106，即可构成增强型的结型场效应晶体管，通过栅极电极103上电位的高低，即可控制源极电极105与漏极电极106之间导通或关断，进而形成高性能的场效应晶体管。可以理解的是，由于氧化镓衬底属于表面电流型的材料，通过设置钝化层104覆盖氧化镓衬底11和p型材料层102，以起到绝缘以及保护场效应晶体管的作用。
本实施例的技术方案，通过采用包括氧化镓衬底、p型材料层、钝化层、源极电极、漏极电极以及栅极电极的场效应晶体管，因氧化镓衬底与p型材料层材料功函数的差别，p型材料层可将其底部的电子耗尽，以形成常关型器件，从而避免了相关技术中的氧化镓材料由于很难实现p型掺杂而用于制作半导体器件时伴随的高技术难度和高成本的情况，由于氧化镓材料具有优异的半导体特性，制作的场效应晶体管可适用于多种特殊的领域，如高压电力电子等，扩展了场效应晶体管的使用范围。
在一实施例中，漏极电极105和源极电极106分别与氧化镓衬底11形成有欧姆接触结构；钝化层104覆盖p型材料层102以及氧化镓衬底11，钝化层104上设置有多个开口，多个开口分别暴露出漏极电极105、源极电极106和栅极电极103。
通过将漏极电极105以及源极电极106分别与氧化镓衬底11之间形成欧姆接触结构，在欧姆接触结构上不产生明显的附加阻抗，而且不会使场效应晶体管内部的平衡载流子浓度发生显著的改变，进一步提高了半导体器件的性能。
在一实施例中，参考图2，图2为本申请实施例提供的又一种场效应晶体管的结构示意图，氧化镓衬底11还包括外延层201；p型材料层102和钝化层104位于氧化镓衬底11的外延层201上；漏极电极105和源极电极106分别与氧化镓衬底11形成有欧姆接触结构；钝化层104覆盖p型材料层102以及氧化镓衬底11，钝化层104上设置有多个开口，多个开口分别暴露出漏极电极105、源极电极106和栅极电极103。
在一实施例中，氧化镓衬底11包括衬底101和外延层201，p型材料层102耗尽p型材料层102与外延层201形成的异质结沟道内的电子，从而形成常关型器件，通过在外延层201上设置源极电极105和漏极电极106，即可构成结型场效应晶体管，通过控制栅极电极103的电位，从而控制源极电极105与漏极电极106之间导通或关断。异质结沟道形成于外延层 201内，可进一步改善场效应晶体管的性能。
本实施例的技术方案，通过采用包括外延层的场效应晶体管，异质结沟道可在外延层内形成，可改善场效应晶体管的性能。
在一实施例中，栅极电极103、源极电极105和漏极电极106均可包含场板结构，以提高场效应晶体管的击穿电压，增强场效应晶体管工作的稳定性。
示例性的，p型材料层102可采用p型In xAl yGa zN单层结构、p型In xAl yGa zN多层交叠结构或p型碳化硅；其中，在p型In xAl yGa zN中，X+Y+Z＝1。
氧化镓衬底采用α-Ga 2O 3衬底，β-Ga 2O 3衬底，γ-Ga 2O 3衬底，δ-Ga 2O 3衬底或ε-Ga 2O 3衬底。例如，可以为α-Ga 2O 3衬底。其中，当氧化镓衬底11包含外延层时，衬底101可采用α-Ga 2O 3衬底，β-Ga 2O 3衬底，γ-Ga 2O 3衬底，δ-Ga 2O 3衬底或ε-Ga 2O 3衬底，相关技术中的商用氧化镓衬底11包括调制掺杂的(Al xGa 1-x) 2O 3外延层201，其中，若x的组分过高会导致材料的晶体类型发生变化，例如若Al 2O 3含量过高，会产生蓝宝石的六方晶体结构，Al 2O 3含量较低时为单斜晶系结构，因此x的组分可以为1％-80％。
p型材料层102厚度范围为20纳米至500纳米。例如可以为100纳米。若p型材料层102过薄，则无法提供有效的空穴，而若p型材料层102过厚，则会引入更多的材料缺陷，增加体电阻和体电容，进而影响场效应晶体管的性能。
本实施例的技术方案，通过设置场效应晶体管的具体材料以及各膜层的厚度，以方便制备性能更为优良的场效应晶体管。
参考图3，图3为本申请实施例提供的一种场效应晶体管的制备方法流程图，场效应晶体管的制备方法包括步骤501至步骤503。
在步骤501中，在氧化镓衬底上形成p型材料层和栅极电极，栅极电极位于p型材料层上。
在一实施例中，氧化镓衬底还包括外延层；在氧化镓衬底上形成p型材料层包括：在氧化镓外延层上形成p型材料层。
在一实施例中，图4-6为本申请实施例提供的对应场效应晶体管的制备方法形成的膜层的结构示意图，参考图4，首先在氧化镓衬底11上生长一层p型材料膜301，生长的方式可为金属有机物化学气相沉积法(Metal Organic Chemical Vapor Deposition，MOCVD)、分子束外延法(Molecular Beam Epitaxy，MBE)、氢化物气相外延法(Hydride Vapor Phase Epitaxy，HVPE)或原子层外延法(Atom Layer Deposition，ALD)。示例性的，由于MBE生长温度较低，适合氧化镓等六方晶系亚稳态衬底生长，在外延层201上通过分子束外延法生长p型铝铟镓氮(如p型的氮化镓)制备p型材料层301的过程中，以镁元素作为p型材料层的掺杂元素，氮源采用氮气射频氮等离子体源，固态镓作为镓源，固态镁作为镁源，V/III比为1/1，生长室压力为1.1×10 -4mbar。若采用金属有机物化学气相沉淀(Metal Organic Chemical Vapor Deposition，MOCVD)，生长使用的反应源和载气主要有：三甲基镓(TMGa)，三甲基铝(TMAl)，三甲基铟(TMIn)，NH 3，二茂镁(Cp 2Mg)，H 2，N 2等；材料生长温度在900℃ -1100℃之间，二茂镁提供p型掺杂剂，即提供镁元素。可以理解的是，上述的p型材料层301是以p型的铝铟镓氮为例，若p型材料层301采用p型的碳化硅，可以采用热壁式CVD或低压力化学气相沉积法(Low Pressure Chemical Vapor Deposition，LPCVD)的方式生长p型的碳化硅，反应气体为纯硅烷和纯丙烷，载气为氢气，p型掺杂剂为三甲基铝。
参考图5和图6，p型材料膜301生长完成后，在p型材料膜301上形成掩膜401，掩膜401的面积小于p型材料膜301的面积，从而利用掩膜401刻蚀掉掩膜401外的p型材料膜301，以形成p型材料层102。
在一实施例中，可首先在p型材料膜301表面采用等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)的方法生长200nm厚的氧化硅作为硬掩膜，在p型材料膜301表面涂布光刻胶，并采用光刻方式将光刻板上栅极图形转移到p型材料膜301表面光刻胶上。通过干法刻蚀的方法将光刻胶上的图像再转移到氧化硅硬掩膜上。再利用干法刻蚀的方法，去除掉p型材料膜301未被掩膜401覆盖的部分，从而形成p型材料层102。P型材料层制作完成后，清洗掉掩膜401。其中，光刻胶可以采用常用的S1818，瑞红304，AZ5314等光刻胶；硬掩膜可以采用氧化硅，氮化硅，金属镍等材料；硬掩膜的生长可以采用等离子增强气相化学沉积，电子束蒸发，磁控溅射等方式形成；干法刻蚀可以采用感应耦合离子刻蚀机，反应离子刻蚀机等方式实现。
在步骤502中，在氧化镓衬底和p型材料层上形成钝化层，钝化层暴露出栅极电极。
在一实施例中，可通过气相沉积的方法，在p型材料层以及氧化镓衬底表面沉积一层氮化硅钝化层，氮化硅的厚度范围为100nm至200nm；钝化层的材料也可选择为氧化硅、氧化铝或氮化铝。
在步骤503中，在p型材料层两侧形成源极电极和漏极电极，钝化层暴露出源极电极和漏极电极。
在一实施例中，首先去除在第一预设区域及第二预设区域内的钝化层，以暴露出氧化镓衬底，去除钝化层的方法可为光刻技术结合湿法腐蚀或干法刻蚀的方法，然后在暴露出的氧化镓衬底上利用光刻和金属蒸镀的方法，制作源极电极和漏极电极。源极电极和漏极电极的材料可为Ni，Ti，Al，Au，TiN，W，Pt，Pd，Mo和ITO中的一种，或多种组成的叠层结构。蒸镀方式包括磁控溅射，电子束蒸发，化学电镀等方案。金属的去除可以采用两种方式：第一种方式是先在晶圆上涂布光刻胶，在需要制作源极和漏极的位置通过光刻曝光的方式将光刻胶去掉，继续蒸镀金属，然后去掉光刻胶，这样只有源极和漏极的位置存在电极，其他位置的金属随着光刻胶一起被去除。第二种方式是先蒸镀金属，然后在晶圆上涂布光刻胶，在需要制作源极和漏极的位置通过光刻曝光的方式将光刻胶留下，在通过干法刻蚀或腐蚀的方法将没有光刻胶覆盖的位置的金属去掉，留下光刻胶覆盖位置的金属作为源极和漏极金属。接着利用高温快速退火设备对源极和漏极金属进行热退火，以使源极和漏极金属分别与氧化镓衬底形成欧姆接触结构。其中，退火温度一般为500度至900度，退火环境可采用氮气或其它气体环境。最后制备成如图2中所示的场效应晶体管的结构。
可以理解的是，在制作源极电极和漏极电极之前，可通过干法刻蚀的方法，去除掉一部分氧化镓外延层201，在槽结构内制作源极电极和漏极电极，来改善场效应晶体管的电学特性，增强场效应晶体管的性能。
需要说明的是，栅极电极可制作完钝化层之后再制作，其制作方法是先将需要制作栅极电极位置的钝化层去除，并通过光刻和金属蒸镀的方法，制作出栅极电极，栅极电极与p型材料层之间形成肖特基接触结构。栅极电极的材料可选Ni，Ti，Al，Au，TiN，W，Pt，Pd，Mo和ITO中的一种，或多种组成的叠层结构。
本实施例的技术方案，通过提供一种场效应晶体管的制备方法，所制备的场效应晶体管因氧化镓衬底与p型材料层材料功函数的差别，p型材料层可将其底部的电子耗尽，以形成常关型器件，从而避免了相关技术中的氧化镓材料由于很难实现p型掺杂而很难用于制作半导体器件的情况，由于氧化镓材料具有优异的半导体特性，制作的场效应晶体管可适用于多种特殊的领域，如高压电力电子等，扩展了场效应晶体管的使用范围。

Claims (10)

  1. 一种场效应晶体管，包括：
    氧化镓衬底；
    位于所述氧化镓衬底上的p型材料层和钝化层；
    位于所述p型材料层第一侧的漏极电极和位于所述p型材料层第二侧的源极电极；
    位于所述p型材料层上的栅极电极。
  2. 根据权利要求1所述的场效应晶体管，其中，所述漏极电极和所述源极电极分别与所述氧化镓衬底形成有欧姆接触结构；
    所述钝化层覆盖所述p型材料层及所述氧化镓衬底，所述钝化层上设置有多个开口，所述多个开口分别暴露出所述漏极电极、所述源极电极和所述栅极电极。
  3. 根据权利要求1所述的场效应晶体管，所述氧化镓衬底还包括外延层；所述p型材料层和所述钝化层位于所述氧化镓衬底的外延层上；
    所述漏极电极和所述源极电极分别与所述氧化镓衬底形成有欧姆接触结构；所述钝化层覆盖所述p型材料层及所述氧化镓衬底，所述钝化层上设置有多个开口，所述多个开口分别暴露出所述漏极电极、源极电极和栅极电极。
  4. 根据权利要求1-3任一项所述的场效应晶体管，其中，所述p型材料层采用p型In xAl yGa zN单层结构、p型In xAl yGa zN多层交叠结构或p型碳化硅；
    其中，在所述p型In xAl yGa zN中，X+Y+Z＝1。
  5. 根据权利要求1-3任一项所述的场效应晶体管，其中，所述p型材料层厚度范围为20纳米至500纳米。
  6. 根据权利要求1或2所述的场效应晶体管，其中，所述氧化镓衬底采用α-Ga 2O 3衬底，β-Ga 2O 3衬底，γ-Ga 2O 3衬底，δ-Ga 2O 3衬底或ε-Ga 2O 3衬底。
  7. 一种场效应晶体管的制备方法，包括：
    在氧化镓衬底上形成p型材料层和栅极电极，所述栅极电极位于所述p型材料层上；
    在所述氧化镓衬底和所述p型材料层上形成钝化层，所述钝化层暴露出所述栅极电极；
    在所述p型材料层第一侧形成源极电极，在所述p型材料层第二侧形成漏极电极，所述钝化层暴露出所述源极电极和所述漏极电极。
  8. 根据权利要求7所述的场效应晶体管的制备方法，所述氧化镓衬底还包括外延层；
    在所述氧化镓衬底上形成p型材料层包括：
    在所述外延层上形成p型材料层。
  9. 根据权利要求7或8所述的场效应晶体管的制备方法，其中，在氧化镓衬底上形成p型材料层和栅极电极，包括：
    在所述氧化镓衬底上生长一层p型材料膜；
    在所述p型材料膜上形成掩膜，所述掩膜的面积小于所述p型材料膜的面积；
    刻蚀掉所述p型材料膜未被所述掩膜覆盖的部分，形成所述p型材料层；
    去除所述掩膜，并在所述p型材料层上形成所述栅极电极。
  10. 根据权利要求7或8所述的场效应晶体管的制备方法，其中，在所述p型材料层上第一侧形成源极电极，在所述p型材料层第二侧形成漏极电极，所述钝化层暴露出所述源极电极和所述漏极电极包括：
    去除第一预设区域及第二预设区域内的钝化层，暴露出所述氧化镓衬底；
    在所述第一预设区域对应的暴露出的所述氧化镓衬底上制作所述源极电极，在所述第二预设区域对应的暴露出的所述氮化镓衬底上制作所述漏极电极。
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