WO2020177245A1 - Goa电路及液晶显示面板 - Google Patents

Goa电路及液晶显示面板 Download PDF

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Publication number
WO2020177245A1
WO2020177245A1 PCT/CN2019/092500 CN2019092500W WO2020177245A1 WO 2020177245 A1 WO2020177245 A1 WO 2020177245A1 CN 2019092500 W CN2019092500 W CN 2019092500W WO 2020177245 A1 WO2020177245 A1 WO 2020177245A1
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Prior art keywords
node
signal
module
electrically connected
goa unit
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PCT/CN2019/092500
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English (en)
French (fr)
Inventor
田新斌
徐向阳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of display technology, in particular to a GOA circuit and a liquid crystal display panel.
  • liquid crystal display Liquid Crystal Display, LCD
  • cathode ray tubes Cathode ray tubes
  • Ray Tube, CRT Ray Tube
  • liquid crystal displays which include liquid crystal display panels and backlight modules (backlight module).
  • backlit liquid crystal displays which include liquid crystal display panels and backlight modules (backlight module).
  • the working principle of the liquid crystal display panel is based on the thin film transistor substrate (Thin Film Transistor Array Substrate, TFT Array Substrate) and the color filter (Color Filter, CF) substrate are filled with liquid crystal molecules, and the pixel voltage and common voltage are applied to the two substrates respectively, and the electric field formed between the pixel voltage and the common voltage controls the liquid crystal molecules Rotate the direction to refract the light from the backlight module to produce a picture.
  • each pixel is electrically connected to a thin film transistor (TFT), the gate of the thin film transistor is connected to the horizontal scan line, the drain is connected to the vertical data line, and the source (Source) ) Is connected to the pixel electrode.
  • TFT thin film transistor
  • Source Source
  • Applying enough voltage on the horizontal scan line will turn on all the TFTs that are electrically connected to the horizontal scan line, so that the signal voltage on the data line can be written to the pixel, and the transmittance of different liquid crystals can be controlled to achieve color control With the effect of brightness.
  • the horizontal scanning line of the active liquid crystal display panel is mainly driven by an external integrated circuit board (Integrated Circuit, IC) to complete, the external IC can control the step-by-step charging and discharging of the horizontal scan lines at all levels.
  • IC integrated circuit board
  • GOA technology Gate Driver on Array is the row driving technology of the array substrate, which can use the array process of the liquid crystal display panel to fabricate the gate driving circuit on the TFT array substrate to realize the driving mode of the gate progressive scan.
  • GOA technology can reduce the bonding process of external ICs, which has the opportunity to increase production capacity and reduce product costs, and it can make LCD panels more suitable for manufacturing narrow or borderless display products.
  • a very important test criterion is to measure the GOA margin under various reliability conditions.
  • the current of the thin film transistor in the GOA circuit increases, resulting in a larger leakage current at the first node, which is the connection point of the pull-up control module, the pull-up module, and the downstream module in the GOA circuit, as shown in Figure 1. , May cause the stage transmission signal and scanning signal to fail to output normally, resulting in failure of the GOA circuit.
  • the purpose of the present invention is to provide a GOA circuit which has a higher high temperature limit and higher reliability.
  • Another object of the present invention is to provide a liquid crystal display panel whose GOA circuit has a higher high temperature limit and higher reliability.
  • the present invention first provides a GOA circuit, including a plurality of cascaded GOA units, each level of GOA unit includes a pull-up control module, a pull-up module, a downstream module and a charging module;
  • N be a positive integer, in the Nth level GOA unit
  • the pull-up control module is connected to the first start signal and is electrically connected to the first node for pulling up the potential of the first node under the control of the first start signal;
  • the pull-up module is electrically connected to the first node and connected to a clock signal for outputting a scan signal by using the clock signal under the control of the potential of the first node;
  • the download module is electrically connected to the first node and connected to a clock signal, and is used to transmit a signal by using the clock signal output stage under the control of the potential of the first node;
  • the charging module includes a seventy-first thin film transistor and a diode.
  • the gate of the seventy-first thin film transistor is electrically connected to the first node, the source is connected to an AC input signal, and the drain is electrically connected to the anode of the diode.
  • the negative electrode of the diode is electrically connected to the first node; in the GOA unit of the same level, when the clock signal is high, the AC input signal is high, and when the clock signal is low, the AC input signal is low.
  • the high potential of the AC input signal is 40-50V.
  • the pull-up module includes a twenty-first thin film transistor; the gate of the twenty-first thin film transistor is electrically connected to the first node, the source is connected with a clock signal, and the drain is output with a scan signal.
  • the downstream module includes a twenty-second thin film transistor; the gate of the twenty-second thin film transistor is electrically connected to the first node, the source is connected to a clock signal, and the drain output stage transmits a signal.
  • Each level of GOA unit also includes a pull-down module; the pull-down module is electrically connected to the first node and connected to a second start signal, a scan signal, and a constant voltage low potential, and is used to control the first node under the control of the second start signal And the potential of the scan signal is pulled down to a constant voltage low potential.
  • Each level of GOA unit also includes a pull-down maintenance module; the pull-down maintenance module is electrically connected to the first node and accesses the scan signal and the constant voltage low potential, and is used to connect the first node and the scan signal when the first node is at a low potential. The potential is maintained at a constant voltage and low potential.
  • Each level of GOA unit also includes a bootstrap module; the bootstrap module is electrically connected to the first node and connected to a scan signal for raising the potential of the first node and maintaining the raised potential during the scan signal output period .
  • the first start signal is the start signal.
  • the first start signal is the N-1 level GOA unit Level transmission signal and scanning signal of N-1 level GOA unit.
  • the second start signal is the start signal.
  • the second start signal is the start signal of the N+1th-stage GOA unit Scan signal.
  • the present invention also provides a liquid crystal display panel including the GOA circuit described above.
  • the GOA circuit of the present invention is provided with a charging module in each level of GOA unit, the charging module includes a seventy-first thin film transistor and a diode, and the gate of the seventy-first thin film transistor is electrically connected to the pull-up
  • the connection point between the control module, the pull-up module and the downstream module is the first node.
  • the source is connected to the AC input signal, the drain is electrically connected to the anode of the diode, and the cathode of the diode is electrically connected to the first node.
  • the high and low potential moments of the input signal correspond to the high and low potential moments of the clock signal connected to the GOA unit of the stage, so that the charging module is used to continuously charge the first node when the first node is at a high potential, so as to avoid circuit failure due to leakage of the first node.
  • the GOA circuit has a higher high temperature limit and higher reliability.
  • the GOA circuit of the liquid crystal display panel of the present invention has a higher high temperature limit and higher reliability.
  • FIG. 1 is a voltage waveform diagram of the first node of a conventional GOA circuit at room temperature and high temperature;
  • FIG. 2 is a schematic diagram of the structure of the GOA circuit of the present invention.
  • FIG. 3 is a circuit diagram of an embodiment of the GOA circuit of the present invention.
  • FIG. 4 is a circuit diagram of the first-stage GOA circuit of an embodiment of the GOA circuit of the present invention.
  • FIG. 5 is a circuit diagram of the last-stage GOA circuit of an embodiment of the GOA circuit of the present invention.
  • the present invention provides a GOA circuit including a plurality of cascaded GOA units.
  • Each level of GOA unit includes a pull-up control module 100, a pull-up module 200, a downstream module 300, a charging module 400, and a pull-down module.
  • the pull-up control module 100 accesses the first activation signal CT1 and is electrically connected to the first node Q(N) for controlling the first activation signal CT1
  • the potential of the first node Q(N) is pulled up and down.
  • the pull-up module 200 is electrically connected to the first node Q(N) and connected to the clock signal Clock for outputting the scanning signal G(N) by using the clock signal Clock under the control of the potential of the first node Q(N).
  • the download module 300 is electrically connected to the first node Q(N) and connected to the clock signal Clock, and is used to output the signal ST(N) by using the clock signal Clock under the control of the potential of the first node Q(N) .
  • the charging module 400 includes a seventy-first thin film transistor T71 and a diode D1.
  • the gate of the seventy-first thin film transistor T71 is electrically connected to the first node Q(N), the source is connected to the AC input signal AC, and the drain is The pole is electrically connected to the anode of the diode D1, and the cathode of the diode D1 is electrically connected to the first node Q(N).
  • the pull-down module 500 is electrically connected to the first node Q(N) and is connected to the second start signal CT2, the scan signal G(N) and the constant voltage low potential VSS, and is used to switch the first node Q(N) under the control of the second start signal CT2
  • the potential of a node Q(N) and the scanning signal G(N) is pulled down to a constant voltage low potential VSS.
  • the pull-down maintenance module 600 is electrically connected to the first node Q(N) and accesses the scan signal G(N) and the constant voltage low potential VSS, and is used to connect the first node Q(N) to a low potential
  • the potentials of Q(N) and the scanning signal G(N) are maintained at a constant voltage low potential VSS.
  • the bootstrap module 700 is electrically connected to the first node Q(N) and connected to the scan signal G(N) for raising the potential of the first node Q(N) during the output of the scan signal G(N) And maintain the elevated potential.
  • the high potential of the AC input signal AC is 40-50V. Preferably it is 40V.
  • the size of the seventy-first thin film transistor T71 can be appropriately adjusted according to requirements.
  • the first activation signal CT1 is the level of the N-1 level GOA unit
  • the second activation signal CT2 is the scan signal G(N+1) of the N+1th level GOA unit.
  • the pull-up control module 100 includes an eleventh thin film transistor T11.
  • the gate of the eleventh thin film transistor T11 is connected to the stage transmission signal ST(N-1) of the N-1th level GOA unit, and the source is connected to the scanning signal G(N-1) of the N-1th level GOA unit ), the drain is electrically connected to the first node.
  • the pull-up module 200 includes a twenty-first thin film transistor T21.
  • the gate of the twenty-first thin film transistor T21 is electrically connected to the first node Q(N), the source is connected to the clock signal Clock, and the drain outputs the scan signal G(N).
  • the download module 300 includes a twenty-second thin film transistor T22.
  • the gate of the twenty-second thin film transistor T22 is electrically connected to the first node Q(N), the source is connected to the clock signal Clock, and the drain outputs the stage transmission signal ST(N).
  • the pull-down module 500 includes a thirty-first thin film transistor T31 and a forty-first thin film transistor T41.
  • the gate of the thirty-first thin film transistor T31 is connected to the scanning signal G(N+1) of the N+1th level GOA unit, the source is connected to the scanning signal G(N), and the drain is connected to the constant voltage low potential VSS.
  • the gate of the forty-first thin film transistor T41 is connected to the scanning signal G(N+1) of the N+1th level GOA unit, the source is electrically connected to the first node Q(N), and the drain is connected to a constant voltage Low potential VSS.
  • the pull-down maintenance module 600 includes a thirty-second thin film transistor T32, a forty-second thin film transistor T42, and an inverter 610.
  • the gate of the thirty-second thin film transistor T32 is electrically connected to the output terminal of the inverter 610, the source is connected to the scan signal G(N), and the drain is connected to the constant voltage low potential VSS.
  • the gate of the forty-second thin film transistor T42 is electrically connected to the output terminal of the inverter 610, the source is electrically connected to the first node Q(N), and the drain is connected to the constant voltage low potential VSS.
  • the input terminal of the inverter 610 is electrically connected to the first node Q(N).
  • the bootstrap module 700 includes a capacitor C1. One end of the capacitor C1 is electrically connected to the first node Q(N), and the other end is connected to the scanning signal G(N).
  • the gate and source of the eleventh thin film transistor T11 are both connected to the start signal STV.
  • the gates of the thirty-first thin film transistor T31 and the 41st thin film transistor T41 are both connected to the start signal STV.
  • the GOA circuit of the present invention provides a charging module 400 in each GOA unit.
  • the charging module 400 includes a seventy-first thin film transistor T71 and a diode D1.
  • the gate of the seventy-first thin film transistor T71 The connection point between the pull-up control module 100, the pull-up module 200, and the downstream module 300 is electrically connected to the first node Q(N), the source is connected to the AC input signal AC, and the drain is electrically connected to the diode D1
  • the anode and the cathode of the diode D1 are electrically connected to the first node Q(N), and the high and low potential moments of the AC input signal AC correspond to the high and low potential moments of the clock signal CLOCK connected to the GOA unit of this stage, so that the GOA circuit is In operation, when the first node Q(N) is at a high potential, the 71st thin film transistor T71 is turned on.
  • the GOA circuit has a higher high temperature limit and higher reliability.
  • the existence of the diode D1 can prevent the reverse conduction problem when the voltage of the first node Q(N) is higher than the voltage of the AC input signal AC, and ensure charging The normal operation of the module 400.
  • the current of the thin film transistor in the GOA circuit is small, and the first node Q(N) has insufficient charging.
  • the setting of the charging module 400 can supplement the voltage of the first node Q(N), increasing The reliability of GOA circuit.
  • the present invention also provides a liquid crystal display panel including the above-mentioned GOA circuit.
  • the structure of the GOA circuit will not be described repeatedly here.
  • the GOA circuit of the liquid crystal display panel of the present invention provides a charging module 400 in each GOA unit.
  • the charging module 400 includes a seventy-first thin film transistor T71 and a diode D1.
  • the gate electrode of the seventy-first thin film transistor T71 The connection point between the pull-up control module 100, the pull-up module 200 and the downstream module 300 is the first node Q(N), the source is connected to the AC input signal AC, and the drain is electrically connected to the anode of the diode D1 , The cathode of the diode D1 is electrically connected to the first node Q(N), and the high and low potential moments of the AC input signal AC correspond to the high and low potential moments of the clock signal CLOCK connected to the GOA unit of the stage, so that the GOA circuit is working When the first node Q(N) is at a high potential, the 71st thin film transistor T71 is turned on.
  • the AC input signal AC is also at a high level to synchronize and continuously charge the first node Q(N), avoiding the failure of the GOA circuit due to the leakage of the first node Q(N), which causes the GOA circuit to fail to normally generate scanning signals and stage transmission signals, thereby
  • the GOA circuit has a higher high temperature limit and higher reliability, and the existence of the diode D1 can prevent the reverse conduction problem when the voltage of the first node Q(N) is higher than the voltage of the AC input signal AC, and ensures the charging module 400 works normally.
  • the current of the thin film transistor in the GOA circuit is small, and the first node Q(N) has insufficient charging.
  • the setting of the charging module 400 can supplement the voltage of the first node Q(N), increasing The reliability of GOA circuit.
  • the GOA circuit of the present invention is provided with a charging module in each level of GOA unit.
  • the charging module includes a seventy-first thin film transistor and a diode.
  • the gate of the seventy-first thin film transistor is electrically connected to the pull-up control
  • the connection point between the module, the pull-up module and the downstream module is the first node.
  • the source is connected to the AC input signal, the drain is electrically connected to the anode of the diode, and the cathode of the diode is electrically connected to the first node.
  • the AC input The high and low potential moments of the signal correspond to the high and low potential moments of the clock signal connected to the GOA unit of this stage, so that the charging module is used to continuously charge the first node when the first node is at a high potential to avoid circuit failure due to leakage of the first node.
  • the GOA circuit has a higher high temperature limit and higher reliability.
  • the GOA circuit of the liquid crystal display panel of the present invention has a higher high temperature limit and higher reliability.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

公开了一种GOA电路及液晶显示面板，该GOA电路在每一级GOA单元中设置一个充电模块(400)，该充电模块(400)包括第七十一薄膜晶体管(T71)及二极管(D1)，第七十一薄膜晶体管(T71)的栅极电性连接上拉控制模块(100)、上拉模块(200)及下传模块(300)之间的连接点也即第一节点Q(N)，源极接入交流输入信号(AC)，漏极电性连接二极管(D1)的正极，二极管(D1)的负极电性连接第一节点Q(N)，该交流输入信号(AC)的高低电位时刻分别与该级GOA单元接入的时钟信号(CLOCK)的高低电位时刻对应，从而利用充电模块(400)在第一节点Q(N)为高电位时持续为其充电，避免因第一节点Q(N)漏电导致电路失效，使GOA电路具有较高的高温温度限度，可靠性较高。

Description

GOA电路及液晶显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路及液晶显示面板。
 背景技术
在显示技术领域，液晶显示装置(Liquid Crystal Display，LCD)等平板显示装置已经逐步取代阴极射线管(Cathode Ray Tube，CRT)显示装置。液晶显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片(Color Filter，CF)基板之间灌入液晶分子，并在两片基板上分别施加像素电压和公共电压，通过像素电压和公共电压之间形成的电场控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
主动式液晶显示器中，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。目前主动式液晶显示面板水平扫描线的驱动主要由外接的集成电路板(Integrated Circuit，IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。
而GOA技术(Gate Driver on Array)即阵列基板行驱动技术，是可以运用液晶显示面板的阵列制程将栅极驱动电路制作在TFT阵列基板上，实现对栅极逐行扫描的驱动方式。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
判定GOA电路设计架构的好坏，很重要的一个测试标准就是量测各种信赖性条件下的GOA限度（margin）。在高温条件下GOA电路中薄膜晶体管的电流增大，导致如图1所示，GOA电路中上拉控制模块、上拉模块及下传模块的连接点也即第一节点处的漏电流较大，可能导致级传信号及扫描信号无法正常输出，导致GOA电路失效。
 技术问题
本发明的目的在于提供一种GOA电路，具有较高的高温温度限度，可靠性较高。
本发明的另一目的在于提供一种液晶显示面板，其GOA电路具有较高的高温温度限度，可靠性较高。
 技术解决方案
为实现上述目的，本发明首先提供一种GOA电路，包括多个级联的GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下传模块及充电模块；
设N为正整数，在第N级GOA单元中，
所述上拉控制模块接入第一启动信号并电性连接第一节点，用于在第一启动信号的控制下上拉第一节点的电位；
所述上拉模块电性连接第一节点并接入时钟信号，用于在第一节点的电位的控制下利用时钟信号输出扫描信号；
所述下传模块电性连接第一节点并接入时钟信号，用于在第一节点的电位的控制下利用时钟信号输出级传信号；
所述充电模块包括第七十一薄膜晶体管及二极管，所述第七十一薄膜晶体管的栅极电性连接第一节点，源极接入交流输入信号，漏极电性连接二极管的正极，所述二极管的负极电性连接第一节点；同一级GOA单元中，当时钟信号为高电位时交流输入信号为高电位，当时钟信号为低电位时交流输入信号为低电位。
所述交流输入信号的高电位为40-50V。
所述上拉模块包括第二十一薄膜晶体管；所述第二十一薄膜晶体管的栅极电性连接第一节点，源极接入时钟信号，漏极输出扫描信号。
所述下传模块包括第二十二薄膜晶体管；所述第二十二薄膜晶体管的栅极电性连接第一节点，源极接入时钟信号，漏极输出级传信号。
每一级GOA单元还包括下拉模块；所述下拉模块电性连接第一节点并接入第二启动信号、扫描信号及恒压低电位，用于在第二启动信号的控制下将第一节点及扫描信号的电位下拉至恒压低电位。
每一级GOA单元还包括下拉维持模块；所述下拉维持模块电性连接第一节点并接入扫描信号及恒压低电位，用于在第一节点为低电位时将第一节点及扫描信号的电位维持在恒压低电位。
每一级GOA单元还包括自举模块；所述自举模块电性连接第一节点并接入扫描信号，用于在扫描信号输出期间使所述第一节点的电位抬升并保持抬升后的电位。
在第一级GOA单元中，所述第一启动信号为起始信号，在除了第一级GOA单元外的第N级GOA单元中，所述第一启动信号为第N-1级GOA单元的级传信号及第N-1级GOA单元的扫描信号。
在最后一级GOA单元中，所述第二启动信号为起始信号，在除了最后一级GOA单元外的第N级GOA单元中，所述第二启动信号为第N+1级GOA单元的扫描信号。
本发明还提供一种液晶显示面板，包括上述的GOA电路。
 有益效果
本发明的有益效果：本发明的GOA电路在每一级GOA单元中设置一个充电模块，该充电模块包括第七十一薄膜晶体管及二极管，第七十一薄膜晶体管的栅极电性连接上拉控制模块、上拉模块及下传模块之间的连接点也即第一节点，源极接入交流输入信号，漏极电性连接二极管的正极，二极管的负极电性连接第一节点，该交流输入信号的高低电位时刻分别与该级GOA单元接入的时钟信号的高低电位时刻对应，从而利用充电模块在第一节点为高电位时持续为其充电，避免因第一节点漏电导致电路失效，使GOA电路具有较高的高温温度限度，可靠性较高。本发明的液晶显示面板的GOA电路具有较高的高温温度限度，可靠性较高。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的GOA电路的第一节点在常温及高温下的电压波形图；
图2为本发明的GOA电路的结构示意图；
图3为本发明的GOA电路的一实施例的电路图；
图4为本发明的GOA电路的一实施例的第一级GOA电路的电路图；
图5为本发明的GOA电路的一实施例的最后一级GOA电路的电路图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明提供一种GOA电路，包括多个级联的GOA单元，每一级GOA单元均包括上拉控制模块100、上拉模块200、下传模块300、充电模块400、下拉模块500、下拉维持模块600及自举模块700。
设N为正整数，在第N级GOA单元中，所述上拉控制模块100接入第一启动信号CT1并电性连接第一节点Q(N)，用于在第一启动信号CT1的控制下上拉第一节点Q(N)的电位。所述上拉模块200电性连接第一节点Q(N)并接入时钟信号Clock，用于在第一节点Q(N)的电位的控制下利用时钟信号Clock输出扫描信号G(N)。所述下传模块300电性连接第一节点Q(N)并接入时钟信号Clock，用于在第一节点Q(N)的电位的控制下利用时钟信号Clock输出级传信号ST(N)。所述充电模块400包括第七十一薄膜晶体管T71及二极管D1，所述第七十一薄膜晶体管T71的栅极电性连接第一节点Q(N)，源极接入交流输入信号AC，漏极电性连接二极管D1的正极，所述二极管D1的负极电性连接第一节点Q(N)。所述下拉模块500电性连接第一节点Q(N)并接入第二启动信号CT2、扫描信号G(N)及恒压低电位VSS，用于在第二启动信号CT2的控制下将第一节点Q(N)及扫描信号G(N)的电位下拉至恒压低电位VSS。所述下拉维持模块600电性连接第一节点Q(N)并接入扫描信号G(N)及恒压低电位VSS，用于在第一节点Q(N)为低电位时将第一节点Q(N)及扫描信号G(N)的电位维持在恒压低电位VSS。所述自举模块700电性连接第一节点Q(N)并接入扫描信号G(N)，用于在扫描信号G(N)输出期间使所述第一节点Q(N)的电位抬升并保持抬升后的电位。
需要重点注意的是，同一级GOA单元中，当时钟信号Clock为高电位时交流输入信号AC为高电位，当时钟信号Clock为低电位时交流输入信号AC为低电位。
具体地，所述交流输入信号AC的高电位为40-50V。优选地为40V。
具体地，所述第七十一薄膜晶体管T71的大小可以依据需求进行适当调整。
具体地，请参阅图3，在本发明的一实施例中，在除了第一级GOA单元外的第N级GOA单元中，所述第一启动信号CT1为第N-1级GOA单元的级传信号ST(N-1)及第N-1级GOA单元的扫描信号G(N-1)。在除了最后一级GOA单元外的第N级GOA单元中，所述第二启动信号CT2为第N+1级GOA单元的扫描信号G(N+1)。
更进一步地，在图3所示的实施例中，在除了第一级及最后一级GOA单元外的第N级GOA单元中，
所述上拉控制模块100包括第十一薄膜晶体管T11。所述第十一薄膜晶体管T11的栅极接入第N-1级GOA单元的级传信号ST(N-1)，源极接入第N-1级GOA单元的扫描信号G(N-1)，漏极电性连接第一节点。
所述上拉模块200包括第二十一薄膜晶体管T21。所述第二十一薄膜晶体管T21的栅极电性连接第一节点Q(N)，源极接入时钟信号Clock，漏极输出扫描信号G(N)。
所述下传模块300包括第二十二薄膜晶体管T22。所述第二十二薄膜晶体管T22的栅极电性连接第一节点Q(N)，源极接入时钟信号Clock，漏极输出级传信号ST(N)。
所述下拉模块500包括第三十一薄膜晶体管T31及第四十一薄膜晶体管T41。所述第三十一薄膜晶体管T31的栅极接入第N+1级GOA单元的扫描信号G(N+1)，源极接入扫描信号G(N)，漏极接入恒压低电位VSS。所述第四十一薄膜晶体管T41的栅极接入第N+1级GOA单元的扫描信号G(N+1)，源极电性连接第一节点Q(N)，漏极接入恒压低电位 VSS。
所述下拉维持模块600包括第三十二薄膜晶体管T32、第四十二薄膜晶体管T42及反相器610。所述第三十二薄膜晶体管T32的栅极电性连接反相器610的输出端，源极接入扫描信号G(N)，漏极接入恒压低电位VSS。所述第四十二薄膜晶体管T42的栅极电性连接反相器610的输出端，源极电性连接第一节点Q(N)，漏极接入恒压低电位VSS。所述反相器610的输入端电性连接第一节点Q(N)。
所述自举模块700包括电容C1。所述电容C1的一端电性连接第一节点Q(N)，另一端接入扫描信号G(N)。
请参阅图4，图3所示的实施例中，在第一级GOA单元中，第十一薄膜晶体管T11的栅极及源极均接入起始信号STV。
请参阅图5，图3所示的实施例中，在最后一级GOA单元中，第三十一薄膜晶体管T31及第四十一薄膜晶体管T41的栅极均接入起始信号STV。
需要说明的是，本发明的GOA电路通过在每一级GOA单元中设置一个充电模块400，该充电模块400包括第七十一薄膜晶体管T71及二极管D1，第七十一薄膜晶体管T71的栅极电性连接上拉控制模块100、上拉模块200及下传模块300之间的连接点也即第一节点Q(N)，源极接入交流输入信号AC，漏极电性连接二极管D1的正极，二极管D1的负极电性连接第一节点Q(N)，并且该交流输入信号AC的高低电位时刻分别与该级GOA单元接入的时钟信号CLOCK的高低电位时刻对应，从而该GOA电路在工作时，当第一节点Q(N)为高电位时将第七十一薄膜晶体管T71导通，若在高温测试环境中，第一节点Q(N)存在漏电，当时钟信号CLOCK为高电位时交流输入信号AC也为高电位从而对第一节点Q(N)进行同步且持续的充电，避免因第一节点Q(N)漏电导致GOA电路无法正常产生扫描信号及级传信号而失效，从而使GOA电路具有较高的高温温度限度，可靠性较高，而二极管D1的存在能够防止第一节点Q(N)的电压高于交流输入信号AC的电压时反向导通的问题，保证充电模块400的正常工作。另外，在低温测试环境中，GOA电路中薄膜晶体管的电流较小，第一节点Q(N)存在充电不足的问题，该充电模块400的设置能够为第一节点Q(N)补充电压，增加GOA电路的可靠性。
基于同一发明构思，本发明还提供一种液晶显示面板，包括上述的GOA电路。在此不再对GOA电路的结构进行重复性描述。本发明的液晶显示面板的GOA电路通过在每一级GOA单元中设置一个充电模块400，该充电模块400包括第七十一薄膜晶体管T71及二极管D1，第七十一薄膜晶体管T71的栅极电性连接上拉控制模块100、上拉模块200及下传模块300之间的连接点也即第一节点Q(N)，源极接入交流输入信号AC，漏极电性连接二极管D1的正极，二极管D1的负极电性连接第一节点Q(N)，并且该交流输入信号AC的高低电位时刻分别与该级GOA单元接入的时钟信号CLOCK的高低电位时刻对应，从而该GOA电路在工作时，当第一节点Q(N)为高电位时将第七十一薄膜晶体管T71导通，若在高温测试环境中，第一节点Q(N)存在漏电，当时钟信号CLOCK为高电位时交流输入信号AC也为高电位从而对第一节点Q(N)进行同步且持续的充电，避免因第一节点Q(N)漏电导致GOA电路无法正常产生扫描信号及级传信号而失效，从而使GOA电路具有较高的高温温度限度，可靠性较高，而二极管D1的存在能够防止第一节点Q(N)的电压高于交流输入信号AC的电压时反向导通的问题，保证充电模块400的正常工作。另外，在低温测试环境中，GOA电路中薄膜晶体管的电流较小，第一节点Q(N)存在充电不足的问题，该充电模块400的设置能够为第一节点Q(N)补充电压，增加GOA电路的可靠性。
综上所述，本发明的GOA电路在每一级GOA单元中设置一个充电模块，该充电模块包括第七十一薄膜晶体管及二极管，第七十一薄膜晶体管的栅极电性连接上拉控制模块、上拉模块及下传模块之间的连接点也即第一节点，源极接入交流输入信号，漏极电性连接二极管的正极，二极管的负极电性连接第一节点，该交流输入信号的高低电位时刻分别与该级GOA单元接入的时钟信号的高低电位时刻对应，从而利用充电模块在第一节点为高电位时持续为其充电，避免因第一节点漏电导致电路失效，使GOA电路具有较高的高温温度限度，可靠性较高。本发明的液晶显示面板的GOA电路具有较高的高温温度限度，可靠性较高。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (18)

  1. 一种GOA电路，包括多个级联的GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下传模块及充电模块；
    设N为正整数，在第N级GOA单元中，
    所述上拉控制模块接入第一启动信号并电性连接第一节点，用于在第一启动信号的控制下上拉第一节点的电位；
    所述上拉模块电性连接第一节点并接入时钟信号，用于在第一节点的电位的控制下利用时钟信号输出扫描信号；
    所述下传模块电性连接第一节点并接入时钟信号，用于在第一节点的电位的控制下利用时钟信号输出级传信号；
    所述充电模块包括第七十一薄膜晶体管及二极管，所述第七十一薄膜晶体管的栅极电性连接第一节点，源极接入交流输入信号，漏极电性连接二极管的正极，所述二极管的负极电性连接第一节点；同一级GOA单元中，当时钟信号为高电位时交流输入信号为高电位，当时钟信号为低电位时交流输入信号为低电位。
  2. 如权利要求1所述的GOA电路，其中，所述交流输入信号的高电位为40-50V。
  3. 如权利要求1所述的GOA电路，其中，所述上拉模块包括第二十一薄膜晶体管；所述第二十一薄膜晶体管的栅极电性连接第一节点，源极接入时钟信号，漏极输出扫描信号。
  4. 如权利要求1所述的GOA电路，其中，所述下传模块包括第二十二薄膜晶体管；所述第二十二薄膜晶体管的栅极电性连接第一节点，源极接入时钟信号，漏极输出级传信号。
  5. 如权利要求1所述的GOA电路，其中，每一级GOA单元还包括下拉模块；所述下拉模块电性连接第一节点并接入第二启动信号、扫描信号及恒压低电位，用于在第二启动信号的控制下将第一节点及扫描信号的电位下拉至恒压低电位。
  6. 如权利要求5所述的GOA电路，其中，每一级GOA单元还包括下拉维持模块；所述下拉维持模块电性连接第一节点并接入扫描信号及恒压低电位，用于在第一节点为低电位时将第一节点及扫描信号的电位维持在恒压低电位。
  7. 如权利要求1所述的GOA电路，其中，每一级GOA单元还包括自举模块；所述自举模块电性连接第一节点并接入扫描信号，用于在扫描信号输出期间使所述第一节点的电位抬升并保持抬升后的电位。
  8. 如权利要求1所述的GOA电路，其中，在第一级GOA单元中，所述第一启动信号为起始信号，在除了第一级GOA单元外的第N级GOA单元中，所述第一启动信号为第N-1级GOA单元的级传信号及第N-1级GOA单元的扫描信号。
  9. 如权利要求5所述的GOA电路，其中，在最后一级GOA单元中，所述第二启动信号为起始信号，在除了最后一级GOA单元外的第N级GOA单元中，所述第二启动信号为第N+1级GOA单元的扫描信号。
  10. 一种液晶显示面板，包括GOA电路；
    所述GOA电路包括多个级联的GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下传模块及充电模块；
    设N为正整数，在第N级GOA单元中，
    所述上拉控制模块接入第一启动信号并电性连接第一节点，用于在第一启动信号的控制下上拉第一节点的电位；
    所述上拉模块电性连接第一节点并接入时钟信号，用于在第一节点的电位的控制下利用时钟信号输出扫描信号；
    所述下传模块电性连接第一节点并接入时钟信号，用于在第一节点的电位的控制下利用时钟信号输出级传信号；
    所述充电模块包括第七十一薄膜晶体管及二极管，所述第七十一薄膜晶体管的栅极电性连接第一节点，源极接入交流输入信号，漏极电性连接二极管的正极，所述二极管的负极电性连接第一节点；同一级GOA单元中，当时钟信号为高电位时交流输入信号为高电位，当时钟信号为低电位时交流输入信号为低电位。
  11. 如权利要求10所述的液晶显示面板，其中，所述交流输入信号的高电位为40-50V。
  12. 如权利要求10所述的液晶显示面板，其中，所述上拉模块包括第二十一薄膜晶体管；所述第二十一薄膜晶体管的栅极电性连接第一节点，源极接入时钟信号，漏极输出扫描信号。
  13. 如权利要求10所述的液晶显示面板，其中，所述下传模块包括第二十二薄膜晶体管；所述第二十二薄膜晶体管的栅极电性连接第一节点，源极接入时钟信号，漏极输出级传信号。
  14. 如权利要求10所述的液晶显示面板，其中，每一级GOA单元还包括下拉模块；所述下拉模块电性连接第一节点并接入第二启动信号、扫描信号及恒压低电位，用于在第二启动信号的控制下将第一节点及扫描信号的电位下拉至恒压低电位。
  15. 如权利要求14所述的液晶显示面板，其中，每一级GOA单元还包括下拉维持模块；所述下拉维持模块电性连接第一节点并接入扫描信号及恒压低电位，用于在第一节点为低电位时将第一节点及扫描信号的电位维持在恒压低电位。
  16. 如权利要求10所述的液晶显示面板，其中，每一级GOA单元还包括自举模块；所述自举模块电性连接第一节点并接入扫描信号，用于在扫描信号输出期间使所述第一节点的电位抬升并保持抬升后的电位。
  17. 如权利要求10所述的液晶显示面板，其中，在第一级GOA单元中，所述第一启动信号为起始信号，在除了第一级GOA单元外的第N级GOA单元中，所述第一启动信号为第N-1级GOA单元的级传信号及第N-1级GOA单元的扫描信号。
  18. 如权利要求14所述的液晶显示面板，其中，在最后一级GOA单元中，所述第二启动信号为起始信号，在除了最后一级GOA单元外的第N级GOA单元中，所述第二启动信号为第N+1级GOA单元的扫描信号。
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