WO2020177026A1 - 发光二极管及其制作方法 - Google Patents

发光二极管及其制作方法 Download PDF

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Publication number
WO2020177026A1
WO2020177026A1 PCT/CN2019/076731 CN2019076731W WO2020177026A1 WO 2020177026 A1 WO2020177026 A1 WO 2020177026A1 CN 2019076731 W CN2019076731 W CN 2019076731W WO 2020177026 A1 WO2020177026 A1 WO 2020177026A1
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emitting diode
light
light emitting
substrate
reflective layer
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PCT/CN2019/076731
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English (en)
French (fr)
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王庆
陈大钟
许圣贤
洪灵愿
彭康伟
林素慧
张家宏
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厦门市三安光电科技有限公司
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Priority to PCT/CN2019/076731 priority Critical patent/WO2020177026A1/zh
Priority to CN201980003933.7A priority patent/CN110998872A/zh
Publication of WO2020177026A1 publication Critical patent/WO2020177026A1/zh
Priority to US17/366,268 priority patent/US11862752B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0058—Processes relating to semiconductor body packages relating to optical field-shaping elements

Definitions

  • the invention relates to the field of semiconductor lighting, in particular to a light emitting diode and a manufacturing method thereof.
  • dicing is to divide the finished wafer into single crystal grains of required size, which is an indispensable process in the semiconductor light-emitting diode chip manufacturing process.
  • the cutting technology of LED has gradually developed from diamond knife cutting to laser cutting.
  • laser cutting There are two main types of laser cutting: surface cutting and hidden cutting. It uses a laser beam with a certain energy density and wavelength to focus on the surface or inside of the wafer, burn the scratches on the surface or inside of the wafer through the laser, and then use a splitter to crack along the scratches.
  • Laser cutting has the advantages of high productivity, high yield, easy automatic operation, and low cost.
  • Chinese patent document CN103943744A discloses a chip processing method that can improve LED light efficiency.
  • the processing method steps are: (1) laser scribing on the upper surface of the device to the vicinity of the interface between the substrate and the epitaxial wafer to form a trench; (2) Use high-temperature acid to etch the trench to obtain the desired morphology; (3) Use a stealth cutting process to form internal scratches at the position facing the trench inside the device; (4) Split the locations of the internal scratches into Each independent light-emitting diode chip.
  • the method of the invention simultaneously adopts a high-temperature sidewall corrosion process and an invisible cutting process, which can improve the brightness of the LED chip to a greater extent.
  • step (1) it is difficult to control the depth of the scribing in step (1), and it is easy to ablate a part of the substrate.
  • the solution cannot completely remove the debris generated during scribing, which will cause light absorption and loss; at the same time, invisible cutting in step (3)
  • the scratches should not be close to the side of the epitaxial layer, so as not to damage the epitaxial layer, which will affect the number of stealth cutting blades and greatly reduce the roughening area of the substrate.
  • the purpose of the present invention is to overcome at least one problem existing in the current LED dicing production process, and it is suitable for light emitting diodes in the visible light range and manufacturing methods.
  • the technical solution of the present invention is a light-emitting diode, including: a substrate having opposite upper and lower surfaces; a DBR reflective layer formed on the upper surface of the substrate; a semiconductor stack formed on the DBR reflective layer On the layer, light having the first wavelength is emitted; the reflectivity of the DBR reflective layer for the first light wave is 30% or less; and the reflectivity for the second light wave having a wavelength different from the first light wave is 60% or more.
  • the first light wave is emitted by the light emitting diode, and its emission wavelength may be 400-900 nm, and the second light wave is not emitted by the light emitting diode, for example, may be a laser beam suitable for face cutting or invisible cutting. .
  • the light emitting diode further includes an AlN buffer layer, and the AlN is formed between the DBR reflective layer and the semiconductor stack. Further, the side surface of the semiconductor stack presents an internal oblique morphology.
  • the side surface of the substrate has multiple undercut traces, which can be evenly distributed on the side surface of the substrate.
  • the present invention also provides a method for manufacturing a light emitting diode, including the steps: (1) providing a substrate on which a DBR reflective layer is formed; (2) forming a semiconductor stack on the DBR reflective layer; wherein The reflectivity of the DBR reflective layer to the first light wave is 30% or less; the reflectivity of the second light wave that is different from the wavelength of the first light wave is more than 60%, where the first light wave is emitted by the light emitting diode, and the Two light waves are not emitted by the light emitting diode.
  • the manufacturing method of the light-emitting diode further includes: (3) using a first laser beam to perform forward scribing; (4) using a second laser beam to perform undercutting; wherein the DBR reflective layer is opposite to the first and second The reflectivity of the laser beam is all 60% or more.
  • Fig. 1 is a production flow chart of a light emitting diode implemented according to the present invention.
  • FIGS. 2 to 6 are schematic cross-sectional views of the process of preparing a gallium nitride-based light-emitting diode chip in Example 1.
  • Figures 7 to 15 are wavelength-reflectivity graphs corresponding to different DBR layers.
  • this embodiment discloses a method for manufacturing a gallium nitride light-emitting diode chip, and the manufacturing steps include S100-S400.
  • a growth substrate 100 is provided, and a DBR layer 110, a buffer layer 120 and a semiconductor stack 130 are sequentially formed on the growth substrate, as shown in FIG. 2.
  • the substrate 100 may be any one of a flat sapphire substrate, a patterned sapphire substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, and a glass substrate.
  • a patterned sapphire substrate is preferred.
  • the substrate 100 has an upper surface S11 and a lower surface S12 opposite to each other, wherein the upper surface S11 is used for depositing a semiconductor stack.
  • the DBR layer 110 has the following characteristics: (1) The high-pass wavelength of the DBR layer is 400nm-900nm, and its reflectivity is preferably below 20%; (2) The high-reflective emission wavelength of the DBR layer is 1064 ⁇ 100nm (the current mainstream invisible cutting The reflectivity of the light wave in the laser band of the machine is more than 60%, preferably more than 90%. This embodiment is designed based on the current mainstream laser cutting machine for stealth cutting in the market with a laser wave band of 1064nm. It should be noted that , The DBR layer can be designed according to the laser cutting machine of different bands to make it high anti-cutting band.
  • the DBR reflective layer can be formed by alternately stacking n pairs of high refractive index materials and low refractive index materials, where the high refractive index materials can be TiO 2 , NB 2 O 5 , TA 2 O 5 , HfO 2 , ZrO 2. ZnO, H4 (the main component is LaTiO 3 ), etc.; low-refractive materials can be SiO 2 , MgF 2 , Al 2 O 5 , SiON, etc.; among them, the optical thickness of high-refractive materials and low-refractive materials is (1/4) k ⁇ 1, where 1000nm ⁇ 1 ⁇ 1200nm, and k is an odd number.
  • the high refractive index materials can be TiO 2 , NB 2 O 5 , TA 2 O 5 , HfO 2 , ZrO 2.
  • ZnO, H4 the main component is LaTiO 3
  • low-refractive materials can be SiO 2 , MgF 2 , Al 2 O 5 ,
  • the value of n is 3 pairs or more, and more preferably, the value of n is 5 pairs or more, for example, it may be 5 pairs, or 7 pairs or 10 pairs.
  • 126nm-thick HfO 2 and 182nm-thick SiO 2 are alternately stacked.
  • the stacking logarithm n is 3 pairs, the reflectivity of the DBR reflective layer to the light wave with the emission wavelength of 1064 ⁇ 100nm It can reach about 70%; when 5 pairs are selected, the reflectivity of the DBR layer to light waves with an emission wavelength of 1064 ⁇ 100nm can reach about 90%.
  • the DBR layer has a 1064 emission wavelength.
  • the reflectance of ⁇ 100nm light waves can exceed 90%. Although more material pairs are beneficial to improve the reflectivity of the DBR for cutting laser beams, too many material layers will form a thicker material layer, which is unfavorable for subsequent cutting. Therefore, the DBR layer preferably has 5-18 pairs Alternate layers of high and low refractive materials.
  • the buffer layer 110 is preferably an AlN layer, which is formed on the DBR layer 110 by means of physical vapor deposition (Physical Vapor Deposition, PVD for short), and has a thickness of 10-100 nm.
  • the semiconductor stack is formed on the AlN buffer layer 120 by metal organic chemical vapor deposition.
  • the semiconductor stack may include an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer.
  • the emission wavelength of the semiconductor stack may be blue or blue. Light, green light, etc.
  • laser scribing is performed along the surface of the semiconductor stack to the vicinity of the interface between the substrate and the semiconductor stack, with a depth of between 5 and 10 microns, forming a longitudinal straight line B in the direction perpendicular to the flat side.
  • a transverse straight cutting lane A is formed in a direction parallel to the flat edge, and the cutting lanes A and B form a network structure of the cutting lane 200.
  • a chemical solution is used to etch the cutting lane 200, so that the side surface S13 of the semiconductor stack presents an internal bevel shape, as shown in FIG. 6.
  • the laser beam emitted by the invisible cutting machine is focused into the substrate to perform at least two cuttings to form multiple laser scratches 101, which are closest to the semiconductor stack.
  • the distance between the scratch 101 of the layer and the upper surface of the substrate 100 is preferably 20 ⁇ m or less, preferably 1-10 ⁇ m.
  • the DBR layer 110 highly reflects the laser beam emitted by the invisible cutting machine, it can effectively block the stealth laser so that it will not damage the semiconductor stack, increase the number of stealth cuts, and enlarge the substrate.
  • the roughened area on the side increases light extraction.
  • the distance of each adjacent laser scratch is 10-30 ⁇ m, and the number of cutting tracks can be selected according to the thickness of the substrate.
  • the thickness of the substrate is 100-150 ⁇ m, it is preferable to perform 3 cuts (that is, to form 3 laser scratches on the sidewall of the substrate).
  • the thickness of the substrate is 150-200 ⁇ m, it is preferable to perform 4-cuts (that is, in the The sidewall of the substrate is formed with 4 laser scratches).
  • the thickness of the substrate is 200 microns or more, it is preferable to perform 5 cuts (that is, 5 laser scratches are formed on the sidewall of the substrate).
  • a P electrode 141 and an N electrode 142 are respectively formed on the P-type semiconductor layer and the exposed N-type semiconductor layer through a photomask and an etching process; after grinding and splitting processes, a light-emitting diode chip is manufactured.
  • Figures 7 and 8 respectively show the wavelength-reflectivity curves corresponding to different logarithms of the DBR layer 110, which is composed of 126 nm thick HfO 2 and 182 nm thick SiO 2 alternately stacked.
  • the reflectivity of the DBR layer for light waves between 1000 and 1100 nm can reach about 70%, and the reflectivity for light waves between 350 ⁇ 20 nm can reach more than 60%, and for light waves between 400 and 800 nm
  • the reflectance for light waves between 400 and 750 nm is 10% or less. That is: most of the blue, cyan or green light emitted by the semiconductor stack can pass through the DBR layer; and most of the laser beam (wavelength about 1064nm) that enters the substrate from the back of the substrate S12 for invisible cutting will be affected by the DBR. Reflection, thereby avoiding damage to the semiconductor stack 130, which can be increased. Further, the DBR layer can also partially reflect the surface-cut laser beam (about 365 nm) directed toward the semiconductor stack, reducing the possibility of ablating the upper surface of the substrate 100.
  • more than three laser scratches 101 can be uniformly distributed on the side surface of the substrate 100, and the distance between the scratches 1011 near the upper surface S11 and the upper surface S11 can reach within 10 ⁇ m, or even within 5 ⁇ m. , Increase the roughening area of the substrate sidewall.
  • the DBR layer 110 of this embodiment has a highly reflective light wave with a wavelength of 365 ⁇ 35nm (laser band of the current mainstream laser scribing machine), and its reflectivity is above 60%, preferably 90% Above, this embodiment is designed based on the current market mainstream laser cutting machine for surface cutting with a laser waveband of 365nm. It should be noted that the DBR layer can be designed according to laser cutting machines of different wavebands to have a high anti-cutting waveband.
  • the DBR reflective layer 110 may be formed by alternately stacking m pairs of high refractive index materials and low refractive index materials, where the high refractive index materials may be TiO 2 , NB 2 O 5 , TA 2 O 5 , HfO 2 , ZrO 2 , ZnO, H4 (the main component is LaTiO 3 ), etc.; low-refractive materials can be SiO 2 , MgF 2 , Al 2 O 5 , SiON, etc.; among them, the optical thickness of high-refractive materials and low-refractive materials is (1/4)k ⁇ ⁇ 2, where 350nm ⁇ 2 ⁇ 380nm, k is an odd number.
  • the value of m is 3 pairs or more, and more preferably, the value of n is 5 pairs or more, for example, it may be 5 pairs, or 7 pairs or 10 pairs.
  • the DBR layer 110 of this embodiment includes n pairs of alternately stacked first material layers and second material layers, and m pairs of alternately stacked third material layers and fourth material layers. Structure two, in which structure one is closer to the substrate than structure two.
  • the materials of the first material layer and the third material layer can be the same or different.
  • the specific material can be selected from TiO 2 , NB 2 O 5 , TA 2 O 5 , HfO 2 , ZrO 2 , ZnO, H4 (the main component is LaTiO 3 ), etc.
  • the materials of the second material layer and the fourth material layer may be the same or different, and the specific materials are selected from SiO 2 , MgF 2 , Al 2 O 5 , SiON and the like.
  • the optical thickness of the first and second material layers of structure one is (1/4)k1 ⁇ 1, where 1000nm ⁇ 1 ⁇ 1200nm, k1 is an odd number, and the optical thickness of the third and fourth material layers of structure two is ( 1/4) k2 ⁇ 2, where 350nm ⁇ 2 ⁇ 380nm, k2 is an odd number.
  • Table 1 lists a DBR structure suitable for this embodiment.
  • Figures 11-15 show the wavelength-reflectivity curves corresponding to several different DBR layers.
  • Table 1 compares the reflectivity of various DBRs, where R1 represents the reflectivity of the DBR layer to the light emitted by the light-emitting layer, mainly visible light above 435nm; R2 represents the reflectivity of the DBR layer to light waves of 1000-1100nm; R3 represents the reflectivity of the DBR layer to light waves of 350 ⁇ 20 nm. If the values of R1, R2, and R3 are both considered, it is preferable that n ⁇ 5 and m ⁇ 3.
  • the substrate 100 of this embodiment may be a non-growth substrate, and the semiconductor stack 130 may be formed on the DBR layer 110 through a transparent adhesive layer.
  • a semiconductor stack can be epitaxially grown on a GaAs substrate, and then the semiconductor stack can be transferred to a transparent substrate such as a sapphire substrate by transparent bonding technology.
  • the sapphire substrate and the semiconductor A DBR layer is formed in advance on the bonding surface of the laminate, and then the growth substrate is removed, and finally, the LED chip is formed by cutting with reference to the method of Embodiment 1.
  • the LED chip is formed by the processes of forward scribing and invisible cutting at the same time. It should be understood that the manufacturing method of the light-emitting diode of the present invention is not limited to using the above two processes at the same time. For example, in some embodiments, only stealth cutting may be used to form the metamorphic layer and cracks inside the sapphire substrate, and then the chips are formed by splitting.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)
  • Dicing (AREA)

Abstract

本发明公开了一种发光二极管及制备方法，该发光二极管包括:衬底，具有相对的上、下表面；DBR反射层，形成于所述衬底的上表面之上；半导体叠层，形成于所述DBR反射层之上，发射具有的第一波长的光；所述DBR反射层对于第一光波的反射率为30%以下；对于不同于第一光波的波长的第二光波的反射率为60%以上，所述第一光波为所述发光二极管发射，所述第二光波非所述发光二极管发射。

Description

发光二极管及其制作方法 技术领域
本发明涉及半导体照明领域，特别是指一种发光二极管及其制作方法。
背景技术
发光二极管芯片制备工艺中，切割就是将制好的晶圆片分割成符合所需尺寸的单一晶粒，这是半导体发光二极管芯片制造工艺中一道必不可少的工序。发光二极管的切割技术由金刚石刀切割逐渐发展为激光切割。激光切割主要有表切和隐切两种。它是用一定能量密度和波长的激光束聚焦在晶圆片表面或内部，通过激光在晶圆片表面或内部灼烧出划痕，然后再用裂片机沿划痕裂开。激光切割具有产能高、成品率高、易于自动化操作、成本低等优势。
中国专利文献CN103943744A公开了一种能提高LED光效的芯片加工方法，加工方法步骤为：(1)在器件上表面进行激光划片至衬底与外延片界面附近，形成沟槽；(2)采用高温酸液对沟槽进行腐蚀，获得期望的形貌；(3)采用隐形切割工艺在器件内部正对沟槽的位置形成内划痕；(4)以内划痕的位置进行裂片，分为各独立的发光二极管芯片。该发明所述方法同时采用高温侧壁腐蚀工艺与隐形切割工艺，能更大程度的提高LED芯片的亮度。然而，步骤(1)中难以控制划片的深度，容易烧蚀一部分衬底，通过溶液无法彻底去除划片时产生的碎屑，会造成光的吸收和损耗；同时步骤(3)中隐形切割的划痕不能靠近外延层一侧，以免损伤到外延层，这样就会影响隐形切割的刀数，使得衬底的粗化面积大大的减少。
发明概述
技术问题
问题的解决方案
技术解决方案
本发明的目的是，在于克服目前LED划片生产过程中存在的至少一个问题，其适用于可见光范围内的发光二极管及制作方法。
本发明的技术方案为一种发光二极管，包括：衬底，具有相对的上、下表面；DBR反射层，形成于所述衬底的上表面之上；半导体叠层，形成于所述DBR反射层之上，发射具有的第一波长的光；所述DBR反射层对于第一光波的反射率为30％以下；对于不同于第一光波的波长的第二光波的反射率为60％以上。
进一步地，所述第一光波为所述发光二极管发射，其发射波长可以为400～900nm，所述第二光波非所述发光二极管发射，例如可以为适用于进行面切或者隐形切割的激光束。
在一些实施例中，该发光二极管还包括AlN缓冲层，该AlN形成于所述DBR反射层与半导体叠层之间。进一步的，该半导体叠层的侧面呈现内斜角的形貌。
在一些实施例中，所述衬底的侧面具有多道隐切的痕迹，其可以均匀的分布于所述衬底的侧面。
本发明同时提供了一种发光二极管的制作方法，包括步骤：(1)提供一衬底，在其上形成DBR反射层；(2)在所述DBR反射层上形成半导体叠层；其中所述DBR反射层对于第一光波的反射率为30％以下；对于不同于第一光波的波长的第二光波的反射率为60％以上，其中该第一光波为所述发光二极管发射，所述第二光波非所述发光二极管发射。
进一步的，该发光二极管的制作方法还包括了：(3)采用第一激光束进行正划；(4)采用第二激光束进行隐切；其中所述DBR反射层对于该第一、第二激光束的反射率均为60％以上。
发明的有益效果
有益效果
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
对附图的简要说明
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。此外，附图数据是描 述概要，不是按比例绘制。
图1为根据本发明实施的一种发光二极管的制作流程图。
图2～图6是实施例1制备氮化镓基发光二极管芯片的流程示意剖面图。
图7～15为不同的DBR层对应的波长-反射率曲线图。
发明实施例
本发明的实施方式
下面结合示意图对本发明提出的一种LED结构及制备方法进行详细的描述，在进一步介绍本发明之前，应当理解，由于可以对特定的实施例进行改造，因此，本发明并不限于下述的特定实施例。还应当理解，由于本发明的范围只由所附权利要求限定，因此所采用的实施例只是介绍性的，而不是限制性的。
实施例1
请参照图1，本实施例公开了一种氮化镓发光二极管芯片的制备方法，制作步骤包括S100～S400。
首先，提供一生长衬底100，在该生长衬底上依次形成DBR层110、缓冲层120和半导体叠层130，如图2所示。
具体的，衬底100可为蓝宝石平片衬底、蓝宝石图形化衬底、硅衬底、碳化硅衬底、氮化镓衬底、玻璃衬底中的任意一种。在本实施例中，优选图形化蓝宝石衬底。该衬底100具有相对的上表面S11和下表面S12，其中上表面S11用于进行沉积半导体叠层。
DBR层110具备以下特征：(1)该DBR层高通波长400nm～900nm的光波，其反射率优选为20％以下；(2)该DBR层高反射发射波长为1064±100nm(目前主流的隐形切割机的激光波段)的光波，其反射率达60％以上，优选为90％以上，本实施例是基于目前市场主流用于隐形切割的激光切割机的激光波段为1064nm进行设计，应注意的是，可以根据不同波段的激光切割机设计DBR层，使其高反切割波段。基于上述要求，该DBR反射层可以由n对高折射率材料和低折射率材料交替堆叠而成，其中高折射率材料可以为TiO 2、NB 2O 5、TA 2O 5、HfO 2、ZrO 2、ZnO、H4(主要成分为LaTiO 3)等；低折射材料可以为SiO 2、MgF 2、Al 2O 5、SiON等；其中高折射材料和低折射材料的光学厚度为(1/4)k×λ1，其 中1000nm＜λ1＜1200nm，k为奇数。优选的，n的取值为3对以上，更佳的，该n的取值为5对以上，例如可以为5对，或者7对或者10对。在一个具体的实施例中，取126nm厚的HfO 2与182nm厚的SiO 2进行交替堆叠，当堆叠对数n为3对时，该DBR反射层对于发射波长为1064±100nm的光波的反射率可达约70％；当取5对时，该DBR层对于发射波长为1064±100nm的光波的反射率可达约90％，当取7对或者更比时，该DBR层对于发射波长为1064±100nm的光波的反射率可以超过90％。尽管多的材料对有利于提升DBR对于切割激光束的反射率，但是太多的材料层会形成较厚的材料层，对于后续进行切割是不利的，因此该DBR层优选具有5～18对的高、低折射材料交替层。
缓冲层110优选为AlN层，采用物理气相沉积(英文为Physical Vapor Deposition，简称PVD)的方式形成在DBR层110上，其厚度为10～100nm。半导体叠层通过金属有机化学气相沉积的方式形成在AlN缓冲层120上，该半导体叠层可以包含N型半导体层、发光层和P型半导体层，该半导体叠层的发射波长可以为蓝光、青光、绿光等。
如图3和4所示，沿半导体叠层表面进行激光划片至衬底与半导体叠层界面附近，深度在5至10微米之间，在垂直于平边的方向形成纵向直线切割道B，在平行于平边的方向上形成横向直线切割道A，切割道A和B构成网络状结构的切割道200。优选的，采用化学溶液对切割道200进行腐蚀，使得半导体叠层的侧面S13呈现内斜角的形貌，如图6所示。
如图5所示，从衬底100的背面侧S12，将隐形切割机发出的激光束聚焦到衬底内部，进行至少两次以上的切割，形成多道激光划痕101，其中最靠近半导体叠层的划痕101与衬底100的上表面的距离优选为20μm以下，较佳为1～10μm。在本实施例中，由于DBR层110高反射隐形切割机发射的激光束，因此可以有效阻挡隐切的激光，使其不会损伤半导体叠层，可以增加隐切的道数，加大衬底侧面的粗化的面积，增加光的萃取。优选的，相邻的各道激光划痕的距离为10-30μm，可以根据衬底的厚度选择切割的道数。当衬底的厚度为100～150μm时，优选进行3道切割(即在衬底的侧壁形成3条激光划痕)，当衬底的厚度为150～200μm，优选进行4道切割(即在衬底的侧壁形成4条激光划痕)，当衬底的厚度为200微 米以上，优选进行5道切割(即在衬底的侧壁形成5条激光划痕)。
如图6所示，通过光罩、蚀刻工艺，分别在P型半导体层和暴露的N型半导体层上制作P电极141和N电极142；经过研磨、劈裂工艺，制得发光二极管芯片。
图7和图8分别显示了不同对数的DBR层110对应的波长-反射率曲线图，该DBR由126nm厚的HfO 2与182nm厚的SiO 2交替堆叠构成。当n＝3时，该DBR层对于1000～1100nm波段之间光波的反射率可以达到约70％左右，对于350±20nm之间的光波的反射率可以达60％以上，对于400～800nm之间的光波的反射率为10％以下；当n＝5时，该DBR层对于1000～1100nm波段之间光波的反射率可以达到约90％，对于350±20nm之间的光波的反射率可以达80％以上，对于400～750nm之间的光波的反射率为10％以下。即：半导体叠层发射的蓝光、青光或者绿光大部分可以通过该DBR层；而从衬底背面S12射入衬底内部的进行隐形切割的激光束(波长约1064nm)大部分会被该DBR反射，从而避免对半导体叠层130造成损伤，如此可以增加。进一步的，该DBR层还可以部分反射射向半导体叠层的面切激光束(约365nm)，减少烧蚀衬底100的上表面的可能性。因此，该发光二极管芯片结构中，衬底100的侧面可以均匀分布有三道以上的激光划痕101，其中靠近上表面S11的划痕1011与上表面S11的距离可以达到10μm以内，甚至5微米以内，增加了衬底侧壁的粗化面积。
实施例2
与实施例1不同的是，本实施例的DBR层110高反射发光波长为365±35nm的光波(目前主流的激光划片机的激光波段)，其反射率达60％以上，优选为90％以上，本实施例是基于目前市场主流用于表面切割的激光切割机的激光波段为365nm进行设计，应注意的是，可以根据不同波段的激光切割机设计DBR层，使其高反切割波段。，该DBR反射层110可以由m对高折射率材料和低折射率材料交替堆叠而成，其中高折射率材料可以为TiO 2、NB 2O 5、TA 2O 5、HfO 2、ZrO 2、ZnO、H4(主要成分为LaTiO 3)等；低折射材料可以为SiO 2、MgF 2、Al 2O 5、SiON等；其中高折射材料和低折射材料的光学厚度为(1/4)k×λ2，其中350nm＜λ2＜380nm，k为奇数。优选的，m的取值为3对以上，更佳的，该n的取值为5对以上，例如可以为5对，或者7对或者10对。
图9和图10分别显示了m＝3和m＝5时该DBR层110的波长-反射率曲线图。当m＝3时，该DBR层对于350±20nm之间的光波的反射率约60～70％，对于435nm以上的可见光的反射率为30％以下；当n＝5时，该DBR层对于350±20nm之间的光波的反射率约80～90％。即：半导体叠层发射的蓝光、青光或者绿光大部分可以通过该DBR层；而射向半导体叠层的面切激光束(约365nm)部分会被该DBR反射，基本上不会烧蚀衬底100的上表面。
实施例3
与实施例1不同是的，本实施例的DBR层110包括n对由第一材料层和第二材料层交替堆叠组成的结构一和m对第三材料层和第四材料层交替堆叠组成的结构二，其中结构一比结构二更靠近衬底。其中第一材料层、第三材料层的材料可以相同，也可以不同，具体材料可以选自TiO 2、NB 2O 5、TA 2O 5、HfO 2、ZrO 2、ZnO、H4(主要成分为LaTiO 3)等，第二材料层和第四材料层的材料可以相同，也可以不同，具体材料选自为SiO 2、MgF 2、Al 2O 5、SiON等。其中结构一的第一、第二材料层的光学厚度为(1/4)k1×λ1，其中1000nm＜λ1＜1200nm，k1为奇数，结构二的第三、第四材料层的光学厚度为(1/4)k2×λ2，其中350nm＜λ2＜380nm，k2为奇数。表一列举了一种适用于本实施例的DBR结构。
表一
Figure PCTCN2019076731-appb-000001
图11～15显了几种不同的DBR层分别对应的波长-反射率曲线图。表一比较了各种DBR的反射率，其中R1表示该DBR层对于发光层发射的光线的反射率，主要为435nm以上的可见光线；R2表示该DBR层对于1000～1100nm的光波的反射率；R3表示该DBR层对于350±20nm的光波的反射率。如果兼顾R1、R2和R3的取值，优选的，n≥5，m≥3。
表二
曲线图 n m R1 R2 R3
图7 3 0 ＜10％ ～70％ 50-60％
图8 5 0 ＜10％ ～90％ 60-90％
图9 0 3 ＜30％ - 60-70％
图10 0 5 ＜30％ - 80-90％
图11 3 2 ＜30％ 55-70％ 80-90％
图12 5 3 ＜30％ ＞90％ 80～95％
图13 7 7 ＜30％ ＞95％ ＞95％
图14 10 10 ＜25％ ～99％ ～99％
图15 15 15 ＜30％ ～99％ ～99％
实施例4
与实施例1不同的是，本实施例的衬底100可以非生长衬底，半导体叠层130可以通过透明粘合层形成在DBR层110上。以AlGaInP系列发光二极管为例，可以先在GaAs衬底上外延生长半导体叠层，接着通过透明粘合技术将该半导体叠层转移至一诸如蓝宝石衬底的透明基板上，该蓝宝石衬底与半导体叠层的接合面上预先形成DBR层，然后去除生长衬底，最后参考实施例1的方法进行切割形成LED芯片。
上述实施例所述发光二极管的制作方法中，同时采用正划和隐形切割的工艺形成LED芯片，应该理解的是，本发明所述发光二极管的制作方法并不限制于同时采用上述两种工艺，例如在一些实施例中，可以只采用隐形切割在蓝宝石衬底内部形成变质层及裂缝，然后进行裂片形成芯片。
以上所述仅为本发明创造的较佳实施例而已，并不用以限制本发明创造，凡在本发明创造的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明创造的保护范围之内。

Claims (20)

  1. 一种发光二极管，包括：
    衬底，具有相对的上、下表面；
    DBR反射层，形成于所述衬底的上表面之上；
    半导体叠层，形成于所述DBR反射层之上，发射具有的第一波长的光；
    其特征在于：所述DBR反射层对于第一光波的反射率为30％以下；对于不同于第一光波的波长的第二光波的反射率为60％以上，所述第一光波为所述发光二极管发射，所述第二光波非所述发光二极管发射。
  2. 根据权利要求1所述的发光二极管，其特征在于：所述第一光波的发射波长为400～900nm。
  3. 根据权利要求1所述的发光二极管，其特征在于：所述第二光波为适用于表切工艺或者隐切工艺的激光。
  4. 根据权利要求1所述的发光二极管，其特征在于：所述第二光波的发射波长为365±35nm或者1064±100nm。
  5. 根据权利要求1所述的发光二极管，其特征在于：所述DBR反射层包括n对由第一材料层和第二材料层交替堆叠组成的结构。
  6. 根据权利要求1所述的发光二极管，其特征在于：所述DBR反射层包括m对第三材料层和第四材料层交替堆叠组成的结构。
  7. 根据权利要求1所述的发光二极管，其特征在于：所述DBR反射层包括n对由第一材料层和第二材料层交替堆叠组成的结构一和m对第三材料层和第四材料层交替堆叠组成的结构二，其中结构一比结构二更靠近所述衬底。
  8. 根据权利要求5或者6或者7所述的发光二极管，其特征在于：第一材料层、第三材料层的材料选自TiO2、NB 2O 5、TA 2O 5、HfO 2、ZrO 2、ZnO或者H 4，第二、第四材料层的材料选自SiO 2、MgF 2、Al 2O 5或者SiON。
  9. 根据权利要求6或者7所述的发光二极管，其特征在于：该第一材料层和该第二材料层的光学厚度为(1/4)k×λ1，其中1000nm＜λ1＜1200nm，k为奇数。
  10. 根据权利要求6或者7所述的发光二极管，其特征在于：该第三材料层和第四材料层的光学厚度为(1/4)k×λ2，其中350nm＜λ2＜380nm，k为奇数。
  11. 根据权利要求7所述的发光二极管，其特征在于：所述n≥3。
  12. 根据权利要求7所述的发光二极管，其特征在于：所述m≥2。
  13. 根据权利要求1所述的发光二极管，其特征在于：还包括一A1N缓冲层，其形成于所述DBR反射层与半导体叠层之间。
  14. 根据权利要求13所述的发光二极管，其特征在于：所述半导体叠层的侧面呈现内斜角的形貌。
  15. 根据权利要求1所述的发光二极管，其特征在于：所述衬底的侧面具有多道激光隐切的痕迹，其均匀的分布于所述衬底的侧面。
  16. 根据权利要求1所述的发光二极管，其特征在于：所述衬底的侧面具有多道激光隐切的痕迹，至少部分痕迹与所述衬底的上表面的距离为10μm以内。
  17. 发光二极管的制作方法，包括步骤：
    (1)提供一衬底，在其上形成DBR反射层；
    (2)在所述DBR反射层上形成半导体叠层；
    其中所述DBR反射层对于第一光波的反射率为30％以下；对于不同于第一光波的波长的第二光波的反射率为60％以上，其中该第一光波为所述发光二极管发射，所述第二光波非所述发光二极管发射。
  18. 根据权利要求17所述的发光二极管，还包括步骤：
    (3)采用第一激光束进行正划；
    (4)采用第二激光束进行隐切；
    其中所述DBR反射层对于该第一、第二激光束的反射率均为60％ 以上。
  19. 根据权利要求18所述的发光二极管，其特征在于：第一激光束的发射波长为365±35nm，第二激光束的发射波长为1064±100nm。
  20. 根据权利要求18所述的发光二极管，其特征在于：所述步骤(2)中先在所述DBR反射层上形成AlN缓冲层，再形成所述半导体叠层。
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