WO2020168852A1 - 阵列基板及其制作方法、显示面板、显示装置 - Google Patents

阵列基板及其制作方法、显示面板、显示装置 Download PDF

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Publication number
WO2020168852A1
WO2020168852A1 PCT/CN2020/071061 CN2020071061W WO2020168852A1 WO 2020168852 A1 WO2020168852 A1 WO 2020168852A1 CN 2020071061 W CN2020071061 W CN 2020071061W WO 2020168852 A1 WO2020168852 A1 WO 2020168852A1
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Prior art keywords
base substrate
orthographic projection
layer
color resist
substrate
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PCT/CN2020/071061
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English (en)
French (fr)
Inventor
王炎
李伟
陈延青
郭攀
王宁
秦伟达
李静
魏威
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US16/954,006 priority Critical patent/US11231629B2/en
Publication of WO2020168852A1 publication Critical patent/WO2020168852A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, a display panel, and a display device.
  • a flexible liquid crystal display device generally includes an array substrate and a color filter substrate arranged oppositely, and a liquid crystal layer disposed between the two.
  • the pixel electrode on the array substrate corresponds to the color resist pattern on the color filter substrate in a one-to-one correspondence.
  • the electrode drives the corresponding sub-pixel, so that the sub-pixel emits light of the color of the color resist pattern corresponding to the pixel electrode.
  • the matching degree between the pixel electrode and the corresponding color resist pattern is unbalanced, and the pixel electrode is adjacent to each other when driving the corresponding sub-pixel.
  • the sub-pixels will also be driven, resulting in color mixing.
  • the first aspect of the present disclosure provides an array substrate, including:
  • a thin film transistor array layer disposed on the base substrate, the thin film transistor array layer including a plurality of driving transistors distributed in an array;
  • the color resist layer includes a plurality of color resist patterns independent of each other, and a second color resist pattern is formed between adjacent color resist patterns.
  • An opening, the orthographic projection of the first opening on the base substrate at least partially overlaps the orthographic projection of the output electrode of each drive transistor on the base substrate;
  • the pixel electrode provided on the side of the color resist layer facing away from the base substrate corresponds to the driving transistor one-to-one, and the pixel electrode communicates with the corresponding driving transistor through the first opening.
  • the output electrode in the transistor is connected.
  • the array substrate further includes:
  • the orthographic projection on the base substrate is located inside the orthographic projection of the first opening on the base substrate, and the orthographic projection of the first via on the base substrate is the same as the first
  • the orthographic projection of the output electrode in the driving transistor corresponding to a via hole on the base substrate at least partially overlaps;
  • the pixel electrode is connected to the output electrode of the corresponding driving transistor through the corresponding first via hole and the first opening.
  • the orthographic projection of the flat layer on the base substrate covers the orthographic projection of each of the color resist patterns on the base substrate.
  • the distance between the boundary of the orthographic projection of the flat layer on the base substrate and the boundary of the corresponding orthographic projection of the color resist pattern on the base substrate is based on the manufactured The dimensional accuracy of the array substrate is determined.
  • the array substrate further includes:
  • a first passivation layer arranged between the common electrode layer and the pixel electrode, and a plurality of second via holes corresponding to the plurality of driving transistors are arranged on the first passivation layer, so The orthographic projection of the second via on the base substrate is located inside the orthographic projection of the first via on the base substrate, and the second via is on the base substrate.
  • the orthographic projection of the output electrode of the driving transistor corresponding to the second via hole on the base substrate at least partially overlaps;
  • the pixel electrode is connected to the output electrode in the corresponding driving transistor through the corresponding second via hole, the second opening, the corresponding first via hole, and the first opening.
  • a second aspect of the present disclosure provides a display panel including the above-mentioned array substrate, and the display panel further includes:
  • a counter substrate arranged opposite to the array substrate, the counter substrate is provided with a black matrix pattern, and the orthographic projection of the black matrix pattern on the base substrate of the array substrate covers the middle phase of the array substrate. Orthographic projection of the first opening formed between adjacent color resist patterns on the base substrate;
  • a liquid crystal layer provided between the array substrate and the counter substrate.
  • the orthographic projection of the black matrix pattern on the base substrate partially overlaps the orthographic projection of each of the color resist patterns located at the periphery of the first opening on the base substrate.
  • the size of the overlapping portion of the orthographic projection of the black matrix pattern on the base substrate and the orthographic projection of each of the color resist patterns located at the periphery of the first opening on the base substrate It is determined according to the dimensional accuracy of the fabricated array substrate and the accuracy of the alignment of the array substrate and the counter substrate.
  • a third aspect of the present disclosure provides a display device including the above display panel.
  • a manufacturing method of an array substrate including:
  • the thin film transistor array layer including a plurality of driving transistors distributed in an array
  • a color resist layer is fabricated on the side of the thin film transistor array layer facing away from the base substrate.
  • the color resist layer includes a plurality of color resist patterns independent of each other, and a first color resist pattern is formed between adjacent color resist patterns.
  • An opening, the orthographic projection of the first opening on the base substrate at least partially overlaps the orthographic projection of the output electrode of each driving transistor on the base substrate;
  • a pixel electrode is fabricated on the side of the color resist layer facing away from the base substrate, the pixel electrode corresponds to the driving transistor one to one, and the pixel electrode passes through the first opening and corresponds to the driving transistor The output electrode in the connection.
  • the manufacturing method further includes:
  • a flat layer is formed between the pixel electrode and the color resist layer, and a plurality of first via holes corresponding to the plurality of driving transistors are formed on the flat layer.
  • the orthographic projection on the base substrate is located inside the orthographic projection of the first opening on the base substrate, and the orthographic projection of the first via on the base substrate is the same as that of the first.
  • the orthographic projection of the output electrode in the drive transistor corresponding to the via hole on the base substrate at least partially overlaps; the pixel electrode passes through the corresponding first via hole and the first opening and the corresponding drive transistor The output electrode in the connection.
  • the forming a flat layer between the pixel electrode and the color resist layer includes:
  • the orthographic projection of the flat layer on the base substrate is arranged to cover the orthographic projection of each of the color resist patterns on the base substrate.
  • the manufacturing method further includes:
  • a common electrode layer is fabricated between the flat layer and the pixel electrode, a second opening is formed on the common electrode layer, and the orthographic projection of the second opening on the base substrate covers each of the first An orthographic projection of a via on the base substrate;
  • a first passivation layer is formed between the common electrode layer and the pixel electrode, and a plurality of second via holes corresponding to the plurality of driving transistors are formed on the first passivation layer.
  • the orthographic projection of the second via on the base substrate is located inside the orthographic projection of the first via on the base substrate, and the second via is on the base substrate.
  • Orthographic projection, the orthographic projection of the output electrode of the driving transistor corresponding to the second via hole on the base substrate at least partially overlaps; the pixel electrode passes through the corresponding second via hole and the second opening , The corresponding first via hole and the first opening are connected to the corresponding output electrode in the driving transistor.
  • FIG. 1 is a schematic diagram of a display panel after bending in the related art
  • FIG. 2 is a schematic diagram of the display panel after bending in an embodiment of the disclosure
  • FIG. 3 is a first schematic diagram of a display panel provided by an embodiment of the disclosure.
  • FIG. 4 is a second schematic diagram of the display panel provided by the embodiment of the disclosure.
  • a flexible liquid crystal display device generally includes an array substrate and a color filter substrate arranged oppositely.
  • the pixel electrode 100 in the array substrate is The corresponding color resist patterns 201 in the color filter substrate are misaligned, which causes the adjacent sub-pixels to be driven when the pixel electrodes drive the corresponding sub-pixels, which causes color mixing in the flexible liquid crystal display device.
  • an embodiment of the present disclosure provides an array substrate, which includes: a base substrate 10, a thin film transistor array layer, a color resist layer 20, and a pixel electrode 100; wherein, the thin film transistor array The layer is arranged on the base substrate 10, the thin film transistor array layer includes a plurality of driving transistors distributed in an array; the color resist layer 20 is arranged on the side of the thin film transistor array layer facing away from the base substrate 10, and the color resist layer 20 includes independent A plurality of color resist patterns 201, a first opening 202 is formed between adjacent color resist patterns 201, the orthographic projection of the first opening 202 on the base substrate 10, and the output electrode 16 of each drive transistor on the base substrate 10 The orthographic projection on at least partially overlaps; the pixel electrode 100 is arranged on the side of the color resist layer 20 facing away from the base substrate 10, the pixel electrode 100 corresponds to the driving transistor one to one, and the pixel electrode 100 passes through the first opening 202 and the corresponding driving transistor The output electrode 16 is connected.
  • the above-mentioned driving transistor specifically includes: an active layer 12, a gate insulating layer 13, a gate layer 14, a dielectric layer 15, an output electrode 16, etc.
  • the above-mentioned array substrate further includes: a light shielding layer 11, a second passivation layer 50 , The first alignment layer 80 and so on.
  • the process of fabricating the above-mentioned array substrate includes: first fabricating a thin film transistor array layer on the base substrate 10, and then continuing to fabricate a color resist layer 20 on the thin film transistor array layer, and the color resist layer 20 includes a plurality of independent layers.
  • the color resist pattern 201, the first opening 202 is formed between adjacent color resist patterns 201, the orthographic projection of the first opening 202 on the base substrate 10, and the output electrode 16 of each drive transistor in the thin film transistor array layer are on the substrate
  • the orthographic projections on the substrate 10 at least partially overlap; then, the pixel electrode 100 is continued to be fabricated.
  • the pixel electrode 100 can be connected to the output electrode 16 in the corresponding driving transistor through the first opening 202 formed by the color resist pattern 201.
  • the above-mentioned array substrate and the counter substrate 60 that does not include the color resist layer 20 may be aligned in a cell, and the liquid crystal layer 70 may be formed in the cell.
  • the color resist layer 20 is provided between the thin film transistor array layer and the pixel electrode 100.
  • the selected counter substrate 60 does not need to be provided with a color resist layer. Therefore, when the array substrate and the counter substrate 60 are aligned, there is no need to consider the pixel electrode 100 and the counter substrate in the array substrate.
  • the precise alignment of the color resist layer in the substrate 60 greatly reduces the difficulty of the cell manufacturing process during the manufacturing process of the display panel and avoids errors in cell alignment.
  • the array substrate provided by the embodiment of the present disclosure can be applied to a curved display device.
  • the color resist layer 20 includes a plurality of mutually independent color resist patterns 201, so that each color resist pattern 201 has an island-like structure.
  • a first opening 202 is formed.
  • the orthographic projection of the first opening 202 on the base substrate 10 at least partially overlaps the orthographic projection of the output electrode 16 of each drive transistor on the base substrate 10, so that pixels are formed on the color resist layer 20
  • the pixel electrode 100 can be directly connected to the output electrode 16 of the corresponding drive transistor through the first opening 202 formed by the color resist pattern 201, without digging holes in the color resist layer 20 to realize the pixel electrode 100 and the output electrode 16 of the driving transistor.
  • the color resist layer 20 does not need to be drilled, and the pixel electrodes located on both sides of the color resist layer 20 can be realized.
  • 100 is connected to the output electrode 16 of the corresponding driving transistor, so as to avoid the unknown hole digging ability of the color resist layer 20.
  • the dug through hole cannot realize the problem of normal connection between the pixel electrode 100 and the output electrode 16 of the corresponding driving transistor.
  • the array substrate provided by the foregoing embodiments further includes:
  • the flat layer 30 is disposed between the pixel electrode 100 and the color resist layer 20.
  • a plurality of first vias corresponding to the plurality of driving transistors are provided on the flat layer 30.
  • the first vias are formed on the base substrate 10 Orthographic projection, located inside the orthographic projection of the first opening 202 on the base substrate 10, and the orthographic projection of the first via on the base substrate 10, and the output electrode 16 in the driving transistor corresponding to the first via
  • the orthographic projections on the base substrate 10 at least partially overlap; the pixel electrode 100 is connected to the output electrode 16 in the corresponding driving transistor through the corresponding first via and the first opening 202.
  • a flat layer 30 can be fabricated on the color resist layer 20.
  • the process of fabricating the flat layer 30 includes: first forming a flat layer film, and then patterning the flat layer film to form The flat layer 30 of the plurality of first vias.
  • the flat layer 30 is fabricated on the side of the color resist layer 20 facing away from the base substrate 10, so that the subsequent surface used to form the pixel electrode 100 is flatter, which is more conducive to the fabrication accuracy of the pixel electrode 100 .
  • the orthographic projection of the first via hole defined on the flat layer 30 on the base substrate 10 is located inside the orthographic projection of the first opening 202 on the base substrate 10, and the first via is perpendicular to the substrate 10 The direction of the substrate 10 overlaps with the output electrode 16 of the corresponding driving transistor, so that the pixel electrode 100 can achieve good connection with the output electrode 16 of the corresponding driving transistor through the first via and the first opening 202, thereby ensuring that the driving transistor Good driving effect on the pixel electrode 100.
  • the orthographic projection of the flat layer 30 on the base substrate 10 provided by the above-mentioned embodiment can be set to cover the orthographic projection of the color resist patterns 201 on the base substrate 10.
  • the orthographic projection of the flat layer 30 on the base substrate 10 covers the orthographic projection of the color resist patterns 201 on the base substrate 10, that is, the flat layer 30 completely covers the color resist patterns 201 (including those covering the color resist patterns 201).
  • the side surface so that the flat layer 30 can completely isolate the color resist pattern 201 from other film layers and pixel electrodes 100 subsequently formed on the flat layer 30, thereby better ensuring the performance of the array substrate.
  • the distance d1 between the boundary of the orthographic projection of the flat layer 30 on the base substrate 10 and the boundary of the orthographic projection of the corresponding color resist pattern 201 on the base substrate 10 can be based on actual needs. Setting and setting values need to consider the dimensional accuracy of the array substrate produced.
  • the dimensional accuracy may be, for example, line width (critical dimension, CD) accuracy.
  • the array substrate provided by the foregoing embodiments further includes:
  • the common electrode layer 40 is provided between the flat layer 30 and the pixel electrode 100.
  • the common electrode layer 40 is provided with a second opening.
  • the orthographic projection of the second opening on the base substrate 10 covers the first via holes in the substrate. Orthographic projection on the substrate 10;
  • the first passivation layer 17 is arranged between the common electrode layer 40 and the pixel electrode 100.
  • the first passivation layer 17 is provided with a plurality of second vias corresponding to the plurality of driving transistors one to one.
  • the orthographic projection on the base substrate 10 is located inside the orthographic projection of the first via on the base substrate 10, and the orthographic projection of the second via on the base substrate 10 corresponds to the drive of the second via
  • the orthographic projection of the output electrode 16 in the transistor on the base substrate 10 at least partially overlaps; the pixel electrode 100 passes through the corresponding second via, the second opening, the corresponding first via, and the first opening 202 and the corresponding driving transistor
  • the output electrode 16 is connected.
  • the common electrode layer 40 can continue to be fabricated on the flat layer 30.
  • the specific shape of the common electrode layer 40 can be set according to actual needs. For example, a comb-shaped common electrode layer can be provided 40.
  • a second opening can be provided on the common electrode layer 40, and the second opening is orthographically projected on the base substrate 10. Cover the orthographic projection of each first via on the base substrate 10.
  • the first passivation layer 17 is continued to be fabricated on the common electrode layer 40, and at the same time, a plurality of second via holes corresponding to the plurality of driving transistors are provided on the first passivation layer 17 through
  • the orthographic projection of the second via on the base substrate 10 is defined, which is located inside the orthographic projection of the first via on the base substrate 10, and the orthographic projection of the second via on the base substrate 10 is the same as the
  • the orthographic projections of the output electrodes 16 of the driving transistors corresponding to the two vias on the base substrate 10 at least partially overlap, so that the pixel electrodes 100 subsequently formed on the first passivation layer 17 can pass through the corresponding second vias and
  • the two openings, the corresponding first via and the first opening 202 are connected to the output electrode 16 of the corresponding driving transistor.
  • the above-mentioned array substrate is arranged to include both the pixel electrode 100 and the common electrode layer 40, so that when the display device made of the array substrate is bent, the common electrode layer 40 and the pixel electrode 100 will not be misaligned, which ensures the bending state Next, a uniform electric field can also be generated between the common electrode layer 40 and the pixel electrode 100, and the display device can work in a stable state.
  • an embodiment of the present disclosure also provides a display panel, including the array substrate provided in the above embodiment, the display panel further includes a counter substrate 60 and a liquid crystal layer 70; wherein the counter substrate 60 It is arranged opposite to the array substrate.
  • a black matrix pattern 601 is provided on the counter substrate 60.
  • the orthographic projection of the black matrix pattern 601 on the base substrate 10 of the array substrate covers the first formed between adjacent color resist patterns 201 in the array substrate.
  • An orthographic projection of an opening 202 on the base substrate 10; the liquid crystal layer 70 is disposed between the array substrate and the counter substrate 60.
  • the above-mentioned opposite substrate 60 further includes a protective layer 602, a second alignment layer 603 and a base 604, and the above-mentioned display panel also includes a spacer 90 disposed between the array substrate and the opposite substrate 60.
  • the array substrate provided by the above-mentioned embodiment and the counter substrate 60 provided with the black matrix pattern 601 can be provided first, and then the array substrate and the counter substrate 60 are boxed together so that the counter substrate
  • the black matrix pattern 601 on the 60 is arranged opposite to each film layer on the array substrate, and the black matrix pattern 601 on the counter substrate 60 is projected on the base substrate 10 of the array substrate to cover the adjacent colors in the array substrate.
  • the driving transistor is blocked.
  • the liquid crystal layer 70 included in the above-mentioned display panel may be formed after the array substrate and the counter substrate 60 are aligned, or before the array substrate and the counter substrate 60 are aligned, the pixel electrode 100 in the array substrate facing away from the base substrate 10 side.
  • the display panel provided by the embodiment of the present disclosure includes the array substrate provided by the above-mentioned embodiment, when the above-mentioned array substrate and the counter substrate 60 are paired to form the display panel provided by the embodiment of the present disclosure, the counter substrate 60 is selected There is no need to provide a color resist layer, so in the process of aligning the array substrate and the counter substrate 60, there is no need to consider the problem of accurately aligning the pixel electrode 100 in the array substrate and the color resist layer in the counter substrate 60 Therefore, the difficulty of the box manufacturing process in the preparation process of the display panel is greatly reduced, and the error in the box setting is avoided.
  • the pixel electrode 100 and the color resist layer 20 are both formed on the array substrate, when the display device manufactured by the display panel provided by the embodiment of the present disclosure is bent, the pixel electrode There will be no misalignment between the 100 and the corresponding color resist pattern 201, thereby well avoiding the phenomenon of color mixing when the display device displays in a curved state.
  • the color resist layer 20 is disposed on the array substrate, and the black matrix pattern 601 is disposed on the opposite substrate 60, so that the shielding function of the black matrix pattern 601 is satisfied while avoiding
  • the black matrix pattern 601 affects the problem of identifying the alignment mark in the array substrate.
  • the orthographic projection of the black matrix pattern 601 on the base substrate 10 can be set to overlap with the orthographic projection of the color resist patterns 201 located at the periphery of the first opening 202 on the base substrate 10.
  • the orthographic projection of the black matrix pattern 601 on the base substrate 10 is set to overlap with the orthographic projection of the color resist patterns 201 located at the periphery of the first opening 202 on the base substrate 10, so that the black matrix pattern 601 is perpendicular to In the direction of the base substrate 10 of the array substrate, the color resist patterns 201 located around the first opening 202 can be partially shielded, so that even if the display panel is in a curved state, the black matrix patterns 601 can still be well shielded on the array substrate
  • the driving transistor is better to ensure the display effect of the display panel.
  • the size d2 of the overlapped portion of the orthographic projection of the black matrix pattern 601 on the base substrate 10 and the orthographic projection of the color resist patterns 201 located around the first opening 202 on the base substrate 10 It can be set according to needs, and the set value needs to consider the dimensional accuracy of the array substrate to be manufactured and the accuracy of the array substrate and the counter substrate 60.
  • the embodiments of the present disclosure also provide a display device, including the display panel provided in the above-mentioned embodiments.
  • the display device may be a curved display device.
  • the display device provided by the embodiment of the present disclosure includes the display panel provided by the above-mentioned embodiment, the display device provided by the embodiment of the present disclosure also has the beneficial effect of reducing the difficulty of the box manufacturing process and avoiding errors in the box during manufacture. . Moreover, when the display device provided by the embodiment of the present disclosure is bent, there will be no misalignment between the pixel electrode 100 and the corresponding color resist pattern 201, thereby well avoiding color mixing when the display device displays in a bent state. phenomenon.
  • the display device provided by the embodiment of the present disclosure satisfies the shielding function of the black matrix pattern 601, it avoids that when the black matrix pattern 601 is arranged on the array substrate, the black matrix pattern 601 affects the recognition of the alignment mark in the array substrate. problem.
  • the embodiments of the present disclosure also provide a manufacturing method of an array substrate, the manufacturing method including:
  • the thin film transistor array layer including a plurality of driving transistors distributed in an array
  • a color resist layer 20 is fabricated on the side of the thin film transistor array layer facing away from the base substrate 10.
  • the color resist layer 20 includes a plurality of color resist patterns 201 independent of each other, and a first opening 202 is formed between adjacent color resist patterns 201.
  • the orthographic projection of the first opening 202 on the base substrate 10 at least partially overlaps with the orthographic projection of the output electrodes 16 of each drive transistor on the base substrate 10;
  • a pixel electrode 100 is fabricated on the side of the color resist layer 20 facing away from the base substrate 10.
  • the pixel electrode 100 corresponds to the driving transistor one to one.
  • the pixel electrode 100 is connected to the output electrode 16 of the corresponding driving transistor through the first opening 202.
  • the process of fabricating the above-mentioned array substrate includes: first fabricating a thin film transistor array layer on the base substrate 10; then continuing to fabricate a color resist layer 20 on the thin film transistor array layer, so that the color resist layer 20 includes a red color resist pattern and a green color resist pattern.
  • the color resist pattern and the blue color resist pattern are taken as examples.
  • a red color resist film can be formed on the side of the thin film transistor array layer facing away from the base substrate 10, and then the red color resist film can be patterned to form a plurality of mutually independent Red color resist pattern, and then make a green resist film on the side of the red resist pattern facing away from the base substrate 10, and pattern the green resist film to form a plurality of mutually independent green resist patterns, and finally A blue color resist film is made on the side of the red color resist pattern and the green color resist pattern facing away from the base substrate 10, and the blue color resist film is patterned to form a plurality of mutually independent blue color resist patterns;
  • the color resist patterns 201 of different colors are all arranged in an island shape, and a first opening 202 is formed between adjacent color resist patterns 201.
  • the orthographic projection of the first opening 202 on the base substrate 10 is different from that in the thin film transistor array layer.
  • the orthographic projection of the output electrode 16 of the driving transistor on the base substrate 10 at least partially overlaps; after the color resist layer 20 is fabricated, the pixel electrode 100 is continued to be fabricated, and the pixel electrode 100 can pass through the first opening 202 formed by the color resist pattern 201 It is connected to the output electrode 16 in the corresponding driving transistor.
  • the above-mentioned fabrication of the thin film transistor array layer and the pixel electrode 100 can be achieved by means in the related art, which will not be described here.
  • a color resist layer 20 is provided between the thin film transistor array layer and the pixel electrode 100, so that when the array substrate manufactured by the manufacturing method provided by the embodiment of the present disclosure is used to form a display panel , The selected counter substrate 60 does not need to be provided with a color resist layer, therefore, when the array substrate and the counter substrate 60 are aligned, there is no need to consider the color of the pixel electrode 100 and the counter substrate 60 in the array substrate.
  • the problem of the precise alignment of the barrier layer greatly reduces the difficulty of the box manufacturing process in the display panel preparation process and avoids the error in the box alignment.
  • the pixel electrode 100 and the color resist layer 20 are both formed on the array substrate, when the display device made from the array substrate is bent, the pixel electrode 100 and the corresponding color resist pattern 201 will not be misaligned, thereby The phenomenon of color mixing when the display device is displayed in a curved state is well avoided.
  • the color resist layer 20 includes a plurality of mutually independent color resist patterns 201, so that each color resist pattern 201 has an island-like structure, and adjacent colors are arranged at the same time.
  • a first opening 202 is formed between the resist patterns 201.
  • the orthographic projection of the first opening 202 on the base substrate 10 at least partially overlaps with the orthographic projection of the output electrode 16 of each drive transistor on the base substrate 10, so that the color resist
  • the pixel electrode 100 can be directly connected to the output electrode 16 of the corresponding driving transistor through the first opening 202 formed by the color resist pattern 201 without digging a hole in the color resist layer 20 , To realize the connection between the pixel electrode 100 and the output electrode 16 of the driving transistor.
  • the color resist layer 20 does not need to be digged to realize the separation
  • the pixel electrodes 100 located on both sides of the color resist layer 20 are connected to the output electrodes 16 of the corresponding driving transistors, so as to avoid the unknown hole digging capability of the color resist layer 20, when digging holes in the color resist layer 20, It is easy to occur that the size of the array substrate fluctuates greatly, and the dug through holes cannot realize the problem of normal connection between the pixel electrode 100 and the output electrode 16 of the corresponding driving transistor.
  • the manufacturing method of the array substrate provided by the foregoing embodiment further includes:
  • a flat layer 30 is formed between the pixel electrode 100 and the color resist layer 20.
  • a plurality of first via holes corresponding to the plurality of driving transistors are formed on the flat layer 30.
  • the first via holes are located on the base substrate 10
  • the projection is located inside the orthographic projection of the first opening 202 on the base substrate 10, and the orthographic projection of the first via on the base substrate 10.
  • the output electrode 16 in the driving transistor corresponding to the first via is in The orthographic projections on the base substrate 10 at least partially overlap; the pixel electrode 100 is connected to the output electrode 16 in the corresponding driving transistor through the corresponding first via and the first opening 202.
  • the flat layer 30 can be continuously fabricated on the color resist layer 20.
  • the process of making the flat layer 30 includes: first forming a flat layer film, and then patterning the flat layer film to form The planar layer 30 of the plurality of first vias.
  • the flat layer 30 is formed on the side of the color resist layer 20 facing away from the base substrate 10, so that the subsequent surface used to form the pixel electrode 100 is flatter, which is more beneficial to pixels.
  • the manufacturing accuracy of the electrode 100 is more beneficial to pixels.
  • the orthographic projection of the first via hole defined on the flat layer 30 on the base substrate 10 is located inside the orthographic projection of the first opening 202 on the base substrate 10, and the first via is perpendicular to the substrate 10
  • the direction of the substrate 10 overlaps with the output electrode 16 of the corresponding driving transistor, so that the pixel electrode 100 can achieve good connection with the output electrode 16 of the corresponding driving transistor through the corresponding first via and the first opening 202, thereby ensuring
  • the driving transistor has a good driving effect on the pixel electrode 100.
  • the orthographic projection of the flat layer 30 on the base substrate 10 can be set to cover the orthographic projection of the color resist patterns 201 on the base substrate 10.
  • the orthographic projection of the flat layer 30 on the base substrate 10 covers the orthographic projection of the color resist patterns 201 on the base substrate 10, that is, the flat layer 30 completely covers the color resist patterns 201 (including those covering the color resist patterns 201).
  • the side surface so that the flat layer 30 can completely isolate the color resist pattern 201 from other film layers and pixel electrodes 100 subsequently formed on the flat layer 30, thereby better ensuring the performance of the array substrate.
  • the manufacturing method of the array substrate provided by the foregoing embodiment further includes:
  • a common electrode layer 40 is fabricated between the flat layer 30 and the pixel electrode 100.
  • a second opening is formed on the common electrode layer 40.
  • the orthographic projection of the second opening on the base substrate 10 covers the first via holes in the base substrate. Orthographic projection on 10;
  • a first passivation layer 17 is formed between the common electrode layer 40 and the pixel electrode 100, and a plurality of second vias corresponding to the plurality of driving transistors are formed on the first passivation layer 17, and the second vias are in the lining
  • the orthographic projection on the base substrate 10 is located inside the orthographic projection of the first via on the base substrate 10, and the orthographic projection of the second via on the base substrate 10, and the drive transistor corresponding to the second via
  • the orthographic projection of the output electrode 16 in the base substrate 10 at least partially overlaps; the pixel electrode 100 passes through the corresponding second via, the second opening, the corresponding first via, and the first opening 202 and the corresponding driving transistor
  • the output electrode 16 is connected.
  • the common electrode layer 40 can be continuously fabricated on the flat layer 30.
  • the specific shape of the common electrode layer 40 can be fabricated according to actual needs. For example, a comb-shaped common electrode layer can be fabricated. 40.
  • a second opening can be formed on the common electrode layer 40, and the second opening is orthographically projected on the base substrate 10. Cover the orthographic projection of each first via on the base substrate 10.
  • the first passivation layer 17 is continued to be fabricated on the common electrode layer 40, and at the same time, a plurality of second via holes corresponding to the plurality of driving transistors are provided on the first passivation layer 17 through
  • the orthographic projection of the second via on the base substrate 10 is defined, which is located inside the orthographic projection of the first via on the base substrate 10, and the orthographic projection of the second via on the base substrate 10 is the same as the
  • the orthographic projections of the output electrodes 16 of the driving transistors corresponding to the two vias on the base substrate 10 at least partially overlap, so that the pixel electrodes 100 subsequently formed on the first passivation layer 17 can pass through the corresponding second vias and
  • the two openings, the corresponding first via and the first opening 202 are connected to the output electrode 16 in the corresponding driving transistor.
  • the pixel electrode 100 and the common electrode layer 40 are both fabricated on the array substrate, so that when the display device fabricated from the array substrate is bent, the common electrode layer 40 and the pixel electrode 100 are There will be no misalignment between them, which ensures that in the bent state, a uniform electric field can be generated between the common electrode layer 40 and the pixel electrode 100, and the display device works in a stable state.

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Abstract

一种阵列基板及其制作方法、显示面板、显示装置，其中阵列基板包括：衬底基板（10）；设置在衬底基板（10）上的薄膜晶体管阵列层，薄膜晶体管阵列层包括呈阵列分布的多个驱动晶体管；设置在薄膜晶体管阵列层背向衬底基板（10）的一侧的色阻层（20），色阻层（20）包括相互独立的多个色阻图形（201），相邻的色阻图形（201）之间形成第一开口（202），第一开口（202）在衬底基板（10）上的正投影，与各驱动晶体管的输出电极（16）在衬底基板（10）上的正投影至少部分重叠；设置在色阻层（20）背向衬底基板（10）的一侧的像素电极（100），像素电极（100）通过第一开口（202）与对应的驱动晶体管中的输出电极（16）连接，阵列基板用于制作显示面板。

Description

阵列基板及其制作方法、显示面板、显示装置
相关申请的交叉引用
本申请主张在2019年2月22日在中国提交的中国专利申请号No.201910133809.4的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示面板、显示装置。
背景技术
随着显示技术的不断发展，柔性液晶显示装置以其低成本、材质适应性强等优点受到广泛关注。柔性液晶显示装置一般包括相对设置的阵列基板和彩膜基板，以及设置在二者之间的液晶层，其中阵列基板上的像素电极与彩膜基板上的色阻图形一一对应，每个像素电极驱动对应的亚像素，使亚像素发出该像素电极所对应的色阻图形的颜色的光。
但是由于柔性液晶显示装置在弯曲时阵列基板和彩膜基板之间会发生错位，使得像素电极和对应的色阻图形之间的匹配度失衡，导致像素电极在驱动对应的亚像素时，相邻的亚像素也会被驱动，从而产生混色现象。
发明内容
本公开的第一方面提供一种阵列基板，包括：
衬底基板；
设置在所述衬底基板上的薄膜晶体管阵列层，所述薄膜晶体管阵列层包括呈阵列分布的多个驱动晶体管；
设置在所述薄膜晶体管阵列层背向所述衬底基板的一侧的色阻层，所述色阻层包括相互独立的多个色阻图形，相邻的所述色阻图形之间形成第一开口，所述第一开口在所述衬底基板上的正投影，与各所述驱动晶体管的输出电极在所述衬底基板上的正投影至少部分重叠；
设置在所述色阻层背向所述衬底基板的一侧的像素电极，所述像素电极与所述驱动晶体管一一对应，所述像素电极通过所述第一开口与对应的所述驱动晶体管中的输出电极连接。
可选的，所述阵列基板还包括：
设置在所述像素电极和所述色阻层之间的平坦层，所述平坦层上设置有与所述多个驱动晶体管一一对应的多个第一过孔，所述第一过孔在所述衬底基板上的正投影，位于所述第一开口在所述衬底基板上的正投影的内部，且所述第一过孔在所述衬底基板上的正投影，与该第一过孔对应的驱动晶体管中的输出电极在所述衬底基板上的正投影至少部分重叠；
所述像素电极通过对应的所述第一过孔和所述第一开口与对应的所述驱动晶体管中的输出电极连接。
可选的，所述平坦层在所述衬底基板上的正投影覆盖各所述色阻图形在所述衬底基板上的正投影。
可选的，所述平坦层在所述衬底基板上的正投影的边界与对应的所述色阻图形在所述衬底基板上的正投影的边界之间的距离根据所制作的所述阵列基板的尺寸精度确定。
可选的，所述阵列基板还包括：
设置在所述平坦层和所述像素电极之间的公共电极层，所述公共电极层上设置有第二开口，所述第二开口在所述衬底基板上的正投影，覆盖各所述第一过孔在所述衬底基板上的正投影；
设置在所述公共电极层和所述像素电极之间的第一钝化层，所述第一钝化层上设置有与所述多个驱动晶体管一一对应的多个第二过孔，所述第二过孔在所述衬底基板上的正投影，位于所述第一过孔在所述衬底基板上的正投影的内部，且所述第二过孔在所述衬底基板上的正投影，与该第二过孔对应的驱动晶体管中的输出电极在所述衬底基板上的正投影至少部分重叠；
所述像素电极通过对应的所述第二过孔、所述第二开口、对应的所述第一过孔和所述第一开口与对应的所述驱动晶体管中的输出电极连接。
基于上述阵列基板的技术方案，本公开的第二方面提供一种显示面板，包括上述阵列基板，所述显示面板还包括：
与所述阵列基板相对设置的对向基板，所述对向基板上设置有黑矩阵图形，所述黑矩阵图形在所述阵列基板的衬底基板上的正投影，覆盖所述阵列基板中相邻色阻图形之间形成的第一开口在所述衬底基板上的正投影；
设置在所述阵列基板和所述对向基板之间的液晶层。
可选的，所述黑矩阵图形在所述衬底基板上的正投影，与位于所述第一开口周边的各所述色阻图形在所述衬底基板上的正投影部分重叠。
可选的，所述黑矩阵图形在所述衬底基板上的正投影，与位于所述第一开口周边的各所述色阻图形在所述衬底基板上的正投影的重叠部分的尺寸根据所制作的所述阵列基板的尺寸精度，以及所述阵列基板和所述对向基板的对盒精度确定。
基于上述显示面板的技术方案，本公开的第三方面提供一种显示装置，包括上述显示面板。
基于上述阵列基板的技术方案，本公开的第四方面提供一种阵列基板的制作方法，包括：
提供一衬底基板；
在所述衬底基板上制作薄膜晶体管阵列层，所述薄膜晶体管阵列层包括呈阵列分布的多个驱动晶体管；
在所述薄膜晶体管阵列层背向所述衬底基板的一侧制作色阻层，所述色阻层包括相互独立的多个色阻图形，相邻的所述色阻图形之间形成第一开口，所述第一开口在所述衬底基板上的正投影，与各所述驱动晶体管的输出电极在所述衬底基板上的正投影至少部分重叠；
在所述色阻层背向所述衬底基板的一侧制作像素电极，所述像素电极与所述驱动晶体管一一对应，所述像素电极通过所述第一开口与对应的所述驱动晶体管中的输出电极连接。
可选的，所述制作方法还包括：
在所述像素电极和所述色阻层之间制作平坦层，所述平坦层上形成有与所述多个驱动晶体管一一对应的多个第一过孔，所述第一过孔在所述衬底基板上的正投影，位于所述第一开口在所述衬底基板上的正投影的内部，且所述第一过孔在所述衬底基板上的正投影，与该第一过孔对应的驱动晶体管中 的输出电极在所述衬底基板上的正投影至少部分重叠；所述像素电极通过对应的所述第一过孔和所述第一开口与对应的所述驱动晶体管中的输出电极连接。
可选的，所述在所述像素电极和所述色阻层之间制作平坦层，包括：
设置所述平坦层在所述衬底基板上的正投影覆盖各所述色阻图形在所述衬底基板上的正投影。
可选的，所述制作方法还包括：
在所述平坦层和所述像素电极之间制作公共电极层，所述公共电极层上形成有第二开口，所述第二开口在所述衬底基板上的正投影，覆盖各所述第一过孔在所述衬底基板上的正投影；
在所述公共电极层和所述像素电极之间制作第一钝化层，所述第一钝化层上形成有与所述多个驱动晶体管一一对应的多个第二过孔，所述第二过孔在所述衬底基板上的正投影，位于所述第一过孔在所述衬底基板上的正投影的内部，且所述第二过孔在所述衬底基板上的正投影，与该第二过孔对应的驱动晶体管中的输出电极在所述衬底基板上的正投影至少部分重叠；所述像素电极通过对应的所述第二过孔、所述第二开口、对应的所述第一过孔和所述第一开口与对应的所述驱动晶体管中的输出电极连接。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为相关技术中显示面板弯曲后的示意图；
图2为本公开实施例中显示面板弯曲后的示意图；
图3为本公开实施例提供的显示面板第一示意图；
图4为本公开实施例提供的显示面板第二示意图。
具体实施方式
为了进一步说明本公开实施例提供的阵列基板及其制作方法、显示面板、 显示装置，下面结合说明书附图进行详细描述。
如图1所示，相关技术中，柔性液晶显示装置一般包括相对设置的阵列基板和彩膜基板，当对柔性液晶显示装置进行弯曲时，如图1所示，阵列基板中的像素电极100与彩膜基板中对应的色阻图形201发生错位，导致像素电极在驱动对应的亚像素时，相邻的亚像素也会被驱动，从而是导致柔性液晶显示装置产生混色现象。
如图2-图4所示，本公开实施例提供的了一种阵列基板，该阵列基板包括：衬底基板10、薄膜晶体管阵列层、色阻层20和像素电极100；其中，薄膜晶体管阵列层设置在衬底基板10上，薄膜晶体管阵列层包括呈阵列分布的多个驱动晶体管；色阻层20设置在薄膜晶体管阵列层背向衬底基板10的一侧，色阻层20包括相互独立的多个色阻图形201，相邻的色阻图形201之间形成第一开口202，第一开口202在衬底基板10上的正投影，与各驱动晶体管的输出电极16在衬底基板10上的正投影至少部分重叠；像素电极100设置在色阻层20背向衬底基板10的一侧，像素电极100与驱动晶体管一一对应，像素电极100通过第一开口202与对应的驱动晶体管中的输出电极16连接。需要说明，上述驱动晶体管具体包括：有源层12、栅极绝缘层13、栅极层14、介质层15、输出电极16等，上述阵列基板还包括：遮光层11、第二钝化层50、第一配向层80等。
具体地，制作上述阵列基板的过程包括：先在衬底基板10上制作薄膜晶体管阵列层，然后继续在薄膜晶体管阵列层上制作色阻层20，且该色阻层20包括相互独立的多个色阻图形201，相邻的色阻图形201之间形成第一开口202，第一开口202在衬底基板10上的正投影，与薄膜晶体管阵列层中各驱动晶体管的输出电极16在衬底基板10上的正投影至少部分重叠；然后继续制作像素电极100，像素电极100能够通过由色阻图形201形成的第一开口202实现与对应的驱动晶体管中的输出电极16连接。
在利用上述阵列基板制作液晶显示面板时，可将上述阵列基板与不包括色阻层20的对向基板60对盒，并在盒内形成液晶层70即可。
根据上述阵列基板的具体结构和应用方式可知，本公开实施例提供的阵列基板中，在薄膜晶体管阵列层和像素电极100之间设置了色阻层20，这样 在利用本公开实施例提供的阵列基板形成显示面板时，所选用的对向基板60中不需要设置有色阻层，因此，在将阵列基板与对向基板60进行对盒时，不需要考虑将阵列基板中像素电极100和对向基板60中的色阻层精确对位的问题，从而很好的降低了显示面板制备过程中对盒制程的难度，避免了对盒时的误差。而且，由于像素电极100和色阻层20均形成在阵列基板上，在对由该阵列基板制作的显示装置进行弯曲时，像素电极100与对应的色阻图形201之间不会发生错位，从而很好的避免了显示装置在弯曲状态下进行显示时，出现混色现象。因此，本公开实施例提供的阵列基板可以应用于曲面显示装置中。
另外，本公开实施例提供的阵列基板中，设置色阻层20包括多个相互独立的色阻图形201，使得各色阻图形201均呈岛状结构，同时设置相邻的色阻图形201之间形成第一开口202，第一开口202在衬底基板10上的正投影，与各驱动晶体管的输出电极16在衬底基板10上的正投影至少部分重叠，这样在色阻层20上制作像素电极100时，像素电极100就可以直接通过由色阻图形201形成的第一开口202实现与对应的驱动晶体管的输出电极16的连接，而无需在色阻层20上挖孔，来实现像素电极100和驱动晶体管的输出电极16之间的连接，因此，本公开实施例提供的阵列基板中，无需对色阻层20进行挖孔，即可实现将分别位于色阻层20两侧的像素电极100与对应的驱动晶体管的输出电极16连接，从而很好的避免了由于色阻层20的挖孔能力未知，在对色阻层20进行挖孔时，容易出现的阵列基板尺寸波动较大，所挖过孔无法实现将像素电极100和对应的驱动晶体管的输出电极16正常连接的问题。
在一些实施例中，上述实施例提供的阵列基板还包括：
设置在像素电极100和色阻层20之间的平坦层30，平坦层30上设置有与多个驱动晶体管一一对应的多个第一过孔，第一过孔在衬底基板10上的正投影，位于第一开口202在衬底基板10上的正投影的内部，且第一过孔在衬底基板10上的正投影，与该第一过孔对应的驱动晶体管中的输出电极16在衬底基板10上的正投影至少部分重叠；像素电极100通过对应的第一过孔和第一开口202与对应的驱动晶体管中的输出电极16连接。
具体地，在制作色阻层20之后，可在色阻层20上制作平坦层30，制作平坦层30的过程包括：先形成平坦层薄膜，然后对该平坦层薄膜进行图案化，形成包括所述多个第一过孔的平坦层30。
上述实施例提供的阵列基板中，在色阻层20背向衬底基板10的一侧制作平坦层30，使得后续用于形成像素电极100的表面更加平坦，更有利于像素电极100的制作精度。而且，在平坦层30上限定的第一过孔在衬底基板10上的正投影，位于第一开口202在衬底基板10上的正投影的内部，且第一过孔在垂直于衬底基板10的方向上与对应的驱动晶体管的输出电极16交叠，使得像素电极100能够通过第一过孔和第一开口202实现与对应的驱动晶体管的输出电极16良好连接，从而保证了驱动晶体管对像素电极100的良好驱动效果。
进一步地，可设置上述实施例提供的平坦层30在衬底基板10上的正投影覆盖各色阻图形201在衬底基板10上的正投影。
具体地，设置平坦层30在衬底基板10上的正投影覆盖各色阻图形201在衬底基板10上的正投影，即设置平坦层30完全覆盖各色阻图形201(包括覆盖各色阻图形201的侧表面)，使得平坦层30能够将色阻图形201与后续形成在平坦层30上的其它膜层和像素电极100完全隔离，从而更好的保证了阵列基板的性能。
值得注意，如图3所示，平坦层30在衬底基板10上的正投影的边界与对应的色阻图形201在衬底基板10上的正投影的边界之间的距离d1可根据实际需要设置，设置的数值需考虑所制作的阵列基板的尺寸精度。所述尺寸精度例如可以为线宽(critical dimension，CD)精度。
在一些实施例中，上述实施例提供的阵列基板还包括：
设置在平坦层30和像素电极100之间的公共电极层40，公共电极层40上设置有第二开口，第二开口在衬底基板10上的正投影，覆盖各第一过孔在衬底基板10上的正投影；
设置在公共电极层40和像素电极100之间的第一钝化层17，第一钝化层17上设置有与多个驱动晶体管一一对应的多个第二过孔，第二过孔在衬底基板10上的正投影，位于第一过孔在衬底基板10上的正投影的内部，且第 二过孔在衬底基板10上的正投影，与该第二过孔对应的驱动晶体管中的输出电极16在衬底基板10上的正投影至少部分重叠；像素电极100通过对应的第二过孔、第二开口、对应的第一过孔和第一开口202与对应的驱动晶体管中的输出电极16连接。
具体地，在制作完平坦层30之后，可继续在平坦层30上制作公共电极层40，该公共电极层40的具体形状可根据实际需求设置，示例性的，可设置梳状的公共电极层40，而且，为了保证像素电极100和对应的驱动晶体管中的输出电极16之间的连接，可在公共电极层40上设置第二开口，且第二开口在衬底基板10上的正投影，覆盖各第一过孔在衬底基板10上的正投影。在制作公共电极层40之后，继续在公共电极层40上制作第一钝化层17，同时在第一钝化层17上设置与多个驱动晶体管一一对应的多个第二过孔，通过限定第二过孔在衬底基板10上的正投影，位于第一过孔在衬底基板10上的正投影的内部，且第二过孔在衬底基板10上的正投影，与该第二过孔对应的驱动晶体管中的输出电极16在衬底基板10上的正投影至少部分重叠，使得后续形成在第一钝化层17上的像素电极100能够通过对应的第二过孔、第二开口、对应的第一过孔和第一开口202与对应的驱动晶体管中的输出电极16连接。
设置上述阵列基板同时包括像素电极100和公共电极层40，使得在对由该阵列基板制作的显示装置进行弯曲时，公共电极层40和像素电极100之间不会发生错位，保证了在弯曲状态下，公共电极层40和像素电极100之间也能够产生均匀的电场，时显示装置工作在稳定的状态。
如图2-图4所示，本公开实施例还提供了一种显示面板，包括上述实施例提供的阵列基板，所述显示面板还包括对向基板60和液晶层70；其中对向基板60与阵列基板相对设置，对向基板60上设置有黑矩阵图形601，黑矩阵图形601在阵列基板的衬底基板10上的正投影，覆盖阵列基板中相邻色阻图形201之间形成的第一开口202在衬底基板10上的正投影；液晶层70设置在阵列基板和对向基板60之间。上述对向基板60还包括保护层602、第二配向层603和基底604，上述显示面板还包括设置在阵列基板和对向基板60之间的隔垫物90。
具体地，在制作上述显示面板时，可先提供上述实施例提供的阵列基板，和设置有黑矩阵图形601的对向基板60，然后将阵列基板与对向基板60对盒，使得对向基板60上的黑矩阵图形601与阵列基板上的各膜层相对设置，并使得对向基板60上的黑矩阵图形601在阵列基板的衬底基板10上的正投影，覆盖阵列基板中相邻色阻图形201之间形成的第一开口202在衬底基板10上的正投影，这样黑矩阵图形601就能够对阵列基板中在垂直于衬底基板10的方向上，与第一开口202交叠的驱动晶体管进行遮挡。上述显示面板包括的液晶层70可在阵列基板和对向基板60对盒后形成，也可以在阵列基板和对向基板60对盒之前，先形成在阵列基板中像素电极100背向衬底基板10的一侧。
由于本公开实施例提供的显示面板包括上述实施例提供的阵列基板，因此，在将上述阵列基板与对向基板60对盒形成本公开实施例提供的显示面板时，所选用的对向基板60中不需要设置有色阻层，这样在将阵列基板与对向基板60进行对盒的过程中，不需要考虑将阵列基板中像素电极100和对向基板60中的色阻层精确对位的问题，从而很好的降低了显示面板制备过程中对盒制程的难度，避免了对盒时的误差。而且，由于本公开实施例提供的显示面板中，像素电极100和色阻层20均形成在阵列基板上，因此，在对由本公开实施例提供的显示面板制作的显示装置进行弯曲时，像素电极100与对应的色阻图形201之间不会发生错位，从而很好的避免了显示装置在弯曲状态下进行显示时，出现混色现象。
另外，本公开实施例提供的显示面板将色阻层20设置在阵列基板上，并将黑矩阵图形601设置在对向基板60上，使得在满足黑矩阵图形601的遮挡功能的同时，避免了将黑矩阵图形601设置在阵列基板上时，黑矩阵图形601影响识别阵列基板中的对位标识的问题。
进一步地，可设置上述黑矩阵图形601在衬底基板10上的正投影，与位于第一开口202周边的各色阻图形201在衬底基板10上的正投影部分重叠。
具体地，设置黑矩阵图形601在衬底基板10上的正投影，与位于第一开口202周边的各色阻图形201在衬底基板10上的正投影部分重叠，使得黑矩阵图形601在垂直于阵列基板的衬底基板10的方向上，能够对位于第一开口 202周边的各色阻图形201进行部分遮挡，这样即使显示面板处于弯曲状态，黑矩阵图形601仍然能够很好的遮挡位于阵列基板上的驱动晶体管，从而更好的保证了显示面板的显示效果。
需要说明，如图3所示，黑矩阵图形601在衬底基板10上的正投影，与位于第一开口202周边的各色阻图形201在衬底基板10上的正投影的重叠部分的尺寸d2可根据需要设置，设置的数值需考虑所制作的阵列基板的尺寸精度，以及阵列基板和对向基板60的对盒精度。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示面板。
在本公开的一些实施例中，所述显示装置可以为曲面显示装置。
由于本公开实施例提供的显示装置包括上述实施例提供的显示面板，因此，本公开实施例提供的显示装置在制作时，同样具有降低对盒制程的难度，避免对盒时的误差的有益效果。而且，在对本公开实施例提供的显示装置进行弯曲时，像素电极100与对应的色阻图形201之间不会发生错位，从而很好的避免了显示装置在弯曲状态下进行显示时，出现混色现象。
另外，本公开实施例提供的显示装置在满足黑矩阵图形601的遮挡功能的同时，避免了将黑矩阵图形601设置在阵列基板上时，黑矩阵图形601影响识别阵列基板中的对位标识的问题。
本公开实施例还提供了一种阵列基板的制作方法，该制作方法包括：
提供一衬底基板10；
在衬底基板10上制作薄膜晶体管阵列层，薄膜晶体管阵列层包括呈阵列分布的多个驱动晶体管；
在薄膜晶体管阵列层背向衬底基板10的一侧制作色阻层20，色阻层20包括相互独立的多个色阻图形201，相邻的色阻图形201之间形成第一开口202，第一开口202在衬底基板10上的正投影，与各驱动晶体管的输出电极16在衬底基板10上的正投影至少部分重叠；
在色阻层20背向衬底基板10的一侧制作像素电极100，像素电极100与驱动晶体管一一对应，像素电极100通过第一开口202与对应的驱动晶体管中的输出电极16连接。
具体地，制作上述阵列基板的过程包括：先在衬底基板10上制作薄膜晶 体管阵列层；然后继续在薄膜晶体管阵列层上制作色阻层20，以色阻层20包括红色色阻图形、绿色色阻图形和蓝色色阻图形为例，可先在薄膜晶体管阵列层背向衬底基板10的一侧制作红色色阻薄膜，然后对该红色色阻薄膜进行图案化，形成多个相互独立的红色色阻图形，接着在红色色阻图形背向衬底基板10的一侧制作绿色色阻薄膜，并对该绿色色阻薄膜进行图案化，形成多个相互独立的绿色色阻图形，最后在红色色阻图形和绿色色阻图形背向衬底基板10的一侧制作蓝色色阻薄膜，并对该蓝色色阻薄膜进行图案化，形成多个相互独立的蓝色色阻图形；所制作的各种颜色的色阻图形201均呈岛状设置，在相邻的色阻图形201之间形成第一开口202，第一开口202在衬底基板10上的正投影，与薄膜晶体管阵列层中各驱动晶体管的输出电极16在衬底基板10上的正投影至少部分重叠；在制作完色阻层20之后，继续制作像素电极100，像素电极100能够通过由色阻图形201形成的第一开口202实现与对应的驱动晶体管中的输出电极16连接。
需要说明，上述制作薄膜晶体管阵列层和像素电极100均可采用相关技术中的手段实现，此处不作说明。
采用本公开实施例提供制作方法制作的阵列基板中，在薄膜晶体管阵列层和像素电极100之间设置了色阻层20，这样在利用本公开实施例提供制作方法制作的阵列基板形成显示面板时，所选用的对向基板60中不需要设置有色阻层，因此，在将阵列基板与对向基板60进行对盒时，不需要考虑将阵列基板中像素电极100和对向基板60中的色阻层精确对位的问题，从而很好的降低了显示面板制备过程中对盒制程的难度，避免了对盒时的误差。而且，由于像素电极100和色阻层20均形成在阵列基板上，在对由该阵列基板制作的显示装置进行弯曲时，像素电极100与对应的色阻图形201之间不会发生错位，从而很好的避免了显示装置在弯曲状态下进行显示时，出现混色现象。
另外，采用本公开实施例提供的制作方法制作的阵列基板中，设置色阻层20包括多个相互独立的色阻图形201，使得各色阻图形201均呈岛状结构，同时设置相邻的色阻图形201之间形成第一开口202，第一开口202在衬底基板10上的正投影，与各驱动晶体管的输出电极16在衬底基板10上的正投影至少部分重叠，这样在色阻层20上制作像素电极100时，像素电极100就 可以直接通过由色阻图形201形成的第一开口202实现与对应的驱动晶体管的输出电极16的连接，而无需在色阻层20上挖孔，来实现像素电极100和驱动晶体管的输出电极16之间的连接，因此，采用本公开实施例提供的制作方法制作的阵列基板中，无需对色阻层20进行挖孔，即可实现将分别位于色阻层20两侧的像素电极100与对应的驱动晶体管的输出电极16连接，从而很好的避免了由于色阻层20的挖孔能力未知，在对色阻层20进行挖孔时，容易出现的阵列基板尺寸波动较大，所挖过孔无法实现将像素电极100和对应的驱动晶体管的输出电极16正常连接的问题。
进一步地，上述实施例提供的阵列基板的制作方法还包括：
在像素电极100和色阻层20之间制作平坦层30，平坦层30上形成有与多个驱动晶体管一一对应的多个第一过孔，第一过孔在衬底基板10上的正投影，位于第一开口202在衬底基板10上的正投影的内部，且第一过孔在衬底基板10上的正投影，与该第一过孔对应的驱动晶体管中的输出电极16在衬底基板10上的正投影至少部分重叠；像素电极100通过对应的第一过孔和第一开口202与对应的驱动晶体管中的输出电极16连接。
具体地，在制作色阻层20之后，可在色阻层20上继续制作平坦层30，制作平坦层30的过程包括：先形成平坦层薄膜，然后对该平坦层薄膜进行图案化，形成包括所述多个第一过孔的平坦层30。
采用上述实施例提供的制作方法制作的阵列基板中，在色阻层20背向衬底基板10的一侧制作平坦层30，使得后续用于形成像素电极100的表面更加平坦，更有利于像素电极100的制作精度。而且，在平坦层30上限定的第一过孔在衬底基板10上的正投影，位于第一开口202在衬底基板10上的正投影的内部，且第一过孔在垂直于衬底基板10的方向上与对应的驱动晶体管的输出电极16交叠，使得像素电极100能够通过对应的第一过孔和第一开口202实现与对应的驱动晶体管的输出电极16良好连接，从而保证了驱动晶体管对像素电极100的良好驱动效果。
进一步地，采用上述实施例提供的制作方法制作平坦层30时，可设置平坦层30在衬底基板10上的正投影覆盖各色阻图形201在衬底基板10上的正投影。
具体地，设置平坦层30在衬底基板10上的正投影覆盖各色阻图形201在衬底基板10上的正投影，即设置平坦层30完全覆盖各色阻图形201(包括覆盖各色阻图形201的侧表面)，使得平坦层30能够将色阻图形201与后续形成在平坦层30上的其它膜层和像素电极100完全隔离，从而更好的保证了阵列基板的性能。
进一步地，上述实施例提供的阵列基板的制作方法还包括：
在平坦层30和像素电极100之间制作公共电极层40，公共电极层40上形成有第二开口，第二开口在衬底基板10上的正投影，覆盖各第一过孔在衬底基板10上的正投影；
在公共电极层40和像素电极100之间制作第一钝化层17，第一钝化层17上形成有与多个驱动晶体管一一对应的多个第二过孔，第二过孔在衬底基板10上的正投影，位于第一过孔在衬底基板10上的正投影的内部，且第二过孔在衬底基板10上的正投影，与该第二过孔对应的驱动晶体管中的输出电极16在衬底基板10上的正投影至少部分重叠；像素电极100通过对应的第二过孔、第二开口、对应的第一过孔和第一开口202与对应的驱动晶体管中的输出电极16连接。
具体地，在制作完平坦层30之后，可继续在平坦层30上制作公共电极层40，该公共电极层40的具体形状可根据实际需求制作，示例性的，可制作梳状的公共电极层40，而且，为了保证像素电极100和对应的驱动晶体管中的输出电极16之间的连接，可在公共电极层40上形成第二开口，且第二开口在衬底基板10上的正投影，覆盖各第一过孔在衬底基板10上的正投影。在制作公共电极层40之后，继续在公共电极层40上制作第一钝化层17，同时在第一钝化层17上设置与多个驱动晶体管一一对应的多个第二过孔，通过限定第二过孔在衬底基板10上的正投影，位于第一过孔在衬底基板10上的正投影的内部，且第二过孔在衬底基板10上的正投影，与该第二过孔对应的驱动晶体管中的输出电极16在衬底基板10上的正投影至少部分重叠，使得后续形成在第一钝化层17上的像素电极100能够通过对应的第二过孔、第二开口、对应的第一过孔和第一开口202与对应的驱动晶体管中的输出电极16连接。
上述实施例提供的制作方法中，将像素电极100和公共电极层40均制作在了阵列基板上，使得在对由该阵列基板制作的显示装置进行弯曲时，公共电极层40和像素电极100之间不会发生错位，保证了在弯曲状态下，公共电极层40和像素电极100之间也能够产生均匀的电场，时显示装置工作在稳定的状态。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种阵列基板，包括：
    衬底基板；
    设置在所述衬底基板上的薄膜晶体管阵列层，所述薄膜晶体管阵列层包括呈阵列分布的多个驱动晶体管；
    设置在所述薄膜晶体管阵列层背向所述衬底基板的一侧的色阻层，所述色阻层包括相互独立的多个色阻图形，相邻的所述色阻图形之间形成第一开口，所述第一开口在所述衬底基板上的正投影，与各所述驱动晶体管的输出电极在所述衬底基板上的正投影至少部分重叠；
    设置在所述色阻层背向所述衬底基板的一侧的像素电极，所述像素电极与所述驱动晶体管一一对应，所述像素电极通过所述第一开口与对应的所述驱动晶体管中的输出电极连接。
  2. 根据权利要求1所述的阵列基板，还包括：
    设置在所述像素电极和所述色阻层之间的平坦层，所述平坦层上设置有与所述多个驱动晶体管一一对应的多个第一过孔，所述第一过孔在所述衬底基板上的正投影，位于所述第一开口在所述衬底基板上的正投影的内部，且所述第一过孔在所述衬底基板上的正投影，与该第一过孔对应的驱动晶体管中的输出电极在所述衬底基板上的正投影至少部分重叠；
    所述像素电极通过对应的所述第一过孔和所述第一开口与对应的所述驱动晶体管中的输出电极连接。
  3. 根据权利要求2所述的阵列基板，其中，所述平坦层在所述衬底基板上的正投影覆盖各所述色阻图形在所述衬底基板上的正投影。
  4. 根据权利要求3所述的阵列基板，其中，所述平坦层在所述衬底基板上的正投影的边界与对应的所述色阻图形在所述衬底基板上的正投影的边界之间的距离根据所制作的所述阵列基板的尺寸精度确定。
  5. 根据权利要求2或3所述的阵列基板，还包括：
    设置在所述平坦层和所述像素电极之间的公共电极层，所述公共电极层上设置有第二开口，所述第二开口在所述衬底基板上的正投影，覆盖各所述 第一过孔在所述衬底基板上的正投影；
    设置在所述公共电极层和所述像素电极之间的第一钝化层，所述第一钝化层上设置有与所述多个驱动晶体管一一对应的多个第二过孔，所述第二过孔在所述衬底基板上的正投影，位于所述第一过孔在所述衬底基板上的正投影的内部，且所述第二过孔在所述衬底基板上的正投影，与该第二过孔对应的驱动晶体管中的输出电极在所述衬底基板上的正投影至少部分重叠；
    所述像素电极通过对应的所述第二过孔、所述第二开口、对应的所述第一过孔和所述第一开口与对应的所述驱动晶体管中的输出电极连接。
  6. 一种显示面板，包括如权利要求1～5中任一项所述的阵列基板，所述显示面板还包括：
    与所述阵列基板相对设置的对向基板，所述对向基板上设置有黑矩阵图形，所述黑矩阵图形在所述阵列基板的衬底基板上的正投影，覆盖所述阵列基板中相邻色阻图形之间形成的第一开口在所述衬底基板上的正投影；
    设置在所述阵列基板和所述对向基板之间的液晶层。
  7. 根据权利要求6所述的显示面板，其中，所述黑矩阵图形在所述衬底基板上的正投影，与位于所述第一开口周边的各所述色阻图形在所述衬底基板上的正投影部分重叠。
  8. 根据权利要求7所述的显示面板，其中，所述黑矩阵图形在所述衬底基板上的正投影，与位于所述第一开口周边的各所述色阻图形在所述衬底基板上的正投影的重叠部分的尺寸根据所制作的所述阵列基板的尺寸精度，以及所述阵列基板和所述对向基板的对盒精度确定。
  9. 一种显示装置，其中，包括如权利要求6-8任一项所述的显示面板。
  10. 一种阵列基板的制作方法，包括：
    提供一衬底基板；
    在所述衬底基板上制作薄膜晶体管阵列层，所述薄膜晶体管阵列层包括呈阵列分布的多个驱动晶体管；
    在所述薄膜晶体管阵列层背向所述衬底基板的一侧制作色阻层，所述色阻层包括相互独立的多个色阻图形，相邻的所述色阻图形之间形成第一开口，所述第一开口在所述衬底基板上的正投影，与各所述驱动晶体管的输出电极 在所述衬底基板上的正投影至少部分重叠；
    在所述色阻层背向所述衬底基板的一侧制作像素电极，所述像素电极与所述驱动晶体管一一对应，所述像素电极通过所述第一开口与对应的所述驱动晶体管中的输出电极连接。
  11. 根据权利要求10所述的阵列基板的制作方法，还包括：
    在所述像素电极和所述色阻层之间制作平坦层，所述平坦层上形成有与所述多个驱动晶体管一一对应的多个第一过孔，所述第一过孔在所述衬底基板上的正投影，位于所述第一开口在所述衬底基板上的正投影的内部，且所述第一过孔在所述衬底基板上的正投影，与该第一过孔对应的驱动晶体管中的输出电极在所述衬底基板上的正投影至少部分重叠；所述像素电极通过对应的所述第一过孔和所述第一开口与对应的所述驱动晶体管中的输出电极连接。
  12. 根据权利要求11所述的阵列基板的制作方法，其中，所述在所述像素电极和所述色阻层之间制作平坦层，包括：
    设置所述平坦层在所述衬底基板上的正投影覆盖各所述色阻图形在所述衬底基板上的正投影。
  13. 根据权利要求11或12所述的阵列基板的制作方法，还包括：
    在所述平坦层和所述像素电极之间制作公共电极层，所述公共电极层上形成有第二开口，所述第二开口在所述衬底基板上的正投影，覆盖各所述第一过孔在所述衬底基板上的正投影；
    在所述公共电极层和所述像素电极之间制作第一钝化层，所述第一钝化层上形成有与所述多个驱动晶体管一一对应的多个第二过孔，所述第二过孔在所述衬底基板上的正投影，位于所述第一过孔在所述衬底基板上的正投影的内部，且所述第二过孔在所述衬底基板上的正投影，与该第二过孔对应的驱动晶体管中的输出电极在所述衬底基板上的正投影至少部分重叠；所述像素电极通过对应的所述第二过孔、所述第二开口、对应的所述第一过孔和所述第一开口与对应的所述驱动晶体管中的输出电极连接。
PCT/CN2020/071061 2019-02-22 2020-01-09 阵列基板及其制作方法、显示面板、显示装置 Ceased WO2020168852A1 (zh)

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CN110021653B (zh) * 2019-04-23 2021-02-12 合肥鑫晟光电科技有限公司 阵列基板及其制造方法、显示面板和显示装置
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