WO2020168550A1 - 薄膜晶体管、像素结构、显示装置和制造方法 - Google Patents

薄膜晶体管、像素结构、显示装置和制造方法 Download PDF

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Publication number
WO2020168550A1
WO2020168550A1 PCT/CN2019/075859 CN2019075859W WO2020168550A1 WO 2020168550 A1 WO2020168550 A1 WO 2020168550A1 CN 2019075859 W CN2019075859 W CN 2019075859W WO 2020168550 A1 WO2020168550 A1 WO 2020168550A1
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Prior art keywords
support portion
semiconductor layer
gate
substrate
thin film
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PCT/CN2019/075859
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English (en)
French (fr)
Inventor
强朝辉
关峰
王治
高宇鹏
吕杨
李超
杜建华
陈蕾
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/641,078 priority Critical patent/US11121257B2/en
Priority to CN201980000188.0A priority patent/CN110178226B/zh
Priority to PCT/CN2019/075859 priority patent/WO2020168550A1/zh
Publication of WO2020168550A1 publication Critical patent/WO2020168550A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a thin film transistor, a pixel structure, a display device and a manufacturing method.
  • the thin film transistor can be connected to a light emitting device as a driving transistor for the light emitting device, etc.
  • a thin film transistor which is provided on a substrate and includes: a gate on the substrate; a gate insulating layer covering the gate and the substrate; Substrate and a non-connected first support portion and a second support portion provided on the gate insulating layer on both sides of the gate; in the first support portion, the second support portion, and cover the The semiconductor layer on the gate insulating layer on the gate; the source and the drain respectively connected to the semiconductor layer; wherein the first support portion and the second support portion are used to support the semiconductor layer, respectively .
  • the surfaces of the first supporting portion and the second supporting portion on the side facing away from the substrate and the portion of the gate insulating layer on the gate facing away from the substrate The surface of one side of the bottom is flush; the first supporting portion and the second supporting portion are arranged at the step formed by the gate insulating layer on both sides of the gate, and the first supporting portion and The extension direction of the second support portion is the same as the extension direction of the semiconductor layer.
  • the orthographic projection of the semiconductor layer on the substrate is on the orthographic projection of the gate, the first support portion, and the second support portion on the substrate internal.
  • the source electrode is above the first support portion, and the drain electrode is above the second support portion.
  • the material of the first support portion and the second support portion includes a conductive material, the first support portion serves as the source electrode, and the second support portion serves as the drain electrode.
  • the conductive material includes a metal material; a solid solution of metal and semiconductor material is formed in the regions where the first support portion and the second support portion are in contact with the semiconductor layer, respectively.
  • the metal material includes aluminum; the material of the semiconductor layer includes polysilicon; and the solid solution is a silicon aluminum solid solution.
  • the material of the gate insulating layer includes MgO.
  • a pixel structure including the thin film transistor as described above.
  • an array substrate including the thin film transistor as described above.
  • a display device including the array substrate as described above.
  • a method of manufacturing a thin film transistor including: forming a gate on a substrate; forming a gate insulating layer covering the gate and the substrate; A non-connected first support portion and a second support portion are formed on the gate insulating layer covering the substrate and located on both sides of the gate; in the first support portion, the second support portion and the cover Forming a semiconductor layer on the gate insulating layer on the gate; forming a source and a drain respectively connected to the semiconductor layer; wherein the first supporting portion and the second supporting portion are used to support the ⁇ Semiconductor layer.
  • the manufacturing method further includes: annealing the semiconductor layer.
  • the manufacturing method further includes: doping a region on the first support portion and a region on the second support portion of the semiconductor layer; And forming the source electrode and the drain electrode respectively connected to the semiconductor layer in the doped region, wherein the source electrode and the drain electrode respectively form an ohmic contact with the doped region.
  • the material of the first support portion and the second support portion includes a conductive material, the first support portion serves as the source electrode, and the second support portion serves as the drain electrode.
  • the conductive material includes a metal material; before annealing the semiconductor layer, the material of the semiconductor layer includes amorphous silicon; the step of annealing the semiconductor layer includes: using a laser The annealing process performs an annealing process on the semiconductor layer to convert the amorphous silicon into polysilicon, wherein, through the laser annealing process, the first support portion and the second support portion are respectively connected to the semiconductor layer
  • the layer contact area forms a solid solution of metal and semiconductor material to form an ohmic contact.
  • the metal material includes aluminum; the solid solution is a silicon aluminum solid solution.
  • FIG. 1 is a schematic cross-sectional view showing a thin film transistor according to some embodiments of the present disclosure
  • FIG. 2 is a schematic cross-sectional view showing thin film transistors according to other embodiments of the present disclosure.
  • FIG. 3 is a schematic cross-sectional view showing a pixel structure according to some embodiments of the present disclosure.
  • FIG. 4 is a schematic cross-sectional view showing a pixel structure according to other embodiments of the present disclosure.
  • FIG. 5 is a flowchart showing a method of manufacturing a thin film transistor according to some embodiments of the present disclosure
  • FIG. 6 is a schematic cross-sectional view showing a structure at a stage in the manufacturing process of a thin film transistor according to some embodiments of the present disclosure
  • FIG. 7 is a schematic cross-sectional view showing a structure at a stage in the manufacturing process of a thin film transistor according to some embodiments of the present disclosure
  • FIG. 8 is a schematic cross-sectional view showing a structure at a stage in the manufacturing process of a thin film transistor according to some embodiments of the present disclosure
  • FIG. 9 is a schematic cross-sectional view showing a structure at a stage in the manufacturing process of thin film transistors according to other embodiments of the present disclosure.
  • FIG. 10 is a flowchart illustrating a method of manufacturing a pixel structure according to some embodiments of the present disclosure
  • FIG. 11 is a schematic cross-sectional view showing a structure at a stage in the manufacturing process of a pixel structure according to some embodiments of the present disclosure
  • FIG. 12 is a flowchart showing a method of manufacturing a pixel structure according to other embodiments of the present disclosure.
  • FIG. 13 is a schematic cross-sectional view showing a structure at a stage in a manufacturing process of a pixel structure according to other embodiments of the present disclosure.
  • a specific device when it is described that a specific device is located between the first device and the second device, there may or may not be an intermediate device between the specific device and the first device or the second device.
  • the specific device When it is described that a specific device is connected to another device, the specific device may be directly connected to the other device without an intermediate device, or may not be directly connected to the other device but has an intermediate device.
  • a patterned gate may cause a height difference of the gate insulating layer.
  • a semiconductor layer for example, an amorphous silicon layer
  • a part of the semiconductor layer is at the position of the height difference. The height difference is not conducive to the crystallization of the semiconductor layer, thereby affecting the performance of the formed thin film transistor.
  • the embodiments of the present disclosure provide a thin film transistor to improve the crystallization effect of the semiconductor layer.
  • the thin film transistors according to some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • FIG. 1 is a schematic cross-sectional view showing a thin film transistor according to some embodiments of the present disclosure.
  • the thin film transistor is disposed on a substrate 110.
  • the substrate 110 may include an initial substrate 111 and a buffer layer 112 on the initial substrate 111.
  • the initial substrate 111 may include a glass substrate or the like.
  • the buffer layer 112 may include at least one of a silicon nitride layer and a silicon dioxide layer.
  • the thickness of the silicon nitride layer may range from 30 nm to 80 nm, and the thickness of the silicon dioxide layer may range from 300 nm to 800 nm.
  • the substrate 110 may include the initial substrate 111 but not the buffer layer 112.
  • the thin film transistor includes a gate 120 on the substrate 110.
  • the material of the gate 120 may include a metal material such as molybdenum (Mo).
  • Mo molybdenum
  • the thickness range of the gate 120 can be to
  • the thin film transistor further includes a gate insulating layer 130 covering the gate 120 and the substrate 110.
  • the portion of the gate insulating layer 130 on the substrate 110 and the portion of the gate insulating layer 130 on the gate 120 are integrated.
  • the thickness of the gate insulating layer may range from 100 nm to 500 nm.
  • the gate 120 causes the gate insulating layer 130 to have a height difference H.
  • the thin film transistor further includes a non-connected first support portion 141 and a second support portion 142 provided on the gate insulating layer 130 covering the substrate 110 and located on both sides of the gate 120.
  • the first support portion 141 and the second support portion 142 are on the portion of the gate insulating layer 130 on the substrate 110.
  • the first supporting portion 141 and the second supporting portion 142 are respectively on two sides of the gate 120.
  • the first supporting portion 141 and the gate 120 are separated by the gate insulating layer 130
  • the second supporting portion 142 and the gate 120 are separated by the gate insulating layer 130.
  • the first support portion 141 and the second support portion 142 can reduce the height difference H.
  • the thin film transistor further includes a semiconductor layer 150 on the first support portion 141, the second support portion 142 and the gate insulating layer 130 covering the gate 120.
  • the semiconductor layer 150 is on the side of the first supporting portion 141, the second supporting portion 142 and the gate insulating layer 130 away from the substrate 110.
  • the material of the semiconductor layer 150 may include amorphous silicon or polysilicon.
  • the semiconductor layer 150 can be made of low-temperature polysilicon material.
  • the first supporting portion 141 and the second supporting portion 142 are used to support the semiconductor layer 150 respectively.
  • the thin film transistor also includes a source electrode and a drain electrode respectively connected to the semiconductor layer 150.
  • the materials of the first support portion 141 and the second support portion 142 may include conductive materials.
  • the conductive material may include a metal material (for example, aluminum (Al), etc.).
  • the first supporting portion 141 may serve as the source electrode
  • the second supporting portion 142 may serve as the drain electrode.
  • the first support portion and the second support portion can be used as the source electrode and the drain electrode, respectively, so that there is no need to form an additional source electrode and a drain electrode, which can simplify the device structure.
  • the thin film transistor includes a gate on a substrate.
  • the thin film transistor also includes a gate insulating layer covering the gate and the substrate.
  • the thin film transistor also includes a non-connected first support portion and a second support portion provided on the gate insulating layer covering the substrate and located on both sides of the gate.
  • the thin film transistor further includes a semiconductor layer on the first supporting portion, the second supporting portion, and the gate insulating layer covering the gate.
  • the first supporting portion and the second supporting portion are respectively used for supporting the semiconductor layer.
  • the thin film transistor includes a source electrode and a drain electrode respectively connected to the semiconductor layer. This embodiment can reduce the height difference of the gate insulating layer caused by the gate. In this way, during the manufacturing process, the crystallization effect of the semiconductor layer on the first support portion, the second support portion and the gate insulating layer can be improved, thereby improving the performance of the thin film transistor.
  • the material of the first support portion 141 and the second support portion 142 includes a metal material
  • the area where the first support portion 141 and the second support portion 142 are in contact with the semiconductor layer 150 A solid solution of metal and semiconductor material is formed.
  • the metal material includes aluminum (that is, the material of the first support portion 141 and the second support portion 142 is aluminum)
  • the material of the semiconductor layer includes polysilicon
  • the solid solution of the metal and the semiconductor material is a silicon aluminum solid solution.
  • the solid solution of the metal and the semiconductor material can make the first support portion and the second support portion form ohmic contact with the semiconductor layer respectively, thereby reducing the contact resistance, thereby improving the response speed and performance of the device, and reducing power consumption.
  • the surfaces of the first support portion 141 and the second support portion 142 facing away from the substrate 110 (in FIG. 1, the first support portion 141 is And the upper surface of the second supporting portion 142) is flush with the surface of the portion of the gate insulating layer 130 on the gate 120 facing away from the substrate.
  • the above-mentioned surface of the part of the gate insulating layer is the upper surface of the part of the gate insulating layer 130 on the gate 120.
  • flush herein includes but is not limited to absolute flush.
  • the upper surfaces of the two supporting parts may be higher or lower than the upper surface of the above-mentioned portion of the gate insulating layer, as long as the height difference between these upper surfaces is within an allowable range.
  • the allowable range can be determined according to actual conditions or actual needs.
  • the upper surfaces of the two support parts and the upper surface of the above-mentioned part of the gate insulating layer may not be flush, but the two support parts can also reduce the gate to a certain extent. Since the height difference H of the polar insulating layer, the crystallization effect of the semiconductor layer can also be improved.
  • the first support portion 141 and the second support portion 142 are disposed at the steps formed by the gate insulating layer 130 located on both sides of the gate 120.
  • the first supporting portion 141 and the second supporting portion 142 are disposed at a step formed by the portion of the gate insulating layer 130 on the substrate 110 and the portion of the gate insulating layer 130 on the gate 120 .
  • the extending direction of the first supporting portion 141 and the second supporting portion 142 is the same as the extending direction of the semiconductor layer 150.
  • the semiconductor layer 150 extends along a certain direction parallel to the substrate, and the first support portion 141 and the second support portion 142 also extend along this direction.
  • the thickness of the first support portion 141 and the thickness of the second support portion 142 may be 100 nm to 300 nm, respectively.
  • the thickness of the first support portion and the thickness of the second support portion described herein are only exemplary, and the scope of the embodiments of the present disclosure is not limited thereto.
  • an orthographic projection (not shown in the figure) of the semiconductor layer 150 on the substrate 110 is located on the gate 120, the first support portion 141, and the second support portion 142 is inside the orthographic projection (not shown in the figure) of the three on the substrate 110.
  • the orthographic projection of the gate 120, the first supporting portion 141 and the second supporting portion 142 on the substrate 110 covers the orthographic projection of the semiconductor layer 150 on the substrate 110.
  • a part of the second supporting portion 142 is not covered by the semiconductor layer 150.
  • the uncovered portion of the second support portion 142 may be used to connect with other structures (for example, electrodes of the light emitting device).
  • a part of the first supporting portion 141 may not be covered by the semiconductor layer 150 (not shown in the figure).
  • the material of the gate insulating layer 130 may include an insulating material with a dielectric constant greater than 3.9.
  • the gate insulating layer adopts a material with a relatively large dielectric constant, which can increase the control ability of the gate to the channel, and can change the gray scale under a small voltage change, thereby improving the response speed of the thin film transistor .
  • the material of the gate insulating layer 130 may include MgO and the like.
  • MgO as the gate insulating layer, in addition to increasing the control ability of the gate to the channel to improve the response speed of the thin film transistor, it can also make the gate insulating layer have better heat insulation performance, so that in the manufacturing process In the laser annealing process, the heat can be dissipated relatively slowly, which can improve the crystallization effect of the semiconductor layer.
  • the material of the gate insulating layer 130 may include silicon dioxide or the like.
  • FIG. 2 is a schematic cross-sectional view showing thin film transistors according to other embodiments of the present disclosure.
  • the thin film transistor is disposed on the substrate 110.
  • the thin film transistor shown in FIG. 2 includes a gate 120, a gate insulating layer 130, a first supporting portion 141, a second supporting portion 142 and a semiconductor layer 150.
  • the thin film transistor may further include a source electrode 171 and a drain electrode 172 respectively connected to the semiconductor layer 150.
  • the source electrode 171 and the drain electrode 172 are respectively on the semiconductor layer 150.
  • the source electrode 171 is above the first supporting portion 141.
  • the drain 172 is above the second supporting portion 142.
  • the thin film transistor may further include an interlevel dielectric (ILD) 160.
  • the interlayer dielectric layer 160 covers the gate insulating layer 130, the first supporting portion 141, the second supporting portion 142 and the semiconductor layer 150.
  • the source electrode 171 and the drain electrode 172 respectively pass through the interlayer dielectric layer 160 to be connected to the semiconductor layer 150.
  • thin film transistors according to other embodiments of the present disclosure are provided.
  • a source electrode and a drain electrode respectively connected to the semiconductor layer are provided. In this way, it is not necessary to use the first support portion and the second support portion as the source and drain respectively.
  • the materials of the first support part and the second support part may not be limited to conductive materials.
  • the material of the first support portion and the second support portion may include insulating materials such as silicon nitride or silicon dioxide.
  • the above-mentioned thin film transistor may be a PMOS (P-channel Metal Oxide Semiconductor) transistor or an NMOS (N-channel Metal Oxide Semiconductor, N-channel Metal Oxide Semiconductor) transistor .
  • a pixel structure is also provided.
  • the pixel structure may include the thin film transistor as described above.
  • FIG. 3 is a schematic cross-sectional view showing a pixel structure according to some embodiments of the present disclosure.
  • the pixel structure may include the thin film transistor as shown in FIG.
  • the pixel structure may include a gate 120, a gate insulating layer 130, a first supporting part 141, a second supporting part 142, and a semiconductor layer 150.
  • the pixel structure may further include an electrode (for example, an anode) 220 connected to the first support portion 141 or the second support portion 142.
  • an electrode for example, an anode
  • the electrode 220 is connected to the second supporting portion 142.
  • the pixel structure may further include a functional layer 240 on the side of the electrode 220 away from the thin film transistor.
  • the functional layer 240 is on the surface of the electrode 220.
  • the functional layer 240 may include an electron transport layer, a hole transport layer, a light emitting layer, and the like.
  • the functional layer 240 may also include an electron blocking layer, a hole blocking layer, and the like.
  • the pixel structure also includes electrodes and functional layers.
  • the electrode is connected to the first supporting part or the second supporting part.
  • the pixel structure may further include an interlayer dielectric layer 160.
  • the interlayer dielectric layer 160 covers the gate insulating layer 130, the first supporting portion 141, the second supporting portion 142 and the semiconductor layer 150.
  • the pixel structure may further include a planarization layer (PLN) 210 on the interlayer dielectric layer 160.
  • PPN planarization layer
  • the electrode 220 passes through the planarization layer 210 and the interlayer dielectric layer 160 and is connected to the second support portion 142.
  • a part of the first supporting part 141 or a part of the second supporting part 142 is not covered by the semiconductor layer 150.
  • the electrode 220 is connected to the uncovered portion of the first support portion 141 or the uncovered portion of the second support portion 142.
  • FIG. 3 shows that the electrode 220 is connected to the uncovered part of the second support portion 142.
  • the pixel structure may further include a pixel definition layer (PDL) 230 on the planarization layer 210 and the electrode 220.
  • the functional layer 240 passes through the pixel defining layer 230 and contacts the electrode 220.
  • the pixel structure may further include a photoresist support pillar (Photo Spacer, PS for short) 250 on the pixel defining layer 230.
  • a photoresist support pillar Photo Spacer, PS for short
  • FIG. 4 is a schematic cross-sectional view showing a pixel structure according to other embodiments of the present disclosure.
  • the pixel structure may include a thin film transistor as shown in FIG. 2.
  • the pixel structure may include a gate 120, a gate insulating layer 130, a first supporting part 141, a second supporting part 142, a semiconductor layer 150, an interlayer dielectric layer 160, a source electrode 171, and a drain electrode 172.
  • the pixel structure may further include an electrode (for example, an anode) 220 connected to the source electrode 171 or the drain electrode 172.
  • an electrode for example, an anode
  • the electrode 220 is connected to the drain 172.
  • the pixel structure may further include a functional layer 240 on the side of the electrode 220 facing away from the thin film transistor.
  • the pixel structure also includes electrodes and functional layers.
  • the electrode is connected to the source or drain.
  • the pixel structure may further include a planarization layer 210 covering the interlayer dielectric layer 160, the source electrode 171 and the drain electrode 172.
  • the electrode 220 passes through the planarization layer 210 and is connected to the drain 172.
  • the pixel structure shown in FIG. 4 may also include a pixel defining layer 230 and a photoresist support pillar 250.
  • the materials of the first support portion 141 and the second support portion 142 are conductive materials
  • the first support portion 141 or the second support portion 142 and the gate respectively form a capacitor.
  • a capacitor is also provided, so there is no need to form an additional capacitor.
  • the gate insulating layer 130 uses an insulating material (such as MgO) with a relatively large dielectric constant (such as a dielectric constant greater than 3.9), the occupied area of the capacitor can be reduced. This can reduce the total area of the pixel structure, thereby increasing the PPI (Pixels Per Inch, the number of pixels per inch) of the display panel.
  • an insulating material such as MgO
  • a relatively large dielectric constant such as a dielectric constant greater than 3.9
  • an array substrate is also provided.
  • the array substrate may include the thin film transistor as described above (for example, the thin film transistor shown in FIG. 1 or FIG. 2).
  • the array substrate may also include a substrate.
  • a display device includes the array substrate as described above.
  • the display device may be a display panel, a display, a mobile phone or a tablet computer, etc.
  • FIG. 5 is a flowchart illustrating a method of manufacturing a thin film transistor according to some embodiments of the present disclosure.
  • 6, FIG. 7, FIG. 8 and FIG. 1 are schematic cross-sectional views showing structures at several stages in the manufacturing process of thin film transistors according to some embodiments of the present disclosure.
  • the manufacturing process of the thin film transistor according to some embodiments of the present disclosure will be described in detail below in conjunction with FIG. 5, FIG. 6, FIG. 7, FIG. 8 and FIG. As shown in FIG. 5, the manufacturing method may include steps S502 to S510.
  • step S502 a gate is formed on the substrate.
  • FIG. 6 is a schematic cross-sectional view showing a structure in step S502 in a manufacturing process of a thin film transistor according to some embodiments of the present disclosure.
  • a buffer layer 112 is formed on the initial substrate (for example, a high-temperature glass substrate) 111 by, for example, a chemical vapor deposition process.
  • the buffer layer 112 may include at least one of a silicon nitride layer and a silicon dioxide layer.
  • the thickness of the silicon nitride layer may range from 30 nm to 80 nm
  • the thickness of the silicon dioxide layer may range from 300 nm to 800 nm.
  • a substrate 110 is formed, and the substrate 110 may include an initial substrate 111 and a buffer layer 112. Then, a gate material layer (for example, molybdenum) is formed on the substrate 110 using, for example, a magnetron sputtering technique, and the gate material layer is patterned to form the gate 120.
  • a gate material layer for example, molybdenum
  • the thickness range of the gate 120 may be to
  • step S504 a gate insulating layer covering the gate and the substrate is formed.
  • FIG. 7 is a schematic cross-sectional view showing a structure in step S504 in a manufacturing process of a thin film transistor according to some embodiments of the present disclosure.
  • an electron beam evaporation technique is used to form a gate insulating layer 130 covering the gate 120 and the substrate 110.
  • the portion of the gate insulating layer 130 on the substrate 110 and the portion of the gate insulating layer 130 on the gate 120 are formed integrally.
  • the material of the gate insulating layer may include MgO and the like.
  • the thickness of the gate insulating layer may range from 100 nm to 500 nm.
  • step S506 a non-connected first support portion and a second support portion are formed on the gate insulating layer covering the substrate and located on both sides of the gate.
  • FIG. 8 is a schematic cross-sectional view showing a structure in step S506 in the manufacturing process of a thin film transistor according to some embodiments of the present disclosure. As shown in FIG. 8, a non-connected first supporting portion 141 and a second supporting portion 142 are formed on the gate insulating layer 130 covering the substrate 110 and located on both sides of the gate 120.
  • a mask may be formed on the gate insulating layer 130, the mask exposing a part of the gate insulating layer 130 (that is, the part on which the first support portion and the second support portion need to be formed). Then, a first support portion 141 and a second support portion 142 are formed on the exposed portion of the gate insulating layer 130 by a deposition process. The mask is then removed, thereby forming the structure shown in FIG. 8.
  • a deposition process is used to form a support material layer (for example, Al) on the side of the gate insulating layer 130 away from the substrate 110, and then the support material layer is patterned to form the first support 141 and the second support 141 Support 142.
  • a support material layer for example, Al
  • the patterned first support portion and the second support portion are respectively in contact with the semiconductor layer to define a contact area. Between the contact regions is the channel region, which defines the actual channel region.
  • the first supporting portion 141 and the second supporting portion 142 are respectively on two sides of the gate 120.
  • the thickness range of the first support portion 141 and the thickness range of the second support portion 142 may be 100 nm to 300 nm, respectively.
  • the first supporting portion 141 and the gate 120 are separated by the gate insulating layer 130, and the second supporting portion 142 and the gate 120 are separated by the gate insulating layer 130.
  • the materials of the first support portion 141 and the second support portion 142 include conductive materials. That is, the material of the support material layer may include a conductive material.
  • the conductive material may include a metal material (such as aluminum).
  • the first supporting portion 141 may serve as a source electrode, and the second supporting portion 142 may serve as a drain electrode.
  • step S508 a semiconductor layer is formed on the first support portion, the second support portion, and the gate insulating layer covering the gate.
  • the first supporting portion and the second supporting portion are respectively used for supporting the semiconductor layer.
  • FIG. 1 is a schematic cross-sectional view showing a structure in step S508 in a manufacturing process of a thin film transistor according to some embodiments of the present disclosure.
  • a semiconductor layer 150 for example, an amorphous silicon layer
  • And patterning the semiconductor layer 150 is formed on the first supporting portion 141, the second supporting portion 142, and the gate insulating layer 130 covering the gate 120, for example, by a deposition process. , And patterning the semiconductor layer 150.
  • the manufacturing method may further include: annealing the semiconductor layer 150.
  • the material of the semiconductor layer may include amorphous silicon.
  • a laser annealing process for example, a microlens array laser local crystallization technology
  • the annealing treatment can crystallize the semiconductor layer.
  • the above-mentioned first support portion and the second support portion facilitate the semiconductor layer to be at the same focal plane of the laser, thereby improving the crystallization effect of the semiconductor layer and improving the performance of the thin film transistor.
  • a solid solution of metal and semiconductor material is formed in the regions where the first support portion 141 and the second support portion 142 respectively contact the semiconductor layer 150 to form an ohmic contact.
  • the metal material of the first support portion 141 and the second support portion 142 may include aluminum
  • the solid solution may be a silicon aluminum solid solution.
  • laser annealing is performed on the contact area to form a solid solution of metal and semiconductor material (for example, a silicon-aluminum solid solution), and therefore an ohmic contact is formed in a self-aligned manner.
  • a solid solution of metal and semiconductor material for example, a silicon-aluminum solid solution
  • an ohmic contact is formed in a self-aligned manner.
  • the process of forming an ohmic contact can solve the problem of photoresist carbonization pollution caused by heavy doping to form an ohmic contact in the related art.
  • step S510 the source and drain respectively connected to the semiconductor layer are formed.
  • the materials of the first support portion 141 and the second support portion 142 include conductive materials.
  • the first supporting portion 141 can serve as the source electrode, and the second supporting portion 142 can serve as the drain electrode. In this case, in the case of forming the first support portion and the second support portion, the source electrode and the drain electrode are formed.
  • a method of manufacturing a thin film transistor is provided.
  • a gate is formed on a substrate.
  • a gate insulating layer covering the gate and the substrate is formed.
  • a non-connected first supporting portion and a second supporting portion are formed on the gate insulating layer covering the substrate and located on both sides of the gate.
  • a semiconductor layer is formed on the first supporting portion, the second supporting portion and the gate insulating layer covering the gate.
  • a source electrode and a drain electrode respectively connected to the semiconductor layer are formed.
  • the first supporting portion and the second supporting portion are respectively used for supporting the semiconductor layer.
  • the gate insulating layer can make the gate insulating layer have better heat insulation performance, so that the heat can be dissipated relatively slowly during the laser annealing process, thereby improving the crystallization effect of the semiconductor layer.
  • the first support portion and the second support portion may not serve as the source electrode and the drain electrode.
  • the manufacturing method may further include: forming a source electrode and a drain electrode respectively connected to the semiconductor layer.
  • the structure shown in FIG. 9 can be formed through the steps of the method shown in FIG. 5.
  • the material of the semiconductor layer 150 is amorphous silicon.
  • the material of the first support part 141 and the second support part 142 may include a conductive material or an insulating material. Then the semiconductor layer 150 is annealed, for example, to convert amorphous silicon into polycrystalline silicon.
  • the source electrode 171 and the drain electrode 172 respectively connected to the semiconductor layer 150 are formed.
  • the process of forming the source and drain is described in detail below.
  • the manufacturing method may further include: doping the region on the first support portion and the region on the second support portion of the semiconductor layer.
  • an interlayer dielectric layer 160 covering the structure shown in FIG. 9 may be formed.
  • the material of the interlayer dielectric layer 160 may include at least one of silicon dioxide and silicon nitride.
  • the thickness range of the interlayer dielectric layer is to Then, etching is performed on the interlayer dielectric layer 160 to form two through holes exposing the semiconductor layer 150.
  • the two through holes respectively expose the area on the first support portion and the area on the second support portion of the semiconductor layer.
  • the semiconductor layer 150 is doped through these two through holes.
  • the manufacturing method may further include: forming a source electrode and a drain electrode respectively connected to the semiconductor layer in the doped region.
  • the source and the drain respectively form ohmic contacts with the doped regions.
  • the source electrode 171 passing through one of the two via holes and the drain electrode 172 passing through the other via hole are formed by processes such as deposition and patterning. In this way, a thin film transistor as shown in FIG. 2 can be formed.
  • FIG. 10 is a flowchart illustrating a method of manufacturing a pixel structure according to some embodiments of the present disclosure. As shown in FIG. 10, the manufacturing method includes steps S1002 to S1014.
  • a gate is formed on the substrate.
  • the gate 120 may be formed on the substrate 110 by processes such as deposition and patterning, thereby forming the structure shown in FIG. 6.
  • a gate insulating layer covering the gate and the substrate is formed.
  • a gate insulating layer 130 covering the gate 120 and the substrate 110 is formed.
  • the portion of the gate insulating layer 130 on the substrate 110 and the portion of the gate insulating layer 130 on the gate 120 are formed integrally. In this way, the structure shown in FIG. 7 is formed.
  • a non-connected first supporting portion and a second supporting portion are formed on the gate insulating layer covering the substrate and located on both sides of the gate.
  • a non-connected first support portion 141 and a second support portion 142 are formed on the gate insulating layer 130 covering the substrate 110 and located on both sides of the gate 120 by using processes such as deposition and patterning.
  • a semiconductor layer is formed on the first supporting portion, the second supporting portion, and the gate insulating layer covering the gate.
  • a semiconductor layer 150 is formed on the first supporting part 141, the second supporting part 142 and the gate insulating layer 130 covering the gate 120 through a deposition and patterning process.
  • the first supporting portion 141 and the second supporting portion 142 are used to support the semiconductor layer 150 respectively.
  • annealing treatment is performed on the semiconductor layer 150.
  • step S1010 source and drain electrodes respectively connected to the semiconductor layer are formed.
  • processes such as deposition and patterning may be used to form the source electrode 171 and the drain electrode 172 respectively connected to the semiconductor layer 150 to form the structure shown in FIG. 2.
  • the interlayer dielectric layer 160 covering the structure shown in FIG. 9 may be formed first, and then the source electrode 171 and the drain electrode 172 that pass through the interlayer dielectric layer 160 and are respectively connected to the semiconductor layer 150 are formed.
  • an electrode connected to the source or drain is formed.
  • the electrode is an anode.
  • a planarization layer 210 may be formed on the structure shown in FIG. 2 to perform a planarization process. Then, the planarization layer 210 is etched to form an opening exposing the drain electrode 172 (or the source electrode 171). The electrode 220 passing through the opening and connected to the drain electrode 172 (or the source electrode 171) is formed by a process such as deposition.
  • a functional layer is formed on the side of the electrode away from the substrate.
  • the pixel defining layer 230 may be formed on the structure shown in FIG. 11 by using processes such as deposition and patterning, and then a functional layer 240 passing through the pixel defining layer and in contact with the electrode 220 may be formed, thereby forming the structure shown in FIG. structure.
  • photoresist support pillars 250 may also be formed on the pixel defining layer 220.
  • a method of manufacturing a pixel structure according to some embodiments of the present disclosure is provided.
  • the first supporting portion and the second supporting portion are formed, the height difference of the gate insulating layer caused by the gate is reduced, which is beneficial for the semiconductor layer to be in the same focal plane of the laser, thereby improving the semiconductor The crystalline quality of the layer.
  • FIG. 12 is a flowchart illustrating a method of manufacturing a pixel structure according to other embodiments of the present disclosure. As shown in FIG. 12, the manufacturing method may include steps S1202 to S1212.
  • a gate is formed on the substrate.
  • the gate 120 may be formed on the substrate 110 by processes such as deposition and patterning, thereby forming the structure shown in FIG. 6.
  • a gate insulating layer covering the gate and the substrate is formed.
  • a gate insulating layer covering the gate 120 and the substrate 110 is formed.
  • the portion of the gate insulating layer 130 on the substrate 110 and the portion of the gate insulating layer 130 on the gate 120 are formed integrally. In this way, the structure shown in FIG. 7 is formed.
  • a non-connected first support portion and a second support portion are formed on the gate insulating layer covering the substrate and located on both sides of the gate. For example, using processes such as deposition and patterning to form a non-connected first support portion 141 and a second support portion 142 on the gate insulating layer 130 covering the substrate 110 and located on both sides of the gate electrode 120, thereby forming as shown in FIG. The structure shown.
  • the first supporting portion 141 and the second supporting portion 142 are respectively on two sides of the gate 120.
  • the material of the first support portion 141 and the second support portion 142 may include a conductive material (for example, a metal material).
  • the first supporting portion 141 may serve as a source electrode
  • the second supporting portion 142 may serve as a drain electrode.
  • a semiconductor layer is formed on the first supporting portion, the second supporting portion, and the gate insulating layer covering the gate.
  • the semiconductor layer 150 is formed on the first support portion 141, the second support portion 142, and the gate insulating layer 130 covering the gate 120 by processes such as deposition and patterning, thereby forming the structure shown in FIG. 1.
  • the first supporting portion 141 and the second supporting portion 142 are used to support the semiconductor layer 150 respectively.
  • annealing treatment is performed on the semiconductor layer 150.
  • the annealing treatment can crystallize the semiconductor layer.
  • a solid solution of metal and semiconductor material is formed in the regions where the first support portion 141 and the second support portion 142 respectively contact the semiconductor layer 150, thereby forming an ohmic contact.
  • step S1210 an electrode connected to the first support part or the second support part is formed.
  • the electrode is an anode.
  • the interlayer dielectric layer 160 may be formed on the structure shown in FIG. 1 by a process such as deposition.
  • the thickness range of the interlayer dielectric layer 160 can be to
  • the interlayer dielectric layer 160 is etched to form a first through hole exposing the second support portion 142 (or the first support portion 141).
  • a planarization layer 210 is formed on the interlayer dielectric layer 160.
  • the planarization layer 210 is etched to form a second through hole, and the second through hole is aligned with the first through hole.
  • the electrode 220 passing through the second through hole and the first through hole and contacting the second support portion 142 (or the first support portion 141) is formed by a process such as deposition.
  • step S1212 a functional layer is formed on the side of the electrode away from the substrate.
  • the pixel defining layer 230 may be formed on the structure shown in FIG. 13 using processes such as deposition and patterning, and then a functional layer 240 passing through the pixel defining layer 230 and in contact with the electrode 220 may be formed, thereby forming the structure shown in FIG. Structure.
  • photoresist support pillars 250 may also be formed on the pixel defining layer 220.
  • the first support portion and the second support portion are formed, the height difference of the gate insulating layer caused by the gate is reduced, which is beneficial for the semiconductor layer to be at the same focal plane of the laser, thereby improving the semiconductor The crystalline quality of the layer.
  • the first supporting portion can be used as a source and the second supporting portion can be used as a drain, thereby simplifying the process flow.

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Abstract

本公开提供了一种薄膜晶体管、像素结构、显示装置和制造方法，涉及显示技术领域。该薄膜晶体管包括栅极、栅极绝缘层、第一支撑部、第二支撑部、半导体层、源极和漏极。该栅极在衬底上。该栅极绝缘层覆盖在栅极和衬底上。第一支撑部和第二支撑部设置在覆盖衬底且位于栅极两侧的栅极绝缘层上。第一支撑部和第二支撑部非连接。半导体层在第一支撑部、第二支撑部和覆盖在栅极上的栅极绝缘层上。源极和漏极与该半导体层分别连接。该第一支撑部和该第二支撑部分别用于支撑半导体层。本公开可以提高半导体层的结晶效果。

Description

薄膜晶体管、像素结构、显示装置和制造方法 技术领域
本公开涉及显示技术领域，特别涉及一种薄膜晶体管、像素结构、显示装置和制造方法。
背景技术
在显示技术领域，常常需要在衬底上形成薄膜晶体管。例如，该薄膜晶体管可以与发光器件连接，作为用于发光器件的驱动晶体管等。
发明内容
根据本公开实施例的一个方面，提供了一种薄膜晶体管，设置于衬底上，包括：在衬底上的栅极；覆盖在栅极和衬底上的栅极绝缘层；在覆盖所述衬底且位于所述栅极两侧的栅极绝缘层上设置的非连接的第一支撑部和第二支撑部；在所述第一支撑部、所述第二支撑部和覆盖在所述栅极上的栅极绝缘层上的半导体层；与所述半导体层分别连接的源极和漏极；其中，所述第一支撑部和所述第二支撑部分别用于支撑所述半导体层。
在一些实施例中，所述第一支撑部和所述第二支撑部的背离所述衬底的一侧的表面与所述栅极绝缘层在所述栅极上的部分的背离所述衬底的一侧的表面齐平；所述第一支撑部和所述第二支撑部设置在位于所述栅极两侧的栅极绝缘层所形成的台阶处，且所述第一支撑部和所述第二支撑部的延伸方向与所述半导体层的延伸方向相同。
在一些实施例中，所述半导体层在所述衬底上的正投影位于所述栅极、所述第一支撑部和所述第二支撑部这三者在所述衬底上的正投影的内部。
在一些实施例中，所述源极在所述第一支撑部的上方，所述漏极在所述第二支撑部的上方。
在一些实施例中，所述第一支撑部和所述第二支撑部的材料包括导电材料，所述第一支撑部作为所述源极，所述第二支撑部作为所述漏极。
在一些实施例中，所述导电材料包括金属材料；在所述第一支撑部和所述第二支撑部分别与所述半导体层接触的区域形成有金属与半导体材料的固溶体。
在一些实施例中，所述金属材料包括铝；所述半导体层的材料包括多晶硅；所述 固溶体为硅铝固溶体。
在一些实施例中，所述栅极绝缘层的材料包括MgO。
根据本公开实施例的另一个方面，提供了一种像素结构，包括如前所述的薄膜晶体管。
根据本公开实施例的另一个方面，提供了一种阵列基板，包括如前所述的薄膜晶体管。
根据本公开实施例的另一个方面，提供了一种显示装置，包括如前所述的阵列基板。
根据本公开实施例的另一个方面，提供了一种薄膜晶体管的制造方法，包括：在衬底上形成栅极；形成覆盖在所述栅极和所述衬底上的栅极绝缘层；在覆盖所述衬底且位于所述栅极两侧的栅极绝缘层上形成非连接的第一支撑部和第二支撑部；在所述第一支撑部、所述第二支撑部和覆盖在所述栅极上的栅极绝缘层上形成半导体层；形成与所述半导体层分别连接的源极和漏极；其中，所述第一支撑部和所述第二支撑部分别用于支撑所述半导体层。
在一些实施例中，所述制造方法还包括：对所述半导体层进行退火处理。
在一些实施例中，在进行退火处理之后，所述制造方法还包括：对所述半导体层的在所述第一支撑部上的区域和在所述第二支撑部上的区域进行掺杂；以及在掺杂区域形成与所述半导体层分别连接的所述源极和所述漏极，其中，所述源极和所述漏极分别与所述掺杂区域形成欧姆接触。
在一些实施例中，所述第一支撑部和所述第二支撑部的材料包括导电材料，所述第一支撑部作为所述源极，所述第二支撑部作为所述漏极。
在一些实施例中，所述导电材料包括金属材料；在对所述半导体层进行退火处理之前，所述半导体层的材料包括非晶硅；对所述半导体层进行退火处理的步骤包括：利用激光退火工艺对所述半导体层进行退火处理以使得所述非晶硅转化成多晶硅，其中，通过所述激光退火工艺，还在所述第一支撑部和所述第二支撑部分别与所述半导体层接触的区域形成金属与半导体材料的固溶体以形成欧姆接触。
在一些实施例中，所述金属材料包括铝；所述固溶体为硅铝固溶体。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是示出根据本公开一些实施例的薄膜晶体管的截面示意图；
图2是示出根据本公开另一些实施例的薄膜晶体管的截面示意图；
图3是示出根据本公开一些实施例的像素结构的截面示意图；
图4是示出根据本公开另一些实施例的像素结构的截面示意图；
图5是示出根据本公开一些实施例的薄膜晶体管的制造方法的流程图；
图6是示出根据本公开一些实施例的薄膜晶体管的制造过程中一个阶段的结构的截面示意图；
图7是示出根据本公开一些实施例的薄膜晶体管的制造过程中一个阶段的结构的截面示意图；
图8是示出根据本公开一些实施例的薄膜晶体管的制造过程中一个阶段的结构的截面示意图；
图9是示出根据本公开另一些实施例的薄膜晶体管的制造过程中一个阶段的结构的截面示意图；
图10是示出根据本公开一些实施例的像素结构的制造方法的流程图；
图11是示出根据本公开一些实施例的像素结构的制造过程中一个阶段的结构的截面示意图；
图12是示出根据本公开另一些实施例的像素结构的制造方法的流程图；
图13是示出根据本公开另一些实施例的像素结构的制造过程中一个阶段的结构的截面示意图。
应当明白，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且 完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定器件位于第一器件和第二器件之间时，在该特定器件与第一器件或第二器件之间可以存在居间器件，也可以不存在居间器件。当描述到特定器件连接其它器件时，该特定器件可以与所述其它器件直接连接而不具有居间器件，也可以不与所述其它器件直接连接而具有居间器件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
本公开的发明人发现，在相关技术中，在形成具有底栅结构的薄膜晶体管的过程中，图案化的栅极会造成栅极绝缘层具有高度差。在该栅极绝缘层上形成半导体层(例如非晶硅层)的过程中，该半导体层的一部分处于该高度差的位置处。该高度差不利于在该半导体层的结晶，从而影响所形成的薄膜晶体管的性能。
鉴于此，本公开的实施例提供了一种薄膜晶体管，以提高半导体层的结晶效果。下面结合附图详细描述根据本公开一些实施例的薄膜晶体管。
图1是示出根据本公开一些实施例的薄膜晶体管的截面示意图。
例如，如图1所示，该薄膜晶体管设置在衬底110上。在一些实施例中，该衬底110可以包括初始衬底111和在该初始衬底111上的缓冲层112。例如，该初始衬底111可以包括玻璃基板等。例如，该缓冲层112可以包括氮化硅层和二氧化硅层中的至少一种。例如，该氮化硅层的厚度范围可以是30nm至80nm，该二氧化硅层的厚度范围可以是300nm至800nm。在另一些实施例中，该衬底110可以包括初始衬底 111而不包括缓冲层112。
如图1所示，该薄膜晶体管包括在该衬底110上的栅极120。例如，该栅极120的材料可以包括诸如钼(Mo)等金属材料。该栅极120的厚度范围可以是
Figure PCTCN2019075859-appb-000001
至
Figure PCTCN2019075859-appb-000002
如图1所示，该薄膜晶体管还包括覆盖在该栅极120和该衬底110上的栅极绝缘层130。该栅极绝缘层130在该衬底110上的部分与该栅极绝缘层130在该栅极120上的部分是一体的。例如，该栅极绝缘层的厚度范围可以为100nm至500nm。如图1所示，该栅极120造成栅极绝缘层130具有高度差H。
如图1所示，该薄膜晶体管还包括在覆盖衬底110且位于栅极120两侧的栅极绝缘层130上设置的非连接的第一支撑部141和第二支撑部142。该第一支撑部141和该第二支撑部142在该栅极绝缘层130在该衬底110上的部分上。该第一支撑部141和该第二支撑部142分别在该栅极120的两边。例如，该第一支撑部141与该栅极120被该栅极绝缘层130隔离开，该第二支撑部142与该栅极120被该栅极绝缘层130隔离开。该第一支撑部141和该第二支撑部142可以减小该高度差H。
如图1所示，该薄膜晶体管还包括在第一支撑部141、第二支撑部142和覆盖在栅极120上的栅极绝缘层130上的半导体层150。该半导体层150在该第一支撑部141、该第二支撑部142和该栅极绝缘层130的背离衬底110的一侧。例如，该半导体层150的材料可以包括非晶硅或多晶硅等。例如，该半导体层150可以采用低温多晶硅材料。上述第一支撑部141和第二支撑部142分别用于支撑该半导体层150。
该薄膜晶体管还包括与半导体层150分别连接的源极和漏极。在一些实施例中，该第一支撑部141和该第二支撑部142的材料可以包括导电材料。例如该导电材料可以包括金属材料(例如铝(Al)等)。例如，该第一支撑部141可以作为该源极，该第二支撑部142可以作为该漏极。在该实施例中，第一支撑部和第二支撑部可以分别作为源极和漏极，这样不需要额外形成源极和漏极，可以简化器件结构。
至此，上述实施例提供了一种薄膜晶体管。该薄膜晶体管包括在衬底上的栅极。该薄膜晶体管还包括覆盖在栅极和衬底上的栅极绝缘层。该薄膜晶体管还包括在覆盖衬底且位于栅极两侧的栅极绝缘层上设置的非连接的第一支撑部和第二支撑部。该薄膜晶体管还包括在第一支撑部、第二支撑部和覆盖在栅极上的栅极绝缘层上的半导体层。该第一支撑部和该第二支撑部分别用于支撑该半导体层。该薄膜晶体管包括与该半导体层分别连接的源极和漏极。该实施例可以减小栅极所造成的栅极绝缘层的高度 差。这样在制造过程中，可以提高在第一支撑部、第二支撑部和栅极绝缘层上的半导体层的结晶效果，从而改善薄膜晶体管的性能。
在一些实施例中，在第一支撑部141和第二支撑部142的材料包括金属材料的情况下，在该第一支撑部141和该第二支撑部142分别与该半导体层150接触的区域形成有金属与半导体材料的固溶体。例如，该金属材料包括铝(即第一支撑部141和第二支撑部142的材料为铝)，半导体层的材料包括多晶硅，则该金属与半导体材料的固溶体为硅铝固溶体。该金属与半导体材料的固溶体可以使得第一支撑部和第二支撑部分别与半导体层形成欧姆接触，降低接触电阻，从而提高器件的响应速度和性能，并可以降低功耗。
在一些实施例中，如图1所示，该第一支撑部141和该第二支撑部142的背离该衬底110的一侧的表面(在图1中，即为该第一支撑部141和该第二支撑部142的上表面)与该栅极绝缘层130在该栅极120上的部分的背离该衬底的一侧的表面齐平。在图1中，该栅极绝缘层的该部分的上述表面即为该栅极绝缘层130在该栅极120上的部分的上表面。通过使得这两个支撑部的上表面与栅极绝缘层的上述部分的上表面齐平，从而有利于在制造过程中提高半导体层的结晶效果。
需要说明的是，这里的术语“齐平”包括但不限于绝对的齐平。例如，这两个支撑部的上表面可以高于或低于栅极绝缘层的上述部分的上表面，只要这些上表面之间的高度差在允许的范围内即可。该允许的范围可以根据实际情况或实际需求来确定。
还需要说明的是，在一些情况下，这两个支撑部的上表面与栅极绝缘层的上述部分的上表面可以不齐平，但这两个支撑部在一定程度上也可以减小栅极绝缘层的高度差H，因此，也可以提高半导体层的结晶效果。
在一些实施例中，该第一支撑部141和该第二支撑部142设置在位于栅极120两侧的栅极绝缘层130所形成的台阶处。或者说，该第一支撑部141和该第二支撑部142设置在该栅极绝缘层130在衬底110上的部分和该栅极绝缘层130在栅极120上的部分所形成的台阶处。该第一支撑部141和该第二支撑部142的延伸方向与该半导体层150的延伸方向相同。例如，该半导体层150沿着平行于衬底的某个方向延伸，该第一支撑部141和该第二支撑部142也沿着该方向延伸。
在一些实施例中，该第一支撑部141的厚度和该第二支撑部142的厚度可以分别为100nm至300nm。当然，本领域技术人员应该理解，这里所描述的第一支撑部的厚度和第二支撑部的厚度仅是示例性的，本公开实施例的范围并不仅限于此。
在一些实施例中，如图1所示，该半导体层150在该衬底110上的正投影(图中未示出)位于该栅极120、该第一支撑部141和该第二支撑部142这三者在该衬底110上的正投影(图中未示出)的内部。或者说，该栅极120、该第一支撑部141和该第二支撑部142这三者在该衬底110上的正投影覆盖该半导体层150在该衬底110上的正投影。
在一些实施例中，如图1所示，该第二支撑部142的一部分未被该半导体层150覆盖。该第二支撑部142未被覆盖的该部分可以用于与其他结构(例如发光器件的电极)连接。在另一些实施例中，该第一支撑部141的一部分可以未被该半导体层150覆盖(图中未示出)。
在一些实施例中，该栅极绝缘层130的材料可以包括介电常数大于3.9的绝缘材料。在该实施例中，栅极绝缘层采用介电常数比较大的材料，这可以增加栅极对沟道的控制能力，可以在较小的电压变化下改变灰阶，从而提高薄膜晶体管的响应速度。
例如，该栅极绝缘层130的材料可以包括MgO等。采用例如MgO等作为栅极绝缘层，除了增加栅极对沟道的控制能力以提高薄膜晶体管的响应速度之外，还可以使得栅极绝缘层具有更好的隔热性能，这样在制造过程中的激光退火的工艺中，可以比较慢地散热，从而可以提高半导体层的结晶效果。
在另一些实施例中，该栅极绝缘层130的材料可以包括二氧化硅等。
图2是示出根据本公开另一些实施例的薄膜晶体管的截面示意图。该薄膜晶体管设置在衬底110上。
与图1所示的薄膜晶体管类似地，该图2所示的薄膜晶体管包括：栅极120、栅极绝缘层130、第一支撑部141、第二支撑部142和半导体层150。如图2所示，该薄膜晶体管还可以包括与该半导体层150分别连接的源极171和漏极172。该源极171和该漏极172分别在该半导体层150上。该源极171在该第一支撑部141的上方。该漏极172在该第二支撑部142的上方。
在一些实施例中，如图2所示，该薄膜晶体管还可以包括层间电介质层(Interlevel Dielectric，简称为ILD)160。该层间电介质层160覆盖在该栅极绝缘层130、该第一支撑部141、该第二支撑部142和该半导体层150上。该源极171和该漏极172分别穿过该层间电介质层160从而与半导体层150连接。
在上述实施例中，提供了根据本公开另一些实施例的薄膜晶体管。在该薄膜晶体管中，设置了分别与半导体层连接的源极和漏极。这样不需要将第一支撑部和第二支 撑部分别作为源极和漏极。
在该实施例中，由于第一支撑部和第二支撑部可以不作为源极和漏极，因此，该第一支撑部和该第二支撑部的材料可以不限于为导电材料。例如，该第一支撑部和该第二支撑部的材料可以包括诸如氮化硅或二氧化硅等绝缘材料。
在一些实施例中，上述薄膜晶体管可以是PMOS(P-channel Metal Oxide Semiconductor，P型沟道金属氧化物半导体)晶体管或NMOS(N-channel Metal Oxide Semiconductor，N型沟道金属氧化物半导体)晶体管。
在本公开的一些实施例中，还提供了一种像素结构。该像素结构可以包括如前所述的薄膜晶体管。
图3是示出根据本公开一些实施例的像素结构的截面示意图。
如图3所示，该像素结构可以包括如图1所示的薄膜晶体管。例如，该像素结构可以包括栅极120、栅极绝缘层130、第一支撑部141、第二支撑部142和半导体层150。
在一些实施例中，该像素结构还可以包括与第一支撑部141或第二支撑部142连接的电极(例如阳极)220。例如，如图3所示，该电极220与第二支撑部142连接。
在一些实施例中，如图3所示，该像素结构还可以包括在电极220的背离该薄膜晶体管的一侧的功能层240。例如该功能层240在该电极220的表面上。例如该功能层240可以包括电子传输层、空穴传输层和发光层等。又例如，该功能层240还可以包括电子阻挡层和空穴阻挡层等。
至此，提供了根据本公开一些实施例中的像素结构。该像素结构除了包括薄膜晶体管之外，还包括电极和功能层。该电极与第一支撑部或第二支撑部连接。
在一些实施例中，如图3所示，该像素结构还可以包括层间电介质层160。该层间电介质层160覆盖在该栅极绝缘层130、该第一支撑部141、该第二支撑部142和该半导体层150上。该像素结构还可以包括在该层间电介质层160上的平坦化层(Planarization layer，简称为PLN)210。
如图3所示，该电极220穿过该平坦化层210和该层间电介质层160并与第二支撑部142连接。例如，第一支撑部141的一部分或第二支撑部142的一部分未被该半导体层150覆盖。该电极220与该第一支撑部141未被覆盖的该部分或该第二支撑部142未被覆盖的该部分连接。图3示出了该电极220与该第二支撑部142未被覆盖的部分连接。
在一些实施例中，如图3所示，该像素结构还可以包括在平坦化层210和电极220 上的像素界定层(Pixel Definition Layer，简称为PDL)230。该功能层240穿过该像素界定层230并与电极220接触。
在一些实施例中，如图3所示，该像素结构还可以包括在像素界定层230上的光阻支撑柱(Photo Spacer，简称为PS)250。
图4是示出根据本公开另一些实施例的像素结构的截面示意图。
如图4所示，该像素结构可以包括如图2所示的薄膜晶体管。例如，该像素结构可以包括栅极120、栅极绝缘层130、第一支撑部141、第二支撑部142、半导体层150、层间电介质层160、源极171和漏极172。
在一些实施例中，该像素结构还可以包括与源极171或漏极172连接的电极(例如阳极)220。例如，如图4所示，该电极220与漏极172连接。
在一些实施例中，如图4所示，该像素结构还可以包括在该电极220的背离该薄膜晶体管的一侧的功能层240。
至此，提供了根据本公开另一些实施例中的像素结构。该像素结构除了包括薄膜晶体管之外，还包括电极和功能层。该电极与源极或漏极连接。
在一些实施例，如图4所示，该像素结构还可以包括覆盖在层间电介质层160、源极171和漏极172上的平坦化层210。该电极220穿过该平坦化层210并与漏极172连接。另外，与图3所示像素结构类似地，图4所示的像素结构也可以包括像素界定层230和光阻支撑柱250。
在一些实施例中，在第一支撑部141和第二支撑部142的材料为导电材料的情况下，该第一支撑部141或该第二支撑部142分别与栅极形成电容器。这样在上述像素结构中，还提供了电容器，因而不需要额外形成电容器。
在栅极绝缘层130采用介电常数比较大(例如介电常数大于3.9)的绝缘材料(例如MgO)的情况下，可以减小上述电容器的占据面积。这样可以减小像素结构的总面积，从而可以提高显示面板的PPI(Pixels Per Inch，每英寸的像素数量)。
在本公开的一些实施例中，还提供了一种阵列基板。该阵列基板可以包括如前所述的薄膜晶体管(例如如图1或图2所示的薄膜晶体管)。例如，该阵列基板还可以包括衬底。
在本公开的一些实施例中，还提供了一种显示装置。该显示装置包括如前所述的阵列基板。例如，该显示装置可以是显示面板、显示器、手机或平板电脑等。
图5是示出根据本公开一些实施例的薄膜晶体管的制造方法的流程图。图6、图 7、图8和图1是示出根据本公开一些实施例的薄膜晶体管的制造过程中若干阶段的结构的截面示意图。下面结合图5、图6、图7、图8和图1详细描述根据本公开一些实施例的薄膜晶体管的制造过程。如图5所示，该制造方法可以包括步骤S502至S510。
如图5所示，在步骤S502，在衬底上形成栅极。
图6是示出根据本公开一些实施例的薄膜晶体管的制造过程中在步骤S502的结构的截面示意图。如图6所示，例如通过化学气相沉积工艺在初始衬底(例如高温玻璃基板)111上形成缓冲层112。例如，该缓冲层112可以包括氮化硅层和二氧化硅层中的至少一种。例如，该氮化硅层的厚度范围可以是30nm至80nm，该二氧化硅层的厚度范围可以是300nm至800nm。经过上述工艺流程，形成了衬底110，该衬底110可以包括初始衬底111和缓冲层112。然后例如利用磁控溅射技术在该衬底110上形成栅极材料层(例如钼)，并对该栅极材料层执行图案化以形成栅极120。例如，该栅极120的厚度范围可以是
Figure PCTCN2019075859-appb-000003
至
Figure PCTCN2019075859-appb-000004
回到图5，在步骤S504，形成覆盖在栅极和衬底上的栅极绝缘层。
图7是示出根据本公开一些实施例的薄膜晶体管的制造过程中在步骤S504的结构的截面示意图。如图7所示，例如利用电子束蒸发技术形成覆盖在栅极120和衬底110上的栅极绝缘层130。该栅极绝缘层130在该衬底110上的部分与该栅极绝缘层130在该栅极120上的部分是一体形成的。例如该栅极绝缘层的材料可以包括MgO等。例如，该栅极绝缘层的厚度范围可以为100nm至500nm。
回到图5，在步骤S506，在覆盖衬底且位于栅极两侧的栅极绝缘层上形成非连接的第一支撑部和第二支撑部。
图8是示出根据本公开一些实施例的薄膜晶体管的制造过程中在步骤S506的结构的截面示意图。如图8所示，在覆盖衬底110且位于栅极120两侧的栅极绝缘层130上形成非连接的第一支撑部141和第二支撑部142。
例如，可以在栅极绝缘层130上形成掩模，该掩模露出该栅极绝缘层130的一部分(即需要在其上形成第一支撑部和第二支撑部的部分)。然后通过沉积工艺在该栅极绝缘层130的被露出部分上形成第一支撑部141和第二支撑部142。然后去除该掩模，从而形成图8所示的结构。
又例如，利用沉积工艺在栅极绝缘层130的背离衬底110的一侧形成支撑部材料层(例如Al)，然后对该支撑部材料层执行图案化以形成第一支撑部141和第二支撑部142。
这里，图形化的第一支撑部和第二支撑部分别与半导体层接触从而定义了接触区域。在接触区域之间即为沟道区域，即定义了实际沟道区域。
如图8所示，该第一支撑部141和该第二支撑部142分别在该栅极120的两边。例如，该第一支撑部141的厚度范围和该第二支撑部142的厚度范围可以分别为100nm至300nm。例如，如图8所示，该第一支撑部141与该栅极120被该栅极绝缘层130隔离开，该第二支撑部142与该栅极120被该栅极绝缘层130隔离开。
在一些实施例中，该第一支撑部141和该第二支撑部142的材料包括导电材料。即支撑部材料层的材料可以包括导电材料。例如，该导电材料可以包括金属材料(例如铝)。该第一支撑部141可以作为源极，该第二支撑部142可以作为漏极。
回到图5，在步骤S508，在第一支撑部、第二支撑部和覆盖在栅极上的栅极绝缘层上形成半导体层。该第一支撑部和该第二支撑部分别用于支撑该半导体层。
图1是示出根据本公开一些实施例的薄膜晶体管的制造过程中在步骤S508的结构的截面示意图。例如，如图1所示，例如通过沉积工艺在第一支撑部141、第二支撑部142和覆盖在栅极120上的栅极绝缘层130上形成半导体层150(例如非晶硅层)150，并对该半导体层150进行图案化。
在一些实施例中，所述制造方法还可以包括：对该半导体层150进行退火处理。例如，在对半导体层进行退火处理之前，该半导体层的材料可以包括非晶硅。例如，利用激光退火工艺(例如微透镜阵列激光局域结晶技术)对该半导体层150进行退火处理以使得该非晶硅转化成多晶硅。因此，该退火处理可以使得半导体层结晶。在该实施例中，上述第一支撑部和第二支撑部有利于半导体层处于激光的同一焦平面，从而提高半导体层的结晶效果，改善薄膜晶体管的性能。
在一些实施例中，通过该激光退火工艺，还在第一支撑部141和第二支撑部142分别与该半导体层150接触的区域形成金属与半导体材料的固溶体，以形成欧姆接触。例如，第一支撑部141和第二支撑部142的金属材料可以包括铝，该固溶体可以为硅铝固溶体。
这里，对接触区域进行激光退火，从而形成金属与半导体材料的固溶体(例如硅铝固溶体)，因此这里自对准地形成了欧姆接触。该形成欧姆接触的过程可以解决在相关技术中通过重掺杂来形成欧姆接触所带来的光刻胶碳化污染等问题。
回到图5，在步骤S510，形成与半导体层分别连接的源极和漏极。
在一些实施例中，该第一支撑部141和该第二支撑部142的材料包括导电材料。 该第一支撑部141可以作为该源极，该第二支撑部142可以作为该漏极。在这样的情况下，在形成第一支撑部和第二支撑部的情况下，就形成了源极和漏极。
至此，提供了根据本公开一些实施例的薄膜晶体管的制造方法。在该制造方法中，在衬底上形成栅极。形成覆盖在该栅极和该衬底上的栅极绝缘层。在覆盖衬底且位于栅极两侧的栅极绝缘层上形成非连接的第一支撑部和第二支撑部。在该第一支撑部、该第二支撑部和覆盖在栅极上的栅极绝缘层上形成半导体层。形成与半导体层分别连接的源极和漏极。该第一支撑部和该第二支撑部分别用于支撑所述半导体层。通过形成第一支撑部和第二支撑部，从而减小了栅极所造成的栅极绝缘层的高度差。
另外，采用例如MgO等作为栅极绝缘层，可以使得栅极绝缘层具有更好的隔热性能，这样在激光退火的过程中，可以比较慢地散热，从而可以提高半导体层的结晶效果。
在一些实施例中，第一支撑部和第二支撑部也可以不作为源极和漏极。该情况下，在进行退火处理之后，所述制造方法还可以包括：形成与半导体层分别连接的源极和漏极。
下面结合图9和图2详细描述根据本公开另一些实施例的薄膜晶体管的制造方法。
例如，可以通过与如图5所示方法的步骤，形成如图9所示的结构。例如半导体层150的材料为非晶硅。在该实施例中，第一支撑部141和第二支撑部142的材料可以包括导电材料或绝缘材料。然后对该半导体层150进行退火处理，例如，使得非晶硅转化成多晶硅。
接下来，如图2所示，形成与半导体层150分别连接的源极171和漏极172。下面详细描述形成源极和漏极的过程。
在一些实施例中，在进行退火处理之后，该制造方法还可以包括：对半导体层的在第一支撑部上的区域和在第二支撑部上的区域进行掺杂。例如，可以形成覆盖在图9所示的结构上的层间电介质层160。该层间电介质层160的材料可以包括二氧化硅和氮化硅的至少一个。例如，该层间电介质层的厚度范围为
Figure PCTCN2019075859-appb-000005
至
Figure PCTCN2019075859-appb-000006
然后对该层间电介质层160执行刻蚀以形成露出半导体层150的两个通孔。这两个通孔分别露出半导体层的在第一支撑部上的区域和在第二支撑部上的区域。通过这两个通孔对半导体层150执行掺杂。
在一些实施例中，该制造方法还可以包括：在掺杂区域形成与半导体层分别连接的源极和漏极。该源极和该漏极分别与掺杂区域形成欧姆接触。例如通过沉积和图案 化等工艺形成穿过这两个通孔中的一个通孔的源极171和穿过另一个通孔的漏极172。这样可以形成如图2所示的薄膜晶体管。
图10是示出根据本公开一些实施例的像素结构的制造方法的流程图。如图10所示，该制造方法包括步骤S1002至S1014。
在步骤S1002，在衬底上形成栅极。例如，可以利用沉积和图案化等工艺在衬底110上形成栅极120，从而形成如图6所示的结构。
在步骤S1004，形成覆盖在栅极和衬底上的栅极绝缘层。例如，形成覆盖在栅极120和衬底110上的栅极绝缘层130。该栅极绝缘层130在该衬底110上的部分与该栅极绝缘层130在该栅极120上的部分是一体形成的。这样形成如图7所示的结构。
在步骤S1006，在覆盖衬底且位于栅极两侧的栅极绝缘层上形成非连接的第一支撑部和第二支撑部。例如，如图9所示，利用沉积和图案化等工艺在覆盖衬底110且位于栅极120两侧的栅极绝缘层130上形成非连接的第一支撑部141和第二支撑部142。
在步骤S1008，在第一支撑部、第二支撑部和覆盖在栅极上的栅极绝缘层上形成半导体层。例如，如图9所示，通过沉积和图案化工艺在第一支撑部141、第二支撑部142和覆盖在栅极120上的栅极绝缘层130上形成半导体层150。该第一支撑部141和该第二支撑部142分别用于支撑该半导体层150。
在一些实施例中，对该半导体层150执行退火处理。
在步骤S1010，形成与半导体层分别连接的源极和漏极。例如，可以利用沉积和图案化等工艺形成与半导体层150分别连接的源极171和漏极172，从而形成如图2所示的结构。例如，可以先形成覆盖在图9所示的结构上的层间电介质层160，然后形成穿过该层间电介质层160并与半导体层150分别连接的源极171和漏极172。
在步骤S1012，形成与源极或漏极连接的电极。例如，该电极为阳极。例如，如图11所示，可以在图2所示的结构上形成平坦化层210，从而执行平坦化处理。然后刻蚀该平坦化层210以形成露出漏极172(或源极171)的开口。通过沉积等工艺形成穿过该开口并与漏极172(或源极171)连接的电极220。
在步骤S1014，在电极的背离衬底的一侧形成功能层。例如，可以利用沉积和图案化等工艺在图11所示的结构上形成像素界定层230，然后形成穿过该像素界定层并与电极220接触的功能层240，从而形成如图4所示的结构。
在一些实施例中，如图4所示，还可以在像素界定层220上形成光阻支撑柱250。
至此，提供了根据本公开一些实施例的像素结构的制造方法。在该制造方法中， 由于形成了第一支撑部和第二支撑部，因此减小了栅极造成的栅极绝缘层的高度差，有利于半导体层处于激光的同一焦平面，从而可以提高半导体层的结晶质量。
图12是示出根据本公开另一些实施例的像素结构的制造方法的流程图。如图12所示，该制造方法可以包括步骤S1202至S1212。
在步骤S1202，在衬底上形成栅极。例如，可以利用沉积和图案化等工艺在衬底110上形成栅极120，从而形成如图6所示的结构。
在步骤S1204，形成覆盖在栅极和衬底上的栅极绝缘层。例如，形成覆盖在栅极120和衬底110上的栅极绝缘层。该栅极绝缘层130在该衬底110上的部分与该栅极绝缘层130在该栅极120上的部分是一体形成的。这样形成如图7所示的结构。
在步骤S1206，在覆盖衬底且位于栅极两侧的栅极绝缘层上形成非连接的第一支撑部和第二支撑部。例如，利用沉积和图案化等工艺在覆盖衬底110且位于栅极120两侧的栅极绝缘层130上形成非连接的第一支撑部141和第二支撑部142，从而形成如图8所示的结构。该第一支撑部141和该第二支撑部142分别在该栅极120的两边。该第一支撑部141和该第二支撑部142的材料可以包括导电材料(例如金属材料)。例如，该第一支撑部141可以作为源极，该第二支撑部142可以作为漏极。
在步骤S1208，在第一支撑部、第二支撑部和覆盖在栅极上的栅极绝缘层上形成半导体层。例如通过沉积和图案化等工艺在第一支撑部141、第二支撑部142和覆盖在栅极120上的栅极绝缘层130上形成半导体层150，从而形成如图1所示的结构。该第一支撑部141和该第二支撑部142分别用于支撑该半导体层150。
在一些实施例中，对该半导体层150执行退火处理。例如，该退火处理可以使得半导体层结晶。又例如，在该退火处理的过程中，在该第一支撑部141和该第二支撑部142分别与该半导体层150接触的区域形成有金属与半导体材料的固溶体，从而形成欧姆接触。
在步骤S1210，形成与第一支撑部或第二支撑部连接的电极。例如，该电极为阳极。
例如，如图13所示，可以利用沉积等工艺在图1所示的结构上形成层间电介质层160。例如该层间电介质层160的厚度范围可以是
Figure PCTCN2019075859-appb-000007
至
Figure PCTCN2019075859-appb-000008
对该层间电介质层160执行刻蚀以形成露出第二支撑部142(或第一支撑部141)的第一通孔。接下来，在层间电介质层160上形成平坦化层210。对该平坦化层210执行刻蚀以形成第二通孔，该第二通孔与第一通孔相对准。然后利用沉积等工艺形成穿过第二通孔和第 一通孔并与第二支撑部142(或第一支撑部141)接触的电极220。
在步骤S1212，在电极的背离衬底的一侧形成功能层。
例如，可以利用沉积和图案化等工艺在图13所示的结构上形成像素界定层230，然后形成穿过该像素界定层230并与电极220接触的功能层240，从而形成如图3所示的结构。
在一些实施例中，如图3所示，还可以在像素界定层220上形成光阻支撑柱250。
至此，提供了根据本公开另一些实施例的像素结构的制造方法。在该制造方法中，由于形成了第一支撑部和第二支撑部，因此减小了栅极造成的栅极绝缘层的高度差，有利于半导体层处于激光的同一焦平面，从而可以提高半导体层的结晶质量。而且，该第一支撑部可以作为源极，该第二支撑部可以作为漏极，从而简化了工艺流程。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (17)

  1. 一种薄膜晶体管，设置于衬底上，包括：
    在衬底上的栅极；
    覆盖在栅极和衬底上的栅极绝缘层；
    在覆盖所述衬底且位于所述栅极两侧的栅极绝缘层上设置的非连接的第一支撑部和第二支撑部；
    在所述第一支撑部、所述第二支撑部和覆盖在所述栅极上的栅极绝缘层上的半导体层；
    与所述半导体层分别连接的源极和漏极；
    其中，所述第一支撑部和所述第二支撑部分别用于支撑所述半导体层。
  2. 根据权利要求1所述的薄膜晶体管，其中，
    所述第一支撑部和所述第二支撑部的背离所述衬底的一侧的表面与所述栅极绝缘层在所述栅极上的部分的背离所述衬底的一侧的表面齐平；
    所述第一支撑部和所述第二支撑部设置在位于所述栅极两侧的栅极绝缘层所形成的台阶处，且所述第一支撑部和所述第二支撑部的延伸方向与所述半导体层的延伸方向相同。
  3. 根据权利要求2所述的薄膜晶体管，其中，
    所述半导体层在所述衬底上的正投影位于所述栅极、所述第一支撑部和所述第二支撑部这三者在所述衬底上的正投影的内部。
  4. 根据权利要求1所述的薄膜晶体管，其中，
    所述源极在所述第一支撑部的上方，所述漏极在所述第二支撑部的上方。
  5. 根据权利要求1所述的薄膜晶体管，其中，
    所述第一支撑部和所述第二支撑部的材料包括导电材料，
    所述第一支撑部作为所述源极，所述第二支撑部作为所述漏极。
  6. 根据权利要求5所述的薄膜晶体管，其中，
    所述导电材料包括金属材料；
    在所述第一支撑部和所述第二支撑部分别与所述半导体层接触的区域形成有金属与半导体材料的固溶体。
  7. 根据权利要求6所述的薄膜晶体管，其中，
    所述金属材料包括铝；
    所述半导体层的材料包括多晶硅；
    所述固溶体为硅铝固溶体。
  8. 根据权利要求1所述的薄膜晶体管，其中，
    所述栅极绝缘层的材料包括MgO。
  9. 一种像素结构，包括：
    如权利要求1至8任意一项所述的薄膜晶体管。
  10. 一种阵列基板，包括：如权利要求1至8任意一项所述的薄膜晶体管。
  11. 一种显示装置，包括如权利要求10所述的阵列基板。
  12. 一种薄膜晶体管的制造方法，包括：
    在衬底上形成栅极；
    形成覆盖在所述栅极和所述衬底上的栅极绝缘层；
    在覆盖所述衬底且位于所述栅极两侧的栅极绝缘层上形成非连接的第一支撑部和第二支撑部；
    在所述第一支撑部、所述第二支撑部和覆盖在所述栅极上的栅极绝缘层上形成半导体层；
    形成与所述半导体层分别连接的源极和漏极；
    其中，所述第一支撑部和所述第二支撑部分别用于支撑所述半导体层。
  13. 根据权利要求12所述的制造方法，还包括：
    对所述半导体层进行退火处理。
  14. 根据权利要求13所述的制造方法，其中，在进行退火处理之后，所述制造方法还包括：
    对所述半导体层的在所述第一支撑部上的区域和在所述第二支撑部上的区域进行掺杂；以及
    在掺杂区域形成与所述半导体层分别连接的所述源极和所述漏极，其中，所述源极和所述漏极分别与所述掺杂区域形成欧姆接触。
  15. 根据权利要求13所述的制造方法，其中，
    所述第一支撑部和所述第二支撑部的材料包括导电材料，所述第一支撑部作为所述源极，所述第二支撑部作为所述漏极。
  16. 根据权利要求15所述的制造方法，其中，
    所述导电材料包括金属材料；
    在对所述半导体层进行退火处理之前，所述半导体层的材料包括非晶硅；
    对所述半导体层进行退火处理的步骤包括：利用激光退火工艺对所述半导体层进行退火处理以使得所述非晶硅转化成多晶硅，
    其中，通过所述激光退火工艺，还在所述第一支撑部和所述第二支撑部分别与所述半导体层接触的区域形成金属与半导体材料的固溶体以形成欧姆接触。
  17. 根据权利要求16所述的制造方法，其中，
    所述金属材料包括铝；
    所述固溶体为硅铝固溶体。
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