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  • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
  • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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  • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
  • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
  • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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  • H01L29/0843—Source or drain regions of field-effect devices
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  • H01L29/41725—Source or drain electrodes for field effect devices
  • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
  • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
  • H01L29/8124—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with multiple gate

Definitions

• the disclosure relates to microelectronic devices and more particularly to gallium nitride high-electron mobility transistors with buried p-type layers.
• the disclosure also relates to a process of making microelectronic devices and more particularly to a process of making gallium nitride high-electron mobility transistors with buried p-type layers.
• Group Ill-Nitride based high-electron mobility transistors are very promising candidates for high power radiofrequency (RF) applications, and also for low frequency high power switching applications since the material properties of Group Ill-nitrides, such as GaN and its alloys, enable achievement of high voltage and high current, along with high RF gain and linearity for RF
• a typical Group Ill-nitride HEMT relies on the formation of a two- dimensional electron gas (2DEG) formed at the interface between a higher band-gap Group-Ill nitride (e.g., AIGaN) barrier layer and a lower band-gap Group-Ill nitride material (e.g., GaN) buffer layer, where the smaller bandgap material has a higher electron affinity.
• the 2DEG is an accumulation layer in the smaller bandgap material and can contain a high electron concentration and high electron mobility.
• drain lag effect can lead to distortion and also complicates pre-distortion correction schemes.
• the drain lag effect may be eliminated by using high purity buffer layers without Fe or C. However, these devices have high leakage current through the buffer layer, which is also not acceptable.
• Overlapping gate structures, or field plates have been used to modify the electric field and improve the performance of Group Ill-nitride HEMTs.
• a transistor device uses a buried p-layer to enable the use of a higher purity buffer layer, thereby reducing the drain lag effect, while reducing the leakage current.
• the transistor device is a group Ill-nitride HEMT that comprises a group Ill-nitride buffer layer on a substrate, and a group Ill-nitride barrier layer on the group Ill-nitride buffer layer.
• the group Ill-nitride (e.g., AIGaN) barrier layer has a higher bandgap than the group Ill-nitride (e.g., GaN) buffer layer.
• Source, gate, and drain contacts are electrically coupled to the group Ill-nitride barrier layer.
• a p-region is provided below said group Ill-nitride barrier layer.
• the transistor device is a group Ill-nitride HEMT that comprises a group Ill-nitride buffer layer on a substrate, and a group Ill- nitride barrier layer on the group Ill-nitride buffer layer.
• the group Ill-nitride (e.g., AIGaN) barrier layer has a higher bandgap than the group Ill-nitride (e.g., GaN) buffer layer.
• Source, gate, and drain contacts are electrically coupled to the group Ill-nitride barrier layer.
• the transistor further includes a contact pad electrically coupled to said p-region.
• the transistor device is a group Ill-nitride HEMT that comprises a group Ill-nitride buffer layer on a substrate, and a group Ill- nitride barrier layer on the group Ill-nitride buffer layer.
• the group Ill-nitride (e.g., AIGaN) barrier layer has a higher bandgap than the group Ill-nitride (e.g., GaN) buffer layer.
• Source, gate, and drain contacts are electrically coupled to the group Ill-nitride barrier layer.
• the gate is electrically coupled to the p-region.
• the p-region is in the substrate and/or on the substrate below the barrier layer.
• the p-region is implanted.
• the p-region is in an epitaxial layer.
• the p-region contains multiple p-regions.
• the p-region has a separate contact.
• the p-region is electrically connected to the source.
• the p-region is electrically connected to the gate.
• the HEMT comprises a field plate
• the field plate is electrically connected to the source.
• the field plate and the p-region is connected to the source.
• the transistor may include a connection connecting the contact pad electrically to the p-region.
• the contact pad is configured to receive at least one of the following: bias and signals.
• the transistor may include a connection connecting the gate electrically to said p-region.
• Figure 1 shows a cross-sectional view of one aspect of a transistor according to the disclosure.
• Figure 2 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 3 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 4 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 5 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 6 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 7 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 8 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 9 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 10 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 1 1 shows a plan view of another aspect of a transistor according to the disclosure.
• Figure 12 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 13 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 14 shows a process for making a transistor according to the disclosure.
• Figure 15 illustrates a distribution of Al implanted with channeling conditions according to aspects of the disclosure in comparison to simulations for conventional implant conditions.
• Figure 16 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 17 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 18 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 19 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 20 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 21 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 22 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 23 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 24 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 25 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 26 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 27 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 28 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 29 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 30 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 31 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 32 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 33 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 34 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 35 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
• the characteristics of the semiconductor material from which a transistor is formed may also affect operating parameters.
• the electron mobility, saturated electron drift velocity, electric breakdown field, and thermal conductivity may have an effect on a transistor's high frequency and high power characteristics.
• Electron mobility is the measurement of how rapidly an electron is accelerated to its saturated velocity in the presence of an electric field.
• semiconductor materials which had a high electron mobility, were preferred because more current could be developed with a lesser field, resulting in faster response times when a field is applied.
• Saturated electron drift velocity is the maximum velocity that an electron can obtain in the semiconductor material. Materials with higher saturated electron drift velocities are preferred for high frequency applications because the higher velocity translates to shorter times from source to drain.
• Electric breakdown field is the field strength at which breakdown of the Schottky junction and the current through the gate of the device suddenly increases.
• a high electric breakdown field material is preferred for high power, high frequency transistors because larger electric fields generally can be supported by a given dimension of material. Larger electric fields allow for faster transients as the electrons can be accelerated more quickly by larger electric fields than by smaller ones.
• Thermal conductivity is the ability of the semiconductor material to dissipate heat. In typical operations, all transistors generate heat. In turn, high power and high frequency transistors usually generate larger amounts of heat than small signal transistors. As the temperature of the semiconductor material increases, the junction leakage currents generally increase and the current through the field effect transistor generally decreases due to a decrease in carrier mobility with an increase in temperature. Therefore, if the heat is dissipated from the semiconductor, the material will remain at a lower temperature and be capable of carrying larger currents with lower leakage currents.
• the disclosure includes both extrinsic and intrinsic semiconductors.
• Intrinsic semiconductors are undoped (pure).
• Extrinsic semiconductors are doped, meaning an agent has been introduced to change the electron and hole carrier concentration of the semiconductor at thermal equilibrium.
• Both p-type and n-type semiconductors are disclosed, with p-types having a larger hole concentration than electron concentration, and n-types having a larger electron concentration than hole concentration.
• Silicon carbide has excellent physical and electronic properties, which should theoretically allow production of electronic devices that can operate at higher temperatures, higher power, and higher frequency than devices produced from silicon (Si) or gallium arsenide (GaAs) substrates.
• the high electric breakdown field of about 4*E6 V/cm, high saturated electron drift velocity of about 2.0*E7 cm/sec and high thermal conductivity of about 4.9 W/cm-°K indicate that SiC would be suitable for high frequency and high power applications.
• the transistor of the present invention comprises Si, GaAs or other suitable substrates.
• the drain lag in the disclosed HEMTs is in some aspects addressed with the addition of structures.
• a buried p-type layer is used to simultaneously achieve high breakdown, and reduce drain lag without unduly increasing leakage current.
• the p-type layer helps in optimizing the breakdown voltage and can be charged and discharged easily which ensures reduction of drain lag.
• the p-type layer is formed in a SiC substrate.
• the p-region is formed in the substrate, two problems can be alleviated: 1. It is difficult to form p-type layers in Group lll-N using ion-implantation. Selective ion-implantation enables optimization of the device structure by allowing different concentrations of dopants to be obtained in different regions. This can be more difficult with epitaxial growth.
• the buried p-region according to different embodiments of the present invention can be provided solely in the substrate, extend from the substrate to the epitaxial layers, or located solely in epitaxial layers. The dopants can be incorporated into the epitaxial layers by ion implantation alone, through epitaxial growth, or a combination of both. 2. P-type doping of GaN using magnesium (Mg) also exhibits memory effects, which precludes the formation of abrupt interfaces.
• Mg magnesium
• the disclosed process and structure may enable development of Group lll-N HEMTs with high voltage capability suitable for power switching with reduced drain lag effects.
• the disclosed process and structure may also lead to more compact device structures (due to optimized field shaping) that will lower costs. Additionally, with proper design, the disclosed structures can also be applied to high power RF devices for telecommunication and other applications. An important advantage is the minimization of device memory effects, which is a serious problem for telecommunication applications.
• Figure 1 shows a cross-sectional view of an embodiment of a transistor according to the disclosure.
• Figure 1 shows a cross-sectional view of a transistor 100.
• the transistor 100 may include a substrate layer 102.
• the substrate layer 102 may be made of Silicon Carbide (SiC).
• SiC Silicon Carbide
• the substrate layer 102 may be a semi-insulating SiC substrate, a p-type substrate, an n-type substrate, and/or the like.
• the substrate layer 102 may be very lightly doped.
• the background impurity levels may be low. In one aspect, the background impurity levels may be 1 E15/cm 3 or less.
• the substrate layer 102 may be formed of SiC selected from the group of 6H, 4H, 15R, 3C SiC, or the like, and the SiC is semi-insulating and doped with vanadium or any other suitable dopant or undoped of high purity with defects providing the semi-insulating properties.
• the substrate layer 102 may be GaAs, GaN, or other material suitable for the applications described herein.
• the substrate layer 102 may include sapphire, spinel, ZnO, silicon, or any other material capable of supporting growth of Group Ill-nitride materials.
• a nucleation layer 136 may be formed on the substrate layer 102 to reduce a lattice mismatch between the substrate layer 102 and a next layer in the transistor 100.
• the nucleation layer 136 is formed directly on the substrate layer 102.
• the nucleation layer 136 is formed on the substrate layer 102 with intervening layer(s), such as SiC epitaxial layer(s) formed on a SiC substrate layer 102.
• the nucleation layer 136 may be formed on the substrate layer 102 using known semiconductor growth techniques such as Metal Oxide Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), or the like.
• MOCVD Metal Oxide Chemical Vapor Deposition
• HVPE Hydride Vapor Phase Epitaxy
• MBE Molecular Beam Epitaxy
• the nucleation layer is AIN or AIGaN, such as undoped AIN or AIGaN.
• a buffer layer 104 is formed directly on the nucleation layer 136 or on the nucleation layer 136 with intervening layer(s).
• the buffer layer 104 may be formed of different suitable materials such as a Group Ill-nitride such as Al x Ga y ln (i-x-y) N (where
• the buffer layer 104 is formed of GaN.
• the buffer layer 104 or portions thereof may be doped with dopants, such as, Fe and/or C or alternatively can be wholly or partly undoped.
• the buffer layer 104 is directly on the substrate layer 102.
• the buffer layer 104 may be high purity GaN. In one aspect, the buffer layer 104 may be high purity GaN that may be a low-doped n-type. In one aspect, the buffer layer 104 may also use a higher band gap Group Ill-nitride layer as a back barrier, such as an AIGaN back barrier, on the other side of the buffer layer 104 from the barrier layer 108 to achieve better electron confinement.
• a back barrier such as an AIGaN back barrier
• the buffer layer 104 may have a buffer layer thickness defined as a distance between an upper surface of the substrate layer 102 and a lower surface of the barrier layer 108.
• the buffer layer thickness may be less than .8 microns, less than .7 microns, less than .6 microns, less than .5 microns, or less than .4 microns.
• the buffer layer thickness may have a range of .8 microns to .6 microns, .7 microns to .5 microns, .6 microns to .4 microns, .5 microns to .3 microns, .4 microns to .2 microns, or .7 microns to .3 microns.
• the transistor 100 may have an intervening layer(s) thickness defined as a length between an upper surface of the substrate layer 102 and a lower surface of the barrier layer 108.
• the intervening layer(s) thickness may be less than .8 microns, less than .7 microns, less than .6 microns, less than .5 microns, or less than .4 microns.
• the intervening layer(s) thickness may have a range of .8 microns to .6 microns, .7 microns to .5 microns, .6 microns to .4 microns, .5 microns to .3 microns, or .4 microns to .2 microns.
• a barrier layer 108 may be formed on the buffer layer 104.
• the barrier layer 108 may be formed directly on the buffer layer 104, and in other aspects, the barrier layer 108 is formed on the buffer layer 104 with intervening layer(s).
• the barrier layer 108 may be AIGaN, and in another aspect the barrier layer 108 is AIN. In one aspect, the barrier layer 108 may be undoped. In one aspect, the barrier layer 108 may be doped. In one aspect, the barrier layer 108 may be an n-type material. In some aspects, the barrier layer 108 may have multiple layers of n-type material having different carrier concentrations. In one aspect, the barrier layer 108 may be a Group Ill-nitride or a combination thereof.
• a bandgap of the buffer layer 104 may be less than a bandgap of the barrier layer 108 to form a two-dimensional electron gas (2DEG) at a heterointerface 152 between the buffer layer 104 and barrier layer 108 when biased at an appropriate level.
• a bandgap of the buffer layer 104 that may be GaN may be less than a bandgap of the barrier layer 108 that may be AIGaN to form the two- dimensional electron gas (2DEG) at a heterointerface 152 between the buffer layer 104 and barrier layer 108 when biased at an appropriate level.
• a source 1 10, a drain 1 12 and a gate 1 14 are formed on the barrier layer 108.
• the source 1 10, drain 1 12, and/or gate 1 14 may be arranged directly on the barrier layer 108 or may be on intervening layer(s) on the barrier layer 108, such as an AIGaN layer on an AIN barrier layer. Other or additional intervening layers are possible.
• a spacer layer 1 16 of SiN, AIO, SiO, S1O2, AIN, or the like or combinations thereof can be provided on the barrier layer 108 or other intervening layers.
• the barrier layer 108 may include a region 164 under the source 1 10 and/or drain 1 12 that is a N+ material.
• the barrier layer 108 may include a region 164 under the source 1 10 and/or drain 1 12 that is Si doped.
• the n-type dopants in the region 164 are implanted.
• a spacer layer 1 16 may be arranged on the barrier layer 108, on a side opposite the buffer layer 104, adjacent the gate 1 14, the drain 1 12 and the source 1 10.
• the spacer layer 1 16 may be a passivation layer made of SiN, AIO, SiO, S1O 2 , AIN, or the like, or a combination incorporating multiple layers thereof.
• the spacer layer 116 is a passivation layer made of SiN.
• the spacer layer 1 16 can be deposited using MOCVD, plasma chemical vapor deposition (CVD), hot-filament CVD, or sputtering.
• the spacer layer 1 16 may include deposition of S1 3 N 4 . In one aspect, the spacer layer 1 16 forms an insulating layer. In one aspect, the spacer layer 1 16 forms an insulator. In one aspect, the spacer layer 1 16 may be a dielectric.
• the gate 1 14 is deposited in a channel formed in the spacer layer 1 16, and a T-gate is formed using semiconductor processing techniques understood by those of ordinary skill in the art. Other gate configurations are possible.
• a second spacer layer 1 17 is formed on the first spacer layer 1 16 and the gate 1 14, and a field plate 132 can be provided on the second spacer layer 1 17.
• the first spacer layer 1 16 is formed on the barrier layer 108 and on the gate 1 14.
• a field plate 132 can be formed directly on the first spacer layer 1 16.
• Other multiple field plate configurations are possible with the field plate 132 overlapping or non-overlapping with the gate 1 14 and/or multiple field plates 132 being used.
• a buried p- region or p-type material layer 120 is formed below the barrier layer 108 between the barrier layer 108 and the substrate layer 102 and/or within the substrate layer 102.
• the p-type material region can be provided solely in the substrate layer 102, extend from the substrate layer 102 to the epitaxial layers, or located solely in epitaxial layers.
• the dopants can be incorporated into the epitaxial layers by ion implantation alone, through epitaxial growth, or a combination of both.
• the p-type material layer 120 can span multiple layers and include multiple areas of different or graded p- doping.
• the p-type material layer 120 or portions thereof can extend from a p-type material contact 1 18 in a recess 1 19 formed in the transistor 100 and can extend up to or beyond the source 1 10, up to or beyond the gate 1 14, prior to the gate 1 14, up to the gate 1 14, and/or across the transistor 100.
• the p-type material contact 1 18 is electrically connected to receive an external signal or bias.
• the source 1 10 is electrically connected to the p-type material layer 120 through a connection 138.
• the field plate 132 is electrically connected to the source 1 10 through a connection 140.
• the field plate 132 is connected to the source 1 10, and the source 1 10 is connected to the p-type material layer 120 through a connection 140, a connection 138, or a single connection to both.
• the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18.
• the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18 without connecting to the source 1 10. In certain embodiments, the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18 without any intervening connections. In certain embodiments, the gate 1 14 is electrically connected to the p- type material layer 120 through a connection 154.
• the substrate layer 102 may include a p-type material layer 120.
• the p-type material layer 120 may be formed by ion implantation of aluminum (Al) and annealing. In other aspects, the p-type material layer 120 may be formed by ion implantation of boron, gallium, or any other material that may form a p-type layer or a combination of these. In one aspect, the p-type material layer 120 may be formed by implantation and annealing of Al prior to the growth of any GaN layers.
• the ion implementation may utilize channeling implants. In one aspect, the channeling implants may include aligning the ion beam to the substrate layer 102. Alignment of the ion beam may result in increased implanting efficiency.
• implant channeling can be used to controllably form implanted regions in silicon carbide that are highly uniform by depth and also result in reduced lattice damage.
• Channeling is experienced when ions are implanted along a crystal axis of a semiconductor.
• the atoms in the crystal lattice appear to "line up" relative to the direction of implantation, and the implanted ions appear to travel down the channels created by the crystal structure. This reduces the likelihood of collisions between the implanted ions and the atoms in the crystal lattice.. As a result, the depth of the implant is greatly increased.
• channeling occurs in silicon carbide when the direction of implantation is within about ⁇ .2° of a crystallographic axis of the silicon carbide crystal.
• the implantation may be greater than ⁇ .2° of the crystallographic axis of the silicon carbide crystal, however the implantation may be less effective.
• the direction of implantation is more than about ⁇ .2° of a crystallographic axis of the silicon carbide crystal, the atoms in the lattice may appear to be randomly distributed relative to the direction of implantation, which may reduce channeling effects.
• implant angle refers to the angle between the direction of implantation and a crystallographic axis, such as the c-axis or ⁇ 0001 > axis, of the semiconductor layer into which ions are implanted.
• a crystallographic axis such as the c-axis or ⁇ 0001 > axis
• an implant angle of less than about 2° relative to the c-axis of a silicon carbide layer may be expected to result in channeling.
• other implant angles may be utilized as well.
• the implant energy may be 20keV to 80keV, 80keV to 120keV, 120keV to 160keV, 160keV to 200keV, 200keV to 240keV,
• the implant dose may be 6E13cm 2 to 8E13cm 2 , 8E13cm 2 to 1.2E13cm 2 , 1.2E13cm 2 to 1.6E13cm 2 , 1.6E13cm 2 to
• the p-type material layer 120 may be formed by implantation of other materials such as Boron (B), Gallium (Ga), and/or the like, and may be followed by a high temperature anneal.
• the ion implantation may result in the p-type material layer 120 being a deep layer. In one aspect, the ion implantation may result in the p- type material layer 120 having a thickness of 1 pm or less. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of .7 pm or less. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of .5 pm or less. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of .3 pm to .5 pm.
• the ion implantation may result in the p-type material layer 120 having a thickness of .2 pm to .6 pm. In one aspect, the ion implantation may result in the p- type material layer 120 having a thickness of .4 pm to .6 pm. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of .6 pm to .8 pm. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of .6 pm to 1.6 pm. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of .6 pm to 2.1 pm.
• the ion implantation may result in the p-type material layer 120 having a thickness of 1 pm to 5 pm.
• the p-type material layer 120 implantation and/or doping may be in the range of 5E15 to 5E17 per cm 3 and extend to depths up to 5 pm.
• the ion implantation may result in the p-type material layer 120 having a thickness of .05% to .3% of a thickness of the substrate layer 102. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of .05% to .1 % of a thickness of the substrate layer 102. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of .1 % to .15% of a thickness of the substrate layer 102. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of .15% to .2% of a thickness of the substrate layer 102.
• the ion implantation may result in the p-type material layer 120 having a thickness of .2% to .25% of a thickness of the substrate layer 102. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of .25% to .3% of a thickness of the substrate layer 102.
• the p-type material layer 120 may be implanted within the substrate layer 102 and may be subsequently annealed. Annealing may allow for the implantation to be activated.
• a masking layer material may be utilized during implantation.
• a cap layer material may be used to cover the wafer surface to prevent dissociation of the substrate at high temperatures.
• the masking layer material may be removed. Annealing may be performed at a temperature range of 1500 - 1850°C for 5 minutes - 30 minutes. Other annealing time and temperature profiles are contemplated as well.
• the substrate layer 102 may be made of a p-type material SiC substrate. Further in this aspect, the substrate layer 102 being a p-type material SiC substrate may be subsequently subjected to the processes as described herein including implantation of additional p-type layers.
• Figures 2-34 show different embodiments and aspects of the present invention with like reference numerals representing analogous parts in the various embodiments and figures. It should be understood that a feature described in one embodiment can be added to another embodiment or replace a feature in another embodiment.
• the substrate layer 102 may include a p+ layer 106.
• the p+ layer 106 may be used to reduce charging time constants and to achieve contact formation.
• the p+ layer 106 may also be formed by ion-implantation and annealing.
• the p+ layer 106 may be doped as highly as possible with minimum achievable sheet resistance.
• the p+ layer 106 may be present in a gate - source region.
• the p+ layer 106 may be present in a gate - source region and also partly under the gate 1 14.
• the p+ layer 106 may be present in limited areas as described in further detail below.
• the p+ layer 106 may be under .6 pm in thickness. In some aspects, the p+ layer 106 may be under .5 pm in thickness. In some aspects, the p+ layer 106 may be under .4 pm in thickness. In some aspects, the p+ layer 106 may be under .3 pm in thickness. In some aspects, the p+ layer 106 may be under .2 pm in thickness. In some aspects, the p+ layer 106 may be between .1 and .6 pm in thickness. In some aspects, the p+ layer 106 may be between .5 and .6 pm in thickness. In some aspects, the p+ layer 106 may be between .4 and .5 pm in thickness.
• the p+ layer 106 may be between .3 and .4 pm in thickness. In some aspects, the p+ layer 106 may be between .2 and .3 pm in thickness. In some aspects, the p+ layer 106 may be between .1 and .3 pm in thickness. In some aspects, the p+ layer 106 may be between .05 and .25 pm in thickness. In some aspects, the p+ layer 106 may be between .15 and .25 pm in thickness.
• the source 1 10 may have a p-type material contact 118 on the p+ layer 106.
• the p-type material contact 1 18 may be formed on the p+ layer 106 in a recess 1 19 provided in the buffer layer 104 and the barrier layer 108.
• the p-type material contact 1 18 may be electrically coupled to the p+ layer 106.
• the recess may extend down to the p+ layer 106 to allow for the p-type material contact 118 to be created there.
• the recess 1 19 may be formed by etching, and may also use a material to define the recess 1 19. The material may be removed after the recess 1 19 has been created.
• the source 1 10 may have a p-type material contact 118 on the p-type material layer 120.
• the p-type material contact 1 18 may be formed on the p-type material layer 120 in a recess 1 19 provided in the buffer layer 104 and the barrier layer 108.
• the p-type material contact 1 18 may be electrically coupled to the p-type material layer 120.
• the recess 1 19 may extend down to the p- type material layer 120 to allow for the p-type material contact 1 18 to be created there.
• the recess 1 19 may be formed by etching, and may also use a material to define the recess 1 19. The material may be removed after the recess 1 19 has been created.
• the p-type material contact 1 18 may be formed in or on a layer of the transistor 100 in a recess 1 19 provided as indicated by a dashed boxes illustrated in Figure 1.
• the recess 1 19 may be configured as a partial recess, partial trench, or the like in a surface of the transistor 100.
• a region or area under or adjacent the p-type material contact 1 18 may be implanted and/or doped with p-dopants to form an electrical connection with the p- type material layer 120 and/or the p+ layer 106.
• the layer may be an epitaxial material on which is provided the p-type material contact 1 18.
• a region or area under or adjacent the p-type material contact 1 18 may be implanted and/or doped during epitaxial growth of the layer or other layers with p- dopants to form an electrical connection with the p-type material layer 120 and/or a p+ layer 106.
• this aspect may be included in any aspect of the transistor 100 illustrated or described herein.
• the p-type material contact 1 18 may be formed in or on the buffer layer 104 in a recess 1 19 provided down to the buffer layer 104 as indicated by a lower dashed box illustrated in Figure 1 .
• the recess 119 may be configured as a partial recess, partial trench, or the like in a surface of the transistor 100.
• a region or area under or adjacent the p-type material contact 1 18 may be implanted and/or doped with p-dopants to form an electrical connection with the p-type material layer 120 and/or the p+ layer 106.
• the buffer layer 104 may be an epitaxial material on which is provided the p-type material contact 1 18.
• a region or area under or adjacent the p-type material contact 1 18 may be implanted and/or doped during epitaxial growth of the buffer layer 104 or other layers with p-dopants to form an electrical connection with the p-type material layer 120 and/or a p+ layer 106.
• this aspect may be included in any aspect of the transistor 100 illustrated or described herein.
• the p-type material contact 1 18 may be formed in or on the barrier layer 108 as indicated by an upper dashed box illustrated in Figure 1 .
• a recess 1 19 may or may not be formed. If a recess 1 19 is formed, the recess 1 19 may be configured as a partial recess, partial trench, or the like in a surface of the transistor 100.
• a region or area under or adjacent the p-type material contact 1 18 may be implanted and/or doped with p-dopants to form an electrical connection with the p-type material layer 120 and/or a p+ layer 106.
• the barrier layer 108 may be an epitaxial material on which is provided the p-type material contact 1 18.
• a region or area under or adjacent the p-type material contact 1 18 may be implanted and/or doped during epitaxial growth of the barrier layer 108 or other layers with p-dopants to form an electrical connection with the p-type material layer 120 and/or a p+ layer 106.
• this aspect may be included in any aspect of the transistor 100 illustrated or described herein.
• a spacer layer 1 16 may be provided on the barrier layer 108.
• a second spacer layer 1 17 may be provided over the gate 114 and the first spacer layer 1 16.
• the spacer layer 1 16 may include non-conducting material such as a dielectric.
• the spacer layer 1 16 may include a number of different layers of dielectrics or a combination of dielectric layers.
• the spacer layer 1 16 may be many different thicknesses, with a suitable range of thicknesses being approximately 0.05 to 2 microns.
• Figure 4 shows a cross-sectional view of another aspect of a transistor according to the disclosure
• Figure 5 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• an epitaxial layer 202 may be formed on the substrate layer 102. In one aspect, an epitaxial layer 202 may be formed on the substrate layer 102. In one aspect, an epitaxial layer 202 may be formed directly on the substrate layer 102. In the aspects of Figure 4 and Figure 5, the p-type material layer 120 may be in the epitaxial layer 202. In some aspects, the p-type material layer 120 may be in the epitaxial layer 202 in certain aspects where the substrate layer 102 includes GaAs, GaN, or the like substrate materials. In some aspects, the epitaxial layer 202 may be a Group Ill-nitride material. In some aspects, the epitaxial layer 202 may be more than one Group Ill-nitride material.
• the epitaxial layer 202 is formed of SiC.
• the p-type material layer 120 may be in the epitaxial layer 202 and may be SiC.
• the p-type material layer 120 may be in the epitaxial layer 202 and may be SiC and the p-type material layer 120 may include Al and/or Br.
• the p-type material layer 120 may be in the epitaxial layer 202 and may be SiC and the p-type material layer 120 may include implantation of Al and/or Br.
• the p-type material layer 120 may be in the epitaxial layer 202.
• the p-type material layer 120 may be in the epitaxial layer 202 and may be GaN. In some aspects, the p-type material layer 120 may be in the epitaxial layer 202 and may be GaN and the p-type material layer 120 may include magnesium (Mg), carbon (C), and/or Zinc. In some aspects, the p-type material layer 120 may be in the epitaxial layer 202 and may be GaN and the p-type material layer 120 may include implantation of magnesium (Mg), carbon (C), and/or Zinc.
• the epitaxial layer 202 may be arranged on top of the substrate layer 102. In one aspect, the epitaxial layer 202 may be arranged directly on top of the substrate layer 102. In one aspect, the buffer layer 104 may be arranged on top of the epitaxial layer 202. In one aspect, the buffer layer 104 may be arranged directly on top of the epitaxial layer 202. In one aspect, the p-type material layer 120 may be implanted within the epitaxial layer 202 and may be subsequently annealed as described herein. Further in this aspect, the epitaxial layer 202 may be subsequently subjected to processes as described herein and may include formation and/or implantation of a p+ layer 106.
• the epitaxial layer 202 may be arranged on top of the substrate layer 102 and the buffer layer 104 may be formed on the epitaxial layer 202. In one aspect, the epitaxial layer 202 may be arranged on top of the substrate layer 102 and the buffer layer 104 may be formed directly on the epitaxial layer 202.
• the ion implantation may result in the p-type material layer 120 having a thickness of 10% to 20% of a thickness of the epitaxial layer 202. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of 20 % to 30 % of a thickness of the epitaxial layer 202. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of 30 % to 40 % of a thickness of the epitaxial layer 202. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of 40 % to 50 % of a thickness of the epitaxial layer 202.
• the ion implantation may result in the p-type material layer 120 having a thickness of 50 % to 60 % of a thickness of the epitaxial layer 202. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of 60 % to 70 % of a thickness of the epitaxial layer 202. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of 70 % to 80 % of a thickness of the epitaxial layer 202. In one aspect, the ion implantation may result in the p-type material layer 120 having a thickness of 80 % to 90 % of a thickness of the epitaxial layer 202.
• the epitaxial layer 202 may utilize a p-type material and the epitaxial layer 202 may be arranged on top of the substrate layer 102.
• the epitaxial layer 202 may utilize a p-type material and the epitaxial layer 202 may be arranged directly on top of the substrate layer 102.
• a p-type material epitaxial layer 202 may be grown that results in an epitaxial layer 202 having the p-type material layer 120 and may not require implantation as described herein to form the p-type material layer 120.
• the epitaxial layer 202 may be subsequently subjected to the processes including implantation of a p+ layer 106 as described herein.
• the epitaxial layer 202 may be formed by epitaxial growth utilizing off-axis oriented wafers.
• Figure 5 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• the epitaxial layer 202 may be formed with a p-type material and the epitaxial layer 202 may be arranged on top of the substrate layer 102.
• the epitaxial layer 202 may be formed with a p-type material and the epitaxial layer 202 may be arranged directly on top of the substrate layer 102.
• the entire epitaxial layer 202 may form the p-type material layer 120. Thereafter, the epitaxial layer 202 may be
• the p-type material layer 120 may also be configured to have a varying doping and/or implantation profile perpendicular to the surface. In some aspects, the p-type material layer 120 may also be configured to have a varying profile perpendicular to the surface extending into the cross-sectional views of the Figures. The profile may be optimized to achieve desired breakdown voltage, device size, switching time, and the like.
• the p-type material layer 120 may be present uniformly under the transistor 100 for certain applications as shown in Figure 2, Figure 4, and Figure 6. In one aspect, the p-type material layer 120 may be present uniformly under the transistor 100 for power switching applications as shown in Figure 2, Figure 4, and Figure 6.
• the p-type material layer 120 may be located in limited areas such as in part of the gate - source region of the transistor 100 as illustrated in Figure 3 and Figure 5 and described in further detail below.
• part of the voltage from a drain 1 12 to a source 110 may be dropped in the p-type material layer 120 region. This may also deplete the channel in the lateral direction. The lateral depletion may reduce the lateral field and increase breakdown voltage. Alternatively, a more compact structure can be obtained for a required breakdown voltage.
• the p-type material layer 120 may eliminate the need to have C or Fe doping of the buffer needed to sustain the applied drain voltage. Elimination of C and Fe leads to decreased current reduction under operating conditions (no trapping). Moreover, in some aspects the p-type material layer 120 may support the field.
• the epitaxial layer 202 may include a p+ layer 106 as shown in Figure 4, Figure 5, and Figure 6.
• the p+ layer 106 may be used to reduce charging time constants and to achieve contact formation.
• the p+ layer 106 may also be formed by ion-implantation and annealing.
• the p+ layer 106 may be doped as highly as possible with minimum achievable sheet resistance.
• the p+ layer 106 may be present in a gate - source region.
• the p+ layer 106 may be present in a gate - source region and also partly under the gate 1 14.
• the p+ layer 106 may be present in limited areas as described in further detail below.
• the p+ layer 106 may be under .3 pm in thickness. In some aspects, the p+ layer 106 may be under .2 pm in thickness. In some aspects, the p+ layer 106 may be between .1 and .3 pm in thickness. In some aspects, the p+ layer 106 may be between .05 and .25 pm in thickness. In some aspects, the p+ layer 106 may be between .15 and .25 pm in thickness.
• Figure 7 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 7 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the Figure 7 aspect illustrates that the buffer layer 104 may include an upper portion 602 of high purity GaN and the buffer layer 104 may also include a lower portion 604 that may form an AIGaN back barrier to achieve better electron confinement.
• the lower portion 604 that forms the back barrier may be AIGaN of n type.
• the back barrier construction may be implemented in any of the aspects of the disclosure.
• the buffer layer 104 may be designed to be of the high purity type where the Fermi level is in the upper half of the bandgap, which minimizes slow trapping effects normally observed in GaN HEMTs. In this regard, the traps under the Fermi level are filled always and thus slow transients may be prevented.
• the buffer layer 104 may be as thin as possible consistent with achieving good crystalline quality. Applicants have already demonstrated 0.4 pm layers with good quality.
• MOCVD Metalorganic Chemical Vapor Deposition
• HVPE Hydride Vapor Phase Epitaxy
• MBE Molecular Beam Epitaxy
• the buffer layer 104 may be formed with Lateral Epitaxial Overgrowth (LEO).
• LEO can, for example, improve the crystalline quality of GaN layers.
• the layer upon which each epitaxial layer is grown may affect the characteristics of the device. For example, LEO may reduce dislocation density in epitaxial GaN layers.
• implantation of the p-type material layer 120 may expand the entire length of the transistor 100 as shown in Figure 2, Figure 4, and Figure 6. In some aspects, implantation of the p- type material layer 120 may partially extend the length of the transistor 100 as shown in Figure 3 and Figure 5.
• the p-type material layer 120 may be neutralized to limit the length of the p-type material layer 120.
• neutralizing may include implantation of impurities.
• the p-type material layer 120 may be formed by growing the p-type material layer 120. Growth may be epitaxial, for example. To limit the length of the p-type material layer 120, the p-type material layer 120 may be etched or otherwise neutralized.
• the substrate layer 102 may be etched and the p-type material layer 120 may be formed by growing the p-type material layer 120.
• the growth may be epitaxial.
• the p-type material layer 120 may be an epitaxial layer formed of SiC. In some aspects, the p-type material layer 120 may be an epitaxial layer and may be SiC and the p-type material layer 120 may include Al and/or Br. In some aspects, the p-type material layer 120 may be an epitaxial layer and may be SiC and the p-type material layer 120 may include implantation of Al and/or Br.
• the p-type material layer 120 may be an epitaxial layer and may be GaN. In some aspects, the p-type material layer 120 may be an epitaxial layer and may be GaN and the p-type material layer 120 may include magnesium (Mg), carbon (C), and/or Zinc. In some aspects, the p-type material layer 120 may be an epitaxial layer and may be GaN and the p-type material layer 120 may include implantation of magnesium (Mg), carbon (C), and/or Zinc.
• the substrate layer 102 may be etched and the p+ layer 106 may be formed by growing the p+ layer 106.
• the growth may be epitaxial.
• the p+ layer 106 may be an epitaxial layer formed of SiC. In some aspects, the p+ layer 106 may be an epitaxial layer and may be SiC and the p+ layer 106 may include Al and/or Br. In some aspects, the p+ layer 106 may be an epitaxial layer and may be SiC and the p+ layer 106 may include implantation of Al and/or Br. [0134] In aspects of the transistor 100 of the disclosure, the p+ layer 106 may be an epitaxial layer and may be GaN.
• the p+ layer 106 may be an epitaxial layer and may be GaN and the p+ layer 106 may include magnesium (Mg), carbon (C), and/or Zinc. In some aspects, the p+ layer 106 may be an epitaxial layer and may be GaN and the p+ layer 106 may include implantation of magnesium (Mg), carbon (C), and/or Zinc.
• the substrate layer 102 may be silicon carbide and include a carbon face.
• the substrate layer 102 may be silicon carbide and include a carbon face arranged adjacent the buffer layer 104.
• the substrate layer 102 may be silicon carbide and include a carbon face and the substrate layer 102 may be flipped so as to be arranged adjacent the buffer layer 104.
• the buffer layer 104 may be GaN having a nitrogen face adjacent the carbon face of the substrate layer 102.
• the buffer layer 104 may be GaN having alternating GaN and N layers with a N layer and/or a nitrogen face adjacent the carbon face of the substrate layer 102.
• the buffer layer 104 may include nonpolar GaN. In one aspect, the buffer layer 104 may include semipolar GaN. In one aspect, the buffer layer 104 may include hot wall epitaxy. In one aspect, the buffer layer 104 may include hot wall epitaxy having a thickness in the range of .15 microns to .25 microns, .2 microns to .3 microns, .25 microns to .35 microns, .3 microns to .35 microns, .35 microns to .4 microns, .4 microns to .45 microns, .45 microns to .5 microns, .5 microns to .55 microns, or .15 microns to .55 microns.
• the p-type material layer 120 may help avoid breakdowns and problems with material impurities. For example, without a p-type material layer 120, the transistor 100 may need impurities, which do not discharge well.
• the p-type material layer 120 may be formed beneath the source 1 10, and may extend toward the gate 114 of the device.
• the p-type material layer 120 may extend the entire length and remain as shown in Figure 2, Figure 4, and Figure 6. In one aspect, the p-type material layer 120 may generally extend the entire length and remain as shown in Figures 3 and 5. [0138] In another aspect of the disclosure, the p-type material layer 120 may not extend over the entire area of the transistor 100 as shown by the arrow LENGTH P 120 as shown in Figure 3 and Figure 5.
• the p-type material layer 120 may be selectively arranged as described herein, the p-type material layer 120 may be arranged over the entire length and selectively removed as described herein, the p-type material layer 120 may be arranged over the entire length and selectively electrically neutralized as described herein, or the like.
• the specific constructions of the p-type material layer 120 described below encompass any of these processes that result in the p-type material layer 120 having an operating construction and arrangement as noted below.
• the length and/or size of the p-type material layer 120 does not include a part that is partially electrically neutralized, partially etched, or the like.
• the length and/or size of the p-type material layer 120 may depend on the application of the transistor 100, requirements for the transistor 100, and the like. Limiting the p-type material layer 120 so that it does not extend beyond the gate 1 14 avoids adverse effects on RF performance for certain transistor applications.
• the p-type material layer 120 may extend horizontally parallel to the arrow LENGTH P 120. Moreover, the p-type material layer 120 may extend horizontally parallel to the arrow LENGTH P 120 to a point defined by a line that is perpendicular to the arrow
• LENGTH P 120 extends through a component of the transistor 100 as illustrated.
• the p-type material layer 120 may extend laterally from at least beneath the source 1 10 toward a first edge 124 of the gate 1 14 as illustrated in Figure 3. In one aspect, of the disclosure, the p-type material layer 120 may extend laterally from at least beneath the source 1 10 to a position beneath a first edge 124 of the gate 1 14.
• the p-type material layer 120 may extend horizontally to a point within about 0 to about 0.7 pm of the first edge 124 of the gate 1 14. In certain aspects of the disclosure, the p-type material layer 120 may extend horizontally to a point within about 0 to about 0.5 pm of the first edge 124 of the gate 1 14. In certain aspects of the disclosure, the p-type material layer 120 may extend horizontally to a point within about 0 to about 0.3 pm of the first edge 124 of the gate 1 14. In one aspect, of the disclosure, the p-type material layer 120 may extend horizontally from at least beneath the source 1 10 to a position beneath a second edge 122 of the gate 1 14.
• the p-type material layer 120 may extend horizontally to a point within about 0 to about 0.7 pm of the second edge 122 of the gate 1 14. In certain aspects of the disclosure, the p-type material layer 120 may extend horizontally to a point within about 0 to about 0.5 pm of the second edge 122 of the gate 1 14. In certain aspects of the disclosure, the p-type material layer 120 may extend horizontally to a point within about 0 to about 0.3 pm of the second edge 122 of the gate 1 14.
• a length of the p-type material layer 120 LENGTH P 120 can be seen in relation to positions and/or lengths of other components as illustrated in Figure 3.
• a length SD may be the length between an edge 142 of the source 1 10 and an edge 144 of the drain 1 12 as shown in Figure 3 by lines 150.
• the length of the p-type material layer 120 may extend from 10% to 20% of the length of SD, meaning the p-type material layer 120 may extend 10% to 20% past the edge 142 of the source 1 10 toward the drain 1 12.
• the length of the p-type material layer 120 may extend from 20% to 30% of the length of SD, meaning the p-type material layer 120 may extend 20% to 30% past the edge 142 of the source 1 10 toward the drain 1 12. In one aspect, the length of the p-type material layer 120 may extend from 30% to 40% of the length of SD, meaning the p-type material layer 120 may extend 30% to 40% past the edge 142 of the source 1 10 toward the drain 1 12. In one aspect, the length of the p-type material layer 120 may extend from 40% to 50% of the length of SD, meaning the p- type material layer 120 may extend 40% to 50% past the edge 142 of the source 1 10 toward the drain 1 12. In one aspect, the length of the p-type material layer 120 may extend from 50% to 60% of the length of SD, meaning the p-type material layer 120 may extend 50% to 60% past the edge 142 of the source 1 10 toward the drain 1 12.
• the p+ layer 106 may not extend over the entire area of the substrate layer 102 as shown by the arrow
• the p+ layer 106 may be selectively arranged as described in detail below, the p+ layer 106 may be arranged over the entire length and selectively removed as described in detail below, the p+ layer 106 may be arranged over the entire length and selectively electrically neutralized as described in detail below, or the like. Accordingly, the specific constructions of the p+ layer 106 described below encompass any of these configurations that result in the p+ layer 106 having an operating construction and arrangement as noted below. In other words, the length and/or size of the p+ layer 106 does not include a part that is partially electrically neutralized or partially etched. The length and/or size of the p+ layer 106 may depend on the application of the transistor 100, requirements for the transistor 100, and the like.
• the p+ layer 106 may extend horizontally parallel to the arrow LENGTH P+ 106. Moreover, the p+ layer 106 may extend horizontally parallel to the arrow LENGTH P+ 106 to a point defined by a line that is perpendicular to the arrow LENGTH P+ 106 and extends through a component of the transistor 100 as illustrated.
• the p+ layer 106 may extend to a point within about 0 to about 0.7 pm of the first edge 124 of the gate 1 14. In certain aspects of the disclosure, the p+ layer 106 may extend to a point within about 0 to about 0.5 pm of the first edge 124 of the gate 1 14. In certain aspects of the disclosure, the p+ layer 106 may extend to a point within about 0 to about 0.3 pm of the first edge 124 of the gate 1 14. In one aspect, of the disclosure, the p+ layer 106 may extend laterally from at least beneath the source 1 10 to a position beneath a second edge 122 of the gate 1 14.
• the p+ layer 106 may extend to a point within about 0 to about 0.7 pm of the second edge 122 of the gate 1 14. In certain aspects of the disclosure, the p+ layer 106 may extend to a point within about 0 to about 0.5 pm of the second edge 122 of the gate 1 14. In certain aspects of the disclosure, the p+ layer 106 may extend to a point within about 0 to about 0.3 pm of the second edge 122 of the gate 1 14.
• a length of the p+ layer 106 LENGTH P+ 106 can also be seen in relation to positions and/or lengths of other components based on the length SD as illustrated in Figure 3.
• the length SD in this case may be the length between an edge 142 of the source 1 10 toward an edge 144 of the drain 1 12 as shown in Figure 3.
• the length of the p+ layer 106 may extend from 10% to 20% of the length of SD, meaning the p+ layer 106 may extend 10% to 20% past the edge 142 of the source 1 10 toward the drain 1 12. In one aspect, the length of the p+ layer 106 may extend from 20% to 30% of the length of SD, meaning the p+ layer 106 may extend 20% to 30% past the edge 142 of the source 1 10 toward the drain 1 12. In one aspect, the length of the p+ layer 106 may extend from 30% to 40% of the length of SD, meaning the p+ layer 106 may extend 30% to 40% past the edge 142 of the source 1 10 toward the drain 1 12.
• the length of the p+ layer 106 may extend from 40% to 50% of the length of SD, meaning the p+ layer 106 may extend 40% to 50% past the edge 142 of the source 1 10 toward the drain 112. In one aspect, the length of the p+ layer 106 may extend from 50% to 60% of the length of SD, meaning the p+ layer 106 may extend 50% to 60% past the edge 142 of the source 1 10 toward the drain 1 12. In one aspect, the length of the p+ layer 106 may extend from 60% to 70% of the length of SD, meaning the p+ layer 106 may extend 60% to 70% past the edge 142 of the source 1 10 toward the drain 1 12.
• the length of the p+ layer 106 may extend from 70% to 80% of the length of SD, meaning the p+ layer 106 may extend 70% to 80% past the edge 142 of the source 1 10 toward the drain 1 12.
• a gate contact may be provided for the gate 1 14 in between the source 1 10 and the drain 1 12. Furthermore, in certain aspects of the disclosure, the gate contact may be disposed on the barrier layer 108. In one aspect, the gate contact may be disposed directly on the barrier layer 108.
• the gate 1 14 may be formed of platinum (Pt), nickel (Ni), and/or gold (Au), however, other metals known to one skilled in the art to achieve the Schottky effect, may be used.
• the gate 1 14 may include a Schottky gate contact that may have a three-layer structure. Such a structure may have advantages because of the high adhesion of some materials.
• the gate 1 14 may further include an overlayer of highly conductive metal.
• the gate 1 14 may be configured as a T-shaped gate.
• one or more metal overlayers may be provided on one or more of the source 1 10, the p-type material contact 1 18, the drain 1 12, and the gate 1 14.
• the overlayers may be Au, Silver (Ag), Al, Pt, Ti, Si, Ni, Al, and/or Copper (Cu). Other suitable highly conductive metals may also be used for the overlayers.
• the metal overlayer may electrically couple to the p-type material contact 1 18.
• the source 1 10, the p-type material contact 1 18, the drain 1 12, and the gate 1 14 may include Au, Silver (Ag), Al, Pt, Ti, Si, Ni, Al, and/or Copper (Cu). Other suitable highly conductive metals may also be used.
• Figure 8 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 8 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the p-type material layer 120 may be formed in or on the substrate layer 102 and the transistor 100 may include a second buffer layer 126.
• Figure 8 illustrates the transistor 100 with the first buffer layer 104 and the second buffer layer 126, the transistor 100 may also use only one buffer layer 104.
• Al may be implanted in the substrate layer 102 and annealed.
• the substrate layer 102 may be doped with the p-type material layer 120.
• the substrate layer 102 may be boron doped to form the p-type material layer 120.
• Other materials are contemplated as well including Ga.
• the length of the p-type material layer 120 near the surface of the p-type material layer 120 can be limited using the techniques described in other aspects.
• the second buffer layer 126 may be deposited or grown on the first buffer layer 104 on a side of the first buffer layer 104 opposite of the substrate layer 102. In one aspect, the second buffer layer 126 is formed directly on the first buffer layer 104. In one aspect, the second buffer layer 126 may be a high-purity material such as Gallium Nitride (GaN), AIN, or the like. In one aspect, the second buffer layer 126 may be a high-purity GaN. In one aspect, the second buffer layer 126 may be a high-purity AIN. The second buffer layer 126 may be a p- type material or n-type material. In another aspect, the second buffer layer 126 may be undoped.
• GaN Gallium Nitride
• AIN AIN
• the second buffer layer 126 may be a p- type material or n-type material. In another aspect, the second buffer layer 126 may be undoped.
• the contacts of the source 1 10, the gate 1 14, and/or the drain 1 12 may include Al, Ti, Si, Ni, and/or Pt.
• the p-type material contact 1 18 may include Al, Ti, Si, Ni, and/or Pt.
• the material of the contacts of the source 1 10, the gate 1 14, and/or the drain 1 12 may be the same material as the p-type material contact 1 18.
• utilizing the same material may be beneficial in that manufacturing may be easier, simplified, and/or less costly.
• the material of the contacts of the source 1 10, the gate 1 14, the drain 1 12, and the p-type material contact 1 18 may be different.
• the p+ layer 106 may be a graded layer. In one aspect, the p+ layer 106 may be a step-graded layer. In one aspect, the p+ layer 106 may be multiple layers. In one aspect, the p-type material layer 120 may be a graded layer. In one aspect, the p-type material layer 120 may be a step-graded layer. In one aspect, the p-type material layer 120 may be multiple layers.
• Figure 9 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 9 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 9 may include the p+ layer 106 (not shown in Figure 9) as described above. In other aspects, the transistor 100 of Figure 9 may not utilize the p+ layer 106 as shown in Figure 9. In one aspect of Figure 9, the transistor 100 may be implemented with only the p+ layer 106. In one aspect of Figure 9, the transistor 100 may be implemented with the p+ layer 106 and the p-type material layer 120. In one aspect of Figure 9, the transistor 100 may be implemented with only the p-type material layer 120.
• Figure 9 further illustrates implementation of a field plate 132.
• the field plate 132 may be arranged on the spacer layer 1 17 between the gate 1 14 and drain 1 12. In one aspect, the field plate 132 may be deposited on the spacer layer 1 17 between the gate 1 14 and the drain 1 12. In one aspect, the field plate 132 may be electrically connected to one or more other components in the transistor 100. In one aspect, the field plate 132 may not be electrically connected to any other components of the transistor 100.
• the field plate 132 may be adjacent the gate 1 14 and an additional spacer layer 1 17 of dielectric material may be included at least partially over the gate 1 14 to isolate the gate 1 14 from the field plate 132. In some aspects, the field plate 132 may overlap the gate 114 and an additional spacer layer 1 17 of dielectric material may be included at least partially over the gate 1 14 to isolate the gate 1 14 from the field plate 132.
• the field plate 132 may extend different distances from the edge of the gate 1 14, with a suitable range of distances being approximately 0.1 to 2 microns.
• the field plate 132 may include many different conductive materials with a suitable material being a metal, or combinations of metals, deposited using standard metallization methods.
• the field plate 132 may include titanium, gold, nickel, titanium/gold, nickel/gold, or the like.
• the field plate 132 may be formed on the spacer layer 1 17 between the gate 1 14 and the drain 1 12, with the field plate 132 being in proximity to the gate 1 14 but not overlapping the gate 1 14.
• a space between the gate 1 14 and field plate 132 may be wide enough to isolate the gate 114 from the field plate 132, while being small enough to maximize a field effect provided by the field plate 132.
• the field plate 132 may reduce a peak operating electric field in the transistor 100. In certain aspects, the field plate 132 may reduce the peak operating electric field in the transistor 100 and may increase the breakdown voltage of the transistor 100. In certain aspects, the field plate 132 may reduce the peak operating electric field in the transistor 100 and may reduce trapping in the transistor 100. In certain aspects, the field plate 132 may reduce the peak operating electric field in the transistor 100 and may reduce leakage currents in the transistor 100.
• the heterointerface 152 may be between the barrier layer 108 and the buffer layer 104.
• the source 110 and the drain 1 12 electrodes may be formed making ohmic contacts such that an electric current flows between the source 1 10 and the drain 1 12 electrodes via a two-dimensional electron gas (2DEG) induced at the heterointerface 152 between the buffer layer 104 and barrier layer 108 when a gate 1 14 electrode is biased at an appropriate level.
• the heterointerface 152 may be in the range of .005 pm to .007 pm, .007 pm to .009 pm, and .009 pm to .01 1 pm.
• Figure 10 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 10 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 10 may include the p+ layer 106 (not shown in Figure 10) as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p-type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• buried p-layers such as the p+ layer 106 and/or the p-type material layer 120 may be beneficial for the transistor 100 implemented as HEMTs for RF applications to obtain high breakdown voltage and good isolation between the input and output.
• the buried p-layer may not be connected to the source 1 10 as described herein.
• a forward bias conduction between the p-layer (the p+ layer 106 and/or the p-type material layer 120) and the drain 1 12 may cause a loss of input-output isolation when the transistor 100 is in the OFF condition.
• aspects illustrated in Figure 10 of this disclosure may include connecting the buried p-layer (the p+ layer 106 and/or the p-type material layer 120) to the gate 1 14.
• connection 154 may be formed on the spacer layer 1 16 and/or the spacer layer 1 17 to extend between the p-type material contact 118 and the gate 1 14.
• connection 154 may include a conductive material, many different conductive materials, a suitable material being a metal, or combinations of metals, deposited using standard metallization methods.
• the materials may include one or more of titanium, gold, nickel, or the like.
• the source 1 10 and the drain 1 12 may be symmetrical with respect to the gate 1 14. In some switch device application aspects, the source 1 10 and the drain 1 12 may be symmetrical with respect to the gate 1 14.
• An additional advantage of the Figure 10 configuration may be that the p-layer may be used as a second gate, which allows use of multiple barrier layers 108 and/or multiple channel layers.
• multiple barrier layers 108 and/or multiple channel layers may reduce the on-resistance of the transistor 100, an important performance characteristic.
• the reduced on-resistance may be obtained without significantly increasing an input-output capacitance, another important characteristic.
• the Figure 10 configuration may enable reduction of Ron-Coff product, an important figure-of-merit for RF switches.
• Figure 1 1 shows a partial plan view of another aspect of a transistor according to the disclosure.
• Figure 1 1 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 1 1 may be configured such that the p-layer may be provided with a separate contact 162 and may be configured to receive its own bias and signals. In this way, the p-layer can be used to modulate the characteristics of the transistor 100.
• Figure 1 1 further illustrates the transistor 100 including the source 1 10, the gate 1 14, and the drain 1 12. In this regard, some of the various layers and components of the transistor 100 may not be shown for clarity of understanding.
• the transistor 100 may be implemented with only the p+ layer 106. In one aspect of Figure 1 1 , the transistor 100 may be implemented with the p+ layer 106 and the p-type material layer 120. In one aspect of Figure 1 1 , the transistor 100 may be implemented with only the p-type material layer 120. In each case, the p+ layer 106 and the p-type material layer 120 are shown with a dashed line indicative of the layer or layers being buried.
• the p-type material layer 120 may be provided with a contact pad 162.
• the p-type material layer 120 through the contact pad 162 may receive its own bias and signals.
• the p-type material layer 120 may be used to modulate characteristics of the transistor 100.
• the p-type material layer 120 may be provided with the p-type material contact 1 18.
• the p-type material contact 1 18 may be electrically connected to a connection 166 that may be electrically connected to a contact pad 162.
• the connection 166 may include a conductive material, many different conductive materials, a suitable material being a metal, or combinations of metals, deposited using standard metallization methods.
• the materials may include one or more of titanium, gold, nickel, or the like.
• the p+ layer 106 may be provided with a contact pad 162.
• the p+ layer 106 through the contact pad 162 may receive its own bias and signals.
• the contact pad 162 may be used to modulate characteristics of the transistor 100.
• the p+ layer 106 may be provided with the p-type material contact 1 18.
• the p-type material contact 1 18 may be electrically connected to a connection 166 that may be electrically connected to a contact pad 162.
• connection 166 may be a metallic connection that extends from the p-type material contact 1 18 to the contact pad 162.
• the contact pad 162 may be a buried contact pad.
• the contact pad 162 may be buried in any one of the above-noted structures of the transistor 100.
• the contact pad 162 may be arranged on the barrier layer 108.
• the contact pad 162 may be arranged directly on the barrier layer 108. In one aspect, the contact pad 162 may be arranged on a spacer layer 1 16 on the barrier layer 108. In one aspect, the contact pad 162 may be separate and separated from the gate 1 14, the source 1 10, and/or the drain 1 12.
• Figure 1 1 further illustrates a gate pad 168 that is electrically connected to the gate 1 14. It should be noted that the size, arrangement, and configuration of the p-type material contact 1 18, the connection 166, the contact pad 162, the p+ layer 106, the p-type material layer 120, and the like illustrated in Figure 1 1 is merely exemplary. Others sizes,
• Figure 12 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 12 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 12 may include the p+ layer 106 as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p- type material layer 120 (not shown in Figure 12).
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• the transistor 100 of Figure 12 illustrates the field plate 132 connected to the source 1 10 through a connection 140 (source - field plate interconnect).
• the field plate 132 may not include a connection to the p-type material layer 120.
• the connection 140 may be formed on the spacer layer 1 16 and/or the spacer layer 1 17 to extend between the field plate 132 and the source 1 10.
• connection 140 may be formed with the field plate 132 during the same manufacturing step. In one aspect, a plurality of the connections 140 may be used. In one aspect, a plurality of the field plates 132 may be used. In one aspect, a plurality of the field plates 132 may be used and each of the plurality of field plates 132 may be stacked with a dielectric material
• connection 140 may include a conductive material, many different conductive materials, a suitable material being a metal, or combinations of metals, deposited using standard metallization methods.
• the materials may include one or more of titanium, gold, nickel, or the like.
• Figure 13 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 13 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 13 may include the p+ layer 106 (not shown in Figure 13) as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p-type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• the transistor 100 of Figure 13 illustrates the field plate 132 connected to the source 1 10 through a connection 140.
• Figure 13 further illustrates that the p-type material contact 1 18 may be electrically connected to the source 1 10 with a connection 138.
• the connection 138 may be formed on a spacer layer 1 16 and/or the spacer layer 1 17 to extend between the p- type material contact 1 18 and the source 1 10.
• the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18.
• the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18 without connecting to the source 1 10.
• the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18 without any intervening connections.
• the connection 138 may include a conductive material, many different conductive materials, a suitable material being a metal or combinations of metals, deposited using standard metallization methods.
• the materials may include one or more of titanium, gold, nickel, or the like.
• Figure 14 shows a process for making a transistor according to the disclosure.
• Figure 14 shows an exemplary process 500 for making the transistor 100 of the disclosure. It should be noted that the process 500 is merely exemplary and may be modified consistent with the various aspects disclosed herein.
• the process 500 may begin at step 502 by forming a substrate layer 102.
• the substrate layer 102 may be made of Silicon Carbide (SiC).
• the substrate layer 102 may be a semi-insulating SiC substrate, a p-type substrate, an n-type substrate, and/or the like.
• the substrate layer 102 may be very lightly doped.
• the background impurity levels may be low. In one aspect, the background impurity levels may be 1 E15/cm 3 or less.
• the substrate layer 102 may be formed of SiC selected from the group of 6H, 4H, 15R, 3C SiC, or the like.
• the substrate layer 102 may be GaAs, GaN, or other material suitable for the applications described herein.
• the substrate layer 102 may include sapphire, spinel, ZnO, silicon, or any other material capable of supporting growth of Group Ill-nitride materials.
• the process 500 may include a step 504 of implanting Al into the substrate layer 102 to form the p-type material layer 120 in the substrate layer 102 as shown, for example, in Figure 2 and Figure 3.
• the p-type material layer 120 may be formed by ion implantation of Al and annealing.
• the p-type material layer 120 may be formed by implantation and annealing of Al prior to the growth of any GaN layers.
• the ion implementation may utilize channeling implants.
• the channeling implants may include aligning the ion beam to the substrate layer 102. Alignment of the ion beam may result in increased implantation efficiency.
• the process 500 may further include implanting Al into the substrate layer 102 to form the p+ layer 106 in the substrate layer 102 as shown, for example, in Figure 2 and Figure 3. Thereafter, the substrate layer 102 may be annealed as defined herein.
• dose 1 E13cm 2 at 25°C.
• other implant energies and doses are contemplated as well.
• the buffer layer 104 may be formed at step 506 on the substrate layer 102.
• the buffer layer 104 may be grown or deposited on the substrate layer 102.
• the buffer layer 104 may be GaN.
• the buffer layer 104 may be formed with LEO.
• a nucleation layer 136 may be formed on the substrate layer 102 and the buffer layer 104 may be formed at step 506 on the nucleation layer 136.
• the buffer layer 104 may be grown or deposited on the nucleation layer 136.
• the buffer layer 104 may be GaN.
• the buffer layer 104 may be formed with LEO.
• the process 500 may include, as a further part of the step 504, forming the epitaxial layer 202 on the substrate layer 102. Thereafter, the epitaxial layer 202 may be removed, etched, damaged, and/or the like to form the p-type material layer 120 in the epitaxial layer 202 as shown in Figure 3 and Figure 4. Additionally, the p+ layer 106 may be formed as described herein.
• the buffer layer 104 may be formed at step 506 on the epitaxial layer 202.
• the buffer layer 104 may be grown or deposited on the epitaxial layer 202.
• the buffer layer 104 may be GaN.
• the buffer layer 104 may be formed with LEO.
• the barrier layer 108 may be formed on the buffer layer 104.
• the barrier layer 108 may be an n-type conductivity layer or may be undoped.
• the barrier layer 108 may be AIGaN.
• the spacer layer 1 16 may be formed.
• the spacer layer 116 may be a passivation layer, such as SiN, AIO, SiO, S1O2, AIN, or the like, or a combination incorporating multiple layers thereof, which may be deposited over the exposed surface of the barrier layer 108.
• a recess may be created by removing at least part of the barrier layer 108 and at least part of the buffer layer 104.
• the recess 1 19 may remove any material above the p-type material layer 120 within a portion of a region associated with the source 1 10, exposing the p-type material layer 120 on a side opposite of the substrate layer 102.
• a recess 1 19 may be created by removing at least part of the barrier layer 108 and at least part of the buffer layer 104.
• the recess formation process may remove any material above the p+ layer 106 within a portion of a region associated with the source 1 10, exposing the p+ layer 106 on a side opposite of the substrate layer 102.
• the source 1 10 may be arranged on the barrier layer 108.
• the source 1 10 may be an ohmic contact of a suitable material that may be annealed.
• the source 1 10 may be annealed at a temperature of from about 500° C. to about 800° C. for about 2 minutes. However, other times and temperatures may also be utilized. Times from about 30 seconds to about 10 minutes may be, for example, acceptable.
• the source 1 10 may include Al, Ti, Si, Ni, and/or Pt.
• a region 164 under the source 1 10 that is a N+ material may be formed in the barrier layer 108.
• a region 164 under the drain 1 12 may be Si doped.
• the drain 1 12 may be arranged on the barrier layer 108.
• the drain 1 12 may be may be an ohmic contact of Ni or another suitable material, and may also be annealed in a similar fashion.
• an n+ implant may be used in conjunction with the barrier layer 108 and the contacts are made to the implant.
• a region 164 under the drain 1 12 that is a N+ material may be formed in the barrier layer 108.
• a region 164 under the drain 1 12 may be Si doped.
• the gate 1 14 may be arranged on the barrier layer 108 between the source 1 10 and the drain 1 12.
• a layer of Ni, Pt, AU, or the like may be formed for the gate 1 14 by evaporative deposition or another technique.
• the gate structure may then be completed by deposition of Pt and Au, or other suitable materials.
• the contacts of the gate 1 14 may include Al, Ti, Si, Ni, and/or Pt.
• the p-type material contact 1 18 may be formed. Once the p+ layer 106 is exposed, nickel or another suitable material may be evaporated to deposit the p-type material contact 118. The nickel or another suitable material may be annealed to form an ohmic contact, for example.
• the contacts of the p-type material contact 1 18 may include Al, Ti, Si, Ni, and/or Pt. Such a deposition and annealing process may be carried out utilizing conventional techniques known to those of skill in the art. For example, an ohmic contact for the p-type material contact 1 18 may be annealed at a temperature of from about 600° C. to about 1050° C.
• a metal overlayer may electrically couple the p-type material contact 1 18 of the p+ layer 106 to the source 1 10. Doing this may maintain the conductivity of the p+ layer 106 and the source 1 10 at the same potential.
• the source 1 10 and the drain 1 12 electrodes may be formed making ohmic contacts such that an electric current flows between the source 1 10 and drain 1 12 electrodes via a two-dimensional electron gas (2DEG) induced at the heterointerface 152 between the buffer layer 104 and barrier layer 108 when a gate 114 electrode is biased at an appropriate level.
• the hetero interface 152 may be in the range of .005 pm to .007 pm, .007 pm to .009 pm, and .009 pm to .01 1 pm.
• the gate 1 14 may extend on top of a spacer or the spacer layer 116.
• the spacer layer 1 16 may be etched and the gate 1 14 deposited such that the bottom of the gate 1 14 is on the surface of barrier layer 108.
• the metal forming the gate 1 14 may be patterned to extend across spacer layer 1 16 so that the top of the gate 1 14 forms a field plate 132.
• a field plate 132 may be arranged on top of another spacer layer 1 17 and may be separated from the gate 1 14.
• the field plate 132 may be deposited on the spacer layer 1 17 between the gate 1 14 and the drain 1 12.
• the field plate 132 may include many different conductive materials with a suitable material being a metal, or combinations of metals, deposited using standard metallization methods.
• the field plate 132 may include titanium, gold, nickel, titanium/gold, nickel/gold, or the like.
• the connection 140 may be formed with the field plate 132 during the same manufacturing step (see Figure 12).
• a plurality of the field plates 132 may be used.
• a plurality of the field plates 132 may be used and each of the plurality of field plates 132 may be stacked with a dielectric material therebetween.
• the field plate 132 extends toward the edge of gate 1 14 towards the drain 1 12.
• the field plate 132 extends towards the source 1 10.
• the field plate 132 extends towards the drain 1 12 and towards the source 1 10.
• the field plate 132 does not extend toward the edge of gate 1 14.
• the structure may be covered with a dielectric spacer layer such as silicon nitride.
• the dielectric spacer layer may also be implemented similar to the spacer layer 1 16.
• the cross-sectional shape of the gate 1 14, shown in the Figures is exemplary.
• the cross-sectional shape of the gate 1 14 in some aspects may not include the T-shaped extensions.
• Other constructions of the gate 1 14 may be utilized, for example, the construction of the gate 1 14 illustrated in Figure 8 or Figure 1.
• connection 154 may be formed.
• the connection 154 may be formed to extend between the p-type material contact 1 18 and the gate 1 14 (see Figure 16).
• connection 154 may be formed on the spacer layer 116 to extend between the p-type material contact 1 18 and the gate 1 14.
• connection 140 may be formed (see Figure 13).
• the field plate 132 may be electrically connected to the source 1 10 with the connection 140.
• the connection 140 may be formed on the spacer layer 1 17 to extend between the field plate 132 and the source 1 10.
• connection 166 and the contact pad 162 may be formed (see Figure 1 1 ).
• the p-type material contact 1 18 may be electrically connected to the connection 166 that may be electrically connected to a contact pad 162.
• the gate pad 168 may be formed.
• the steps of process 500 may be performed in a different order consistent with the aspects described above. Moreover, the process 500 may be modified to have more or fewer process steps consistent with the various aspects disclosed herein.
• the transistor 100 may be implemented with only the p+ layer 106. In one aspect of the process 500, the transistor 100 may be implemented with the p+ layer 106 and the p- type material layer 120. In one aspect of the process 500, the transistor 100 may be implemented with only the p-type material layer 120.
• Figure 15 illustrates a distribution of Al implanted with channeling conditions according to aspects of the disclosure in comparison to simulations for conventional implant conditions.
• Figure 15 illustrates a distribution of 27 AI in 4H-SiC implanted with channeling conditions along C-axis (secondary ion mass spectrometry (SIMS) data) in comparison with simulations for conventional implant conditions (TRIM) off axis.
• the p-type material layer 120 may be implanted consistent with this implant energy and dose.
• other implant energies and doses are contemplated as well as described herein.
• the p-type material layer 120 may have a doping concentration less than the p+ layer 106. In one aspect, p+ layer 106 may be doped as highly as possible with minimum achievable sheet resistance. In one aspect, the p-type material layer 120 may have an implantation concentration less than the p+ layer 106. In one aspect, p+ layer 106 may have an implantation concentration as high as possible with minimum achievable sheet resistance. In one aspect, the p- type material layer 120 may have an implantation concentration less than 10 19 . In one aspect, the p-type material layer 120 may have an implantation concentration less than 10 20 .
• the p-type material layer 120 may have an implantation concentration of 10 17 - 10 20 , 10 19 - 10 20 , 10 18 - 10 19 , or 10 17 - 10 18 .
• the p + layer 106 may have an implantation concentration 10 19 or greater.
• the p + layer 106 may have an implantation concentration of ⁇ o 18 — 10 20 , 10 18 — 10 19 , or 10 19 - 10 20 .
• the p-type material layer 120 doping may be less than 1 E17 cm 3 . In one aspect, the p-type material layer 120 doping may be less than 2E17 cm 3 . In one aspect, the p-type material layer 120 doping may be less than 6E17 cm 3 . In one aspect, the p-type material layer 120 doping may be less than 2E18 cm 3 . In one aspect, the p-type material layer 120 doping may be in the range of 5E15 to 5E17 per cm 3 . In these aspects, the p+ layer 106 doping concentration may be greater than a doping concentration of the p-type material layer 120.
• Figure 16 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 16 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 16 may include the p+ layer 106 (not shown in Figure 16) as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p-type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 16 illustrates a transistor 100 that may include a gate 1 14 as well as a connection 154.
• the connection 154 may connect the gate 1 14 to the p-type material contact 1 18.
• the gate 1 14 may be a T-shaped gate.
• the gate 1 14 may be a non-T shaped gate.
• Figure 17 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 17 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 17 may include the p+ layer 106 as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p- type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 17 illustrates a transistor 100 that may include a p+ layer 106 in the substrate layer 102.
• the transistor 100 may include a p-type material layer 120 in the substrate layer 102.
• the transistor 100 may include a p+ layer 106 in the epitaxial layer 202.
• the transistor 100 may include a p-type material layer 120 in the epitaxial layer 202.
• a transistor 100 may include a p+ layer 106 in the substrate layer 102, a p-type material layer 120 in the substrate layer 102, a p+ layer 106 in the epitaxial layer 202, and a p-type material layer 120 in the epitaxial layer 202.
• Figure 17 further illustrates that the transistor 100 may include a field plate 132
• Figure 18 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 18 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 18 may include the p+ layer 106 (not shown) as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p-type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 18 illustrates that the transistor 100 may include a field plate 132.
• the transistor 100 may further include a connection 140 to connect the field plate 132 to the source 1 10.
• the transistor 100 may further include a connection 138 to connect the field plate 132 and/or the source 1 10 to the p-type material contact 1 18.
• the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18.
• the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18 without connecting to the source 1 10.
• the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18 without any intervening connections.
• Figure 19 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 19 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 19 may include the p+ layer 106 (not shown) as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p-type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein. In aspects that utilize the p+ layer 106, the p+ layer 106 may be implanted as described herein. In aspects that utilize the p+ layer 106, the p+ layer 106 may be formed as described herein. [0216] In particular, Figure 19 illustrates a transistor 100 that may include a p-type material layer 120 in the substrate layer 102. In one aspect, the transistor 100 may include a p-type material layer 120 in the epitaxial layer 202. In one aspect, the transistor 100 may include a p-type material layer 120 in the substrate layer 102 and may include a p-type material layer 120 in the epitaxial layer 202.
• the transistor 100 may include a field plate 132. In one aspect, the transistor 100 may further include a connection 140 to connect the field plate 132 to the source 1 10. In one aspect, the transistor 100 may further include a connection 138 (source interconnect) to connect the field plate 132 and/or the source 1 10 to the p-type material contact 1 18. In one aspect, the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18. In one aspect, the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 118 without connecting to the source 1 10. In one aspect, the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18 without any intervening connections.
• Figure 20 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 20 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 20 may include the p+ layer 106 as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p- type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 20 illustrates a transistor 100 that may include a p+ layer 106 in an epitaxial layer 202.
• Figure 20 further illustrates that the transistor 100 may include a p-type material layer 120 in the epitaxial layer 202.
• the transistor 100 may include a field plate 132. In one aspect, the transistor 100 may further include a connection 140 to connect the field plate 132 to the source 1 10. In one aspect, the transistor 100 may further include a connection 138 (source interconnect) to connect the field plate 132 and/or the source 1 10 to the p-type material contact 1 18. In one aspect, the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18. In one aspect, the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 118 without connecting to the source 1 10. In one aspect, the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18 without any intervening connections.
• Figure 21 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 21 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 21 may include the p+ layer 106 (not shown) as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p-type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 21 illustrates a transistor 100 that may include a p-type material layer 120 in the substrate layer 102.
• the transistor 100 may include a gate 1 14 having a T-shaped cross section.
• the gate 1 14 may be a non-T shaped gate.
• the transistor 100 may include a field plate 132. In one aspect, the transistor 100 may further include a connection 140 to connect the field plate 132 to the source 1 10. In one aspect, the transistor 100 may further include a connection 138 to connect the field plate 132 and/or the source 1 10 to the p-type material contact 1 18. In one aspect, the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18. In one aspect, the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18 without connecting to the source 1 10. In one aspect, the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18 without any intervening connections.
• Figure 22 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 22 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 22 may include the p+ layer 106 (not shown) as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p-type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 22 illustrates a transistor 100 that may include a p-type material layer 120 in the substrate layer 102.
• the transistor 100 may include a gate 1 14 having a T-shaped cross section.
• the gate 1 14 may be a non-T shaped gate.
• the transistor 100 may include a connection 154.
• the connection 154 may connect the gate 1 14 to the p-type material contact 1 18.
• Figure 23 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 23 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 23 may include the p+ layer 106 (not shown) as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p-type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 23 illustrates a transistor 100 that may include a p-type material layer 120 in the epitaxial layer 202.
• the transistor 100 may include a gate 1 14 having a T-shaped cross section.
• the transistor 100 may include a connection 154.
• the connection 154 may connect the gate 1 14 to the p-type material contact 118.
• Figure 24 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 24 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 24 may include the p+ layer 106 as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p- type material layer 120 (not shown).
• the transistor 100 may be implemented with only the p-type material layer 120 (not shown).
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 24 illustrates a transistor 100 that may include a p+ layer 106 in the epitaxial layer 202.
• the transistor 100 may include a gate 1 14 having a T-shaped cross section.
• the gate 1 14 may be a non-T shaped gate.
• the transistor 100 may include a connection 154.
• the connection 154 may connect the gate 1 14 to the p-type material contact 1 18.
• Figure 25 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 25 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 25 may include the p+ layer 106 (not shown) as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p-type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 25 illustrates a transistor 100 that may include a p-type material layer 120 in the substrate layer 102.
• the transistor 100 may include a p-type material layer 120 in the epitaxial layer 202.
• the transistor 100 may include a p-type material layer 120 in the substrate layer 102 and may include a p-type material layer 120 in the epitaxial layer 202.
• the transistor 100 may include a gate 1 14 having a T-shaped cross section.
• the transistor 100 may include a connection 154.
• the connection 154 may connect the gate 1 14 to the p-type material contact 1 18.
• Figure 26 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 26 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 26 may include the p+ layer 106 as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p- type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 26 illustrates a transistor 100 that may include a p+ layer 106 in an epitaxial layer 202.
• Figure 26 further illustrates that the transistor 100 may include a p-type material layer 120 in the epitaxial layer 202.
• a transistor 100 may include a p+ layer 106 in an epitaxial layer 202 and may include a p-type material layer 120 in the epitaxial layer 202.
• the transistor 100 may include a gate 1 14 having a T-shaped cross section.
• the transistor 100 may include a connection 154.
• the connection 154 may connect the gate 1 14 to the p-type material contact 1 18.
• Figure 27 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 27 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 27 may include the p+ layer 106 as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p- type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 27 illustrates a transistor 100 that may include a p+ layer 106 in an epitaxial layer 202.
• Figure 27 further illustrates that the transistor 100 may include a p-type material layer 120 in the epitaxial layer 202.
• a transistor 100 may include a p+ layer 106 in an epitaxial layer 202 and a p-type material layer 120 in the epitaxial layer 202.
• the transistor 100 may include a gate 1 14 having a T-shaped cross section. In one aspect, the transistor 100 may include a connection 154. In one aspect, the connection 154 may connect the gate 1 14 to the p-type material contact 1 18. In one aspect as illustrated in Figure 27, the transistor 100 may further include a field plate 132.
• Figure 28 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 28 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 28 may include the p+ layer 106 (not shown) as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p-type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 28 illustrates a transistor 100 that may include a p-type material layer 120 in the epitaxial layer 202.
• the transistor 100 may include a gate 1 14 having a T-shaped cross section.
• the p-type material layer 120 may be provided with the p-type material contact 1 18.
• the p-type material contact 1 18 may be electrically connected to a connection 166 that may be electrically connected to a contact pad 162.
• the contact pad 162 may be used to modulate characteristics of the transistor 100.
• Figure 29 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 29 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 29 may include the p+ layer 106 (not shown) as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p-type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• the transistor 100 may include a gate 1 14 having a T-shaped cross section.
• the gate 1 14 may be a non-T shaped gate.
• the p-type material layer 120 may be provided with the p-type material contact 1 18.
• the p-type material contact 1 18 may be electrically connected to a connection 166 that may be electrically connected to a contact pad 162.
• the contact pad 162 may be used to modulate characteristics of the transistor 100.
• Figure 30 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 30 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 30 may include the p+ layer 106 (not shown) as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p-type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 30 illustrates a transistor 100 that may include a p-type material layer 120 in the substrate layer 102 and may include a p-type material layer 120 in the epitaxial layer 202.
• the transistor 100 may include a gate 1 14 having a T-shaped cross section.
• the p-type material layer 120 may be provided with the p-type material contact 1 18.
• the p-type material contact 1 18 may be electrically connected to a connection 166 that may be electrically connected to a contact pad 162.
• the contact pad 162 may be used to modulate characteristics of the transistor 100.
• Figure 31 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 31 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 31 may include the p+ layer 106 as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p- type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 31 illustrates a transistor 100 that may include a p+ layer 106 in the substrate layer 102.
• the transistor 100 may include a p-type material layer 120 in the substrate layer 102.
• a transistor 100 may include a p+ layer 106 in the substrate layer 102 and may include a p-type material layer 120 in the substrate layer 102.
• the transistor 100 may include a gate 1 14 having a T-shaped cross section.
• the p-type material layer 120 may be provided with the p-type material contact 1 18.
• the p-type material contact 1 18 may be electrically connected to a connection 166 that may be electrically connected to a contact pad 162.
• the contact pad 162 may be used to modulate characteristics of the transistor 100.
• the p+ layer 106 may be provided with the p-type material contact 1 18.
• the p-type material contact 1 18 may be electrically connected to a connection 166 that may be electrically connected to a contact pad 162.
• the contact pad 162 may be used to modulate characteristics of the transistor 100.
• Figure 32 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 32 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 32 may include the p+ layer 106 as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p- type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 32 illustrates a transistor 100 that may include a p+ layer 106 in the substrate layer 102.
• the transistor 100 may include a p-type material layer 120 in the substrate layer 102.
• a transistor 100 may include a p+ layer 106 in the substrate layer 102 and may include a p-type material layer 120 in the substrate layer 102.
• the p-type material layer 120 may be provided with the p-type material contact 1 18.
• the p-type material contact 1 18 may be electrically connected to a connection 166 that may be electrically connected to a contact pad 162.
• the contact pad 162 may be used to modulate characteristics of the transistor 100.
• the transistor 100 may include a field plate 132.
• the p+ layer 106 may be provided with the p-type material contact 1 18.
• the p-type material contact 1 18 may be electrically connected to a connection 166 that may be electrically connected to a contact pad 162.
• the contact pad 162 may be used to modulate characteristics of the transistor 100.
• Figure 33 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 33 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 33 may include the p+ layer 106 as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p- type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 33 illustrates a transistor 100 that may include a p+ layer 106 in the substrate layer 102.
• the transistor 100 may include a p-type material layer 120 in the substrate layer 102.
• a transistor 100 may include a p+ layer 106 in the substrate layer 102 and may include a p-type material layer 120 in the substrate layer 102.
• the transistor 100 may include a field plate 132 adjacent the gate 1 14.
• the transistor 100 may include a gate 1 14 having a T-shaped cross section.
• the p-type material layer 120 may be provided with the p-type material contact 1 18.
• the p-type material contact 1 18 may be electrically connected to a connection 166 that may be electrically connected to a contact pad 162.
• the contact pad 162 may be used to modulate characteristics of the transistor 100.
• the p+ layer 106 may be provided with the p-type material contact 1 18.
• the p-type material contact 1 18 may be electrically connected to a connection 166 that may be electrically connected to a contact pad 162.
• the contact pad 162 may be used to modulate characteristics of the transistor 100.
• Figure 34 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 34 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 34 may include the p+ layer 106 as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p- type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein.
• the p-type material layer 120 may be formed as described herein.
• the p+ layer 106 may be implanted as described herein.
• the p+ layer 106 may be formed as described herein.
• Figure 34 illustrates a transistor 100 that may include a p+ layer 106 in the substrate layer 102.
• the transistor 100 may include a p-type material layer 120 in the substrate layer 102.
• a transistor 100 may include a p+ layer 106 in the substrate layer 102 and may include a p-type material layer 120 in the substrate layer 102.
• the transistor 100 may include a field plate 132.
• the transistor 100 may include a gate 1 14 having a T-shaped cross section.
• the gate 1 14 may be a non-T shaped gate.
• the transistor 100 may further include a connection 140 to connect the field plate 132 to the source 1 10.
• the p-type material layer 120 may be provided with the p-type material contact 1 18.
• the p-type material contact 1 18 may be electrically connected to a connection 166 that may be electrically connected to a contact pad 162.
• the contact pad 162 may be used to modulate characteristics of the transistor 100.
• the transistor 100 may further include a connection 138 to connect the field plate 132 and/or the source 1 10 to the p-type material contact 1 18.
• the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18.
• the transistor 100 may further include a connection 138 and a connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18 without connecting to the source 1 10.
• the transistor 100 may further include a connection 138 and a
• connection 140 configured to connect the field plate 132 directly to the p-type material contact 1 18 without any intervening connections.
• the p+ layer 106 may be provided with the p-type material contact 1 18.
• the p-type material contact 1 18 may be electrically connected to a connection 166 that may be electrically connected to a contact pad 162.
• the contact pad 162 may be used to modulate characteristics of the transistor 100.
• Figure 35 shows a cross-sectional view of another aspect of a transistor according to the disclosure.
• Figure 35 illustrates a transistor 100 that may include any one or more aspects of the disclosure described herein.
• the transistor 100 of Figure 35 may include the p+ layer 106 as described above. Other aspects may not utilize the p+ layer 106.
• the transistor 100 may be implemented with only the p+ layer 106.
• the transistor 100 may be implemented with the p+ layer 106 and the p- type material layer 120.
• the transistor 100 may be implemented with only the p-type material layer 120.
• the p-type material layer 120 may be implanted as described herein. In aspects that utilize the p-type material layer 120, the p-type material layer 120 may be formed as described herein. In aspects that utilize the p+ layer 106, the p+ layer 106 may be implanted as described herein. In aspects that utilize the p+ layer 106, the p+ layer 106 may be formed as described herein.
• Figure 35 illustrates a transistor 100 that may be implemented without the p-type material contact 1 18.
• the transistor 100 of Figure 35 together with the p-type material layer 120 and/or the p+ layer 106 may also reduce drain lag effect compared to a transistor without such p-layers.
• the disclosure has set forth a simpler alternative solution to forming p-type layers in HEMTs.
• the disclosed structure can be readily fabricated with currently available techniques.
• the disclosed use of a high-purity material minimizes drain lag effects.
• the disclosed p-type material layer provides a retarding electric field to obtain good electron confinement with low leakage.
• aspects of this disclosure have described in detail variations of transistors with p-type layers and the ways those p-type layers are formed. The disclosed transistors maximize RF power, allow for efficient discharge, and maximize breakdowns.
• transistors such as GaN HEMTs, fabricated on high resistivity substrates may be utilized for high power RF (radio frequency) amplifiers, for high power radiofrequency (RF) applications, and also for low frequency high power switching applications.
• RF radio frequency
• RF radiofrequency
• the advantageous electronic and thermal properties of GaN HEMTs also make them very attractive for switching high power RF signals.
• the disclosure has described a structure with a buried p-layer under the source region to obtain high breakdown voltage in HEMTs for various applications including power amplifiers while at the same time eliminating drifts in device characteristics arising from trapping in the buffer and/or semi-insulating substrates.
• Use of buried p-layers may also be important in HEMTs for RF switches to obtain high breakdown voltage and good isolation between the input and output.
• Example 1 An apparatus, comprising: a substrate; a group Ill- Nitride buffer layer on the substrate; a group Ill-Nitride barrier layer on the group Ill- Nitride buffer layer, the group Ill-Nitride barrier layer comprising a higher bandgap than a bandgap of the group Ill-Nitride buffer layer; a source electrically coupled to the group Ill-Nitride barrier layer; a gate electrically coupled to the group Ill-Nitride barrier layer; a drain electrically coupled to the group Ill-Nitride barrier layer; and a p- region being at least one of the following: in the substrate or on the substrate below said group Ill-Nitride barrier layer.
• Example 2 The apparatus of Example 1 , wherein the p-region is on the substrate below said group Ill-Nitride barrier layer.
• Example 3 The apparatus of Example 2, wherein the p-region is implanted.
• Example 4 The apparatus of Example 2, wherein the p-region comprises at least two p-regions.
• Example 5 The apparatus of Example 1 , wherein the p-region is in the substrate below said group Ill-Nitride barrier layer.
• Example 6 The apparatus of Example 5, wherein the p-region is implanted.
• Example 7 The apparatus of Example 5, wherein the p-region comprises at least two p-regions.
• Example 8 The apparatus of Example 1 , further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer.
• Example 9 The apparatus of Example 8, wherein the p-region is implanted in the epitaxial layer.
• Example 10 The apparatus of Example 8, wherein the p-region comprises at least two p-regions in the epitaxial layer.
• Example 1 1. The apparatus of Example 8, wherein the epitaxial layer is below the group Ill-Nitride barrier layer.
• Example 12 The apparatus of Example 1 , further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer, wherein the p-region is also in the substrate below said group Ill-Nitride barrier layer.
• Example 13 The apparatus of Example 12, wherein at least one of the p-regions in implanted.
• Example 14 The apparatus of Example 12, wherein the p-region comprises at least two p-regions.
• Example 15 The apparatus of Example 1 , wherein the p-region is on the substrate below said group Ill-Nitride barrier layer, wherein the p-region is also in the substrate below said group Ill-Nitride barrier layer.
• Example 16 The apparatus of Example 15, wherein at least one of the p-regions is implanted.
• Example 17 The apparatus of Example 15, wherein the p-region comprises at least two p-regions.
• Example 18 The apparatus of Example 1 , further comprising a field plate, wherein the field plate is at least one of the following: adjacent the gate and on the gate.
• Example 19 The apparatus of Example 18, wherein the field plate is electrically coupled to said p-region.
• Example 20 The apparatus of Example 18, wherein the field plate is electrically coupled to the source.
• Example 21 The apparatus of Example 18, wherein the field plate is electrically coupled to the source and said p-region.
• Example 22 The apparatus of Example 21 , wherein the p-region is on the substrate below said group Ill-Nitride barrier layer.
• Example 23 The apparatus of Example 22, wherein the p-region is implanted.
• Example 24 The apparatus of Example 22, wherein the p-region comprises at least two p-regions.
• Example 25 The apparatus of Example 21 , wherein the p-region is in the substrate below said group Ill-Nitride barrier layer.
• Example 26 The apparatus of Example 25, wherein the p-region is implanted.
• Example 27 The apparatus of Example 25, wherein the p-region comprises at least two p-regions.
• Example 28 The apparatus of Example 21 , further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer.
• Example 29 The apparatus of Example 28, wherein the p-region is implanted in the epitaxial layer.
• Example 30 The apparatus of Example 28, wherein the p-region comprises at least two p-regions in the epitaxial layer.
• Example 31 The apparatus of Example 28, wherein the epitaxial layer is below the group Ill-Nitride barrier layer.
• Example 32 The apparatus of Example 21 , further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer, wherein the p-region is also in the substrate below said group Ill-Nitride barrier layer.
• Example 33 The apparatus of Example 32, wherein at least one of the p-regions in implanted.
• Example 34 The apparatus of Example 32, wherein the p-region comprises at least two p-regions.
• Example 35 The apparatus of Example 21 , wherein the p-region is on the substrate below said group Ill-Nitride barrier layer, wherein the p-region is also in the substrate below said group Ill-Nitride barrier layer.
• Example 36 The apparatus of Example 35, wherein at least one of the p-regions is implanted.
• Example 37 The apparatus of Example 35, wherein the p-region comprises at least two p-regions.
• Example 38 The apparatus of Example 1 , further comprising a field plate, wherein the field plate is at least one of the following: adjacent the gate and on the gate.
• Example 39 The apparatus of Example 1 , wherein the gate comprises a T-shaped cross-section.
• Example 40 The apparatus of Example 39, wherein the gate is electrically coupled to the p-region.
• Example 41 The apparatus of Example 39, wherein the p-region is on the substrate below said group Ill-Nitride barrier layer.
• Example 42 The apparatus of Example 41 , wherein the p-region is implanted.
• Example 43 The apparatus of Example 41 , wherein the p-region comprises at least two p-regions.
• Example 44 The apparatus of Example 39, wherein the p-region is in the substrate below said group Ill-Nitride barrier layer.
• Example 45 The apparatus of Example 44, wherein the p-region is implanted.
• Example 46 The apparatus of Example 44, wherein the p-region comprises at least two p-regions.
• Example 47 The apparatus of Example 39, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer.
• Example 48 The apparatus of Example 47, wherein the p-region is implanted in the epitaxial layer.
• Example 49 The apparatus of Example 47, wherein the p-region comprises at least two p-regions in the epitaxial layer.
• Example 50 The apparatus of Example 47, wherein the epitaxial layer is below the group Ill-Nitride barrier layer.
• Example 51 The apparatus of Example 39, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer, wherein the p-region is also in the substrate below said group Ill-Nitride barrier layer.
• Example 52 The apparatus of Example 51 , wherein at least one of the p-regions in implanted.
• Example 53 The apparatus of Example 51 , wherein the p-region comprises at least two p-regions.
• Example 54 The apparatus of Example 39, wherein the p-region is on the substrate below said group Ill-Nitride barrier layer, wherein the p-region is also in the substrate below said group Ill-Nitride barrier layer.
• Example 55 The apparatus of Example 54, wherein at least one of the p-regions is implanted.
• Example 56 The apparatus of Example 54, wherein the p-region comprises at least two p-regions.
• Example 57 The apparatus of Example 39, further comprising a field plate, wherein the field plate is at least one of the following: adjacent the gate and on the gate.
• Example 58 The apparatus of Example 1 , wherein the source is electrically coupled to said p-region.
• Example 59 The apparatus of Example 58, further comprising a connection configured to couple the source to said p-region.
• Example 60 The apparatus of Example 59, wherein the p-region is on the substrate below said group Ill-Nitride barrier layer.
• Example 61 The apparatus of Example 60, wherein the p-region is implanted.
• Example 62 The apparatus of Example 60, wherein the p-region comprises at least two p-regions.
• Example 63 The apparatus of Example 59, wherein the p-region is in the substrate below said group Ill-Nitride barrier layer.
• Example 64 The apparatus of Example 63, wherein the p-region is implanted.
• Example 65 The apparatus of Example 63, wherein the p-region comprises at least two p-regions.
• Example 66 The apparatus of Example 59, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer.
• Example 67 The apparatus of Example 66, wherein the p-region is implanted in the epitaxial layer.
• Example 68 The apparatus of Example 66, wherein the p-region comprises at least two p-regions in the epitaxial layer.
• Example 69 The apparatus of Example 66, wherein the epitaxial layer is below the group Ill-Nitride barrier layer.
• Example 70 The apparatus of Example 59, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer, wherein the p-region is also in the substrate below said group Ill-Nitride barrier layer.
• Example 71 The apparatus of Example 70, wherein at least one of the p-regions in implanted.
• Example 72 The apparatus of Example 70, wherein the p-region comprises at least two p-regions.
• Example 73 The apparatus of Example 59, wherein the p-region is on the substrate below said group Ill-Nitride barrier layer, wherein the p-region is also in the substrate below said group Ill-Nitride barrier layer.
• Example 74 The apparatus of Example 73, wherein at least one of the p-regions is implanted.
• Example 75 The apparatus of Example 73, wherein the p-region comprises at least two p-regions.
• Example 76 The apparatus of Example 59, further comprising a field plate, wherein the field plate is at least one of the following: adjacent the gate and on the gate.
• Example 77 The apparatus of Example 1 , further comprising a contact pad electrically coupled to said p-region.
• Example 78 The apparatus of Example 77, further comprising a connection connecting the contact pad electrically to said p-region.
• Example 79 The apparatus of Example 77, wherein the contact pad is configured to receive at least one of the following: bias and signals.
• Example 80 The apparatus of Example 77, wherein the contact pad is configured to receive at least one of the following: bias to modulate characteristics of the apparatus and signals to modulate characteristics of the apparatus.
• Example 81 The apparatus of Example 80, wherein the p-region is on the substrate below said group Ill-Nitride barrier layer.
• Example 82 The apparatus of Example 81 , wherein the p-region is implanted.
• Example 83 The apparatus of Example 81 , wherein the p-region comprises at least two p-regions.
• Example 84 The apparatus of Example 80, wherein the p-region is in the substrate below said group Ill-Nitride barrier layer.
• Example 85 The apparatus of Example 84, wherein the p-region is implanted.
• Example 86 The apparatus of Example 84, wherein the p-region comprises at least two p-regions.
• Example 87 The apparatus of Example 80, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer.
• Example 88 The apparatus of Example 87, wherein the p-region is implanted in the epitaxial layer.
• Example 89 The apparatus of Example 87, wherein the p-region comprises at least two p-regions in the epitaxial layer.
• Example 90 The apparatus of Example 87, wherein the epitaxial layer is below the group Ill-Nitride barrier layer.
• Example 91 The apparatus of Example 80, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer, wherein the p-region is also in the substrate below said group Ill-Nitride barrier layer.
• Example 92 The apparatus of Example 91 , wherein at least one of the p-regions in implanted.
• Example 93 The apparatus of Example 91 , wherein the p-region comprises at least two p-regions.
• Example 94 The apparatus of Example 80, wherein the p-region is on the substrate below said group Ill-Nitride barrier layer, wherein the p-region is also in the substrate below said group Ill-Nitride barrier layer.
• Example 95 The apparatus of Example 94, wherein at least one of the p-regions is implanted.
• Example 96 The apparatus of Example 94, wherein the p-region comprises at least two p-regions.
• Example 97 The apparatus of Example 80, further comprising a field plate, wherein the field plate is at least one of the following: adjacent the gate and on the gate.
• Example 98 The apparatus of Example 1 , further comprising a nucleation layer on the substrate, wherein the group Ill-Nitride buffer layer is on the nucleation layer.
• Example 99 The apparatus of Example 98, further comprising intervening layers between the nucleation layer and the group Ill-Nitride buffer layer.
• Example 100 The apparatus of Example 1 , wherein a length of the p-region being less than an entire length of the substrate.
• Example 101 The apparatus of Example 1 , wherein the p-region is provided in the substrate; and wherein the p-region comprises aluminum implanted in the substrate.
• Example 102 The apparatus of Example 1 , wherein the p-region is provided in a layer arranged on the substrate; wherein the layer is an epitaxial layer; and wherein the layer is at least one of the following: GaN or SiC.
• Example 103 The apparatus of Example 1 , wherein a thickness of the group Ill-Nitride buffer layer defined as a distance between an upper surface of the substrate and a lower surface of the group Ill-Nitride barrier layer has a range of .7 microns to .3 microns.
• Example 104 The apparatus of Example 1 , wherein a thickness of one or more layers between an upper surface of the substrate and a lower surface of the group Ill-Nitride barrier layer has a range of .7 microns to .3 microns.
• Example 105 An apparatus, comprising: a substrate; a group Ill- Nitride buffer layer on the substrate; a group Ill-Nitride barrier layer on the group Ill- Nitride buffer layer, the group Ill-Nitride barrier layer comprising a higher bandgap than a bandgap of the group Ill-Nitride buffer layer; a source electrically coupled to the group Ill-Nitride barrier layer; a gate electrically coupled to the group Ill-Nitride barrier layer; a drain electrically coupled to the group Ill-Nitride barrier layer; a p- region being at least one of the following: in the substrate or on the substrate below said group Ill-Nitride barrier layer; and a contact pad electrically coupled to said p- region.
• Example 106 The apparatus of Example 105, further comprising a connection connecting the contact pad electrically to said p-region.
• Example 107 The apparatus of Example 105, wherein the contact pad is configured to receive at least one of the following: bias and signals.
• Example 108 The apparatus of Example 105, wherein the contact pad is configured to receive at least one of the following: bias to modulate characteristics of the apparatus and signals to modulate characteristics of the apparatus.
• Example 109 The apparatus of Example 105, wherein the p-region is on the substrate below said group Ill-Nitride barrier layer.
• Example 1 10. The apparatus of Example 109, wherein the p-region is implanted.
• Example 1 1 1. The apparatus of Example 105, wherein the p-region comprises at least two p-regions.
• Example 1 12. The apparatus of Example 105, wherein the p-region is in the substrate below said group Ill-Nitride barrier layer.
• Example 1 13 An apparatus, comprising: a substrate; a group Ill- Nitride buffer layer on the substrate; a group Ill-Nitride barrier layer on the group Ill- Nitride buffer layer, the group Ill-Nitride barrier layer comprising a higher bandgap than a bandgap of the group Ill-Nitride buffer layer; a source electrically coupled to the group Ill-Nitride barrier layer; a gate electrically coupled to the group Ill-Nitride barrier layer; a drain electrically coupled to the group Ill-Nitride barrier layer; and a p- region being at least one of the following: in the substrate or on the substrate below said group Ill-Nitride barrier layer, wherein the gate is electrically coupled to the p- region.
• Example 1 14 The apparatus of Example 1 13, further comprising a connection connecting the gate electrically to said p-region.
• Example 1 15 The apparatus of Example 1 13, wherein the p-region is on the substrate below said group Ill-Nitride barrier layer.
• Example 1 16 The apparatus of Example 1 15, wherein the p-region is implanted.
• Example 1 17 The apparatus of Example 1 13, wherein the p-region comprises at least two p-regions.
• Example 1 18. The apparatus of Example 1 13, wherein the p-region is in the substrate below said group Ill-Nitride barrier layer.
• Example 1 19 The apparatus of Example 1 18, wherein the p-region is implanted.
• Example 120 The apparatus of Example 1 18, wherein the p-region comprises at least two p-regions.
• Example 121 The apparatus of Example 1 13, further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer.
• Example 122 A method of making a device comprising: providing a substrate; providing a group Ill-Nitride buffer layer on the substrate; providing a group Ill-Nitride barrier layer on the group Ill-Nitride buffer layer, the group Ill-Nitride barrier layer comprising a higher bandgap than a bandgap of the group Ill-Nitride buffer layer; electrically coupling a source to the group Ill-Nitride barrier layer;
• Example 123 The method of making a device of Example 122, further comprising implanting the p-region.
• Example 124 The method of making a device of Example 122, wherein the p-region is in the substrate below said group Ill-Nitride barrier layer.
• Example 125 The method of making a device of Example 122, further comprising providing an epitaxial layer on the substrate and the p-region is in the epitaxial layer.
• Example 126 The method of making a device of Example 122, further comprising providing an epitaxial layer on the substrate and the p-region is in the epitaxial layer, wherein the p-region is also in the substrate below said group Ill- Nitride barrier layer.
• Example 127 The method of making a device of Example 122, further comprising providing a field plate, wherein the field plate is electrically coupled to said p-region.
• Example 128 The method of making a device of Example 127, further comprising providing a field plate, wherein the field plate is electrically coupled to the source.
• Example 129 The method of making a device of Example 128, wherein the field plate is electrically coupled to the source and said p-region.

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