WO2020158085A1 - 実装構造体 - Google Patents

実装構造体 Download PDF

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Publication number
WO2020158085A1
WO2020158085A1 PCT/JP2019/043307 JP2019043307W WO2020158085A1 WO 2020158085 A1 WO2020158085 A1 WO 2020158085A1 JP 2019043307 W JP2019043307 W JP 2019043307W WO 2020158085 A1 WO2020158085 A1 WO 2020158085A1
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WO
WIPO (PCT)
Prior art keywords
package
motherboard
mounting structure
vrm
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2019/043307
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English (en)
French (fr)
Inventor
誠司 服部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2020569378A priority Critical patent/JP7062097B2/ja
Priority to CN201980069489.9A priority patent/CN112913007B/zh
Priority to KR1020217009663A priority patent/KR102430745B1/ko
Publication of WO2020158085A1 publication Critical patent/WO2020158085A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0262—Arrangements for regulating voltages or for using plural voltages
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/119—Details of rigid insulating substrates therefor, e.g. three-dimensional details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/60—Securing means for detachable heating or cooling arrangements, e.g. clamps
    • H10W40/641—Snap-on arrangements, e.g. clips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09072—Hole or recess under component or special relationship between hole and component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10189—Non-printed connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10325—Sockets, i.e. female type connectors comprising metallic connector elements integrated in, or bonded to a common dielectric support
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10393—Clamping a component by an element or a set of elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/105—Mechanically attached to another device
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/1053—Mounted components directly electrically connected to each other, i.e. not via the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10545—Related components mounted on both sides of the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10568—Integral adaptations of a component or an auxiliary PCB for mounting, e.g. integral spacer element
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10598—Means for fastening a component, a casing or a heat sink whereby a pressure is exerted on the component towards the PCB
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to a mounting structure.
  • a semiconductor element such as an arithmetic element (CPU, GPU, etc.) has a lower operating voltage and an increased power consumption. Is in progress. For example, in order to stably operate such a low voltage and high power arithmetic element, through a board and a package. It is necessary to supply a low voltage with a small voltage fluctuation to the arithmetic element with a large current.
  • a mounting structure of the present disclosure includes a package having an electronic component mounted on an upper surface, a voltage regulator module mounted on a lower surface of the package at a position facing the electronic component, a motherboard having the package mounted on an upper surface, and a motherboard.
  • the lower surface of the device includes a driver mounted at a position facing the package, and a plurality of connectors for electrically connecting the conductor layer of the motherboard and the conductor layer of the package.
  • the motherboard has a through hole for accommodating the voltage regulator module and a through hole for passing a part of the connectors from the upper surface to the lower surface of the motherboard. One end of the connector passing through the through hole is connected near the driver, and the other end is connected near the voltage regulator module.
  • a heat sink is connected to the voltage regulator module through a through hole for housing the voltage regulator module.
  • a voltage regulator module may be used to supply a low voltage with small voltage fluctuations to a large current to electronic components such as a computing element.
  • VRM voltage regulator module
  • the current path between the driver and VRM should also be short.
  • the VRM since the VRM supplies a large amount of electric power to the electronic components, the VRM tends to generate heat and become hot during operation. Therefore, it is necessary to efficiently dissipate the generated heat to the outside of the mounting structure so that the electronic components and the driver are not adversely affected by the heat.
  • the electronic components mounted on the package and the VRM, and the VRM and the driver are connected by a relatively short current path.
  • the mounting structure of the present disclosure can stably operate the electronic component.
  • a heat sink is connected to the VRM. As a result, the heat generated during the operation of the VRM can be efficiently dissipated to the outside of the mounting structure, and the electronic components and the driver are less likely to be adversely affected by the heat.
  • a package 11 is mounted on a motherboard 14.
  • the package 11 includes a core layer and insulating layers laminated on both surfaces of the core layer.
  • the core layer is not particularly limited as long as it is made of an insulating material.
  • the insulating material include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. You may use these resins in mixture of 2 or more types.
  • the core layer may contain an insulating cloth material such as glass fiber, glass non-woven fabric, aramid non-woven fabric, aramid fiber, polyester fiber as a reinforcing material, silica, barium sulfate, talc, clay, glass, carbonic acid.
  • An inorganic insulating filler such as calcium or titanium oxide may be dispersed.
  • the -Through hole conductors are formed in the core layer to electrically connect the upper and lower surfaces of the core layer.
  • the through-hole conductor is formed in a through-hole penetrating the upper and lower surfaces of the core layer.
  • the through-hole conductor is formed of, for example, a conductor made of metal plating such as copper plating.
  • the insulating layer is not particularly limited as long as it is made of an insulating material.
  • Each insulating layer may be formed of the same resin or different resins.
  • the insulating layer and the core layer may be formed of the same resin or different resins.
  • the insulating layer is usually formed with a via hole filled with a via hole conductor for electrically connecting the layers.
  • the via hole is formed by laser processing such as CO 2 laser and UV-YAG laser.
  • Conductor layer is formed on the surface of the insulating layer.
  • the conductor layer includes wiring conductors for power supply, ground, signal, etc., pads, and the like.
  • Such a conductor layer is formed by depositing an electroless copper plating layer and an electrolytic copper plating layer on the surface of the insulating layer by, for example, a semi-additive method.
  • a conductor layer may be formed on the surface of the insulating layer by performing exposure, development, and etching using an insulating plate having a conductor (for example, copper foil) formed on the surface.
  • Electronic components 12 are mounted on the upper surface of the package 11.
  • the electronic component 12 include an arithmetic element (CPU, GPU, etc.), a semiconductor element, a capacitor, and the like.
  • an electronic component 12 having a low operating voltage and a large power consumption may be mounted in the mounting structure 1 according to an embodiment.
  • the operating voltage of such an electronic component 12 may be about 0.65 to 0.8 V, and the power consumption may be about 500 to 1000 W.
  • an arithmetic element having an operating voltage of about 0.65 to 0.8 V and a power consumption of about 500 to 1000 W may be used as the electronic component 12.
  • a voltage regulator module (VRM) 13 is mounted on the lower surface of the package 11, that is, the surface opposite to the mounting surface of the electronic component 12, at a position facing the electronic component 12.
  • the “opposing position” may be a position where the electronic component 12 and the VRM 13 face each other and at least partially overlap each other, and may not be a position where the electronic component 12 and the VRM 13 face each other and completely overlap each other.
  • the VRM 13 is used to reduce a high voltage (for example, about 24 to 48 V) supplied from the mother board 14 to an operating voltage of the electronic component 12, and supply the voltage to the electronic component 12 with a small voltage fluctuation.
  • the package 11 on which the electronic component 12 and the VRM 13 are mounted is fixed to the upper surface of the motherboard 14 with an adhesive 15.
  • a driver 16 is mounted on the lower surface of the mother board 14, that is, the surface opposite to the mounting surface of the package 11.
  • the driver 16 is used to monitor the temperature and current of the VRM 13 and appropriately supply current to the electronic component 12.
  • the driver 16 and the VRM 13 are preferably connected by a relatively short current path. Therefore, the driver 16 is mounted at a position facing the package 11.
  • the “opposing position” may be a position where the package 11 and the driver 16 face each other and at least partially overlap each other, and need not be a position where the package 11 and the driver 16 face each other and completely overlap each other.
  • the conductor layer formed on the package 11 and the conductor layer formed on the motherboard 14 are electrically connected by the connector 17.
  • Some of the connectors 17 electrically connect the conductor layer of the package 11 mounted on the upper surface of the mother board 14 and the conductor layer formed on the lower surface of the mother board 14. Therefore, the motherboard 14 is formed with through holes for passing some of the connectors 17 from the upper surface to the lower surface of the motherboard.
  • the connector 17 passing through this through hole has one end connected near the driver 16 and the other end connected near the VRM 13.
  • the driver 16 and the VRM 13 are connected via the through hole in this manner, the driver 16 and the VRM 13 are connected via a relatively short current path. Further, by passing through the through hole, it is possible to reduce the influence of heat generated when the VRM 13 operates.
  • the VRM 13 mounted on the lower surface of the package 11 is housed in a through hole for housing the VRM 13 formed on the motherboard 14.
  • the VRM 13 does not need to be completely housed in the through hole, and as shown in FIG. 1, at least a part of the VRM 13 may be in the through hole.
  • a certain space can be provided between the package 11 and the mother board 14 while ensuring the connectivity between the lower side of the VRM 13 and the heat sink 18, which will be described later, and it becomes easy to secure the arrangement area of the connector 17. ..
  • the heat sink 18 is included in the mounting structure 1 according to the embodiment in order to dissipate heat generated during the operation of the VRM 13 to the outside.
  • the heat sink 18 is connected to the VRM 13 via a through hole for accommodating the VRM 13 formed on the motherboard 14. Specifically, as shown in FIG. 1, a part of the heat sink 18 is housed in a through hole formed in the motherboard 14, and the VRM 13 and the heat sink 18 are connected in the through hole. In this way, since the motherboard 14 has the through hole for accommodating the VRM 13, it is easy to connect the VRM 13 and the heat sink 18, and the heat generated during the operation of the VRM 13 can be efficiently dissipated to the outside.
  • the mounting structure of the present disclosure is not limited to the one embodiment described above.
  • the adhesive 15 is used to mount the package 11 on the upper surface of the motherboard 14.
  • the method of mounting the package on the upper surface of the motherboard is not limited.
  • the package 21 on which the electronic component 22 and the VRM 23 are mounted is fixed to the upper surface of the motherboard 24 using the IC socket 25.
  • the package 21 on which the electronic component 22 and the VRM 23 are mounted is housed in the IC socket 25.
  • the IC socket 25 accommodating the package 21 and the motherboard 24 may be electrically connected.
  • the members other than the IC socket 25 included in the mounting structure 2, that is, the package 21, the electronic component 22, the VRM 23, the mother board 24, the driver 26, the connector 27, and the heat sink 28 are as described above, and detailed description thereof is omitted. To do.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本開示の実装構造体は、上面に電子部品が搭載されたパッケージと、電圧レギュレーターモジュールと、上面にパッケージが搭載されるマザーボードと、ドライバーと、マザーボードの導体層とパッケージの導体層とを電気的に接続するための複数のコネクターと、ヒートシンクとを含む。

Description

実装構造体
　本開示は、実装構造体に関する。
　特許文献１に記載のように、半導体素子がパッケージ基板に実装された実装構造体において、演算素子（ＣＰＵ、ＧＰＵなど）などのような半導体素子は、作動電圧の低電圧化や消費電力の増加が進行している。例えば、このような低電圧で大電力の演算素子を安定して作動させるためには、ボードおよびパッケージを介して。電圧変動の小さな低電圧を大電流で演算素子に供給する必要がある。
特許第４６４４７１７号公報
　本開示の実装構造体は、上面に電子部品が搭載されたパッケージと、パッケージの下面に、電子部品と対向する位置に搭載された電圧レギュレーターモジュールと、上面にパッケージが搭載されるマザーボードと、マザーボードの下面に、パッケージと対向する位置に搭載されたドライバーと、マザーボードの導体層とパッケージの導体層とを電気的に接続するための複数のコネクターとを含む。マザーボードは、電圧レギュレーターモジュールを収容するための貫通孔と、一部のコネクターをマザーボードの上面から下面まで通すための貫通孔とを有する。貫通孔を通るコネクターの一方の端部がドライバー近傍で接続され、他方の端部が電圧レギュレーターモジュール近傍で接続されている。電圧レギュレーターモジュールには、電圧レギュレーターモジュールを収容するための貫通孔を介してヒートシンクが接続されている。
本開示の一実施形態に係る実装構造体を示す概略断面図である。 本開示の他の実施形態に係る実装構造体を示す概略断面図である。
　電圧変動の小さな低電圧を大電流で演算素子などの電子部品に供給するために、電圧レギュレーターモジュール（ＶＲＭ）が使用されることがある。ＶＲＭを使用する場合、電圧の低下や電力の損失を抑制するためには、電子部品とＶＲＭとの間の電流経路を短くする方がよい。同様に、ドライバーとＶＲＭとの間の電流経路も短い方がよい。しかし、ＶＲＭは電子部品に大きな電力を供給するため、作動時に発熱して高温になりやすい。したがって、発生した熱を効率よく実装構造体の外部に放散し、電子部品やドライバーなどに熱による悪影響を及ぼさないようにする必要がある。
　本開示の実装構造体では、パッケージに搭載された電子部品とＶＲＭとの間、およびＶＲＭとドライバーとの間が比較的短い電流経路で接続されている。その結果、本開示の実装構造体は、電子部品を安定して作動させることができる。さらに、本開示の実装構造体では、ＶＲＭにヒートシンクが接続されている。その結果、ＶＲＭの作動時に発生する熱を効率よく実装構造体の外部に放散することができ、電子部品やドライバーなどが熱による悪影響を受けにくくなる。
　図１に示すように、本開示の一実施形態に係る実装構造体１は、パッケージ１１がマザーボード１４に搭載されている。パッケージ１１は、コア層と、コア層の両面に積層された絶縁層を含む。コア層は、絶縁性を有する素材で形成されていれば特に限定されない。絶縁性を有する素材としては、例えば、エポキシ樹脂、ビスマレイミド－トリアジン樹脂、ポリイミド樹脂、ポリフェニレンエーテル樹脂などの樹脂が挙げられる。これらの樹脂は２種以上を混合して用いてもよい。さらに、コア層には、ガラス繊維、ガラス不織布、アラミド不織布、アラミド繊維、ポリエステル繊維などの絶縁性布材が補強材として含まれていてもよく、シリカ、硫酸バリウム、タルク、クレー、ガラス、炭酸カルシウム、酸化チタンなどの無機絶縁性フィラーが、分散されていてもよい。
　コア層には、コア層の上下面を電気的に接続するために、スルーホール導体が形成されている。スルーホール導体は、コア層の上下面を貫通しているスルーホールに形成されている。スルーホール導体は、例えば、銅めっきなどの金属めっきからなる導体で形成されている。
　コア層の両面には、絶縁層が積層されている。図１に示すパッケージ１１では、絶縁層は、コア層の両面それぞれに２層積層されている。絶縁層は、コア層と同様、絶縁性を有する素材で形成されていれば特に限定されない。各絶縁層は、同じ樹脂で形成されていてもよく、異なる樹脂で形成されていてもよい。絶縁層とコア層とは、同じ樹脂で形成されていてもよく、異なる樹脂で形成されていてもよい。
　絶縁層には、通常、層間を電気的に接続するためのビアホール導体が充填されるビアホールが形成されている。ビアホールは、例えばＣＯ２レーザー、ＵＶ－ＹＡＧレーザーなどのようなレーザー加工によって形成される。
　絶縁層の表面には導体層が形成されている。導体層には、電源用、グランド用、信号用などの配線導体や、パッドなどが含まれる。このような導体層は、例えば、例えばセミアディティブ法により、無電解銅めっき層、および電解銅めっき層を絶縁層の表面に析出させることで形成される。あるいは、表面に導体（例えば、銅箔など）が形成された絶縁板を用いて、露光、現像およびエッチングを行い、絶縁層の表面に導体層を形成してもよい。
　パッケージ１１の上面には電子部品１２が搭載されている。電子部品１２としては、例えば、演算素子（ＣＰＵ、ＧＰＵなど）、半導体素子、コンデンサなどが挙げられる。一実施形態に係る実装構造体１では、例えば、作動電圧が低電圧で消費電力が大きな電子部品１２が搭載されていてもよい。このような電子部品１２の作動電圧は、０．６５～０．８Ｖ程度であってもよく、消費電力は５００～１０００Ｗ程度であってもよい。特に電子部品１２として、作動電圧が０．６５～０．８Ｖ程度であり、消費電力が５００～１０００Ｗ程度の演算素子を使用してもよい。
　パッケージ１１の下面、すなわち電子部品１２の搭載面と反対側の面には、電子部品１２と対向する位置に電圧レギュレーターモジュール（ＶＲＭ）１３が搭載されている。ここで「対向する位置」とは、電子部品１２とＶＲＭ１３とが対向して少なくとも一部で重なる位置であればよく、電子部品１２およびＶＲＭ１３が対向して完全に重なる位置でなくてもよい。ＶＲＭ１３は、マザーボード１４から供給される高電圧（例えば、２４～４８Ｖ程度）を、電子部品１２の作動電圧に下げ、電圧変動の少ない状態で電子部品１２に電圧を供給するために使用される。
　電子部品１２とＶＲＭ１３とが搭載されたパッケージ１１は、マザーボード１４の上面に接着剤１５で固定されている。マザーボード１４の下面、すなわちパッケージ１１の搭載面と反対側の面には、ドライバー１６が搭載されている。ドライバー１６は、ＶＲＭ１３の温度や電流などを監視し、電子部品１２に電流を適切に供給するために使用される。ドライバー１６とＶＲＭ１３とは比較的短い電流経路で接続されるのがよい。そのため、ドライバー１６は、パッケージ１１と対向する位置に搭載される。ここで「対向する位置」とは、パッケージ１１とドライバー１６とが対向して少なくとも一部で重なる位置であればよく、パッケージ１１およびドライバー１６が対向して完全に重なる位置でなくてもよい。
　パッケージ１１に形成された導体層とマザーボード１４に形成された導体層とは、コネクター１７によって電気的に接続されている。一部のコネクター１７は、マザーボード１４の上面に搭載されたパッケージ１１の導体層とマザーボード１４の下面に形成された導体層とを電気的に接続している。そのため、マザーボード１４には、一部のコネクター１７をマザーボードの上面から下面まで通すための貫通孔が形成されている。この貫通孔を通るコネクター１７は、一方の端部がドライバー１６近傍で接続され、他方の端部がＶＲＭ１３近傍で接続されている。このように貫通孔を介して接続されていると、ドライバー１６とＶＲＭ１３とは比較的短い電流経路で接続される。さらに、貫通孔を通ることによって、ＶＲＭ１３の作動時に発生する熱の影響を低減することができる。
　パッケージ１１の下面に搭載されたＶＲＭ１３は、マザーボード１４に形成されたＶＲＭ１３を収容するための貫通孔に収容されている。ＶＲＭ１３は貫通孔に完全に収容されている必要はなく、図１に示すように、少なくともＶＲＭ１３の一部が貫通孔に入っていればよい。これにより、ＶＲＭ１３の下側と後述するヒートシンク１８との接続性を確保しつつ、パッケージ１１とマザーボード１４との間に一定の間隔を設けることができ、コネクター１７の配置領域の確保が容易になる。
　ＶＲＭ１３の作動時に発生する熱を外部に放散させるため、一実施形態に係る実装構造体１には、ヒートシンク１８が含まれる。ヒートシンク１８は、マザーボード１４に形成されたＶＲＭ１３を収容するための貫通孔を介してＶＲＭ１３と接続されている。具体的には、図１に示すように、ヒートシンク１８の一部がマザーボード１４に形成された貫通孔に収容され、この貫通孔の中でＶＲＭ１３とヒートシンク１８とが接続されている。このように、マザーボード１４がＶＲＭ１３を収容するための貫通孔を有することによって、ＶＲＭ１３とヒートシンク１８とを接続しやすく、ＶＲＭ１３の作動時に発生する熱を効率よく外部に放散させることができる。
　本開示の実装構造体は、上述の一実施形態に限定されない。例えば、上述の配線基板１では、パッケージ１１をマザーボード１４の上面に搭載するために、接着剤１５が使用されている。しかし、パッケージをマザーボードの上面に搭載する方法は限定されない。
　例えば、図２に示す他の実施形態に係る実装構造体２では、電子部品２２とＶＲＭ２３とが搭載されたパッケージ２１は、マザーボード２４の上面にＩＣソケット２５を使用して固定されている。具体的には、まず、電子部品２２とＶＲＭ２３とが搭載されたパッケージ２１をＩＣソケット２５に収容する。パッケージ２１が収容されたＩＣソケット２５とマザーボード２４とを電気的に接続すればよい。実装構造体２に含まれるＩＣソケット２５以外の部材、すなわちパッケージ２１、電子部品２２、ＶＲＭ２３、マザーボード２４、ドライバー２６、コネクター２７、およびヒートシンク２８については上述の通りであり、詳細な説明については省略する。
　１、２　実装構造体
　１１、２１　パッケージ
　１２、２２　電子部品
　１３、２３　電圧レギュレーターモジュール（ＶＲＭ）
　１４、２４　マザーボード
　１５　　接着剤
　２５　　ＩＣソケット
　１６、２６　ドライバー
　１７、２７　コネクター
　１８、２８　ヒートシンク

Claims (5)

  1. 　上面に電子部品が搭載されたパッケージと、
    　パッケージの下面に、電子部品と対向する位置に搭載された電圧レギュレーターモジュールと、
    　上面にパッケージが搭載されるマザーボードと、
    　マザーボードの下面に、パッケージと対向する位置に搭載されたドライバーと、
    　マザーボードの導体層とパッケージの導体層とを電気的に接続するための複数のコネクターと、
    を含み、
    　マザーボードは、電圧レギュレーターモジュールを収容するための貫通孔と、一部のコネクターをマザーボードの上面から下面まで通すための貫通孔とを有し、
    　貫通孔を通るコネクターの一方の端部がドライバー近傍で接続され、他方の端部が電圧レギュレーターモジュール近傍で接続されており、
    　電圧レギュレーターモジュールには、電圧レギュレーターモジュールを収容するための貫通孔を介してヒートシンクが接続されている、
    ことを特徴とする実装構造体。
  2. 　前記電圧レギュレーターモジュールを収容するための貫通孔に、前記電圧レギュレーターモジュールの一部のみが位置している請求項１に記載の実装構造体。
  3. 　前記パッケージが、ＩＣソケットを用いて前記マザーボードに固定されている請求項１または２に記載の実装構造体。
  4. 　前記電子部品が演算素子である請求項１～３のいずれかに記載の実装構造体。
  5. 　前記演算素子の作動電圧が０．６５～０．８Ｖであり、消費電力が５００～１０００Ｗである請求項４に記載の実装構造体。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022099258A (ja) * 2020-12-22 2022-07-04 インテル コーポレイション 電子装置とともに使用するための信号伝達ルーティングを有する熱管理システム

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11596052B2 (en) * 2020-06-08 2023-02-28 Intel Corporation Integrated voltage regulator for high performance devices
US12183999B2 (en) * 2021-12-17 2024-12-31 International Business Machines Corporation Separable interface cable structure for high voltage under-module power input
US12002795B2 (en) * 2022-04-13 2024-06-04 Google Llc Pluggable CPU modules with vertical power
US12308543B2 (en) 2022-04-18 2025-05-20 Google Llc Structure for optimal XPU socket compression
CN116845038B (zh) * 2023-08-29 2023-12-22 之江实验室 一种针对晶圆级处理器的散热装置及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0382060A (ja) * 1989-08-24 1991-04-08 Nec Corp 半導体装置
JPH09102565A (ja) * 1995-10-05 1997-04-15 Ibiden Co Ltd 半導体パッケージ
JP2007521574A (ja) * 2003-11-04 2007-08-02 インテル コーポレイション 取り外し可能なオンパッケージ電圧制御モジュール

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7791889B2 (en) * 2005-02-16 2010-09-07 Hewlett-Packard Development Company, L.P. Redundant power beneath circuit board
US7778041B2 (en) * 2006-06-28 2010-08-17 Hon Hai Precision Ind. Co., Ltd. Interconnection system between CPU and voltage regulator
US20080116589A1 (en) * 2006-11-17 2008-05-22 Zong-Fu Li Ball grid array package assembly with integrated voltage regulator
US8455766B2 (en) * 2007-08-08 2013-06-04 Ibiden Co., Ltd. Substrate with low-elasticity layer and low-thermal-expansion layer
JP4644717B2 (ja) 2008-01-11 2011-03-02 富士通株式会社 基板ユニット
US8922243B2 (en) * 2012-12-23 2014-12-30 Advanced Micro Devices, Inc. Die-stacked memory device with reconfigurable logic
US20140187058A1 (en) * 2012-12-27 2014-07-03 Hongfei Yan Modular Multiple Piece Socket For Enhanced Thermal Management
US9331058B2 (en) * 2013-12-05 2016-05-03 Apple Inc. Package with SoC and integrated memory
JP2016066699A (ja) * 2014-09-25 2016-04-28 京セラサーキットソリューションズ株式会社 複合配線基板およびその実装構造体
US10163751B2 (en) * 2016-11-29 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Heat transfer structures and methods for IC packages

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0382060A (ja) * 1989-08-24 1991-04-08 Nec Corp 半導体装置
JPH09102565A (ja) * 1995-10-05 1997-04-15 Ibiden Co Ltd 半導体パッケージ
JP2007521574A (ja) * 2003-11-04 2007-08-02 インテル コーポレイション 取り外し可能なオンパッケージ電圧制御モジュール

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022099258A (ja) * 2020-12-22 2022-07-04 インテル コーポレイション 電子装置とともに使用するための信号伝達ルーティングを有する熱管理システム

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