JP2007521574A - 取り外し可能なオンパッケージ電圧制御モジュール - Google Patents
取り外し可能なオンパッケージ電圧制御モジュール Download PDFInfo
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
- H05K1/0262—Arrangements for regulating voltages or for using plural voltages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10325—Sockets, i.e. female type connectors comprising metallic connector elements integrated in, or bonded to a common dielectric support
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/1053—Mounted components directly electrically connected to each other, i.e. not via the PCB
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
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- Combinations Of Printed Boards (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
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- Continuous-Control Power Sources That Use Transistors (AREA)
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Abstract
Description
Claims (30)
- 集積回路(IC)パッケージであって:
ICダイ;
該ICダイが動作可能なように結合された基板であり、当該基板と前記ICダイとの間に結合された第1の接続セット、及びコネクタ又はプリント回路基板の何れかと結合するための第2の接続セット、を有する基板;
安定化された電圧を前記ICダイに供給する電圧調整モジュール(VRM);及び
前記VRMと前記基板との間に結合され、前記VRMを前記基板上の前記第1及び第2の接続セットの少なくとも一部分に電気的に結合させる複数の電気経路を提供する相互接続部材;
を有するICパッケージ。 - 請求項1に記載のICパッケージであって、前記相互接続部材が前記ICダイが熱的に結合された一体化ヒートスプレッダを有する、ところのICパッケージ。
- 請求項2に記載のICパッケージであって、前記一体化ヒートスプレッダに熱的に結合されたヒートシンクをさらに有するICパッケージ。
- 請求項1に記載のICパッケージであって、前記基板が、前記第2接続セットに結合された複数のピンを介して、動作可能なように結合されたソケットをさらに有する、ところのICパッケージ。
- 請求項1に記載のICパッケージであって、前記ICダイが、前記第1接続セットとしても機能する複数の半田バンプを介して、前記基板にフリップ接合されている、ところのICパッケージ。
- 請求項1に記載のICパッケージであって、前記相互接続部材が前記基板に複数の半田接合部を介して結合されている、ところのICパッケージ。
- 請求項1に記載のICパッケージであって、前記相互接続部材が、前記VRM及び前記基板上の前記第1及び第2の接続セットの中の少なくとも1つのコネクタに電気的に結合された接地面又は電源面の何れかとして機能する導電性ボディを有する、ところのICパッケージ。
- 請求項6に記載のICパッケージであって、前記相互接続部材が、前記電気経路の一部が形成された少なくとも1つの相互接続レイヤーを有し、該少なくとも1つの相互接続レイヤーが絶縁レイヤーによって前記導電性ボディから分離されている、ところのICパッケージ。
- 請求項1に記載のICパッケージであって、前記電気経路が、前記ICダイ及び前記VRMに、制御入力/出力接続間の相互接続を提供するための経路を有する、ところのICパッケージ。
- 請求項1に記載のICパッケージであって、前記ICダイがプロセッサダイを有する、ところのICパッケージ。
- 請求項1に記載のICパッケージであって、前記VRMが前記相互接続部材に少なくとも1つの固定具を介して結合されている、ところのICパッケージ。
- 請求項1に記載のICパッケージであって、前記VRMが前記相互接続部材にエッジコネクタを介して電気的に結合されている、ところのICパッケージ。
- 請求項1に記載のICパッケージであって、前記VRMが前記相互接続部材にパラレル結合部材を介して結合されている、ところのICパッケージ。
- 請求項1に記載のICパッケージであって、前記相互接続部材に結合された第2のVRMをさらに有するICパッケージ。
- 請求項1に記載のICパッケージであって、前記VRMが複数の電圧調整部品が実装されたプリント基板を有し、かつ、前記VRMが前記相互接続部材に取り外し可能な方法で結合されている、ところのICパッケージ。
- 請求項15に記載のICパッケージであって、前記VRMが前記プリント基板に結合されたコネクタを有し、該コネクタを介して前記VRMが前記前記相互接続部材に電気的に結合されている、ところのICパッケージ。
- 請求項1に記載のICパッケージであって、前記VRMが前記相互接続部材に少なくとも1つのワイヤー接合で電気的に結合されている、ところのICパッケージ。
- 請求項1に記載のICパッケージであって、前記相互接続部材が前記基板に少なくとも1つのワイヤー接合で電気的に結合されている、ところのICパッケージ。
- 集積回路(IC)パッケージであって:
プロセッシング手段;
該プロセッシング手段が結合された基板;
安定化された電圧を前記プロセッシング手段に供給する電圧調整手段;
前記電圧調整手段を前記プロセッシング手段に電気的に結合する相互接続手段;及び
複数の電気接続を前記基板に提供する接続手段;
を有するICパッケージ。 - 請求項19に記載のICパッケージであって、前記相互接続手段が前記プロセッシング手段に熱的に結合された一体化ヒートスプレッダを有する、ところのICパッケージ。
- 請求項20に記載のICパッケージであって、前記一体化ヒートスプレッダに熱的に結合された熱放散手段をさらに有するICパッケージ。
- 請求項19に記載のICパッケージであって、前記相互接続手段が、前記VRM及び前記プロセッシング手段に電気的に結合された接地面又は電源面の何れかとして機能する導電性ボディを有する、ところのICパッケージ。
- 請求項19に記載のICパッケージであって、前記相互接続手段が、前記VRMと前記基板との間の相互接続を提供するために、複数の電気配線が形成された少なくとも1つの相互接続レイヤーを有する、ところのICパッケージ。
- 請求項19に記載のICパッケージであって、前記相互接続手段が、入力/出力信号を電気的に結合するための相互接続を前記VRMと前記プロセッシング手段との間に有する、ところのICパッケージ。
- 請求項19に記載のICパッケージであって、前記相互接続手段に結合された、安定化された電圧を前記プロセッシング手段に提供するための第2のVRMをさらに有するICパッケージ。
- マザーボード;
電力を前記マザーボードに供給する電源;
動作可能なように前記マザーボードに結合されたプロセッサパッケージであって、
プロセッサダイ;
該プロセッサダイが動作可能なように結合された基板であり、当該基板と前記プロセッサダイとの間に結合された第1の接続セット、及び前記マザーボードに結合された第2の接続セットを有する基板;
を有するプロセッサパッケージ;
前記電源により供給された電気入力に応じて安定化された電圧を前記プロセッサダイに供給する電圧調整モジュール(VRM);及び
前記VRMと前記基板との間に結合され、前記VRMを前記基板上の前記第1及び第2の接続セットの少なくとも一部分に電気的に結合させる複数の電気経路を提供する相互接続部材;
を有するシステム。 - 請求項26に記載のシステムであって、前記相互接続部材が、前記プロセッサダイが熱的に結合された一体化ヒートスプレッダを有し、該一体化ヒートスプレッダに熱的に結合されるヒートシンクをさらに有するシステム。
- 請求項26に記載のシステムであって、前記プロセッサダイが、前記第1接続セットとしても機能する複数の半田バンプを介して、前記基板にフリップ接合されている、ところのシステム。
- 請求項26に記載のシステムであって、前記電圧調整モジュールが複数の電圧調整部品が実装されたプリント基板を有する、ところのシステム。
- 請求項26に記載のシステムであって、前記プロセッサパッケージが前記マザーボードにソケットの付いたコネクタを介して結合されている、ところのシステム。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/701,765 US7091586B2 (en) | 2003-11-04 | 2003-11-04 | Detachable on package voltage regulation module |
PCT/US2004/035997 WO2005048323A2 (en) | 2003-11-04 | 2004-10-28 | Detachable on package voltage regulation module |
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Publication Number | Publication Date |
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JP2007521574A true JP2007521574A (ja) | 2007-08-02 |
JP4287474B2 JP4287474B2 (ja) | 2009-07-01 |
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Application Number | Title | Priority Date | Filing Date |
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JP2006538303A Expired - Fee Related JP4287474B2 (ja) | 2003-11-04 | 2004-10-28 | 取り外し可能なオンパッケージ電圧制御モジュール |
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Country | Link |
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US (1) | US7091586B2 (ja) |
JP (1) | JP4287474B2 (ja) |
KR (1) | KR100806424B1 (ja) |
CN (1) | CN100527396C (ja) |
DE (1) | DE112004002072T5 (ja) |
HK (1) | HK1099964A1 (ja) |
TW (1) | TWI260488B (ja) |
WO (1) | WO2005048323A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2020158085A1 (ja) * | 2019-01-30 | 2020-08-06 | 京セラ株式会社 | 実装構造体 |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8143108B2 (en) * | 2004-10-07 | 2012-03-27 | Stats Chippac, Ltd. | Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate |
US20020121707A1 (en) * | 2001-02-27 | 2002-09-05 | Chippac, Inc. | Super-thin high speed flip chip package |
US6921462B2 (en) | 2001-12-17 | 2005-07-26 | Intel Corporation | Method and apparatus for producing aligned carbon nanotube thermal interface structure |
US7091586B2 (en) | 2003-11-04 | 2006-08-15 | Intel Corporation | Detachable on package voltage regulation module |
US7180174B2 (en) * | 2003-12-30 | 2007-02-20 | Intel Corporation | Nanotube modified solder thermal intermediate structure, systems, and methods |
US7456052B2 (en) * | 2003-12-30 | 2008-11-25 | Intel Corporation | Thermal intermediate apparatus, systems, and methods |
US7345359B2 (en) * | 2004-03-05 | 2008-03-18 | Intel Corporation | Integrated circuit package with chip-side signal connections |
US7271034B2 (en) * | 2004-06-15 | 2007-09-18 | International Business Machines Corporation | Semiconductor device with a high thermal dissipation efficiency |
US7145782B2 (en) * | 2004-07-16 | 2006-12-05 | Intel Corporation | Reducing loadline impedance in a system |
US7235880B2 (en) * | 2004-09-01 | 2007-06-26 | Intel Corporation | IC package with power and signal lines on opposing sides |
US7278853B1 (en) * | 2006-06-20 | 2007-10-09 | International Business Machines Corporation | Power card connection structure |
US20080002365A1 (en) * | 2006-06-29 | 2008-01-03 | Ashish Gupta | Socket enabled cooling of in-substrate voltage regulator |
JP5259945B2 (ja) * | 2006-10-30 | 2013-08-07 | スリーエム イノベイティブ プロパティズ カンパニー | 熱放散機能を備えたicソケット |
US20080191794A1 (en) * | 2007-02-08 | 2008-08-14 | Mediatek Inc. | Method and apparatus for tuning an active filter |
US20080237845A1 (en) * | 2007-03-28 | 2008-10-02 | Jesse Jaejin Kim | Systems and methods for removing heat from flip-chip die |
US8212352B2 (en) * | 2007-03-28 | 2012-07-03 | Stats Chippac Ltd. | Integrated circuit package system with heat sink spacer structures |
US7808101B2 (en) * | 2008-02-08 | 2010-10-05 | Fairchild Semiconductor Corporation | 3D smart power module |
US8018738B2 (en) * | 2008-06-02 | 2011-09-13 | Oracle America, Inc., | Voltage regulator attach for high current chip applications |
US7705447B2 (en) * | 2008-09-29 | 2010-04-27 | Intel Corporation | Input/output package architectures, and methods of using same |
US8716855B2 (en) * | 2010-11-10 | 2014-05-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit system with distributed power supply comprising interposer and voltage regulator module |
US9538633B2 (en) * | 2012-12-13 | 2017-01-03 | Nvidia Corporation | Passive cooling system integrated into a printed circuit board for cooling electronic components |
CN103633073A (zh) * | 2013-12-04 | 2014-03-12 | 江苏长电科技股份有限公司 | 一种可拆卸、可组装的SiP封装结构 |
US9787188B2 (en) | 2014-06-26 | 2017-10-10 | Intel Corporation | High-frequency on-package voltage regulator |
US9911723B2 (en) * | 2015-12-18 | 2018-03-06 | Intel Corporation | Magnetic small footprint inductor array module for on-package voltage regulator |
CN105653765A (zh) * | 2015-12-23 | 2016-06-08 | 无锡江南计算技术研究所 | 多相vrm电源电路的四面布局方法 |
EP3854186A1 (en) * | 2018-09-19 | 2021-07-28 | Tesla, Inc. | Mechanical architecture for a multi-chip module |
US11004783B2 (en) * | 2019-05-29 | 2021-05-11 | Microsoft Technology Licensing, Llc | Integrated circuit chip design for symmetric power delivery |
US11264358B2 (en) * | 2019-09-11 | 2022-03-01 | Google Llc | ASIC package with photonics and vertical power delivery |
US11276668B2 (en) | 2020-02-12 | 2022-03-15 | Google Llc | Backside integrated voltage regulator for integrated circuits |
US11395408B2 (en) * | 2020-08-28 | 2022-07-19 | Apple Inc. | Wafer-level passive array packaging |
US11616019B2 (en) | 2020-12-21 | 2023-03-28 | Nvidia Corp. | Semiconductor assembly |
US20210112679A1 (en) * | 2020-12-22 | 2021-04-15 | Intel Corporation | System and method to help mitigate heat in an electronic device |
US20210112685A1 (en) * | 2020-12-22 | 2021-04-15 | Intel Corporation | Thermally conductive shock absorbers for electronic devices |
CN117597774A (zh) * | 2021-12-23 | 2024-02-23 | 英特尔公司 | 集成顶侧电力输送热技术 |
US20230363093A1 (en) * | 2022-05-05 | 2023-11-09 | Nvidia Corp. | Power regulator interfaces for integrated circuits |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5734555A (en) | 1994-03-30 | 1998-03-31 | Intel Corporation | Shared socket multi-chip module and/or piggyback pin grid array package |
US5982635A (en) | 1996-10-23 | 1999-11-09 | Concept Manufacturing, Incorporated | Signal adaptor board for a pin grid array |
WO2001065344A2 (en) | 2000-02-18 | 2001-09-07 | Incep Technologies, Inc. | Method and apparatus for providing power to a microprocessor with integrated thermal and emi management |
US6366467B1 (en) * | 2000-03-31 | 2002-04-02 | Intel Corporation | Dual-socket interposer and method of fabrication therefor |
US6791846B2 (en) * | 2000-10-30 | 2004-09-14 | Sun Microsystems, Inc. | Power distribution system with a dedicated power structure and a high performance voltage regulator |
US7091586B2 (en) | 2003-11-04 | 2006-08-15 | Intel Corporation | Detachable on package voltage regulation module |
-
2003
- 2003-11-04 US US10/701,765 patent/US7091586B2/en not_active Expired - Fee Related
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2004
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- 2004-10-28 WO PCT/US2004/035997 patent/WO2005048323A2/en active Application Filing
- 2004-10-28 DE DE112004002072T patent/DE112004002072T5/de not_active Withdrawn
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- 2004-10-29 TW TW093132993A patent/TWI260488B/zh not_active IP Right Cessation
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Cited By (7)
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WO2020158085A1 (ja) * | 2019-01-30 | 2020-08-06 | 京セラ株式会社 | 実装構造体 |
KR20210052524A (ko) * | 2019-01-30 | 2021-05-10 | 교세라 가부시키가이샤 | 실장 구조체 |
CN112913007A (zh) * | 2019-01-30 | 2021-06-04 | 京瓷株式会社 | 安装构造体 |
JPWO2020158085A1 (ja) * | 2019-01-30 | 2021-10-14 | 京セラ株式会社 | 実装構造体 |
JP7062097B2 (ja) | 2019-01-30 | 2022-05-02 | 京セラ株式会社 | 実装構造体 |
KR102430745B1 (ko) | 2019-01-30 | 2022-08-09 | 교세라 가부시키가이샤 | 실장 구조체 |
CN112913007B (zh) * | 2019-01-30 | 2023-10-10 | 京瓷株式会社 | 安装构造体 |
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CN1902751A (zh) | 2007-01-24 |
TWI260488B (en) | 2006-08-21 |
KR20060085920A (ko) | 2006-07-28 |
US7091586B2 (en) | 2006-08-15 |
HK1099964A1 (en) | 2007-08-31 |
DE112004002072T5 (de) | 2006-09-28 |
WO2005048323A2 (en) | 2005-05-26 |
TW200523724A (en) | 2005-07-16 |
KR100806424B1 (ko) | 2008-02-21 |
US20050093120A1 (en) | 2005-05-05 |
CN100527396C (zh) | 2009-08-12 |
WO2005048323A3 (en) | 2005-07-07 |
JP4287474B2 (ja) | 2009-07-01 |
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