WO2020155719A1 - 高散热硅基封装基板、制作方法及高散热封装结构 - Google Patents

高散热硅基封装基板、制作方法及高散热封装结构 Download PDF

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WO2020155719A1
WO2020155719A1 PCT/CN2019/115256 CN2019115256W WO2020155719A1 WO 2020155719 A1 WO2020155719 A1 WO 2020155719A1 CN 2019115256 W CN2019115256 W CN 2019115256W WO 2020155719 A1 WO2020155719 A1 WO 2020155719A1
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silicon
heat dissipation
vertical
substrate
high heat
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PCT/CN2019/115256
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English (en)
French (fr)
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孙海燕
赵继聪
孙玲
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南通大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/094—Feed-through, via
    • B81B2207/096—Feed-through, via through the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Definitions

  • the invention belongs to the field of packaging technology, and specifically relates to a high heat dissipation silicon-based packaging substrate and a manufacturing method thereof, and a packaging structure based on the high heat dissipation silicon-based packaging substrate.
  • packaging structure needs to have excellent electrical performance, but also the packaging structure needs to have good heat dissipation performance to ensure the long-term chip Work steadily.
  • the packaging of integrated circuit chips it is necessary to connect the integrated circuit chip with the packaging substrate to realize the electrical interconnection between the chip and the outside world.
  • the traditional packaging substrate is prepared by the PCB process, and the heat dissipation performance is poor, and the electrical signal passes through the internal through holes of the PCB to cause a large loss, which is difficult to meet the application requirements of future integrated circuit chips.
  • the chip and the heat sink are usually connected by solder bonding to form a heat dissipation channel with low thermal resistance.
  • heat sinks based on metal substrates are large in size, difficult to integrate on-chip, and it is difficult to achieve lossless extraction of weak RF signals, which is contrary to the development trend of integrated circuit chips.
  • the solder bonding process introduced increases the packaging manufacturing cost to a certain extent.
  • the traditional integrated circuit chip uses the PCB board as the packaging substrate, and is wired on the PCB board and connected with the chip solder joints to realize the extraction of electrical signals.
  • the thermal conductivity of the PCB board is only 0.2 to 0.8 W/m ⁇ K, which makes it difficult to dissipate the heat emitted by the integrated circuit chip, which easily causes reliability problems.
  • metal heat sinks can be introduced into the package structure to solve the heat dissipation problem of integrated circuit chips, such as a metal copper heat sink with a thermal conductivity of 387.6W/m ⁇ K, this traditional heat dissipation structure not only makes the size of the integrated circuit chip It is difficult to shrink further, and it also increases manufacturing costs.
  • silicon wafers are commonly used as substrates for integrated circuits and semiconductor devices and have good heat dissipation performance.
  • the use of silicon wafers as the base to make the package heat dissipation substrate is beneficial to the rapid heat dissipation, miniaturization, and integration of the chip, and can meet the application needs of future integrated circuit chips, it is urgent to design high heat dissipation with high heat dissipation and low loss characteristics.
  • the purpose of the present invention is to address one or more of the existing technical problems.
  • the present invention provides a high heat dissipation silicon-based packaging substrate.
  • the invention provides a high heat dissipation silicon-based packaging substrate, which includes a silicon substrate.
  • the silicon substrate is longitudinally provided with a plurality of vertical through holes, the vertical through holes penetrate the upper and lower surfaces of the silicon substrate, and the vertical through holes are provided with conductive and heat conductive columns, Both ends of the conductive and heat-conducting pillars are exposed on the upper and lower surfaces of the silicon substrate, an electrical isolation layer is arranged on the inner side wall of the vertical through hole, and the diameter of the vertical through hole is in the range of 50-200 ⁇ m.
  • the high heat dissipation silicon-based packaging substrate provided by the present invention has high integration of a heat dissipation module, small size and low cost, is beneficial to the application of the packaging structure, and avoids the defects existing in the traditional PCB packaging substrate manufacturing process.
  • the present invention provides a high-heat-dissipation package structure based on a high-heat-dissipation silicon-based packaging substrate, including the above-mentioned high-heat-dissipation silicon-based packaging substrate, a chip attached to the upper surface of the silicon substrate of the high-heat-dissipation silicon-based packaging substrate, and A plastic package located on the periphery, the chip includes solder joints, and the solder joints are electrically connected with the conductive and heat-conducting pillars.
  • the number of electrically and thermally conductive pillars is multiple, and a part of the electrically and thermally conductive pillars are electrically connected to the chip.
  • the solder joint is located on the side of the chip that is not in contact with the silicon substrate, and the package structure includes a gold wire electrically connecting the conductive and heat-conducting column and the solder joint.
  • the present invention provides a method for manufacturing a high heat dissipation silicon-based packaging substrate, which includes the following steps:
  • Step 1 Etch the bottom silicon of the SOI wafer with preset parameters to the insulating layer to form vertical through holes;
  • Step 2 Making an electrical isolation layer on the inner side wall of the vertical through hole
  • Step 3 Etching the insulating layer at the bottom of the vertical via
  • Step 4 Form a conductive and thermally conductive column in the vertical through hole
  • Step 5 Remove the top silicon and insulating layer, and planarize the surface of the bottom silicon.
  • the middle SOI wafer in step 1, includes a top layer of silicon, a bottom layer of silicon, and an insulating layer between the top layer of silicon and the bottom layer of silicon.
  • the top layer of silicon is low-resistance silicon with a resistivity of less than 0.002 ⁇ cm.
  • the low-resistance top silicon can replace the traditional electroplating seed layer, laying the foundation for the selection of the manufacturing process of the conductive and heat-conducting pillars.
  • the bottom silicon is etched using a deep silicon etching process, such as Bosch DRIE process.
  • the insulating layer can be used as a stop layer to realize the self-stop effect of deep silicon etching.
  • step 2 the method of fabricating the electrical isolation layer is to use a thermal oxidation process to fabricate a thermal oxygen layer on the sidewall of the vertical via.
  • step 3 the etching in step 3 adopts a reactive ion etching process.
  • step 4 an electroplating process is used to fabricate the conductive and thermally conductive pillars in the vertical through holes, the top silicon is used as the plating seed layer, and the bottom-up metal copper plating method is used to realize the metalization inside the vertical through holes. Form a vertical conductive and thermal column.
  • step 5 a chemical mechanical polishing process is used to remove the top silicon, the insulating layer, and planarize the bottom silicon surface.
  • the high heat dissipation silicon-based packaging substrate provided by the present invention is made of SOI wafers, replacing traditional PCB board packaging substrates and metal heat sinks.
  • the bottom silicon is the substrate material of the integrated circuit chip, and its thermal conductivity is 148W/m ⁇ K.
  • Vertical through holes are formed in the bottom silicon, and a thermal oxygen layer and conductive and thermally conductive pillars are formed in the vertical through holes.
  • the conductive and thermally conductive pillars are electrically isolated from the underlying silicon by the thermal oxygen layer. Furthermore, one can selectively divide a part of the number of conductive and thermally conductive pillars It is used to conduct heat and dissipate heat, and transmit electrical signals to another number of conductive and heat-conducting pillars.
  • the present invention provides a high heat dissipation silicon-based package substrate with good heat dissipation performance, low-loss transmission of chip electrical signals, long-term stable operation of the chip, simple structure and low cost, and its manufacturing process and its manufacturing process based on the high-heat dissipation silicon-based package substrate.
  • the package structure of the package substrate is not limited to, but not limited to, but not limited to, but not limited to, but not limited to the package substrate.
  • FIG. 1 is a schematic structural diagram of an embodiment of a high heat dissipation silicon-based packaging substrate provided by the present invention
  • FIG. 2 is a schematic structural diagram of an embodiment of a high heat dissipation package structure provided by the present invention
  • FIG. 3 is a schematic diagram of the structure after step 1 of the method for manufacturing a high heat dissipation silicon-based packaging substrate provided by the present invention
  • step 2 is a schematic structural diagram after step 2 of a method for manufacturing a high heat dissipation silicon-based packaging substrate provided by the present invention
  • FIG. 5 is a schematic structural diagram after step 3 of an implementation method of a manufacturing method of a high heat dissipation silicon-based packaging substrate provided by the present invention
  • FIG. 6 is a schematic diagram of the structure after step 4 of an implementation method of a manufacturing method of a high heat dissipation silicon-based packaging substrate provided by the present invention
  • FIG. 7 is a schematic structural diagram after step 5 of an implementation method of a manufacturing method of a high heat dissipation silicon-based packaging substrate provided by the present invention.
  • Figure 8 is a thermal simulation result diagram of the PCB package substrate
  • Figure 9 is a thermal simulation result diagram of a PCB package substrate with heat dissipation pillars
  • Figure 10 is a thermal simulation result diagram of a silicon substrate
  • FIG. 11 is a schematic diagram of thermal simulation of the high heat dissipation silicon-based package substrate provided by the present invention.
  • the corresponding reference signs in the figure are: 1-bottom silicon, 2-electrically conductive and thermally conductive pillars, 3-chips, 4-solder joints, 5-gold wires, 6-electrical isolation layer, 7-top silicon, 8-insulation Layer, 9-vertical through hole.
  • the present invention provides a high heat dissipation silicon-based packaging substrate, including a silicon substrate.
  • the silicon substrate is provided with a plurality of vertical through holes 9 longitudinally, and the vertical through holes 9 penetrate the upper and lower sides of the silicon substrate.
  • the vertical through holes 9 are provided with electrically and thermally conductive pillars 2, both ends of the electrically conductive and thermally conductive pillars 2 are exposed on the upper and lower surfaces of the silicon substrate.
  • the diameter of 9 ranges from 50-200 ⁇ m.
  • the high heat dissipation silicon-based packaging substrate provided by the present invention has high integration of a heat dissipation module, small size and low cost, is beneficial to the application of the packaging structure, and avoids the defects existing in the traditional PCB packaging substrate manufacturing process.
  • the present invention provides a high heat dissipation package structure based on a high heat dissipation silicon-based packaging substrate, including the above-mentioned high heat dissipation silicon-based packaging substrate and a silicon liner attached to the high heat dissipation silicon-based packaging substrate.
  • the number of electrically and thermally conductive pillars 2 is multiple, and part of the electrically and thermally conductive pillars 2 are electrically connected to the chip 3.
  • the solder joint 4 is located on the side of the chip 3 that is not in contact with the silicon substrate, and the package structure includes a gold wire 5 electrically connecting the conductive and thermally conductive pillar 2 and the solder joint 4.
  • the present invention provides a method for manufacturing a high heat dissipation silicon-based packaging substrate, which includes the following steps:
  • Step 1 Etch the bottom silicon 1 to the insulating layer 8 of the SOI wafer with preset parameters to form vertical through holes 9;
  • Step 2 Fabricate an electrical isolation layer 6 on the inner side wall of the vertical through hole 9;
  • Step 3 Etching the insulating layer 8 at the bottom of the vertical through hole 9;
  • Step 4 An electrically and thermally conductive column 2 is formed in the vertical through hole 9;
  • Step 5 Remove the top silicon 7 and the insulating layer 8, and planarize the surface of the bottom silicon 1.
  • the middle SOI wafer includes top silicon 7, bottom silicon 1, and an insulating layer 8 between the top silicon 7 and the bottom silicon 1.
  • the top silicon 7 selects low-resistance silicon with a resistivity lower than 0.002 ⁇ cm .
  • Low-resistance top silicon can replace the traditional electroplating seed layer, laying the foundation for the selection of the manufacturing process of the conductive and heat-conducting pillars;
  • the bottom silicon 1 is etched using a deep silicon etching process, such as the Bosch DRIE process.
  • the insulating layer 8 can be used as a stop layer to realize the self-stop effect of deep silicon etching.
  • step 2 specifically, and preferably, the method of fabricating the electrical isolation layer 6 is to fabricate a thermal oxygen layer on the sidewall of the vertical through hole 9 by a thermal oxidation process.
  • step 3 specifically, the etching in step 3 should adopt a reactive ion etching process.
  • step 4 specifically, an electroplating process should be used to fabricate the conductive and thermally conductive pillars 2 in the vertical through holes 9 with the top silicon as the plating seed layer, and the bottom-up method of electroplating metal copper to realize the metalization of the vertical through holes 9 ,Form a vertical conductive and thermal column 2.
  • step 5 specifically, a chemical mechanical polishing CMP process should be used to remove the top silicon 7, the insulating layer 8 and planarize the surface of the bottom silicon 1.
  • the high heat dissipation silicon-based packaging substrate provided by the present invention is made of SOI wafers, replacing traditional PCB board packaging substrates and metal heat sinks.
  • the bottom silicon is the substrate material of the integrated circuit chip, and its thermal conductivity is 148W/m ⁇ K.
  • Vertical through holes are formed in the bottom silicon, and a thermal oxygen layer and conductive and thermally conductive pillars are formed in the vertical through holes.
  • the conductive and thermally conductive pillars are electrically isolated from the underlying silicon by the thermal oxygen layer. Furthermore, one can selectively divide a part of the number of conductive and thermally conductive pillars It is used to conduct heat and dissipate heat, and transmit electrical signals to another number of conductive and heat-conducting pillars.
  • the Ansys software is used to analyze four different substrate structures including PCB substrate, PCB substrate with heat dissipation pillars, silicon substrate, and high heat dissipation silicon provided by the present invention.
  • Base package substrate for modeling and simulation. In the simulation process, a 1W heat radiation source was applied to these four substrate structures.
  • the above-mentioned four substrate sizes are all 2.1 ⁇ 2.1 ⁇ 0.5mm, the chip size is 1.5 ⁇ 1.5 ⁇ 0.01mm, the chip is placed in the middle of the upper surface of the substrate, and the power consumption is 1W.
  • the thermal conductivity of PCB, silicon and copper are 0.35W/m ⁇ K, 148W/m ⁇ K, and 387.6W/m ⁇ K, respectively.
  • all the conductive and thermally conductive pillars are made of copper with a diameter of 0.1mm, the distance between adjacent dissipative and thermally conductive pillars is 0.05mm, and the number of conductive and heat conductive pillars is 169. ⁇ 13 array arrangement;
  • all heat dissipation pillars are made of copper and have a diameter of 0.1mm.
  • the distance between adjacent heat dissipation pillars is 0.05mm.
  • the number of heat dissipation pillars is 169, which are also arranged in a 13 ⁇ 13 array.
  • the PCB substrate with heat dissipation pillars improves the heat dissipation performance of the substrate to a certain extent, and the maximum surface temperature is reduced from 458.174°C to 1.955°C.
  • the highest surface temperature is only 0.889°C.
  • its heat dissipation performance is improved by 99.81%, 54.53% and 30.49%, respectively.
  • the high heat dissipation silicon-based package substrate structure provided by the present invention has excellent heat dissipation performance.
  • the high heat dissipation silicon-based packaging substrate structure provided by the present invention has great advantages.
  • the high heat dissipation silicon-based packaging substrate prepared has vertical through holes formed in the underlying silicon, and a thermal oxygen layer is formed in the vertical through holes, and electroplated to produce electrical and thermal conductivity
  • the column and the thermal oxygen layer can realize the electrical isolation between the conductive and thermally conductive column and the underlying silicon, and the conductive and thermally conductive column formed after electroplating can simultaneously realize the functions of transmitting electrical signals and heat dissipation.
  • the high heat dissipation silicon-based packaging substrate provided by the present invention has high integration, and has excellent thermal matching performance after being combined with the silicon-based chip, and its heat dissipation performance and electrical signal transmission performance are better than traditional PCB packaging substrates.
  • the manufacturing method of the high heat dissipation silicon-based packaging substrate of the present invention uses the top silicon with low resistance characteristics as the electroplating seed layer, instead of the traditional metal thin film seed layer structure, and adopts the bottom-up metal copper electroplating method to achieve communication
  • the inside of the hole is metallized to form a conductive and thermal column 2, and the insulating layer can realize the self-stop effect of deep silicon etching, the manufacturing process is simple, and the production efficiency is high.
  • the high heat dissipation silicon-based packaging substrate provided by the present invention has the advantages of small size, compact structure, reliable work, convenient use, wide versatility, and easy realization of package miniaturization.
  • this article can provide demonstrations of parameters containing specific values, but these parameters need not be exactly equal to the corresponding values, but can be approximated to the corresponding values within acceptable error tolerances or design constraints.
  • the directional terms mentioned in the embodiments such as “upper”, “lower”, “front”, “rear”, “left”, “right”, etc., are only directions with reference to the drawings, and are not used to limit the application protected range.
  • the steps are specifically described or must occur sequentially, the order of the above steps is not limited to the above list, and can be changed or rearranged according to the required design.
  • the above-mentioned embodiments can be mixed and matched with each other or mixed and matched with other embodiments based on the consideration of design and reliability, that is, the technical features in different embodiments can be freely combined to form more embodiments.

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种高散热硅基封装基板，包括硅衬底，硅衬底纵向设置多个垂直通孔（9），垂直通孔（9）贯穿硅衬底的上、下表面，垂直通孔（9）内设置导电导热柱（2），导电导热柱（2）两端裸露于硅衬底的上下表面，导电导热柱（2）外侧壁设置电学隔离层（6），垂直通孔（9）的直径范围为50～200μm，上述高散热硅基封装基板，具备散热模块集成度高，体积小巧，成本低，有利于封装结构的应用，此外还提供了其制作方法及基于其的封装结构。

Description

高散热硅基封装基板、制作方法及高散热封装结构 技术领域
本发明属于封装技术领域，具体涉及一种高散热硅基封装基板及其制作方法及基于该高散热硅基封装基板的封装结构。
背景技术
随着集成电路芯片向高功耗、高频率的方向发展，对封装技术提出了更高的要求，不仅需要封装结构具有优异的电学性能，还需要封装结构具有良好的散热性能，以保证芯片长期稳定地工作。
对于集成电路芯片的封装，需要将集成电路芯片与封装基板进行连接，以实现芯片与外界的电学互连。传统的封装基板是采用PCB工艺制备，散热性能较差，且电学信号经过PCB板内部通孔而引起的损耗较大，难以满足未来集成电路芯片的应用需求。为了解决封装结构的散热问题，通常将芯片与热沉通过焊料键合连接，形成低热阻的散热通道。然而，基于金属基板的热沉尺寸较大，难以片上集成，且不易实现射频微弱信号的无损引出，与集成电路芯片的发展趋势相悖。另外，引入的焊料键合工艺一定程度上增加了封装制造成本。
传统的集成电路芯片是以PCB板材作为封装基板，在PCB板上布线并与芯片焊点相连，实现电学信号的引出。然而，PCB板材的导热系数只有0.2～0.8W/m·K，难以将集成电路芯片散发的热量导出，易引起可靠性问题。虽然，可以在封装结构中引入金属热沉而解决集成电路芯片的散热问题，如导热系数为387.6W/m·K的金属铜热沉，但是这种传统的散热结构不仅使得集成电路芯片的尺寸增大并难以进一步缩小，还增加了制造成本。
目前，硅圆片通常用于集成电路和半导体器件的基底，具有良好的散热性能。虽然以硅圆片为基底制作封装散热基板，有益于芯片的快速散热、小型化、集成化等，能够满足未来集成电路芯片的应用需求，但是亟需设计具有高散热、低损耗特性的高散热硅基封装基板及基于其的封装结构，以及开发高可靠、低成本的微纳制造工艺。
因此，如何针对上述现有技术所存在的缺点进行研发改良，实为相关业界所需努力 研发的目标，本申请设计人有鉴于此，乃思及创作的意念，遂以多年的经验加以设计，经多方探讨并试作样品试验，及多次修正改良，乃推出本申请。
发明内容
本发明的目的是针对现有技术问题中的一个或者多个，本发明提供一种高散热硅基封装基板。
本发明提供一种高散热硅基封装基板，包括硅衬底，硅衬底纵向设置多个垂直通孔，垂直通孔贯穿硅衬底的上、下表面，垂直通孔内设置导电导热柱，导电导热柱两端裸露于硅衬底的上下表面，垂直通孔内侧壁设置电学隔离层，垂直通孔的直径范围为50～200μm。
本发明提供的高散热硅基封装基板，具备散热模块集成度高，体积小巧，成本低，有利于封装结构的应用，避免了传统PCB封装基板制作工艺中存在的缺点。
另一方面，本发明基于高散热硅基封装基板，提供了一种高散热封装结构，包括上述的高散热硅基封装基板、附着于高散热硅基封装基板的硅衬底上表面的芯片及位于外围的塑封体，芯片包括焊点，焊点与导电导热柱电连接。
在一些实施方式中，导电导热柱的数目为多个，其中部分数目的导电导热柱与芯片电连接。
在一些实施方式中，焊点位于芯片非接触于硅衬底的一面，封装结构包括电连接导电导热柱与焊点的金丝线。
再一方面，本发明提供了一种高散热硅基封装基板的制作方法，包括如下步骤：
步骤1、刻蚀预设参数的SOI片的底层硅至绝缘层形成垂直通孔；
步骤2、垂直通孔的内侧壁制作电学隔离层；
步骤3、刻蚀垂直通孔底部的绝缘层；
步骤4、于垂直通孔内形成导电导热柱；
步骤5、去除顶层硅、绝缘层，并平坦化底层硅表面。
在一些实施方式中，步骤1中，中SOI片包括顶层硅、底层硅及位于顶层硅与底层硅之间的绝缘层，顶层硅选择低电阻硅，电阻率低于0.002Ω·cm。
低电阻顶层硅可替代传统的电镀种子层，为导电导热柱的制作工艺选择奠定基础。
刻蚀底层硅采用深硅刻蚀工艺，例Bosch DRIE工艺，绝缘层可作为截止层，实现 深硅刻蚀的自停止效应。
在一些实施方式中，步骤2中，制作电学隔离层方法为采用热氧化工艺于垂直通孔的侧壁制作热氧层。
在一些实施方式中，步骤3中，步骤3中刻蚀采用反应离子刻蚀工艺。
在一些实施方式中，步骤4中，于垂直通孔内制作导电导热柱采用电镀工艺，以顶层硅作为电镀种子层，采用自底向上电镀金属铜的方法，实现垂直通孔内部的金属化，形成垂直导电导热柱。
在一些实施方式中，步骤5中，采用化学机械抛光工艺去除顶层硅、绝缘层以及平坦化底层硅表面。
本发明提供的高散热硅基封装基板采用SOI片制作，取代传统的PCB板材封装基板和金属热沉，底层硅为集成电路芯片的衬底材料，其导热系数为148W/m·K。在底层硅中形成垂直通孔，在垂直通孔内形成热氧层与导电导热柱，导电导热柱通过热氧层与底层硅电学隔离，进而，人们可以有选择地将部分数目的导电导热柱用于导热散热，将另部分数目的导电导热柱传输电学信号。
综述，本发明提供一种散热性能良好、芯片电学信号能够低损耗传输、芯片能够长期稳定地工作，并且结构简单、成本低的高散热硅基封装基板及其制作工艺及基于该高散热硅基封装基板的封装结构。
附图说明
为了更清楚地说明本发明的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它附图。
图1为本发明提供的一种高散热硅基封装基板的一种实施方式的结构示意图；
图2为本发明提供的高散热封装结构的一种实施方式的结构示意图；
图3为本发明提供的一种高散热硅基封装基板的制作方法的一种实施方法的步骤1处理后的结构示意图；
图4为本发明提供的一种高散热硅基封装基板的制作方法的一种实施方法的步骤2处理后的结构示意图；
图5为本发明提供的一种高散热硅基封装基板的制作方法的一种实施方法的步骤3处理后的结构示意图；
图6为本发明提供的一种高散热硅基封装基板的制作方法的一种实施方法的步骤4处理后的结构示意图；
图7是本发明提供的一种高散热硅基封装基板的制作方法的一种实施方法的步骤5处理后的结构示意图；
图8是PCB封装基板的热仿真结果图；
图9是带有散热柱的PCB封装基板的热仿真结果图；
图10是硅基板的热仿真结果图；
图11是本发明提供的高散热硅基封装基板的热仿真示意图。
其中，图中对应的附图标记为：1-底层硅，2-导电导热柱，3-芯片，4-焊点，5-金丝线，6-电学隔离层，7-顶层硅，8-绝缘层，9-垂直通孔。
具体实施方式
下面将结合本发明实施例中的附图，对发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
一方面，如图1所示，本发明提供一种高散热硅基封装基板，包括硅衬底，硅衬底纵向设置多个垂直通孔9，垂直通孔9贯穿硅衬底的上、下表面，垂直通孔9内设置导电导热柱2，导电导热柱2两端裸露于硅衬底的上下表面，垂直通孔9内侧壁即导电导热柱2外侧壁设置电学隔离层6，垂直通孔9的直径范围为50-200μm。
本发明提供的高散热硅基封装基板，具备散热模块集成度高，体积小巧，成本低，有利于封装结构的应用，避免了传统PCB封装基板制作工艺中存在的缺点。
另一方面，如图2所示，本发明基于高散热硅基封装基板，提供了一种高散热封装结构，包括上述的高散热硅基封装基板、附着于高散热硅基封装基板的硅衬底上表面的芯片3及位于外围的塑封体，芯片3包括焊点4，焊点4与导电导热柱2电连接。
在一些实施方式中，导电导热柱2的数目为多个，其中部分数目的导电导热柱2与芯片3电连接。
在一些实施方式中，焊点4位于芯片3非接触于硅衬底的一面，封装结构包括电连接导电导热柱2与焊点4的金丝线5。
请参阅图3～7。再一方面，本发明提供了一种高散热硅基封装基板的制作方法，包括如下步骤：
步骤1、刻蚀预设参数的SOI片的底层硅1至绝缘层8形成垂直通孔9；
步骤2、垂直通孔9的内侧壁制作电学隔离层6；
步骤3、刻蚀垂直通孔9底部的绝缘层8；
步骤4、于垂直通孔9内形成导电导热柱2；
步骤5、去除顶层硅7、绝缘层8，并平坦化底层硅1表面。
步骤1中，具体的，中SOI片包括顶层硅7、底层硅1及位于顶层硅7与底层硅1之间的绝缘层8，顶层硅7选择低电阻硅，电阻率低于0.002Ω·cm。
低电阻顶层硅可替代传统的电镀种子层，为导电导热柱的制作工艺选择奠定基础；
刻蚀底层硅1采用深硅刻蚀工艺，例Bosch DRIE工艺，绝缘层8可作为截止层，实现深硅刻蚀的自停止效应。
步骤2中，具体的，可优选，制作电学隔离层6方法为采用热氧化工艺于垂直通孔9的侧壁制作热氧层。
步骤3中，具体的，步骤3中刻蚀宜采用反应离子刻蚀工艺。
步骤4中，具体的，于垂直通孔9内制作导电导热柱2宜采用电镀工艺，以顶层硅作为电镀种子层，采用自底向上电镀金属铜的方法，实现垂直通孔9内部的金属化，形成垂直导电导热柱2。
步骤5中，具体的，宜采用化学机械抛光CMP工艺去除顶层硅7、绝缘层8以及平坦化底层硅1表面。
本发明提供的高散热硅基封装基板采用SOI片制作，取代传统的PCB板材封装基板和金属热沉，底层硅为集成电路芯片的衬底材料，其导热系数为148W/m·K。在底层硅中形成垂直通孔，在垂直通孔内形成热氧层与导电导热柱，导电导热柱通过热氧层与底层硅电学隔离，进而，人们可以有选择地将部分数目的导电导热柱用于导热散热，将另部分数目的导电导热柱传输电学信号。
仿真结果证实本发明提供的高散热硅基封装基板及基于其的封装结构具有优异的散热性能，在集成化、热匹配等方面具有巨大的优势，其散热性能和电学信号传输性能优于传统PCB封装基板及基于传统PCB封装基板的封装结构。
为了验证本发明提供的高散热硅基封装基板结构具有优异的热学性能，利用Ansys软件对四种不同基板结构包括PCB基板、带有散热柱的PCB基板、硅基板、本发明提供的高散热硅基封装基板进行建模仿真。在仿真过程中，对这四种基板结构均施加1W的热辐射源。
仿真试验中，示例性采用上述四种基板尺寸大小均为2.1×2.1×0.5mm，芯片尺寸大小为1.5×1.5×0.01mm，芯片置于基板上表面正中间，功耗为1W。PCB、硅以及铜的热传导率分别为0.35W/m·K、148W/m·K、387.6W/m·K。设定模型的上、前、后、左和右5个表面设置为绝热属性，模型环境温度设置为0℃，用来验证不同基板设置情况下的单向散热特性。
对于本发明提供的高散热硅基封装基板，所有的导电导热柱材质均为铜，直径为0.1mm，相邻散导电导热柱的间距为0.05mm，导电导热柱的数量为169个，按13×13阵列排布；
对于带有散热柱的PCB基板，所有散热柱材质也均为铜，直径也为0.1mm，相邻散热柱的间距为0.05mm，散热柱的数量为169个，也按13×13阵列排布
如图8所示，对于PCB基板，仿真结果显示其表面温度最高达到458.174℃，
如图9所示。带有散热柱的PCB基板一定程度上提高了基板的散热性能，表面最高温度从458.174℃降至1.955℃，
如图10所示。如果选用硅基板，其表面最高温度进一步下降至1.279℃，
如图11所示。进一步地，以本发明提供的高散热硅基封装基板结构，表面最高温度只有0.889℃，相比于以上三种基板，其散热性能分别提高99.81％、54.53％以及30.49％。
上述仿真结果证实本发明提供的高散热硅基封装基板结构具有优异的散热性能。此外，在集成化以及热匹配等方面，本发明提供的高散热硅基封装基板结构具有巨大的优势。
实施本发明，具有如下有益效果：
(1)本发明的高散热硅基封装基板的制作工艺，制得的高散热硅基封装基板，在底层硅中形成垂直通孔，在垂直通孔内形成热氧层，并电镀制作导电导热柱，热氧层能够实现导电导热柱与底层硅的电学隔离，而电镀后形成的导电导热柱可以同时实现传输电学信号和散热的功能。
(2)本发明提供的高散热硅基封装基板具有高集成化，且与硅基芯片组合后具备优异的热匹配性能，其散热性能和电学信号传输性能均优于传统的PCB封装基板。
(3)本发明的高散热硅基封装基板的制作方法，以具有低阻特性的顶层硅作为电镀种子层，取代传统的金属薄膜种子层结构，采用自底向上电镀金属铜的方法，实现通孔内部的金属化，形成导电导热柱2，绝缘层能够实现深硅刻蚀的自停止效应，制作工艺简单，生产效率高。
(4)本发明提供的高散热硅基封装基板，体积小巧、结构紧凑，工作可靠，使用方便，通用性广，易于实现封装小型化。
以上所述的具体实施例，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请的具体实施例而已，并不用于限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内
至此，已经结合附图对本实施例进行了详细描述。依据以上描述，本领域技术人员应当对本申请有了清楚的认识。
需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方式。
还需要说明的是，本文可提供包含特定值的参数的示范，但这些参数无需确切等于相应的值，而是可在可接受的误差容限或设计约束内近似于相应值。实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本申请的保护范围。此外，除非特别描述或必须依序发生的步骤，上述步骤的顺序并无限制于以上所列，且可根据所需设计而变化或重新安排。并且上述实施例可基于设计及可靠度的考虑，彼此混合搭配使用或与其他实施例混合搭配使用，即不同实施例中的技术特征可以自由组合形成更多的实施例。
以上所述的具体实施例，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请的具体实施例而已，并不用于限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 高散热硅基封装基板，其特征在于，包括硅衬底，所述硅衬底纵向设置多个垂直通孔(9)，所述垂直通孔(9)贯穿所述硅衬底的上、下表面，所述垂直通孔(9)内设置导电导热柱(2)，所述导电导热柱(2)两端裸露于所述硅衬底的上下表面，所述导电导热柱(2)外侧壁设置电学隔离层(6)，所述垂直通孔(9)的直径范围为50～200μm。
  2. 高散热封装结构，其特征在于，包括权利要求1的封装基板、附着于所述封装基板的硅衬底上表面的芯片(3)及位于外围的塑封体，所述芯片(3)包括焊点(4)，所述焊点(4)与所述导电导热柱(2)电连接。
  3. 根据权利要求2所述的高散热封装结构，其特征在于，所述导电导热柱(2)的数目为多个，其中部分数目的所述导电导热柱(2)与所述芯片(3)电连接。
  4. 根据权利要求2所述的高散热封装结构，其特征在于，所述焊点(4)位于芯片(3)非接触于硅衬底的一面，所述封装结构包括电连接所述导电导热柱(2)与所述焊点(4)的金丝线(5)。
  5. 权利要求1所述的封装基板的制作方法，其特征在于，包括如下步骤：
    步骤1、刻蚀预设参数的SOI片的底层硅(1)至绝缘层(8)形成垂直通孔(9)；
    步骤2、所述垂直通孔(9)的内侧壁制作电学隔离层(6)；
    步骤3、刻蚀垂直通孔(9)底部的绝缘层(8)；
    步骤4、于所述垂直通孔(9)内形成导电导热柱(2)；
    步骤5、去除顶层硅(7)、绝缘层(8)，并平坦化底层硅(1)表面。
  6. 根据权利要求5所述的高散热硅基封装基板的制作方法，其特征在于，步骤1中所述预设参数的SOI片包括顶层硅(7)、底层硅(1)及位于所述顶层硅(7)与所述底层硅(1)之间的绝缘层(8)，所述顶层硅(7)选自低电阻硅，电阻率低于0.002 Ω·cm。
  7. 根据权利要求5所述的高散热硅基封装基板的制作方法，其特征在于，步骤1中刻蚀底层硅(1)采用深硅刻蚀工艺，步骤3中所述刻蚀为采用反应离子刻蚀工艺。
  8. 根据权利要求5所述的高散热硅基封装基板的制作方法，其特征在于，步骤2中所述制作电学隔离层(6)方法为热氧化工艺于垂直通孔(9)的侧壁制作热氧层。
  9. 根据权利要求5所述的高散热硅基封装基板的制作方法，其特征在于，所述步骤4、于所述垂直通孔(9)内制作导电导热柱(2)采用电镀工艺，以所述顶层硅作为电镀种子层，采用自底向上电镀金属铜的方法，实现垂直通孔(9)内部的金属化，形成垂直导电导热柱(2)。
  10. 根据权利要求5所述的高散热硅基封装基板的制作方法，其特征在于，所述步骤5采用化学机械抛光(CMP)工艺去除顶层硅(7)、绝缘层(8)以及平坦化底层硅(1)表面。
PCT/CN2019/115256 2019-01-28 2019-11-04 高散热硅基封装基板、制作方法及高散热封装结构 WO2020155719A1 (zh)

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