WO2020155218A1 - 显示面板、驱动方法和驱动电路 - Google Patents

显示面板、驱动方法和驱动电路 Download PDF

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WO2020155218A1
WO2020155218A1 PCT/CN2019/075518 CN2019075518W WO2020155218A1 WO 2020155218 A1 WO2020155218 A1 WO 2020155218A1 CN 2019075518 W CN2019075518 W CN 2019075518W WO 2020155218 A1 WO2020155218 A1 WO 2020155218A1
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pixel
gate line
gate
pull
time
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English (en)
French (fr)
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单剑锋
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HKC Co Ltd
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HKC Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0469—Details of the physics of pixel operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0847—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/028—Improving the quality of display appearance by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors

Definitions

  • This application relates to the field of display technology, and in particular to a display panel, a driving method and a driving circuit.
  • Flat panel displays include Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and Organic Light-Emitting Diode (OLED) displays.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • the thin film transistor liquid crystal display refracts the light from the backlight module to produce a picture by controlling the rotation direction of the liquid crystal molecules, and has many advantages such as thin body, power saving, and no radiation.
  • the organic light emitting diode display is made of organic electroluminescent diodes, and has many advantages such as self-luminescence, short response time, high definition and contrast, flexible display and large-area full-color display.
  • the definition and stability of the displayed picture are often affected by the driving voltage, which leads to a decrease in definition and stability of the picture, and some flickers are often caused.
  • the present application provides a display panel, a driving method, and a driving circuit that reduce or even eliminate the phenomenon of flickering of the display panel caused by the redistribution of the parasitic capacitance on the liquid crystal capacitance and the storage capacitance.
  • the present application provides a display panel, including a plurality of data lines, a plurality of gate lines, and a plurality of pixels.
  • the gate lines and the data lines are interlaced to form a plurality of pixels; each pixel is composed of a corresponding The gate line and the data line are driven, and each pixel includes a corresponding pixel electrode; wherein the pixel electrode of the pixel overlaps with another adjacent gate line to form an overlapping area.
  • the gate line includes a main gate line and an auxiliary gate line that are mutually conductive, and the main gate line is arranged to cross the data line.
  • auxiliary gate line and the data line are arranged in parallel.
  • the same gate line connects two adjacent pixels to form a pixel group, and the pixel group includes a first pixel and a second pixel connected to different data lines; wherein, the first pixel of the pixel group The pixel electrode of the pixel electrode overlaps the previous gate line to form a first overlapping area; the pixel electrode of the second pixel of the pixel group overlaps the next gate line to form a second overlapping area.
  • the auxiliary gate line includes a first auxiliary gate line and a second auxiliary gate line, and the pixel electrode of the second pixel corresponding to the first auxiliary gate line and the previous gate line forms a first In an overlapping area, the second auxiliary gate line and the pixel electrode of the first pixel corresponding to the next gate line form a second overlapping area.
  • the same data line connects two adjacent pixels to form a pixel group, and the pixel group includes a first pixel and a second pixel connected to different gate lines; wherein the first pixel of the pixel group The pixel electrode of one pixel overlaps with the previous gate line to form a first overlap area; the pixel electrode of the second pixel of the pixel group overlaps with the next gate line to form a second overlap area.
  • the same data line connects two adjacent pixels to form a pixel group, and the pixel group includes a first pixel and a second pixel connected to different gate lines; a gate connected to the first pixel
  • the pole line is a first gate line.
  • the first gate line includes a first main gate line and a first auxiliary gate line.
  • the gate line connected to the second pixel is a second gate line.
  • the second gate line includes a second main gate line and a second auxiliary gate line; the pixel electrode of the second pixel corresponding to the first auxiliary gate line and the second main gate line forms a first overlapping area
  • the pixel electrode of the first pixel corresponding to the second auxiliary gate line and the first main gate line forms a second overlapping area.
  • a first safety distance is set between the auxiliary gate line and the pixel electrode of the first pixel corresponding to the current main gate line and between the pixel electrode of the second pixel corresponding to the previous main gate line .
  • a second safety distance is provided between the auxiliary gate line and the corresponding data line.
  • the application also discloses a driving method, which is applied to the display panel as described above, and the display panel includes a plurality of pixels formed by a plurality of data lines and a plurality of gate lines interlaced with each other;
  • the driving method includes a step of outputting a gate driving signal to a gate line corresponding to the display panel;
  • one signal period of the gate drive signal includes a sustain time, a first pull-down time, an open time, and a second pull-down time; the duration of the first pull-down time and the open time and the second pull-down time The durations are equal; the gate drive signal is at the first low level during the maintenance time; at the high level during the on time; and at the second low level during the first pull-down time and the second pull-down time; The voltage value of the second low level is lower than the voltage value of the first low level.
  • the first pull-down time is before the turn-on time
  • one signal period of the gate drive signal further includes a second pull-down time after the turn-on time
  • the gate drive signal is at the second pull-down time
  • the time is the third low level
  • the voltage value of the third low level is lower than the voltage value of the first low level.
  • the first pull-down time and the turn-on time duration are equal; when the gate drive signal of the previous gate line corresponds to the turn-on time, the gate drive signal of the current gate line Corresponds to the first pull-down time.
  • the turn-on time and the second pull-down time period are equal; when the gate drive signal of the previous gate line corresponds to the second pull-down time, the gate drive signal of the current gate line corresponds to the Open time.
  • the voltage value of the second low level is equal to the voltage value of the third low level.
  • each pixel includes a pixel electrode, the same gate line connects two adjacent pixels to form a pixel group, and the pixel group includes a first pixel and a second pixel connected to different data lines;
  • the pixel electrode of the first pixel of the pixel group overlaps with the previous gate line to form a first overlapping area; the area of the first overlapping area is S1, and the first overlapping area of the first pixel is
  • the storage capacitor formed by overlapping a gate line is Cst1, the pixel capacitance of the first pixel is Clc1, and the parasitic capacitance formed by the pixel electrode of the first pixel and the current gate line is Cgs1;
  • the voltage value of the third low level is V'GL
  • the voltage value of the high level is VGH
  • the voltage value of the second low level is VGL;
  • Cst1 (VGH-VGL)*Cgs1/(VGL -V'GL).
  • each pixel includes a pixel electrode, the same gate line connects two adjacent pixels to form a pixel group, and the pixel group includes a first pixel and a second pixel connected to different data lines;
  • the pixel electrode of the second pixel of the pixel group overlaps with the next gate line to form a second overlap region; the area of the second overlap region is S2, and the second overlap region of the second pixel and the next gate line
  • the storage capacitor formed by the overlapping of polar lines is Cst2, the pixel capacitance of the second pixel is Clc2, and the parasitic capacitance formed by the pixel electrode of the second pixel and the current gate line is Cgs2; the first low level and the first
  • the voltage value of the three low levels is V'GL, the voltage value of the high level is VGH, and the voltage value of the second low level is VGL;
  • Cst2 (VGH-VGL)*Cgs2/(VGL-V 'GL).
  • the present application also discloses a driving circuit that drives the display panel as described above, and the driving circuit includes a gate driving circuit that outputs a gate driving signal to the gate line corresponding to the display panel
  • a signal period of the gate driving signal includes a sustain time, a first pull-down time, an open time, and a second pull-down time; the duration of the first pull-down time and the duration of the open time, and the second pull-down time
  • the durations are equal;
  • the gate drive signal is at the first low level during the maintenance time; at the high level during the on time; and at the second low level during the first pull-down time and the second pull-down time ;
  • the voltage value of the second low level is lower than the voltage value of the first low level.
  • the first pull-down time and the turn-on time duration are equal; when the gate drive signal of the previous gate line corresponds to the turn-on time, the gate drive signal of the current gate line Corresponds to the first pull-down time.
  • the turn-on time and the second pull-down time period are equal; when the gate drive signal of the previous gate line corresponds to the second pull-down time, the gate drive signal of the current gate line corresponds to the Open time.
  • a plurality of data lines and a plurality of gate lines in this application are interlaced to form a plurality of pixels, and each pixel includes A pixel electrode, the pixel electrode and the gate line easily form a parasitic capacitance.
  • the pixel electrode and phase corresponding to the current gate line Another adjacent gate line overlaps to form an overlapping area, which increases the storage capacitance, and reduces or even eliminates the phenomenon of flicker caused by the redistribution of the parasitic capacitance on the liquid crystal capacitance and the storage capacitance.
  • FIG. 1 is a schematic diagram of a pixel structure according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a pixel structure circuit of an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a pixel structure of an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a pixel structure according to another embodiment of the present application.
  • FIG. 5 is a schematic diagram of a pixel structure of another embodiment of the present application.
  • FIG. 6 is a schematic diagram of driving waveforms of another embodiment of the present application.
  • FIG. 7 is a schematic diagram of a driving circuit of another embodiment of the present application.
  • FIG. 8 is a schematic diagram of a display device according to another embodiment of the present application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating relative importance or implicitly indicating the number of indicated technical features. Therefore, unless otherwise specified, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features; “plurality” means two or more.
  • the term “comprising” and any variations thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components, and/or combinations thereof may be present or added.
  • connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection , It can also be electrical connection; it can be directly connected, it can also be indirectly connected through an intermediate medium, or the internal connection of two components.
  • connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection , It can also be electrical connection; it can be directly connected, it can also be indirectly connected through an intermediate medium, or the internal connection of two components.
  • an embodiment of the present application discloses a display panel 110, which includes a plurality of data lines 130, and a plurality of gate lines 140 and a plurality of pixels 150.
  • the gate lines 140 and the data lines 130 are mutually Staggered; a plurality of pixels 150 formed by interlacing each pixel 150 are driven by corresponding data lines 130 and gate lines 140, and each pixel 150 includes a corresponding pixel electrode; wherein, the pixel electrode of the pixel 150 is adjacent to another A gate line 140 overlaps, forming an overlap area.
  • the current gate line 140 corresponds to the pixel 150, and the gate line 140 adjacent to the current gate line 140 is called another gate line 140, and the pixel electrode of the pixel 150 overlaps the other gate line 140. , Forming an overlapping area.
  • a plurality of data lines 130 and a plurality of gate lines 140 are interlaced to form a plurality of pixels 150.
  • Each pixel 150 includes a pixel electrode.
  • the pixel electrode and the gate line 140 easily form a parasitic capacitance. In order to avoid parasitic capacitance This has a greater impact.
  • the gate line 140 includes a main gate line 141 and a sub-gate line 142 that are mutually conductive.
  • the main gate line 141 and the data line 130 are arranged to cross each other, and the auxiliary gate line 142 and the data line 130 are arranged in parallel. .
  • the gate line 140 is divided into a main gate line 141 and an auxiliary gate line 142.
  • the main gate line 141 and the data line 130 are alternately arranged, and the added auxiliary gate line 142 is parallel to the data line 130, and the main gate line
  • the pole line 141 and the auxiliary gate line 142 are connected to each other, which can reduce the influence of the data line 130 on the pixel electrode voltage, causing the so-called crosstalk and thus affecting the image quality. In addition, it can also reduce the parasitic capacitance between the main gate line 141 and the pixel electrode. The resulting effect causes display flicker on the display panel 110.
  • the same gate line 140 connects two adjacent pixels 150 to form a pixel group 160.
  • the pixel group 160 includes a first pixel 161 and a second pixel 161 connected to different data lines 130. Pixels 162; among them, the pixel electrode of the first pixel 161 of the pixel group 160 overlaps the previous gate line 140 to form a first overlap region 170; the pixel electrode of the second pixel 162 of the pixel group 160 and the next gate line 140 Overlap to form a second overlap area 180.
  • the two pixels 150 in the pixel group 160 respectively correspond to different data lines 130, which can better ensure the data driving voltage of each pixel 150, and prevent the load of the pixel electrode itself from causing the data voltage to decrease.
  • the pixel electrodes of the different pixels 150 in the group 160 overlap with the previous gate line 140 and the next gate line 140 to form two different storage capacitors.
  • Increasing the storage capacitor can reduce the pixel electrode and the gate line 140.
  • the influence of parasitic capacitance can reduce or even eliminate the redistribution effect of parasitic capacitance on the liquid crystal capacitance and storage capacitance, which causes the display panel 110 to produce flicker. It can also reduce the aperture ratio, increase the penetration rate of liquid crystal molecules, and achieve a large viewing role. .
  • the auxiliary gate line 142 includes a first auxiliary gate line 144 and a second auxiliary gate line 143, and the first auxiliary gate line 144 corresponds to the previous gate line 140
  • the pixel electrode of the second pixel 162 forms a second overlapping area 180
  • the pixel electrode of the first pixel 161 corresponding to the second auxiliary gate line 143 and the next gate line 140 forms a first overlapping area 170.
  • the auxiliary gate line 142 extending from the main gate line 141 and the pixel group 160 form an overlapping area.
  • the auxiliary gate line 142 can have the effect of shielding the electric field, reducing the formation of the electric field between the pixel electrode and the data line 130. between.
  • the same data line 130 connects two adjacent pixels 150 to form a pixel group 160.
  • the pixel group 160 includes a first pixel 161 and a second pixel 162 connected to different gate lines 140;
  • the pixel electrode of the first pixel 161 of the group 160 overlaps with the previous gate line 140 to form a first overlap area 170;
  • the pixel electrode of the second pixel 162 of the pixel group 160 overlaps with the next gate line 140 to form a second overlap District 180.
  • the area of the first overlap region is S1
  • the storage capacitor formed by overlapping the first overlap region 170 of the first pixel 161 with the previous gate line 140 is Cst1
  • the pixel capacitance of the first pixel 161 is Clc1
  • the pixel capacitance of the first pixel 161 is Clc1.
  • the parasitic capacitance formed by the electrode and the current gate line is Cgs1; the voltage value of the first low level and the third low level is V'GL, the voltage value of the high level is VGH, and the voltage value of the second low level is VGL;
  • ⁇ V’1 (VGH-V’GL)*Cgs1/(Cgs+Cst+Clc)
  • ⁇ V”1 (V’GL-VGH)*Cst1/(Cgs+Cst+Clc)
  • ⁇ V’2 (V’GL-VGL)*Cgs1/(Cgs+Cst+Clc)
  • ⁇ V”2 (VGH-V’GL)*Cst1/(Cgs+Cst+Clc)
  • the storage capacitor formed by overlapping the second overlap region 180 of the second pixel 162 with the next gate line 140 is Cst2, the pixel capacitance of the second pixel 162 is Clc2, and the parasitic capacitance formed by the pixel electrode of the second pixel 162 and the current gate line Is Cgs2;
  • the voltage value of the first low level and the third low level is V'GL, the voltage value of the high level is VGH, and the voltage value of the second low level is VGL;
  • ⁇ V’1 (VGH-V’GL)*Cgs2/(Cgs+Cst+Clc)
  • ⁇ V”1 (V’GL-VGL)*Cst2/(Cgs+Cst+Clc)
  • At3, ⁇ V2 (V’GL-VGL)*Cgs2/(Cgs+Cst+Clc)
  • the same data line 130 connects two adjacent pixels 150 to form a pixel group 160, and the pixel group 160 includes a first pixel 161 and a second pixel 162 connected to different gate lines 140; as shown in FIG. 4
  • the gate line 140 connected to the first pixel 161 is a first gate line
  • the first gate line includes a first main gate line 146 and a first auxiliary gate line 144
  • the line 140 is a second gate line
  • the second gate line includes a second main gate line 145 and a second auxiliary gate line 143
  • the first auxiliary gate line 144 and the second main gate line 145 correspond to the second
  • the pixel electrode of the pixel 162 forms a second overlapping area 180
  • the pixel electrode of the first pixel 161 corresponding to the second auxiliary gate line 143 and the first main gate line 146 forms a first overlapping area 170.
  • the provision of the auxiliary gate line 142 is based on the structure of connecting two adjacent pixels 150 to the same data line 130 and different gate lines 140 to weaken the parasitic capacitance formed by the data line 130 and the pixel electrode.
  • both the auxiliary gate line 142 and the pixel electrode of the first pixel 161 corresponding to the current main gate line 141 and the pixel electrode of the second pixel 162 corresponding to the previous main gate line 141 are provided. There is the first safety distance.
  • the preset threshold of the first safety distance is set.
  • This preset threshold is obtained by those skilled in the art through experiments or related data. Within the preset threshold, the solution is feasible. If the preset threshold is exceeded, the solution will Unable to implement, an electric field will be generated between the pixel electrode and the auxiliary gate line 142. If the distance is too close, the generated electric field will be relatively strong, which will affect the transmission of the data voltage signal, causing voltage instability and affecting the display of the screen.
  • the setting is safe The distance prevents the influence of electric field.
  • a second safe distance is provided between the auxiliary gate line 142 and the corresponding data line 130.
  • the auxiliary gate line 142 and the data line 130 are arranged in parallel, and the second safety distance is a preset threshold.
  • the preset threshold is obtained by those skilled in the art through experiments or related data. Within the preset threshold, the solution is feasible Yes, if the preset threshold is exceeded, this solution will not be implemented. Set a safe distance to reduce crosstalk and prevent the image quality of the display panel 110 from being affected.
  • the display panel 110 includes a plurality of data lines 130 and a plurality of gate lines 140.
  • the driving method includes a step of outputting a gate driving signal to a gate line corresponding to the display panel 110;
  • one signal period of the gate driving signal includes a sustain time, a first pull-down time, an open time, and a second pull-down time; the duration of the first pull-down time, the duration of the turn-on time, and the duration of the second pull-down time are all equal;
  • the gate drive signal is at the first low level during the maintenance time; at the high level during the open time; at the second low level during the first pull-down time and the second pull-down time; the second low level
  • the voltage value is lower than the voltage value of the first low level.
  • one cycle of each gate drive signal includes four time periods, namely the sustain time, the first pull-down time, The turn-on time and the second pull-down time, the turn-on time is between the first pull-down time and the second pull-down time, and the duration of the three is the same.
  • the voltage value of the second low level corresponding to the first pull-down time and the second pull-down time is equal to and lower than the voltage value of the first low level of the maintenance time, which can form a correct loop and eliminate the phenomenon that the voltage of the original pixel 150 is charged back (kickback) , Reduce or even eliminate the flicker problem of LCD display.
  • a driving circuit 120 As shown in FIG. 7, as another embodiment of the present application, a driving circuit 120 is disclosed.
  • the driving circuit 120 drives any display panel 110 as described above.
  • the driving circuit 120 includes:
  • the gate driving circuit 121 outputs a gate driving signal to the gate line corresponding to the display panel 110;
  • one signal period of the gate driving signal includes a sustain time, a first pull-down time, an open time, and a second pull-down time; the duration of the first pull-down time, the duration of the turn-on time, and the duration of the second pull-down time are all equal;
  • the gate drive signal is at the first low level during the maintenance time; at the high level during the on time; at the second low level during the first pull-down time and the second pull-down time; the voltage at the second low level The value is lower than the voltage value of the first low level.
  • a driving circuit 120 is provided to drive the display panel 110 of the present application.
  • the gate driving circuit 121 in the driving circuit 120 outputs a signal to the corresponding gate line of the display panel 110, and outputs a corresponding signal to turn on the corresponding gate line.
  • the gate drive signal of the previous gate line corresponds to the on time
  • the gate drive signal of the current gate line corresponds to the first pull-down time
  • the gate drive signal of the previous gate line When corresponding to the second pull-down time, the gate drive signal of the current gate line corresponds to the turn-on time
  • the gate drive signal cycle is divided into four time periods, namely the sustain time, the first pull-down time, the turn-on time and The second pull-down time, the turn-on time is between the first pull-down time and the second pull-down time, and the durations of the three are the same.
  • the voltage value of the second low level corresponding to the first pull-down time corresponds to the second pull-down time
  • the voltage value of the third low level is equal to and lower than the voltage value of the first low level of the maintenance time, forming a correct loop to solve the flicker problem caused by the reverse voltage.
  • a display device 100 which includes the above-mentioned display panel 110 and a driving circuit 120.
  • the technical solution of this application can be widely used in various display panels, such as TN-type display panels (the full name is Twisted Nematic, that is, twisted nematic panels), IPS-type display panels (In-Plane Switching), and VA-type displays Panel (Vertical Alignment, vertical alignment technology), MVA type display panel (Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology), of course, can also be other types of display panels, such as organic light-emitting diodes , Referred to as OLED display panel), all of the above solutions are applicable.
  • TN-type display panels the full name is Twisted Nematic, that is, twisted nematic panels
  • IPS-type display panels In-Plane Switching
  • VA-type displays Panel Very Alignment, vertical alignment technology
  • MVA type display panel Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology
  • OLED display panel organic light-emitting diodes

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Abstract

一种显示面板（110）、驱动方法和驱动电路（120），显示面板（110）包括多条数据线（130）、多条栅极线（140），栅极线（140）与数据线（130）互相交错；显示面板（110）还包括多个像素（150），分别由对应的栅极线（140）和数据线（130）驱动，每个像素（150）包括一个对应的像素电极；像素（150）的像素电极与相邻的另一栅极线（140）重叠，形成重叠区。

Description

显示面板、驱动方法和驱动电路
本申请要求于2019年1月30日提交中国专利局，申请号为CN201910089178.0，申请名称为“一种显示面板、驱动方法和驱动电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板、驱动方法和驱动电路。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着科技的发展和进步，平板显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。平板显示器包括薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等。其中，薄膜晶体管液晶显示器通过控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面，具有机身薄、省电、无辐射等众多优点。而有机发光二极管显示器是利用有机电致发光二极管制成，具有自发光、响应时间短、清晰度与对比度高、可实现柔性显示与大面积全色显示等诸多优点。
在一般液晶显示器的使用中，显示画面的清晰度以及稳定性，常受到驱动电压的影响，导致清晰度下降，画面的稳定性下降，经常会产生一些闪烁。
技术解决方案
本申请提供了一种减少甚至消除因寄生电容对液晶电容和存储电容的再分配作用而导致显示面板产生闪烁的现象的显示面板、驱动方法和驱动电路。
为实现上述目的，本申请提供了一种显示面板，包括多条数据线、多条栅极线和多个像素，栅极线与数据线互相交错形成的多个像素；每个像素由对应的栅极线和数据线进行驱动，每个像素包括一个对应的像素电极；其中，所述像素的像素电极与相邻的另一栅极线重叠，形成重叠区。
可选的，所述栅极线包括相互导通的主栅极线和辅栅极线，所述主栅极线与所述数据线交叉设置.
可选的，所述辅栅极线与所述数据线平行设置。
可选的，同一栅极线连接相邻的两个像素为一像素组，所述像素组包括与不同的数据线连接的第一像素和第二像素；其中，所述像素组的第一像素的像素电极与上一栅极线重叠， 形成第一重叠区；所述像素组的第二像素的像素电极与下一栅极线重叠，形成第二重叠区。
可选的，所述辅栅极线包括第一辅栅极线和第二辅栅极线，所述第一辅栅极线与上一栅极线对应的第二像素的像素电极形成第一重叠区，所述第二辅栅极线与所述下一栅极线对应的第一像素的像素电极形成第二重叠区。
可选的，所述同一数据线连接相邻的两个像素为一个像素组，所述像素组包括与不同的栅极线连接的第一像素和第二像素；其中，所述像素组的第一像素的像素电极与上一栅极线重叠，形成第一重叠区；所述像素组的第二像素的像素电极与下一栅极线重叠，形成第二重叠区。
可选的，所述同一数据线连接相邻的两个像素为一个像素组，所述像素组包括与不同的栅极线连接的第一像素和第二像素；所述第一像素连接的栅极线为第一栅极线，所述第一栅极线包括第一主栅极线和第一辅栅极线，所述第二像素连接的栅极线为第二栅极线，所述第二栅极线包括第二主栅极线和第二辅栅极线；所述第一辅栅极线与所述第二主栅极线对应的第二像素的像素电极形成第一重叠区，所述第二辅栅极线与所述第一主栅极线对应的第一像素的像素电极形成第二重叠区。
可选的，所述辅栅极线与当前主栅极线对应的第一像素的像素电极之间以及上一主栅极线对应的第二像素的像素电极之间都设有第一安全距离。
可选的，所述辅栅极线与对应的数据线之间设有第二安全距离。
本申请还公开了一种驱动方法，应用于如上任一所述的显示面板，所述显示面板包括由多条数据线和多条栅极线互相交错形成的多个像素；
所述驱动方法包括输出栅极驱动信号给所述显示面板对应的栅极线的步骤；
其中，所述栅极驱动信号的一个信号周期包括维持时间、第一下拉时间、打开时间和第二下拉时间；所述第一下拉时间的时长和打开时间的时长以及第二下拉时间的时长都相等；所述的栅极驱动信号在维持时间内为第一低电平；在打开时间为高电平；在第一下拉时间内和第二下拉时间内为第二低电平；所述第二低电平的电压值低于所述的第一低电平的电压值。
可选的，所述第一下拉时间位于所述打开时间之前，所述栅极驱动信号的一个信号周期还包括位于打开时间之后的第二下拉时间；所述栅极驱动信号在第二下拉时间内为第三低电平；所述第三低电平的电压值低于所述的第一低电平的电压值。
可选的，所述第一下拉时间和所述打开时间时长相等；在上一栅极线的栅极驱动信号对应于所述打开时间时，所述的当前栅极线的栅极驱动信号对应于第一下拉时间内。
可选的，所述打开时间和所述第二下拉时间时长相等；在上一栅极线的栅极驱动信号对应于第二下拉时间时，当前栅极线的栅极驱动信号对应于所述打开时间。
可选的，所述第二低电平的电压值和所述第三低电平的电压值相等。
可选的，所述每个像素包括一个像素电极，同一栅极线连接相邻的两个像素为一像素组，所述像素组包括与不同的数据线连接的第一像素和第二像素；其中，所述像素组的第一像素的像素电极与上一栅极线重叠，形成第一重叠区；所述第一重叠区的面积为S1，所述第一像素的第一重叠区与上一栅极线重叠形成的存储电容为Cst1，所述第一像素的像素电容为Clc1，所述第一像素的像素电极与当前栅线形成的寄生电容为Cgs1；所述第一低电平和所述第三低电平的电压值为V’GL，所述高电平的电压值为VGH，所述第二低电平的电压值为VGL；Cst1＝(VGH-VGL)*Cgs1/(VGL-V’GL)。
可选的，所述每个像素包括一个像素电极，同一栅极线连接相邻的两个像素为一像素组，所述像素组包括与不同的数据线连接的第一像素和第二像素；所述像素组的第二像素的像素电极与下一栅极线重叠，形成第二重叠区；所述第二重叠区的面积为S2，所述第二像素的第二重叠区与下一栅极线重叠形成的存储电容为Cst2，所述第二像素的像素电容为Clc2，所述第二像素的像素电极与当前栅线形成的寄生电容为Cgs2；所述第一低电平和所述第三低电平的电压值为V’GL，所述高电平的电压值为VGH，所述第二低电平的电压值为VGL；Cst2＝(VGH-VGL)*Cgs2/(VGL-V’GL)。
本申请还公开了一种驱动电路，所述驱动电路驱动如上任一所述的显示面板，所述驱动电路包括：栅极驱动电路，输出栅极驱动信号给所述显示面板对应的栅极线；其中，所述栅极驱动信号的一个信号周期包括维持时间、第一下拉时间、打开时间和第二下拉时间；所述第一下拉时间的时长和打开时间的时长以及第二下拉时间的时长都相等；所述的栅极驱动信号在维持时间内为第一低电平；在打开时间为高电平；在第一下拉时间内和第二下拉时间内为第二低电平；所述第二低电平的电压值低于所述的第一低电平的电压值。
可选的，所述第一下拉时间和所述打开时间时长相等；在上一栅极线的栅极驱动信号对应于所述打开时间时，所述的当前栅极线的栅极驱动信号对应于第一下拉时间内。
可选的，所述打开时间和所述第二下拉时间时长相等；在上一栅极线的栅极驱动信号对应于第二下拉时间时，当前栅极线的栅极驱动信号对应于所述打开时间。
相对于当前栅极线对应的像素的像素电极与当前栅极线形成存储电容的的方案来说，本申请多条数据线与多条栅极线互相交错形成多个像素，每个像素都包括一个像素电极，像素电极与栅极线容易形成寄生电容，为了避免寄生电容产生较大的影响，我们增大了像素电极与栅极线形成的存储电容，当前栅极线对应的像素电极与相邻的另一栅极线重叠，形成重叠区，加大存储电容，减少甚至消除因寄生电容对液晶电容和存储电容的再分配作用而导致显示面板产生闪烁的现象。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请的一实施例的一种像素结构的示意图；
图2是本申请的一实施例的像素结构电路的示意图；
图3是本申请的一实施例的像素结构的示意图；
图4是本申请的另一实施例的一种像素结构的示意图；
图5是本申请的另一实施例的像素结构的示意图；
图6是本申请的另一实施例的驱动波形的示意图；
图7是本申请的另一实施例的驱动电路的示意图；
图8是本申请的另一实施例的显示装置的示意图。
具体实施方式
需要理解的是，这里所使用的术语、公开的具体结构和功能细节，仅仅是为了描述具体实施例，是代表性的，但是本申请可以通过许多替换形式来具体实现，不应被解释成仅受限于这里所阐述的实施例。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示相对重要性，或者隐含指明所指示的技术特征的数量。由此，除非另有说明，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征；“多个”的含义是两个或两个以上。术语“包括”及其任何变形，意为不排他的包含，可能存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
另外，“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系的术语，是基于附图所示的方位或相对位置关系描述的，仅是为了便于描述本申请的简化描述，而不是指示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
下面参考附图和可选的实施例对本申请作进一步说明。
如图1至图5所示，本申请实施例公布了一种显示面板110，包括多条数据线130、和 多条栅极线140和多个像素150，栅极线140和数据线130互相交错；每个像素150互相交错形成的多个像素150分别由对应的数据线130和栅极线140驱动，每个像素150包括对应的像素电极；其中，像素150的像素电极与相邻的另一栅极线140重叠，形成重叠区。
如图1所示，当前栅极线140对应像素150，与当前栅极线140相邻的栅极线140称为另一栅极线140，像素150的像素电极与另一栅极线140重叠，形成重叠区。
本方案中，多条数据线130与多条栅极线140互相交错形成多个像素150，每个像素150都包括一个像素电极，像素电极与栅极线140容易形成寄生电容，为了避免寄生电容产生较大的影响，我们增大了像素电极与栅极线140形成的存储电容，参考图2的电路所示当前栅极线140对应的像素电极与相邻的另一栅极线140重叠，形成重叠区，加大存储电容，减少甚至消除因寄生电容对液晶电容和存储电容的再分配作用而导致显示面板110产生闪烁的现象。
在一实施例中，栅极线140包括相互导通的主栅极线141和辅栅极线142，主栅极线141与数据线130交叉设置，辅栅极线142与数据线130平行设置。
本方案中，栅极线140分为主栅极线141和辅栅极线142，主栅极线141与数据线130交错设置，增加的辅栅极线142与数据线130平行，且主栅极线141与辅栅极线142相互导通，可以减少数据线130对像素电极电压的影响，造成所谓的串扰从而影响画质，另外也可以减少主栅极线141与像素电极产生的寄生电容所带来的对显示面板110造成显示闪烁的影响。
在一实施例中，如图3所示，同一栅极线140连接相邻的两个像素150为一像素组160，像素组160包括与不同的数据线130连接的第一像素161和第二像素162；其中，像素组160的第一像素161的像素电极与上一栅极线140重叠，形成第一重叠区170；像素组160的第二像素162的像素电极与下一栅极线140重叠，形成第二重叠区180。
本方案中，像素组160内的两个像素150分别对应不同的数据线130，能够更好保证每个像素150的数据驱动电压的大小，防止像素电极本身的负载导致数据电压的降低，另外像素组160内的不同像素150的像素电极分别与上一栅极线140和下一栅极线140重叠，形成两个不同的存储电容，加大存储电容，可以减少像素电极与栅极线140产生的寄生电容的影响，减少甚至消除寄生电容对液晶电容和存储电容的再分配作用而导致显示面板110产生闪烁的问题，还可以降低开口率，提高液晶分子的穿透率，实现大视角色偏。
在一实施例中，如图3所示，辅栅极线142包括第一辅栅极线144和第二辅栅极线143，第一辅栅极线144与上一栅极线140对应的第二像素162的像素电极形成第二重叠区180，第二辅栅极线143与下一栅极线140对应的第一像素161的像素电极形成第一重叠区170。本方案中，由主栅极线141延伸出来的辅栅极线142与像素组160形成重叠区，辅栅极线 142可以具备屏蔽电场的效果，减少了电场形成于像素电极与数据线130之间。
如图4所示，同一数据线130连接相邻的两个像素150为一个像素组160，像素组160包括与不同的栅极线140连接的第一像素161和第二像素162；其中，像素组160的第一像素161的像素电极与上一栅极线140重叠，形成第一重叠区170；像素组160的第二像素162的像素电极与下一栅极线140重叠，形成第二重叠区180。第一重叠区的面积为S1，第一像素161的第一重叠区170与上一栅极线140重叠形成的存储电容为Cst1，第一像素161的像素电容为Clc1，第一像素161的像素电极与当前栅线形成的寄生电容为Cgs1；第一低电平和所述第三低电平的电压值为V’GL，高电平的电压值为VGH，第二低电平的电压值为VGL；
Cst1＝(VGH-VGL)*Cgs1/(VGL-V’GL)。
At①,，Vpixel＝Vdata
At②,，ΔV1＝ΔV’1+ΔV”1
ΔV’1＝(VGH-V’GL)*Cgs1/(Cgs+Cst+Clc)
ΔV”1＝(V’GL-VGH)*Cst1/(Cgs+Cst+Clc)
At③，ΔV2＝ΔV’2+ΔV”2
ΔV’2＝(V’GL-VGL)*Cgs1/(Cgs+Cst+Clc)
ΔV”2＝(VGH-V’GL)*Cst1/(Cgs+Cst+Clc)
At④，ΔV3＝(V’GL-VGL)*Cst1/(Cgs+Cst+Clc)
为了减少kickback造成闪烁，设置，Cst1＝(VGH-VGL)*Cgs1/(VGL-V’GL)，形成正确的回路，消除反向电压的影响，避免出现闪烁。
第二像素162的第二重叠区180与下一栅极线140重叠形成的存储电容为Cst2，第二像素162的像素电容为Clc2，第二像素162的像素电极与当前栅线形成的寄生电容为Cgs2；第一低电平和所述第三低电平的电压值为V’GL，高电平的电压值为VGH，第二低电平的电压值为VGL；
Cst2＝(VGH-VGL)*Cgs2/(VGL-V’GL)。
At①，Vpixel＝Vdata
At②，ΔV1＝ΔV’1+ΔV”1
ΔV’1＝(VGH-V’GL)*Cgs2/(Cgs+Cst+Clc)
ΔV”1＝(V’GL-VGL)*Cst2/(Cgs+Cst+Clc)
At③，ΔV2＝(V’GL-VGL)*Cgs2/(Cgs+Cst+Clc)
为了减少kickback造成闪烁，设置，Cst2＝(VGH-VGL)*Cgs1/(VGL-V’GL)，同样能形成正确的回路，消除反向电压的影响，避免出现闪烁，本方案中，同一数据线130连接相邻 的两个像素150为一个像素组160，输入相同的数据电压进行驱动，相邻的两个像素150分别于不同的栅极线140连接,减少负载带来的影响。
在一实施例中，同一数据线130连接相邻的两个像素150为一个像素组160，像素组160包括与不同的栅极线140连接的第一像素161和第二像素162；如图4所示，第一像素161连接的栅极线140为第一栅极线，第一栅极线包括第一主栅极线146和第一辅栅极线144，第二像素162连接的栅极线140为第二栅极线，第二栅极线包括第二主栅极线145和第二辅栅极线143；第一辅栅极线144与第二主栅极线145对应的第二像素162的像素电极形成第二重叠区180，第二辅栅极线143与第一主栅极线146对应的第一像素161的像素电极形成第一重叠区170。
本方案中，设置基于相邻两个像素150连接同一数据线130，不同的栅极线140的架构下，设置辅栅极线142，削弱了数据线130与像素电极形成的寄生电容。
在一实施例中，辅栅极线142与当前主栅极线141对应的第一像素161的像素电极之间以及上一主栅极线141对应的第二像素162的像素电极之间都设有第一安全距离。
本方案中，设置的第一安全距离的预设阈值，此预设阈值由本领域人员通过实验或者相关数据得出，在预设阈值内，方案是可行的，超过本预设阈值，本方案将无法实施，像素电极与辅栅极线142之间会产生电场，如果距离太近，产生的电场会比较强，从而会影响数据电压信号的传输，造成电压不稳而影响画面的显示，设置安全距离防止电场影响。
在一实施例中，辅栅极线142与对应的数据线130之间设有第二安全距离。
本方案中，辅栅极线142与数据线130平行设置，第二安全距离为一预设阈值，此预设阈值由本领域人员通过实验或者相关数据得出，在预设阈值内，方案是可行的，超过本预设阈值，本方案将无法实施，设置安全距离减少串扰现象，防止显示面板110的画质被影响，
如图1和图6所示，作为本申请的另一实施例，公开了一种驱动方法，应用于上述的显示面板110，显示面板110包括由多条数据线130和多条栅极线140互相交错形成的多个像素150；
驱动方法包括输出栅极驱动信号给显示面板110对应的栅极线的步骤；
其中，栅极驱动信号的一个信号周期包括维持时间、第一下拉时间、打开时间和第二下拉时间；第一下拉时间的时长和打开时间的时长以及第二下拉时间的时长都相等；的栅极驱动信号在维持时间内为第一低电平；在打开时间为高电平；在第一下拉时间内和第二下拉时间内为第二低电平；第二低电平的电压值低于的第一低电平的电压值。
本方案中，栅极线140跟像素电极存在寄生电容Cgs，当像素150充电后元件关闭时，栅极电压的变化透过寄生电容Cgs对于画素的液晶电容及储存电容电荷产生再分配作用，使得原像素150充电后的电压产生反向(kickback)的现象，为改善电压产生方向的现象，每 个栅极驱动信号的一个周期包括四个时间段，分别是维持时间、第一下拉时间、打开时间和第二下拉时间，打开时间位于第一下拉时间和第二下拉时间之间，且三者的时长都相等，第一下拉时间对应的第二低电平的电压值和第二下拉时间对应的第三低电平的电压值相等且低于维持时间的第一低电平的电压值，能够形成正确的回路，消除原像素150充电后的电压产生反向(kickback)的现象，减少甚至消除液晶显示的闪烁问题。
如图7所示，作为本申请的另一实施例，公开了一种驱动电路120，驱动电路120驱动如上任意的显示面板110，驱动电路120包括：
栅极驱动电路121，输出栅极驱动信号给显示面板110对应的栅极线；
其中，栅极驱动信号的一个信号周期包括维持时间、第一下拉时间、打开时间和第二下拉时间；第一下拉时间的时长和打开时间的时长以及第二下拉时间的时长都相等；栅极驱动信号在维持时间内为第一低电平；在打开时间为高电平；在第一下拉时间内和第二下拉时间内为第二低电平；第二低电平的电压值低于的第一低电平的电压值。
本方案中，设置驱动电路120驱动本申请的显示面板110，驱动电路120中的栅极驱动电路121输出信号给显示面板110对应的栅极线，输出相应的信号开启对应的栅极线，在上一栅极线的栅极驱动信号对应于所述打开时间时，所述的当前栅极线的栅极驱动信号对应于第一下拉时间内；在上一栅极线的栅极驱动信号对应于第二下拉时间时，当前栅极线的栅极驱动信号对应于所述打开时间；栅极驱动信号周期分为四个时间段，分别是维持时间、第一下拉时间、打开时间和第二下拉时间，打开时间位于第一下拉时间和第二下拉时间之间，且三者的时长都相等，第一下拉时间对应的第二低电平的电压值和第二下拉时间对应的第三低电平的电压值相等且低于维持时间的第一低电平的电压值，形成正确的回路，解决反向电压带来的闪烁问题。
如图8所示，作为本申请的另一实施例，公开了一种显示装置100，包括上述显示面板110及驱动电路120。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的技术方案可以广泛用于各种显示面板，如TN型显示面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS型显示面板(In-Plane Switching，平面转换)、VA型显示面板(Vertical Alignment，垂直配向技术)、MVA型显示面板(Multi-domain Vertical Alignment，多象限垂直配向技术)，当然，也可以是其他类型的显示面板，如有机发光显示面板(organic light-emitting diode，简称OLED显示面板)，均可适用上述方案。
以上内容是结合具体的可选实施方式对本申请所作的进一步详细说明，不能认定本申请 的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (19)

  1. 一种显示面板，包括：
    多条数据线；
    多条栅极线，所述栅极线和所述数据线互相交错；以及
    多个像素，分别由对应的数据线和栅极线驱动，所述每个像素包括一个对应的像素电极；
    其中，所述像素的像素电极与相邻的另一栅极线重叠，形成重叠区。
  2. 如权利要求1所述的一种显示面板，其中，所述栅极线包括相互导通的主栅极线和辅栅极线，所述主栅极线与所述数据线交叉设置。
  3. 如权利要求2所述的一种显示面板，其中，所述辅栅极线与所述数据线平行设置。
  4. 如权利要求3所述的一种显示面板，其中，同一栅极线连接相邻的两个像素为一像素组，所述像素组包括与不同的数据线连接的第一像素和第二像素；
    其中，所述像素组的第一像素的像素电极与上一栅极线重叠，形成第一重叠区；所述像素组的第二像素的像素电极与下一栅极线重叠，形成第二重叠区。
  5. 如权利要求3所述的一种显示面板，其中，所述辅栅极线包括第一辅栅极线和第二辅栅极线，所述第一辅栅极线与上一栅极线对应的第二像素的像素电极形成第一重叠区，所述第二辅栅极线与所述下一栅极线对应的第一像素的像素电极形成第二重叠区。
  6. 如权利要求3所述的一种显示面板，其中，所述同一数据线连接相邻的两个像素为一个像素组，所述像素组包括与不同的栅极线连接的第一像素和第二像素；
    其中，所述像素组的第一像素的像素电极与上一栅极线重叠，形成第一重叠区；所述像素组的第二像素的像素电极与下一栅极线重叠，形成第二重叠区。
  7. 如权利要求6所述的一种显示面板，其中，所述同一数据线连接相邻的两个像素为一个像素组，所述像素组包括与不同的栅极线连接的第一像素和第二像素；
    所述第一像素连接的栅极线为第一栅极线，所述第一栅极线包括第一主栅极线和第一辅栅极线，所述第二像素连接的栅极线为第二栅极线，所述第二栅极线包括第二主栅极线和第二辅栅极线；
    所述第一辅栅极线与所述第二主栅极线对应的第二像素的像素电极形成第一重叠区，所述第二辅栅极线与所述第一主栅极线对应的第一像素的像素电极形成第二重叠区。
  8. 如权利要求3所述的一种显示面板，其中，所述辅栅极线与当前主栅极线对应的第一像素的像素电极之间以及上一主栅极线对应的第二像素的像素电极之间都设有第一安全距离。
  9. 如权利要求3所述的一种显示面板，其中，所述辅栅极线与对应的数据线之间设有 第二安全距离。
  10. 一种驱动方法，应用于显示面板，所述显示面板包括：
    多条数据线；
    多条栅极线，所述栅极线和所述数据线互相交错；以及
    多个像素，分别由对应的数据线和栅极线驱动，所述每个像素包括对应的像素电极；
    所述驱动方法包括输出栅极驱动信号给所述显示面板对应的栅极线的步骤；
    其中，所述栅极驱动信号的一个信号周期包括维持时间、第一下拉时间、打开时间和第二下拉时间；所述第一下拉时间的时长和打开时间的时长以及第二下拉时间的时长都相等；所述的栅极驱动信号在维持时间内为第一低电平；在打开时间为高电平；在第一下拉时间内和第二下拉时间内为第二低电平；所述第二低电平的电压值低于所述的第一低电平的电压值。
  11. 如权利要求10所述的一种驱动方法，其中，所述第一下拉时间位于所述打开时间之前，所述栅极驱动信号的一个信号周期还包括位于打开时间之后的第二下拉时间；所述栅极驱动信号在第二下拉时间内为第三低电平；所述第三低电平的电压值低于所述的第一低电平的电压值。
  12. 如权利要求11所述的一种驱动方法，其中，所述第一下拉时间和所述打开时间时长相等；在上一栅极线的栅极驱动信号对应于所述打开时间时，所述的当前栅极线的栅极驱动信号对应于第一下拉时间内。
  13. 如权利要求12所述的一种驱动方法，其中，所述打开时间和所述第二下拉时间时长相等；在上一栅极线的栅极驱动信号对应于第二下拉时间时，当前栅极线的栅极驱动信号对应于所述打开时间。
  14. 如权利要求12所述的一种驱动方法，其中，所述第二低电平的电压值和所述第三低电平的电压值相等。
  15. 如权利要求13所述的一种驱动方法，其中，所述每个像素包括一个像素电极，同一栅极线连接相邻的两个像素为一像素组，所述像素组包括与不同的数据线连接的第一像素和第二像素；
    其中，所述像素组的第一像素的像素电极与上一栅极线重叠，形成第一重叠区；所述第一重叠区的面积为S1，所述第一像素的第一重叠区与上一栅极线重叠形成的存储电容为Cst1，所述第一像素的像素电容为Clc1，所述第一像素的像素电极与当前栅线形成的寄生电容为Cgs1；
    所述第一低电平和所述第三低电平的电压值为V’GL，所述高电平的电压值为VGH，所述第二低电平的电压值为VGL；
    Cst1＝(VGH-VGL)*Cgs1/(VGL-V’GL)。
  16. 如权利要求15所述的一种驱动方法，其中，所述每个像素包括一个像素电极，同一栅极线连接相邻的两个像素为一像素组，所述像素组包括与不同的数据线连接的第一像素和第二像素；
    所述像素组的第二像素的像素电极与下一栅极线重叠，形成第二重叠区；所述第二重叠区的面积为S2，所述第二像素的第二重叠区与下一栅极线重叠形成的存储电容为Cst2，所述第二像素的像素电容为Clc2，所述第二像素的像素电极与当前栅线形成的寄生电容为Cgs2；
    所述第一低电平和所述第三低电平的电压值为V’GL，所述高电平的电压值为VGH，所述第二低电平的电压值为VGL；
    Cst2＝(VGH-VGL)*Cgs2/(VGL-V’GL)。
  17. 一种驱动电路，所述驱动电路驱动所述的显示面板，所述显示面板包括：
    多条数据线；
    多条栅极线，所述栅极线和所述数据线互相交错；以及
    多个像素，分别由对应的数据线和栅极线驱动，所述每个像素包括对应的像素电极；
    其中，所述像素的像素电极与相邻的另一栅极线重叠，形成重叠区；
    所述驱动电路包括：
    栅极驱动电路，输出栅极驱动信号给所述显示面板对应的栅极线；
    其中，所述栅极驱动信号的一个信号周期包括维持时间、第一下拉时间、打开时间和第二下拉时间；所述第一下拉时间的时长和打开时间的时长以及第二下拉时间的时长都相等；所述的栅极驱动信号在维持时间内为第一低电平；在打开时间内为高电平；在第一下拉时间内和第二下拉时间内为第二低电平；所述第二低电平的电压值低于所述的第一低电平的电压值。
  18. 如权利要求17所述的一种驱动电路，其中，所述第一下拉时间和所述打开时间时长相等；在上一栅极线的栅极驱动信号对应于所述打开时间时，所述的当前栅极线的栅极驱动信号对应于第一下拉时间内。
  19. 如权利要求18所述的一种驱动电路，其中，所述打开时间和所述第二下拉时间时长相等；在上一栅极线的栅极驱动信号对应于第二下拉时间时，当前栅极线的栅极驱动信号对应于所述打开时间。
PCT/CN2019/075518 2019-01-30 2019-02-20 显示面板、驱动方法和驱动电路 Ceased WO2020155218A1 (zh)

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