WO2020155219A1 - 驱动方法、显示面板和驱动电路 - Google Patents

驱动方法、显示面板和驱动电路 Download PDF

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Publication number
WO2020155219A1
WO2020155219A1 PCT/CN2019/075520 CN2019075520W WO2020155219A1 WO 2020155219 A1 WO2020155219 A1 WO 2020155219A1 CN 2019075520 W CN2019075520 W CN 2019075520W WO 2020155219 A1 WO2020155219 A1 WO 2020155219A1
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Prior art keywords
pixel
line
time
common
gate
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PCT/CN2019/075520
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English (en)
French (fr)
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单剑锋
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惠科股份有限公司
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Priority to US16/461,371 priority Critical patent/US11341929B2/en
Publication of WO2020155219A1 publication Critical patent/WO2020155219A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0847—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • This application relates to the field of display technology, and in particular to a driving method, a display panel, and a driving circuit.
  • Flat panel displays include Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and Organic Light-Emitting Diode (OLED) displays.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • the thin film transistor liquid crystal display refracts the light from the backlight module to produce a picture by controlling the rotation direction of the liquid crystal molecules, and has many advantages such as thin body, power saving, and no radiation.
  • the organic light emitting diode display is made of organic electroluminescent diodes, and has many advantages such as self-luminescence, short response time, high definition and contrast, flexible display and large-area full-color display.
  • the present application provides a driving method, a display panel, and a driving circuit to reduce flicker caused by reverse voltage.
  • the present application provides a driving method applied to a display panel
  • the display panel includes: a plurality of data lines and a plurality of gate lines, the gate lines and the data lines are interlaced; and It includes a plurality of pixels, each pixel is driven by a corresponding data line and a gate line, and each pixel includes a corresponding pixel electrode; and a plurality of common lines, and a plurality of common lines are respectively arranged on the upper and lower gates Between the lines, the common line overlaps the pixel electrode of the pixel corresponding to the previous gate line; and overlaps the pixel electrode of the pixel corresponding to the next gate line; and the driving method includes outputting a gate driving signal to all The step of the gate line corresponding to the display panel; wherein one signal period of the common level signal of the common line includes a first time and a second time, the first time corresponds to the first common level, and the second The second time corresponds to the second common level; the voltage value of the first common level in the
  • the common line corresponding to the Nth gate line is turned on at the first time, and the corresponding Nth gate line is also turned on.
  • the starting time of the second time and the closing time of the N+1th gate line are the same time.
  • each pixel includes a pixel electrode, the same common line connects two adjacent pixels to form a pixel group, and the pixel group includes a first pixel and a second pixel, and the first pixel and the The second pixel is connected to different data lines and gate lines; wherein, the pixel electrode of the first pixel of the pixel group overlaps the common line to form a first overlap area; the first overlap area of the first pixel
  • the first storage capacitor formed with the common line is Cst1, the pixel capacitor of the first pixel is Clc1, and the parasitic capacitor formed by the pixel electrode of the first pixel and the Nth gate line is Cgs1;
  • the first common level corresponding to one time is Vcom
  • the second common level corresponding to the second time is V'com;
  • the high-level voltage value of the gate on time is VGH, and the gate is off
  • the low voltage value is VGL;
  • the pixel electrode of the second pixel of the pixel group overlaps the same common line corresponding to the first pixel to form a second overlap region; the second overlap region of the second pixel and the common line form a second overlap region.
  • the second storage capacitor is Cst2
  • the pixel capacitance of the second pixel is Clc2
  • the parasitic capacitance formed by the pixel electrode of the second pixel and the N+1th gate line is Cgs2;
  • Cst2 (VGH-VGL)*Cgs2 /(V'com-Vcom).
  • the present application discloses a display panel using the above-mentioned driving method.
  • the display panel includes a plurality of pixels, a plurality of data lines, and a plurality of gate lines.
  • the gate lines and the data lines are interlaced with each other, and each pixel has a corresponding The data line and the gate line are driven, and each pixel corresponds to a pixel electrode; and a plurality of common lines are arranged between the upper and lower gate lines; wherein, two pixels adjacent to the same common line are a pixel group ,
  • the pixel group includes a first pixel and a second pixel; the first pixel and the second pixel are connected to different data lines and gate lines; wherein the first pixel and the second pixel are
  • the pixel electrode overlaps the same common line to form a first overlap area and a second overlap area respectively.
  • the common line includes a main common line and an auxiliary common line that are connected to each other; the main common line is arranged to cross the data line, and the auxiliary common line is arranged parallel to the data line;
  • the common line overlaps the pixel electrode of the first pixel and the pixel electrode of the second pixel to form a first main overlap area and a second main overlap area respectively;
  • the auxiliary common line includes a first auxiliary common line and a second auxiliary common Line, the pixel electrode of the first pixel and the first auxiliary common line form a first auxiliary overlapping area, and the pixel electrode of the second pixel and the second auxiliary common line form a second auxiliary overlapping area.
  • first auxiliary common lines which are respectively arranged at positions close to the data line on both sides of the first pixel, and the two first auxiliary common lines overlap with the pixel electrode of the first pixel.
  • second auxiliary common lines which are respectively arranged on both sides of the second pixel near the data line, the two second auxiliary common lines and the pixel of the second pixel The electrodes all overlap, forming two overlapping areas.
  • the first auxiliary common line and the second auxiliary common line are a straight line.
  • the two second auxiliary common lines and the two first auxiliary common lines form two straight lines.
  • a first safety distance is provided between the first auxiliary common line and the pixel electrode of the first pixel.
  • a second safe distance is provided between the auxiliary common line and the corresponding data line.
  • the present application discloses a driving circuit for driving a display panel.
  • the display panel includes a plurality of data lines and a plurality of gate lines.
  • the gate lines and the data lines are interlaced with each other; and also includes a plurality of pixels, each The pixels are respectively driven by corresponding data lines and gate lines, and each pixel corresponds to a pixel electrode; and a plurality of common lines are respectively arranged between the upper and lower gate lines; among them, two adjacent ones of the same common line
  • Each pixel is a pixel group, and the pixel group includes a first pixel and a second pixel; the first pixel and the second pixel are connected to different data lines and gate lines; wherein the common line is connected to the upper
  • the pixel electrode of the first pixel corresponding to one gate line overlaps to form a first overlapping area; the common line overlaps with the pixel electrode of the second pixel corresponding to the next gate line to form a second overlapping area;
  • the driving circuit It includes: a gate driving
  • the common line corresponding to the Nth gate line is turned on at the first time, and the Nth gate line is also turned on.
  • the starting time of the second time and the closing time of the N+1th gate line are the same time.
  • each pixel includes a pixel electrode, the same common line connects two adjacent pixels to form a pixel group, and the pixel group includes a first pixel and a second pixel, and the first pixel and the The second pixel is connected to different data lines and gate lines; wherein, the pixel electrode of the first pixel of the pixel group overlaps the common line to form a first overlap area; the first overlap area of the first pixel
  • the first storage capacitor formed with the common line is Cst1, the pixel capacitor of the first pixel is Clc1, and the parasitic capacitor formed by the pixel electrode of the first pixel and the Nth gate line is Cgs1;
  • the first common level corresponding to one time is Vcom
  • the second common level corresponding to the second time is V'com;
  • the high-level voltage value of the gate on time is VGH, and the gate is off
  • the low voltage value is VGL;
  • the cycle time of the first time is three times the cycle time of one gate line.
  • the pixel electrode of the second pixel of the pixel group overlaps the same common line corresponding to the first pixel to form a second overlap region; the second overlap region of the second pixel and the common line form a second overlap region.
  • the second storage capacitor is Cst2
  • the pixel capacitance of the second pixel is Clc2
  • the parasitic capacitance formed by the pixel electrode of the second pixel and the N+1th gate line is Cgs2;
  • Cst2 (VGH-VGL)*Cgs2 /(V'com-Vcom).
  • the gate and the pixel electrode will generate parasitic capacitance Cgs, and the reverse voltage generated by the parasitic capacitance Cgs will redistribute the storage capacitor and the liquid crystal capacitor.
  • the same common line corresponds to the upper and lower gate lines.
  • Two pixels are respectively formed with storage capacitors Cst. When the corresponding n gate lines are turned off, the charging voltage of the pixel electrode will drop due to the influence of parasitic capacitance.
  • two different common levels are set.
  • the voltage value of the first common level in the first time is less than the voltage value of the second common level in the second time.
  • the common line changes from lower There is a rising edge from the first common level to the higher second common level, which will affect the charging voltage of the corresponding pixel, which can offset at least part of the drop; the storage capacitor can be increased as much as possible to reduce the reverse voltage formation Flicker, and increase the voltage maintenance rate to reduce the voltage drop of the pixel electrode, without sacrificing the transparent opening area, will not affect the panel transmittance, and will not increase the cost of the backlight.
  • FIG. 1 is a schematic diagram of a pixel structure circuit of one embodiment of the present application.
  • Fig. 2 is a schematic diagram of a driving waveform of one embodiment of the present application.
  • FIG. 3 is a schematic diagram of driving waveforms of one embodiment of the present application.
  • FIG. 4 is a schematic diagram of a driving waveform of another embodiment of the present application.
  • FIG. 5 is a schematic diagram of driving waveforms of another embodiment of the present application.
  • FIG. 6 is a schematic diagram of a pixel structure of another embodiment of the present application.
  • FIG. 7 is a schematic diagram of a pixel structure with auxiliary common lines according to another embodiment of the present application.
  • FIG. 8 is a schematic diagram of a display panel according to another embodiment of the present application.
  • FIG. 9 is a schematic diagram of a driving circuit of another embodiment of the present application.
  • FIG. 10 is a schematic diagram of a display device according to another embodiment of the present application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating relative importance or implicitly indicating the number of indicated technical features. Therefore, unless otherwise specified, a feature defined with “first” and “second” may explicitly or implicitly include one or more of these features; “plurality” means two or more.
  • the term “comprising” and any variations thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components, and/or combinations thereof may be present or added.
  • connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection , It can also be electrical connection; it can be directly connected, it can also be indirectly connected through an intermediate medium, or the internal connection of two components.
  • connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection , It can also be electrical connection; it can be directly connected, it can also be indirectly connected through an intermediate medium, or the internal connection of two components.
  • an embodiment of the present application discloses a driving method applied to a display panel 110.
  • the display panel 110 includes a display panel 110 including a plurality of data lines 130 and a plurality of gates.
  • Line 140, a plurality of pixels 150 and a plurality of common lines 190, the data line 130 and the gate line 140 are interlaced with each other;
  • each pixel 150 is driven by a corresponding data line 130 and gate line 140, and
  • each pixel 150 includes a corresponding Pixel electrodes, each common line 190 is respectively arranged between the upper and lower gate lines 140, the common line 190 overlaps with the pixel electrode of the pixel corresponding to the previous gate line; and the pixel of the pixel corresponding to the next gate line
  • the driving method includes the step of outputting a gate driving signal to the gate line 140 corresponding to the display panel 110; as shown in FIG.
  • a signal period of the common level signal of the common line 190 includes a first time and a second time ,
  • the first time corresponds to the first common level
  • the second time corresponds to the second common level
  • the voltage value of the first common level in the first time is less than the voltage value of the second common level in the second time
  • corresponding The common line 190 of the Nth gate line 140, the start time of the first time is no later than the opening time of the corresponding Nth gate line 140; the start time of the second time is no earlier than the N+1th gate
  • the closing moment of the polar line 140 is the first time and a second time .
  • the common voltage on the color filter substrate can be the level signal of any common line 190, that is, it can be the first common level or the second common level.
  • the gate and the pixel 150 The electrode generates a parasitic capacitance Cgs, and the reverse voltage generated by the parasitic capacitance Cgs redistributes the storage capacitance and the liquid crystal capacitance.
  • the same common line 190 corresponds to the upper and lower gate lines 140 and the two pixels 150 corresponding to the upper and lower gate lines 140 respectively form storage capacitors Cst. When the corresponding n gate lines 140 are turned off, the charging voltage of the pixel 150 electrode will drop ( ⁇ V) due to the influence of parasitic capacitance.
  • the common line 190 changes from the lower first common voltage.
  • Level to the higher second common level there is a rising edge, which will affect the charging voltage of the corresponding pixel 150, which can offset at least part of the drop ( ⁇ V); the storage capacitor can be increased as much as possible to reduce the reverse voltage formation Flicker, and increase the voltage maintenance rate to reduce the voltage dropped by the electrode of the pixel 150.
  • the common line 190 corresponding to the Nth gate line 140 is turned on for the first time, and the Nth gate line 140 is also turned on.
  • the common line 190 corresponding to the Nth gate line 140 is opened, the Nth gate line 140 is also opened.
  • the gate line 140 is opened, the parasitic capacitance will redistribute the reverse voltage.
  • the charging voltage of the electrode 150 will have a drop ( ⁇ V).
  • the common line 190 has the effect of shielding the electric field.
  • the electric field is formed between the electrode of the pixel 150 and the common line 190.
  • the opening of the common line 190 reduces the electric field formed on the electrode of the pixel 150 and the data. Between the lines 130, the storage capacitor is also increased to offset the drop ( ⁇ V).
  • the starting time of the second time and the closing time of the N+1th gate line 140 are the same time.
  • the turn-off time of the N+1th gate line 140 is also the start time of the second time.
  • the common line 190 changes from a lower first common level to a higher The second common level, which has a rising edge, will affect the charging voltage of the corresponding pixel 150, which can offset at least part of the drop ( ⁇ V); at the same time, it can also offset a part of the influence of signal fluctuations on the electrode of the pixel 150, so that the driving The voltage tends to be more stable.
  • each pixel 150 includes a pixel 150 electrode, the same common line 190 connects two adjacent pixels 150 to form a pixel group 160, and the pixel group 160 includes first pixels 161 connected to different data lines 130 And the second pixel 162; wherein the electrode of the pixel 150 of the first pixel 161 of the pixel group 160 overlaps the common line 190 to form a first overlap region 170; the first overlap region 170 of the first pixel 161 forms the first common line 190
  • the storage capacitor is Cst1, the pixel capacitor Clc1 of the first pixel 161, the parasitic capacitance formed by the pixel 150 electrode of the first pixel 161 and the current gate line is Cgs1; the first common level corresponding to the first time is Vcom, The second common level corresponding to the second time is V'com;
  • the pixel 150 electrode of the second pixel 162 of the pixel group 160 overlaps with the same common line 190 corresponding to the first pixel 161 to form a second overlap area 180; the second overlap area 180 of the second pixel 162 overlaps the common line 190
  • ⁇ V’1 (VGH-VGL)*Cgs2/(Cgs+Cst+Clc)
  • ⁇ V”1 (V’com-Vcom)*Cst2/(Cgs+Cst+Clc)
  • the period of the first time is three times the period of the turn-on time of one gate line 140.
  • the charging voltage of the electrode of the pixel 150 will drop ( ⁇ V), and the first turn-on period is when one gate line 140 is turned on. Three times the time period, close to or even completely offset ⁇ V, making the driving voltage of the pixel 150 more stable.
  • At3, ⁇ V2 (Vcom-V’com)*Cst2/(Cgs+Cst+Clc)
  • the present application also discloses a display panel 110 using the above driving method, which includes a plurality of data lines 130, a plurality of gate lines 140, a plurality of pixels 150, and a plurality of common lines 190.
  • the data lines 130 and the gate lines 140 are interleaved with each other.
  • Each pixel 150 is driven by the corresponding data line 130 and the gate line 140, and each pixel 150 corresponds to a pixel electrode; each common line 190 is arranged on the upper and lower gates.
  • the pixel group 160 includes a first pixel 161 and a second pixel 162; the first pixel 161 and the second pixel 162 have different data
  • the line 130 is connected to the gate line 140; wherein, the common line 190 overlaps with the pixel electrode of the first pixel 161 corresponding to the previous gate line 140 to form a first overlap region 170; the common line 190 corresponds to the next gate line 140
  • the pixel electrodes of the second pixel 162 overlap to form a second overlap area 180. .
  • the two pixels 150 corresponding to the same common line 190 corresponding to the upper and lower gate lines 140 are respectively formed with storage capacitors. Both sides of the common line 190 can have the effect of shielding the electric field.
  • the electric field is formed on the electrode of the pixel 150 and the common line.
  • this pixel 150 design makes it possible to realize the above-mentioned driving method, reduce or even eliminate the redistribution effect of parasitic capacitance on the liquid crystal capacitance and storage capacitance, which causes the display panel 110 to flicker. Increase the aperture ratio, improve the penetration rate of liquid crystal molecules, and achieve large visual role deviation.
  • the common line 190 includes a main common line 200 and an auxiliary common line 210 that are connected to each other.
  • the main common line 200 and the data line 130 are arranged to cross each other, and the auxiliary common line 210 and the data line 130 are arranged in parallel. It overlaps the pixel 150 electrode of the first pixel 161 and the pixel 150 electrode of the second pixel 162 to form a first main overlap area 220 and a second main overlap area 230, respectively.
  • the auxiliary common line 210 includes a first auxiliary common line 240 and a second auxiliary common line 240.
  • the auxiliary common line 250, the pixel 150 electrode of the first pixel 161 and the first auxiliary common line 240 form a first auxiliary overlapping area 260, and the pixel 150 electrode of the second pixel 162 and the second auxiliary common line 250 form a second auxiliary overlapping area 270 .
  • the common line 190 is divided into a main common line 200 and an auxiliary common line 210.
  • the main common line 200 and the data line 130 are alternately arranged, the added auxiliary common line 210 is parallel to the data line 130, and the main common line 200 is parallel to the auxiliary common line.
  • the interconnection of the lines 210 can reduce the influence of the electrodes of the pixel 150 on the voltage on the data line 130, causing so-called crosstalk and thus affecting the image quality. In addition, it can also reduce the interference caused by the parasitic capacitance generated by the gate line 140 and the electrode of the pixel 150.
  • the display panel 110 causes the influence of display flicker.
  • first auxiliary common line 240 and the second auxiliary common line 250 are a straight line.
  • first auxiliary common line 240 and the second auxiliary common line 250 are a straight line, which is more convenient and time-saving in the manufacturing process.
  • first auxiliary common lines 240 which are respectively arranged on both sides of the first pixel 161 near the data line 130.
  • the two first auxiliary common lines 240 and the pixel 150 electrode of the first pixel 161 Are overlapped to form two overlapping areas;
  • there are two second auxiliary common lines 250 which are respectively arranged on both sides of the second pixel 162 near the data line 130.
  • the two second auxiliary common lines 250 and the second pixel 162 The electrodes of the pixels 150 overlap to form two overlapping regions; the two second auxiliary common lines 250 and the two first auxiliary common lines 240 form two straight lines.
  • both sides of the common common line 190 can have the effect of shielding the electric field.
  • the electric field is formed between the electrode of the pixel 150 and the common line 190, which reduces the formation of the electric field between the electrode of the pixel 150 and the data line 130.
  • the gate electrode and the electrode of the pixel 150 are prone to generate parasitic capacitance Cgs.
  • the reverse voltage generated by the parasitic capacitance Cgs will redistribute the storage capacitor and the liquid crystal capacitor.
  • This application uses the pixel The space on both sides of the electrode 150 forms a storage capacitor Cst.
  • the two pixels 150 in the pixel group 160 correspond to different data lines 130, which better guarantees the data driving voltage of each pixel 150 and prevents the load of the pixel 150 electrode itself from causing data With the decrease of the voltage, an electric field is formed between the electrode of the pixel 150 and the gate line 140.
  • the auxiliary common line 210 is provided on both sides of the first pixel 161 and the second pixel 162, and is connected to the pixels of the first pixel 161 and the second pixel 162.
  • the 150 electrodes all form an overlapping area to increase the storage capacitance and increase the pixel openings to increase the light output of the liquid crystal display.
  • a first safety distance is provided between the first auxiliary common line 240 and the pixel 150 electrode of the first pixel 161; a second safety distance is provided between the auxiliary common line 210 and the corresponding data line 130.
  • an electric field will be generated between the electrode of the pixel 150 and the auxiliary common line 210. If the distance is too close, the generated electric field will be relatively strong, which will affect the transmission of the data voltage signal, causing voltage instability and affecting the display of the screen.
  • the safety distance prevents the influence of the electric field, reduces the crosstalk phenomenon, and prevents the image quality of the display panel 110 from being affected.
  • a driving circuit 120 drives the above-mentioned display panel 110.
  • the driving circuit 120 includes: a gate driving circuit 121, which outputs a gate driving signal to the gate line 140 corresponding to the display panel 110; wherein, the common line A signal period of the common level signal of 190 includes a first time and a second time.
  • the first time corresponds to the first common level
  • the second time corresponds to the second common level; the first common level in the first time
  • the voltage value is less than the voltage value of the second common level in the second time;
  • the common line 190 corresponding to the Nth gate line 140 is turned on at the first time no later than the corresponding Nth gate line 140 is turned on; second The opening time is later than the closing time of the N+1th gate line.
  • the driving circuit 120 is used to drive the display panel 110, and the gate driving circuit 121 in the driving circuit 120 outputs a signal to the gate line 140 corresponding to the display panel 110, and outputs a corresponding signal to turn on the corresponding gate line 140.
  • the electrode driving signal cycle is divided into three time periods, which output different levels respectively. Because of the influence of the reverse voltage caused by the parasitic capacitance generated by the pixel 150 electrode and the gate line 140, the voltage pull-down time is set in different time periods to form The correct circuit can solve the flicker caused by reverse voltage.
  • a display device 100 including the above-mentioned display panel 110 and a driving circuit 120, and the driving circuit 120 drives the display panel 110.
  • the technical solution of this application can be widely used in various display panels, such as TN-type display panels (the full name is Twisted Nematic, that is, twisted nematic panels), IPS-type display panels (In-Plane Switching), and VA-type displays Panel (Vertical Alignment, vertical alignment technology), MVA type display panel (Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology), of course, can also be other types of display panels, such as organic light-emitting diodes , Referred to as OLED display panel), all of the above solutions are applicable.
  • TN-type display panels the full name is Twisted Nematic, that is, twisted nematic panels
  • IPS-type display panels In-Plane Switching
  • VA-type displays Panel Very Alignment, vertical alignment technology
  • MVA type display panel Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology
  • OLED display panel organic light-emitting diodes

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Abstract

一种驱动方法、显示面板和驱动电路，驱动方法包括输出栅极驱动信号给对应栅极线的步骤；公共线的公共电平信号的一个信号周期包括第一时间和第二时间，第一时间对应第一公共电平，第二时间对应第二公共电平；第一公共电平的电压值小于第二公共电平；对应第N条栅极线的公共线，第一时间起始时刻不晚于对应第N条栅极线打开时刻；第二时间起始时刻不早于第N+1条栅极线关闭时刻。

Description

驱动方法、显示面板和驱动电路
本申请要求于2019年1月30日提交中国专利局，申请号为CN201910089177.6，申请名称为“一种驱动方法、显示面板和驱动电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种驱动方法、显示面板和驱动电路。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着科技的发展和进步，平板显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。平板显示器包括薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等。其中，薄膜晶体管液晶显示器通过控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面，具有机身薄、省电、无辐射等众多优点。而有机发光二极管显示器是利用有机电致发光二极管制成，具有自发光、响应时间短、清晰度与对比度高、可实现柔性显示与大面积全色显示等诸多优点。
在一般液晶显示器的使用中，像素电压的变化通常会导致闪烁，影响显示效果。
申请内容
本申请提供一种驱动方法、显示面板和驱动电路，以减少反向电压形成的闪烁。
为实现上述目的，本申请提供了一种驱动方法，应用于显示面板，所述显示面板包括：多条数据线和多条栅极线,所述栅极线和所述数据线互相交错；还包括多个像素，每个像素分别由对应的数据线和栅极线驱动，所述每个像素包括对应的像素电极；以及多条公共线，多条公共线，分别设置在上下两条栅极线之间，所述公共线与上一条栅极线对应的像素的像素电极重叠；并与下一条栅极线对应的像素的像素电极重叠；；所述驱动方法包括输出栅极驱动信号给所述显示面板对应的栅极线的步骤；其中，所述公共线的公共电平信号的一个信号周期包括第一时间和第二时间，所述第一时间对应第一公共电平，所述第二时间对应第二公共电平；所述第一时间内的第一公共电平的电压值小于所述第二时间内的第二公共电平的电压值；对应第N条栅极线的公共线，所述第一时间的起始时刻不晚于对应的第N条栅极线打开时刻；所述第二时间的起始时刻不早于所述第N+1条栅极线的关闭时刻；N为大于等于1的自然数。
可选的，在同一时刻，对应第N条栅极线的公共线在所述第一时间打开，对应的第N条栅极线也打开。
可选的，所述第二时间的起始时刻与所述第N+1条栅极线的关闭时刻为同一时刻。
可选的，所述每个像素包括一个像素电极，同一公共线连接相邻的两个像素为一像素组，所述像素组包括第一像素和第二像素，所述第一像素和所述第二像素与不同的数据线和栅极线连接；其中，所述像素组的第一像素的像素电极与所述公共线重叠，形成第一重叠区；所述第一像素的第一重叠区与所述公共线形成的第一存储电容为Cst1，所述第一像素的像素电容为Clc1，所述第一像素的像素电极与第N条栅极线形成的寄生电容为Cgs1；所述第一时间对应的第一公共电平为Vcom，所述第二时间对应的第二公共电平为V’com；所述栅极开启时间的高电平的电压值为VGH，所述栅极关闭低电平的电压值为VGL；
Cst1＝(VGH-VGL)*Cgs1/(V’com-Vcom)。
可选的，所述像素组的第二像素的像素电极与第一像素对应的同一公共线重叠，形成第二重叠区；所述第二像素的第二重叠区与所述公共线形成的第二存储电容为Cst2，所述第二像素的像素电容为Clc2，所述第二像素的像素电极与第N+1条栅极线形成的寄生电容为Cgs2；Cst2＝(VGH-VGL)*Cgs2/(V’com-Vcom)。
本申请公开了一种使用上述驱动方法的显示面板，包括多个像素、多条数据线和多条栅极线，所述栅极线和所述数据线互相交错，每个像素分别由对应的数据线和栅极线驱动，所述每个像素对应一个像素电极；以及多条公共线，设置在上下两条栅极线之间；其中，同一公共线相邻的两个像素为一个像素组，所述像素组包括第一像素和第二像素；所述第一像素和所述第二像素与不同的数据线和栅极线连接；其中，所述第一像素和所述第二像素的像素电极与同一公共线重叠，分别形成第一重叠区和第二重叠区。
可选的，所述公共线包括相互导通的主公共线和辅公共线；所述主公共线与所述数据线交叉设置，所述辅公共线与所述数据线平行设置；所述主公共线与所述第一像素的像素电极以及第二像素的像素电极重叠，分别形成第一主重叠区和第二主重叠区；所述辅公共线包括第一辅公共线和第二辅公共线，所述第一像素的像素电极与所述第一辅公共线形成第一辅重叠区，所述第二像素的像素电极与所述第二辅公共线形成第二辅重叠区。
可选的，所述第一辅公共线为两条，分别设置在所述第一像素的两侧靠近数据线的位置，两条第一辅公共线与所述第一像素的像素电极都重叠，形成两个重叠区；所述第二辅公共线为两条，分别设置在所述第二像素的两侧靠近数据线的位置，两条第二辅公共线与所述第二像素的像素电极都重叠，形成两个重叠区。
可选的，所述第一辅公共线与第二辅公共线为一条直线。
可选的，两条所述第二辅助公共线与两条所述第一辅公共线形成两条直线。
可选的，所述第一辅公共线与所述第一像素的像素电极之间设有第一安全距离。
可选的，所述辅公共线与对应的数据线之间设有第二安全距离。
本申请公开了一种驱动电路，驱动显示面板，所述显示面板包括多条数据线和多条栅极线，所述栅极线和所述数据线互相交错；还包括多个像素，每个像素分别由对应的数据线和栅极线驱动，所述每个像素对应一个像素电极；以及多条公共线，分别设置在上下两条栅极线之间；其中，同一公共线相邻的两个像素为一个像素组，所述像素组包括第一像素和第二像素；所述第一像素和所述第二像素与不同的数据线和栅极线连接；其中，所述公共线与上一条栅极线对应的第一像素的像素电极重叠，形成第一重叠区；所述公共线与下一条栅极线对应的第二像素的像素电极重叠，形成第二重叠区；所述驱动电路包括：栅极驱动电路，输出栅极驱动信号给所述显示面板对应的栅极线；其中，所述公共线的公共电平信号的一个信号周期包括第一时间和第二时间，所述第一时间对应第一公共电平，所述第二时间对应第二公共电平；所述第一时间内的第一公共电平的电压值小于所述第二时间内的第二公共电平的电压值；对应第N条栅极线的公共线，所述第一时间打开不晚于对应的第N条栅极线打开；所述第二时间打开晚于所述第N+1条栅线的关闭时刻；N为大于等于1的自然数。
可选的，对应第N条栅极线的公共线在所述第一时间打开，所述第N条栅极线也打开。
可选的，所述第二时间的起始时刻与所述第N+1条栅极线的关闭时刻为同一时刻。
可选的，所述每个像素包括一个像素电极，同一公共线连接相邻的两个像素为一像素组，所述像素组包括第一像素和第二像素，所述第一像素和所述第二像素与不同的数据线和栅极线连接；其中，所述像素组的第一像素的像素电极与所述公共线重叠，形成第一重叠区；所述第一像素的第一重叠区与所述公共线形成的第一存储电容为Cst1，所述第一像素的像素电容为Clc1，所述第一像素的像素电极与第N条栅极线形成的寄生电容为Cgs1；所述第一时间对应的第一公共电平为Vcom，所述第二时间对应的第二公共电平为V’com；所述栅极开启时间的高电平的电压值为VGH，所述栅极关闭低电平的电压值为VGL；
Cst1＝(VGH-VGL)*Cgs1/(V’com-Vcom)。
可选的，所述第一时间的周期时间为一条栅极线开启时间的周期的三倍。
可选的，所述像素组的第二像素的像素电极与第一像素对应的同一公共线重叠，形成第二重叠区；所述第二像素的第二重叠区与所述公共线形成的第二存储电容为Cst2，所述第二像素的像素电容为Clc2，所述第二像素的像素电极与第N+1条栅极线形成的寄生电容为Cgs2；Cst2＝(VGH-VGL)*Cgs2/(V’com-Vcom)。
相对于将RGB各子像素再划分为main/sub次像素，使得整体大视角亮度随电压变化较为接近正视，这种藉由空间上主次像素给予不同的驱动电压来解决视角色偏得缺陷的方案来说，本申请中，栅极与像素电极会产生寄生电容Cgs，寄生电容Cgs产生的反向电压会对存 储电容和液晶电容实行再分配，同一公共线对应上下两条栅极线对应的两个像素分别形成有存储电容Cst，在对应n条栅极线关闭的时候，因为寄生电容的影响，像素电极的充电电压会有一个下降，本方案，设置了两个不同的公共电平，且所述第一时间内的第一公共电平的电压值小于所述第二时间内的第二公共电平的电压值，N+1条栅极线的关闭时刻后，公共线从较低的第一公共电平到较高的第二公共电平，有一个上升沿，会影响对应像素的充电电压，可以抵消至少部分的下降；可尽可能加大储存电容可以减少反向电压形成的闪烁，并且提高电压维持率减少像素电极下降的电压，不需要牺牲可透光开口区，不会影响面板透率，也不会造成背光成本的提升。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请的其中一个实施例的一种像素结构电路的示意图；
图2是本申请的其中一个实施例的一种驱动波形的示意图；
图3是本申请的其中一个实施例的驱动波形的示意图；
图4是本申请的另一实施例的一种驱动波形的示意图；
图5是本申请的另一实施例的驱动波形的示意图；
图6是本申请的另一实施例的像素结构的示意图；
图7是本申请的另一实施例的有辅公共线的像素结构示意图；
图8是本申请的另一实施例的显示面板的示意图；
图9是本申请的另一实施例的驱动电路的示意图；
图10是本申请的另一实施例的显示装置示意图。
具体实施方式
需要理解的是，这里所使用的术语、公开的具体结构和功能细节，仅仅是为了描述具体实施例，是代表性的，但是本申请可以通过许多替换形式来具体实现，不应被解释成仅受限于这里所阐述的实施例。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示相对重要性，或者隐含指明所指示的技术特征的数量。由此，除非另有说明，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征；“多个”的含义是两个或两个 以上。术语“包括”及其任何变形，意为不排他的包含，可能存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
另外，“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系的术语，是基于附图所示的方位或相对位置关系描述的，仅是为了便于描述本申请的简化描述，而不是指示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
下面参考附图和可选的实施例对本申请作进一步说明。
如图1至图8所示，本申请实施例公开了一种驱动方法，应用于显示面板110，如图8所示，显示面板110包括显示面板110包括多条数据线130、多条栅极线140、多个像素150和多条公共线190，数据线130和栅极线140互相交错；每个像素150分别由对应的数据线130和栅极线140驱动，每个像素150包括对应的像素电极，每条公共线190分别设置在上下两条栅极线140之间，公共线190与上一条栅极线对应的像素的像素电极重叠；并与下一条栅极线对应的像素的像素电极重叠；驱动方法包括输出栅极驱动信号给显示面板110对应的栅极线140的步骤；如图2所示，公共线190的公共电平信号的一个信号周期包括第一时间和第二时间，第一时间对应第一公共电平，第二时间对应第二公共电平；第一时间内的第一公共电平的电压值小于第二时间内的第二公共电平的电压值；对应第N条栅极线140的公共线190，第一时间的起始时刻不晚于对应的第N条栅极线140打开时刻；第二时间的起始时刻不早于第N+1条栅极线140的关闭时刻。
本方案中，彩膜基板(Color Filter Substrate)上公共电压可以为任一个公共线190的电平信号，即可以是第一公共电平，也可以是第二公共电平，栅极与像素150电极会产生寄生电容Cgs，寄生电容Cgs产生的反向电压会对存储电容和液晶电容实行再分配，同一公共线190对应上下两条栅极线140对应的两个像素150分别形成有存储电容Cst，在对应n条栅极线140关闭的时候，因为寄生电容的影响，像素150电极的充电电压会有一个下降(△V)，本方案，设置了两个不同的公共电平，且第一时间内的第一公共电平的电压值小于第二时间内的第二公共电平的电压值，N+1条栅极线140的关闭时刻后，公共线190从较低的第一公共电平到较高的第二公共电平，有一个上升沿，会影响对应像素150的充电电压，可以抵消至少部分的下降(△V)；可尽可能加大储存电容可以减少反向电压形成的闪烁，并且提高电压维持率减少像素150电极下降的电压。
在一实施例中，如图2所示，在同一时刻，对应第N条栅极线140的公共线190第一时间打开，第N条栅极线140也打开。
本方案中，第N条栅极线140对应的公共线190打开的同时，第N条栅极线140也打开，栅极线140打开的时候，寄生电容会进行反向电压的再分配，像素150电极的充电电压会有一个下降(△V)，公共线190具备遮蔽电场的效果，电场形成于像素150电极与公共线190之间，公共线190打开减少了电场形成于像素150电极与数据线130之间，另外也加大了了存储电容，抵消部分的下降(△V)，N条栅极线140打开时，对应第N条的公共线190还没有打开，则无法抵消(△V)，不能实现对应，造成混乱，导致显示面板110显示异常,也就是说同时打开主要还可以先抵消一部分信号波动对像素150电极的影响，使得驱动电压趋于更稳定,显示效果更有保障。
在一实施例中，第二时间的起始时刻与第N+1条栅极线140的关闭时刻为同一时刻。本方案中，第N+1条栅极线140的关闭时刻也是第二时间的起始时刻，第一时间到第二时间时，公共线190从较低的第一公共电平到较高的第二公共电平，有一个上升沿，会影响对应像素150的充电电压，可以抵消至少部分的下降(△V)；同时进行主要还可以先抵消一部分信号波动对像素150电极的影响，使得驱动电压趋于更稳定。
在一实施例中，每个像素150包括一个像素150电极，同一公共线190连接相邻的两个像素150为一像素组160，像素组160包括与不同的数据线130连接的第一像素161和第二像素162；其中，像素组160的第一像素161的像素150电极与公共线190重叠，形成第一重叠区170；第一像素161的第一重叠区170公共线190形成的第一存储电容为Cst1，第一像素161的像素电容Clc1，第一像素161的像素150电极与当前栅栅极线形成的寄生电容为Cgs1；；第一时间对应的第一公共电平为Vcom，第二时间对应的第二公共电平为V’com；
栅极开启时间的高电平的电压值为VGH，栅极关闭低电平的电压值为VGL；Cst1＝(VGH-VGL)*Cgs1/(V’com-Vcom)。
本方案中，栅极电压的变化通过寄生电容Cgs对于画素的液晶电容及储存电容电荷产生再分配作用，使得像素150电极充电后的电压产生反向(kickback)的现象，参考图2所示：
At①,Vpixel＝Vdata
At②,ΔV1＝(VGH-VGL)*Cgs1/(Cgs+Cst+Clc)
At③,ΔV2＝(Vcom-V’com)*Cst1/(Cgs+Cst+Clc)
为了减少kick back造成闪烁(flicker issue)，设计使ΔV1+ΔV2＝0
Cst1＝(VGH-VGL)*Cgs1/(V’com-Vcom)
在一实施例中，像素组160的第二像素162的像素150电极与第一像素161对应的同一公共线190重叠，形成第二重叠区180；第二像素162的第二重叠区180与公共线190形成 的第二存储电容为Cst2，第二像素的像素电容Clc2，第二像素162的像素150电极与下一栅极线140形成的寄生电容为Cgs2；Cst2＝(VGH-VGL)*Cgs2/(V’com-Vcom)。
本方案中，参考图3所示，
At①,Vpixel＝Vdata
At②,ΔV1＝ΔV’1+ΔV”1
ΔV’1＝(VGH-VGL)*Cgs2/(Cgs+Cst+Clc)
ΔV”1＝(V’com-Vcom)*Cst2/(Cgs+Cst+Clc)
为了减少kick back造成flicker issue，设计使ΔV1＝0
Cst2＝(VGH-VGL)*Cgs2/(V’com-Vcom)。
在一实施例中，所述第一时间的周期时间为一条栅极线140开启时间的周期的三倍。
本方案中，在对应n条栅极线140关闭的时候，因为寄生电容的影响，像素150电极的充电电压会有一个下降(△V)，第一时间的打开周期为一条栅极线140开启时间的周期的三倍，接近甚至完全抵消△V，使得像素150的驱动电压更趋于稳定。
如图4所示，
At①,Vpixel＝Vdata
At②,ΔV1＝(VGH-VGL)*Cgs1/(Cgs+Cst+Clc)
At④,ΔV2＝(Vcom-V’com)*Cst1/(Cgs+Cst+Clc)
为了减少kick back造成flicker issue，设计使ΔV1+ΔV2＝0
Cst1＝(VGH-VGL)*Cgs1/(V’com-Vcom)
如图5所示，
At①,Vpixel＝Vdata
At②,ΔV1＝(VGH-VGL)*Cgs2/(Cgs+Cst+Clc)
At③,ΔV2＝(Vcom-V’com)*Cst2/(Cgs+Cst+Clc)
为了减少kick back造成flicker issue，设计使ΔV1+ΔV2＝0
Cst2＝(VGH-VGL)*Cgs2/(V’com-Vcom)
如图6至图8所示，本申请还公开了一种使用上述驱动方法的显示面板110，包括多条数据线130、多条栅极线140、多个像素150和多条公共线190，数据线130和栅极线140互相交错，每个像素150分别由对应的数据线130和栅极线140驱动，每个像素150对应一个像素电极；每条公共线190，设置在上下两条栅极线140之间；同一公共线190相邻的两个像素150为一个像素组160，像素组160包括第一像素161和第二像素162；第一像素161和第二像素162与不同的数据线130和栅极线140连接；其中，公共线190与上一条栅极线140对应的第一像素161的像素电极重叠，形成第一重叠区170；公共线190与下一条栅极 线140对应的第二像素162的像素电极重叠，形成第二重叠区180。。
本方案中，同一公共线190对应上下两条栅极线140对应的两个像素150分别形成有存储电容，共用的公共线190两旁可以具备遮蔽电场的效果，电场形成于像素150电极与公共线190之间，减少了电场形成于像素150电极与数据线130之间，将栅极跨到用以形成储存电容的共用的公共线190上方，增加画素开口以及液晶显示器的出光量，可以获得节能、节省成本或者高亮度的显示效果，这样的像素150设计使得可以实现上述的驱动方法，减少甚至消除寄生电容对液晶电容和存储电容的再分配作用而导致显示面板110产生闪烁的现象，还可以增加开口率，提高液晶分子的穿透率，实现大视角色偏。
在一实施例中，公共线190包括相互导通的主公共线200和辅公共线210，主公共线200与数据线130交叉设置，辅公共线210与数据线130平行设置，主公共线200与第一像素161的像素150电极以及第二像素162的像素150电极重叠，分别形成第一主重叠区220和第二主重叠区230，辅公共线210包括第一辅公共线240和第二辅公共线250，第一像素161的像素150电极与第一辅公共线240形成第一辅重叠区260，第二像素162的像素150电极与第二辅公共线250形成第二辅重叠区270。
本方案中，公共线190分为主公共线200和辅公共线210，主公共线200与数据线130交错设置，增加的辅公共线210与数据线130平行，且主公共线200与辅公共线210相互导通，可以减少像素150电极对数据线130上电压的影响，造成所谓的串扰从而影响画质，另外也可以减少栅极线140与像素150电极产生的寄生电容所带来的对显示面板110造成显示闪烁的影响。
在一实施例中，第一辅公共线240与第二辅公共线250为一条直线。本方案中，第一辅公共线240与第二辅公共线250为一条直线在制程上更方便省时。
在一实施例中，第一辅公共线240为两条，分别设置在第一像素161的两侧靠近数据线130的位置，两条第一辅公共线240与第一像素161的像素150电极都重叠，形成两个重叠区；第二辅公共线250为两条，分别设置在第二像素162的两侧靠近数据线130的位置，两条第二辅公共线250与第二像素162的像素150电极都重叠，形成两个重叠区；两条第二辅公共线250与两条第一辅公共线240形成两条直线。
本方案中，共用的公共线190两旁可以具备遮蔽电场的效果，电场形成于像素150电极与公共线190之间，减少了电场形成于像素150电极与数据线130之间，将像素150电极跨到用以形成储存电容的共用的公共线190上方，栅极与像素150电极容易产生寄生电容Cgs，寄生电容Cgs产生的反向电压会对存储电容和液晶电容实行再分配，本申请利用了像素150电极两旁的空间形成储存电容Cst，像素组160内的两个像素150分别对应不同的数据线130，更好保证每个像素150的数据驱动电压的大小，防止像素150电极本身的负载导致数据电压 的降低，电场形成于像素150电极与栅极线140之间，在第一像素161和第二像素162的两边都设置辅公共线210，并与第一像素161和第二像素162的像素150电极都形成重叠区，增强存储电容，亦可增加画素开口增加了液晶显示器的出光量，这些效应可以获得节能、节省成本或者高亮度的显示效果，减少像素150电极与栅极线140产生的寄生电容的影响，减少甚至消除寄生电容对液晶电容和存储电容的再分配作用而导致显示面板110产生闪烁。
在一实施例中，第一辅公共线240与第一像素161的像素150电极之间设有第一安全距离；辅公共线210与对应的数据线130之间设有第二安全距离。
本方案中，像素150电极与辅公共线210之间会产生电场，如果距离太近，产生的电场会比较强，从而会影响数据电压信号的传输，造成电压不稳而影响画面的显示，设置安全距离防止电场影响，减少串扰现象，防止显示面板110的画质被影响。
如图9所示，一种驱动电路120，驱动上述的显示面板110，驱动电路120包括：栅极驱动电路121，输出栅极驱动信号给显示面板110对应的栅极线140；其中，公共线190的公共电平信号的一个信号周期包括第一时间和第二时间，第一时间对应第一公共电平，第二时间对应第二公共电平；第一时间内的第一公共电平的电压值小于第二时间内的第二公共电平的电压值；对应第N条栅极线140的公共线190，第一时间打开不晚于对应的第N条栅极线140打开；第二时间打开晚于第N+1条栅极线的关闭时刻。
本方案中，驱动电路120用于驱动显示面板110，驱动电路120中的栅极驱动电路121输出信号给显示面板110对应的栅极线140，输出相应的信号开启对应的栅极线140，栅极驱动信号周期分为三个时间段，分别输出不同的电平，因为受到像素150电极与栅极线140产生的寄生电容所带来的反向电压影响，不同时间段设置电压下拉时间，形成正确的回路，解决反向电压带来的闪烁现象。
如图10所示，作为本申请的另一实施例，公开了一种显示装置100，包括上述的显示面板110以及驱动电路120，所述驱动电路120驱动所述显示面板110。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的技术方案可以广泛用于各种显示面板，如TN型显示面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS型显示面板(In-Plane Switching，平面转换)、VA型显示面板(Vertical Alignment，垂直配向技术)、MVA型显示面板(Multi-domain Vertical Alignment，多象限垂直配向技术)，当然，也可以是其他类型的显示面板，如有机发光显示面板(organic light-emitting diode，简称OLED显示面板)，均可适用上述方案。
以上内容是结合具体的可选实施方式对本申请所作的进一步详细说明，不能认定本申请 的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (19)

  1. 一种驱动方法，应用于显示面板，所述显示面板包括：
    多条数据线；
    多条栅极线，所述栅极线和所述数据线互相交错；
    多个像素，分别由对应的数据线和栅极线驱动，每个像素包括对应的像素电极；以及
    多条公共线，分别设置在上下两条栅极线之间，所述公共线与上一条栅极线对应的像素的像素电极重叠；并与下一条栅极线对应的像素的像素电极重叠；
    所述驱动方法包括输出栅极驱动信号给所述显示面板对应的栅极线的步骤；
    其中，所述公共线的公共电平信号的一个信号周期包括第一时间和第二时间，所述第一时间对应第一公共电平，所述第二时间对应第二公共电平；所述第一时间内的第一公共电平的电压值小于所述第二时间内的第二公共电平的电压值；
    对应第N条栅极线的公共线，所述第一时间的起始时刻不晚于对应的第N条栅极线打开时刻；所述第二时间的起始时刻不早于所述第N+1条栅极线的关闭时刻；
    N为大于等于1的自然数。
  2. 如权利要求1所述的一种驱动方法，其中，在同一时刻，对应第N条栅极线的公共线在所述第一时间打开，所述第N条栅极线也打开。
  3. 如权利要求1所述的一种驱动方法，其中，所述第二时间的起始时刻与所述第N+1条栅极线的关闭时刻为同一时刻。
  4. 如权利要求1所述的一种驱动方法，其中，所述每个像素包括一个像素电极，同一公共线连接相邻的两个像素为一像素组，所述像素组包括第一像素和第二像素，所述第一像素和所述第二像素与不同的数据线和栅极线连接；
    其中，所述像素组的第一像素的像素电极与所述公共线重叠，形成第一重叠区；所述第一像素的第一重叠区与所述公共线形成的第一存储电容为Cst1，所述第一像素的像素电容为Clc1，所述第一像素的像素电极与第N条栅极线形成的寄生电容为Cgs1；所述第一时间对应的第一公共电平为Vcom，所述第二时间对应的第二公共电平为V’com；
    所述栅极开启时间的高电平的电压值为VGH，所述栅极关闭低电平的电压值为VGL；
    Cst1＝(VGH-VGL)*Cgs1/(V’com-Vcom)。
  5. 如权利要求4所述的一种驱动方法，其中，所述第一时间的周期时间为一条栅极线开启时间的周期的三倍。
  6. 如权利要求4所述的一种驱动方法，其中，所述像素组的第二像素的像素电极与第一像素对应的同一公共线重叠，形成第二重叠区；所述第二像素的第二重叠区与所述公共线 形成的第二存储电容为Cst2，所述第二像素的像素电容为Clc2，所述第二像素的像素电极与第N+1条栅极线形成的寄生电容为Cgs2；
    Cst2＝(VGH-VGL)*Cgs2/(V’com-Vcom)。
  7. 一种使用如权利要求1所述的驱动方法的显示面板，包括：
    多条数据线；
    多条栅极线，所述栅极线和所述数据线互相交错；
    多个像素，分别由对应的数据线和栅极线驱动，每个像素包括对应的像素电极；以及
    多条公共线，分别设置在上下两条栅极线之间；
    其中，同一公共线相邻的两个像素为一个像素组，所述像素组包括第一像素和第二像素；所述第一像素和所述第二像素与不同的数据线和栅极线连接；
    其中，所述公共线与上一条栅极线对应的第一像素的像素电极重叠，形成第一重叠区；所述公共线与下一条栅极线对应的第二像素的像素电极重叠，形成第二重叠区。
  8. 如权利要求7所述的一种显示面板，其中，所述公共线包括相互导通的主公共线和辅公共线；
    所述主公共线与所述数据线交叉设置，所述辅公共线与所述数据线平行设置；
    所述主公共线与所述第一像素的像素电极以及第二像素的像素电极重叠，分别形成第一主重叠区和第二主重叠区；
    所述辅公共线包括第一辅公共线和第二辅公共线，所述第一像素的像素电极与所述第一辅公共线形成第一辅重叠区，所述第二像素的像素电极与所述第二辅公共线形成第二辅重叠区。
  9. 如权利要求8所述的一种显示面板，其中，所述第一辅公共线为两条，分别设置在所述第一像素的两侧靠近数据线的位置，两条第一辅公共线与所述第一像素的像素电极都重叠，形成两个重叠区；
    所述第二辅公共线为两条，分别设置在所述第二像素的两侧靠近数据线的位置，两条第二辅公共线与所述第二像素的像素电极都重叠，形成两个重叠区。
  10. 如权利要求9所述的一种显示面板，其中，第一辅公共线与第二辅公共线为一条直线。
  11. 如权利要求9所述的一种显示面板，其中，两条所述第二辅助公共线与两条所述第一辅公共线形成两条直线。
  12. 如权利要求8所述的一种显示面板，其中，所述第一辅公共线与所述第一像素的像素电极之间设有第一安全距离。
  13. 如权利要求8所述的一种显示面板，其中，所述辅公共线与对应的数据线之间设有 第二安全距离。
  14. 一种驱动电路，驱动显示面板，所述显示面板包括：
    多条数据线；
    多条栅极线，所述栅极线和所述数据线互相交错；
    多个像素，分别由对应的数据线和栅极线驱动，每个像素对应一个像素电极；以及
    多条公共线，分别设置在上下两条栅极线之间；
    其中，同一公共线相邻的两个像素为一个像素组，所述像素组包括第一像素和第二像素；所述第一像素和所述第二像素与不同的数据线和栅极线连接；
    其中，所述公共线与上一条栅极线对应的第一像素的像素电极重叠，形成第一重叠区；所述公共线与下一条栅极线对应的第二像素的像素电极重叠，形成第二重叠区。
    所述驱动电路包括：
    栅极驱动电路，输出栅极驱动信号给所述显示面板对应的栅极线；
    其中，所述公共线的公共电平信号的一个信号周期包括第一时间和第二时间，所述第一时间对应第一公共电平，所述第二时间对应第二公共电平；所述第一时间内的第一公共电平的电压值小于所述第二时间内的第二公共电平的电压值；
    对应第N条栅极线的公共线，所述第一时间打开不晚于对应的第N条栅极线打开；所述第二时间打开晚于所述第N+1条栅线的关闭时刻；
    N为大于等于1的自然数。
  15. 如权利要求14所述的一种驱动电路，其中，对应第N条栅极线的公共线在所述第一时间打开，所述第N条栅极线也打开。
  16. 如权利要求14所述的一种驱动电路，其中，所述第二时间的起始时刻与所述第N+1条栅极线的关闭时刻为同一时刻。
  17. 如权利要求14所述的一种驱动电路，其中，所述每个像素包括一个像素电极，同一公共线连接相邻的两个像素为一像素组，所述像素组包括第一像素和第二像素，所述第一像素和所述第二像素与不同的数据线和栅极线连接；
    其中，所述像素组的第一像素的像素电极与所述公共线重叠，形成第一重叠区；所述第一像素的第一重叠区与所述公共线形成的第一存储电容为Cst1，所述第一像素的像素电容为Clc1，所述第一像素的像素电极与第N条栅极线形成的寄生电容为Cgs1；
    所述第一时间对应的第一公共电平为Vcom，所述第二时间对应的第二公共电平为V’com；
    所述栅极开启时间的高电平的电压值为VGH，所述栅极关闭低电平的电压值为VGL；
    Cst1＝(VGH-VGL)*Cgs1/(V’com-Vcom)。
  18. 如权利要求14所述的一种驱动电路，其中，所述第一时间的周期时间为一条栅极线开启时间的周期的三倍。
  19. 如权利要求14所述的一种驱动电路，其中，所述像素组的第二像素的像素电极与第一像素对应的同一公共线重叠，形成第二重叠区；所述第二像素的第二重叠区与所述公共线形成的第二存储电容为Cst2，所述第二像素的像素电容为Clc2，所述第二像素的像素电极与第N+1条栅极线形成的寄生电容为Cgs2；
    Cst2＝(VGH-VGL)*Cgs2/(V’com-Vcom)。
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