WO2020154843A1 - 融合型存储器 - Google Patents

融合型存储器 Download PDF

Info

Publication number
WO2020154843A1
WO2020154843A1 PCT/CN2019/073434 CN2019073434W WO2020154843A1 WO 2020154843 A1 WO2020154843 A1 WO 2020154843A1 CN 2019073434 W CN2019073434 W CN 2019073434W WO 2020154843 A1 WO2020154843 A1 WO 2020154843A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
memory
gate
layer
ferroelectric layer
Prior art date
Application number
PCT/CN2019/073434
Other languages
English (en)
French (fr)
Inventor
吕杭炳
罗庆
许晓欣
龚天成
刘明
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to PCT/CN2019/073434 priority Critical patent/WO2020154843A1/zh
Priority to US17/424,998 priority patent/US11776607B2/en
Publication of WO2020154843A1 publication Critical patent/WO2020154843A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/223—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2259—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods

Definitions

  • the present disclosure relates to the field of memory, and further relates to a fusion memory.
  • Traditional DRAM uses a memory cell structure of 1 T1C (1 Transistor-1 Capacitor, 1 transistor-1 capacitor). When the word line connected to the gate of the transistor is strobed, the transistor is strobed and can be selected from the bit line. Read the bit information stored on the capacitor; traditional NAND uses a floating gate or charge trap structure; one of them is to achieve dynamic random storage, the other is to achieve non-volatile storage, so the two There are huge differences in the preparation process of similar memories, and they cannot be integrated in a chip-on-chip (SOC) at the same time. Therefore, the advantages of the two types of memories cannot be combined, which limits the storage capacity and computing performance of the SOC chip.
  • SOC chip-on-chip
  • synaptic devices are implemented by simulations of memristors or three-terminal transistors at both ends. Synaptic devices are generally connected to each other in a parallel NOR structure. After weight training, current convergence is used to complete the calculation. This type of structure has problems such as large operating current and high power consumption training, which limits the number of parallels.
  • the purpose of the present disclosure is to provide a fusion memory to integrate the advantages of the above two types of memory.
  • a converged memory including a plurality of memory units, wherein the memory unit includes:
  • the ferroelectric layer is located on the channel region
  • the gate is located on the ferroelectric layer.
  • a converged memory including a plurality of memory units, wherein the memory unit includes:
  • the first interface layer is located on the channel
  • the ferroelectric layer is located above the first interface layer
  • the gate is located on the ferroelectric layer.
  • a converged memory including a plurality of memory units, wherein the memory unit includes:
  • the first interface layer is located on the channel
  • the ferroelectric layer is located above the first interface layer
  • the second interface layer is located above the ferroelectric layer
  • the gate is located on the second interface layer.
  • the ferroelectric layer material is doped HfO x , ZrO x , PZT, BFO or BST.
  • the doping element in the ferroelectric layer is Si, Zr, Hf, Al, Y, Gd, La, Sr, Ti, and/or N.
  • it further includes a gate voltage controller, which is electrically connected to the gate of the storage unit, and is used to control the gate voltage to work at a first voltage, and the absolute value of the first voltage It is less than the reversal voltage at which the ferroelectric layer undergoes polarization reversal.
  • a gate voltage controller which is electrically connected to the gate of the storage unit, and is used to control the gate voltage to work at a first voltage, and the absolute value of the first voltage It is less than the reversal voltage at which the ferroelectric layer undergoes polarization reversal.
  • it further includes a gate voltage controller, which is electrically connected to the gate of the storage unit, and is used to control the gate voltage to work at a second voltage.
  • the absolute value of the second voltage is It is greater than the reversal voltage at which the polarization reversal of the ferroelectric layer occurs.
  • the plurality of memory cells form a 3D stacked structure
  • the fusion memory of the present disclosure enables the memory cell to work in the charge trapping mode and the polarization inversion mode. Therefore, the memory combines the functions of DRAM and NAND, and combines the advantages of the two.
  • the gate voltage controller of the present disclosure can control the gate voltage to work at the first voltage and the second voltage, so that the memory operates in the charge trap mode and the polarization flip mode respectively, and has high efficiency and flexibility.
  • FIG. 1 is a schematic cross-sectional view of a memory cell in a converged memory according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic cross-sectional view of a memory cell in another fusion memory according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic cross-sectional view of a memory cell in another converged memory according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of the principle of the converged memory implemented in the present disclosure.
  • FIG. 5 is a schematic diagram of a writing method for a converged memory according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of an erasing method for a converged memory according to an embodiment of the present disclosure.
  • 7A, 7B, and 7C are respectively a voltage scan curve diagram, a schematic diagram of writing and erasing, and a schematic diagram of reading in the charge trap mode of the fusion memory according to an embodiment of the disclosure.
  • 8A, 8B, and 8C are respectively schematic diagrams of single-cycle operation, multi-cycle operation, and write and erase in the ferroelectric flip mode of the fusion memory according to the embodiments of the disclosure.
  • 9A-9C are respectively schematic cross-sectional views of memory cells of three types of memories in the embodiments of the disclosure.
  • Figure 10 is a schematic diagram of a neural network computing device.
  • Figure 11 is a schematic diagram of neuron composition.
  • FIG. 12 is a schematic diagram of the principle of a neural network operation system according to an embodiment of the disclosure.
  • FIG. 13 is a schematic diagram of a storage unit in the neural network computing system in FIG. 12.
  • FIG. 14 is a block diagram of a neural network computing system according to an embodiment of the disclosure.
  • a fusion memory which includes a plurality of memory cells, and each memory cell contains a ferroelectric layer, so that the memory cell can work in a charge trap mode and a polarization flip mode.
  • the memory combines the functions of DRAM and NAND, combining the advantages of both.
  • FIG. 1 is a schematic cross-sectional view of a memory cell in a converged memory according to an embodiment of the present disclosure.
  • a fusion type memory is provided in FIG. 1, which includes a plurality of memory cells 10, wherein the memory cell 10 includes: a bulk substrate; a source and a drain above the bulk substrate and between the source and drain regions An extended channel region; a ferroelectric layer, located above the channel region; and a gate, located above the ferroelectric layer.
  • the memory cell in this embodiment includes the channel region and the ferroelectric layer above, which are in direct contact. By adjusting the voltage applied to the gate, the ferroelectric layer can be in the charge trap mode and the polarization switching mode. Work down.
  • the ferroelectric layer in Figure 1 uses a ferroelectric layer as the gate dielectric between the gate and the channel.
  • the memory can work in two modes: on the one hand, it uses a large number of lattice defects in the ferroelectric material for charge storage, so that it can work in the charge trapping mode, and store data by capturing and releasing charges; on the other hand, it can also work in The ferroelectric flip mode uses polarization flip to store data.
  • the material of the ferroelectric layer can be doped HfO x , ZrO x , PZT, BFO or BST, more preferably HfO x ;
  • the doping species can be Si, Zr, Hf, Al, Y , Gd, La, Sr, Ti, and/or N, etc.
  • the preferred doping is Zr; the doping content is between 10% and 75%
  • the ferroelectric layer has a thickness of 3 nm to 10 nm; the length of the channel is 5 nm to 200 nm, and the width of the channel is 5 nm to 500 nm.
  • the above-mentioned block, source, drain, and gate can be configured according to the existing memory cell arrangement, and the corresponding preparation process can also be performed with reference to the existing process flow and participation.
  • the fusion memory further includes a control circuit, and a gate control sub-circuit connected to each memory cell for individually applying a specific first voltage to the gate so that the ferroelectric layer under the gate Capture electrons and change the threshold voltage during charging or discharging.
  • the control circuit can also be integrated in the read-write circuit of the memory to control the corresponding voltage pulse value during the read-write process.
  • the read-write circuit writes the content into the accessed storage unit at the first voltage according to the CPU's read-write instruction; or reads information from the accessed storage unit.
  • the absolute value of the first voltage should be less than the switching voltage value required for the polarization reversal of the ferroelectric material in the ferroelectric layer. As the first voltage increases, the more electrons trapped by the ferroelectric layer, the threshold value of the memory cell The voltage will gradually rise.
  • control circuit is also used to separately apply a specific second voltage to the gate, so that the gate charge realizes a polarization reversal, and accordingly changes the threshold voltage, which increases with the second voltage ,decreasing gradually.
  • the read-write circuit writes the content into the accessed storage unit with the second voltage according to the CPU's read-write instruction; or reads information from the accessed storage unit.
  • the absolute value of the second voltage should be greater than the switching voltage value required for the polarization inversion of the ferroelectric material in the ferroelectric layer.
  • the source region and the drain region can be kept in a floating state, or adjusted to the corresponding state (positive voltage, negative voltage) according to the working state of the memory (writing, erasing or reading). Voltage or ground).
  • the specific adjustment method can refer to the following embodiment of the writing method for converged memory.
  • the above-mentioned control circuit can control the voltage applied to the gate to be at the first voltage or the second voltage, that is, two voltage modes can appear at the same time in a process, which can play The respective advantages of DRAM and traditional flash.
  • the fusion memory of the embodiments of the present disclosure may use the word line, bit line, and source line architecture known in the prior art to configure the memory cell array.
  • the word line is coupled to the gate of the corresponding memory cell
  • the bit line is coupled to the drain of the corresponding memory cell
  • the source line is coupled to the source of the corresponding Fe memory cell.
  • the fusion memory of the embodiments of the present disclosure further includes a readout circuit for reading the information stored in each memory cell, which can be read out in the polarization inversion mode or the mode of trapping electrons in the ferroelectric layer by applying A smaller reading voltage (for example, 0.6V) is used to read the information in the memory cell.
  • a smaller reading voltage for example, 0.6V
  • FIG. 2 is a schematic cross-sectional view of a memory cell in another fusion memory according to an embodiment of the present disclosure.
  • a fusion memory is provided in FIG. 2 and includes a plurality of memory cells 20, wherein the memory cell 20 includes: a bulk substrate; source and drain above the bulk substrate and between the source and drain regions The extended channel region; the first interface layer is located on the channel; the ferroelectric layer is located on the first interface layer; the gate is located on the ferroelectric layer.
  • the structure of the memory cell in this embodiment is basically similar to that in FIG. 1, except that a first interface layer is provided between the ferroelectric layer and the channel region.
  • the first interface layer can be used to control the growth of ferroelectric materials, such as lattice orientation control or defect distribution.
  • the material of the first interface layer may be SiO 2 , SiN, SiON, AlO x , TiO 2 or HfO x .
  • the material of the first interface layer may be SiO 2 ; the first interface layer The thickness of the first interface layer can be 0.3nm ⁇ 3nm; the material of the first interface layer is adjusted according to the ferroelectric layer material to be grown, for example, when the ferroelectric layer material is HfO x , the corresponding first interface layer material can be SiON; for example When the ferroelectric layer material is SBT, the corresponding first interface layer material may be HfO x or AlO x .
  • FIG. 3 is a schematic cross-sectional view of a memory cell in another converged memory according to an embodiment of the present disclosure.
  • a fusion memory is provided in FIG. 3, which includes a plurality of memory cells 30, wherein the memory cell 30 includes: a bulk substrate; source and drain above the bulk substrate and between the source and drain regions The extended channel region; the first interface layer is located on the channel; the ferroelectric layer is located on the first interface layer; the second interface layer is located on the ferroelectric layer; the gate is located on the second interface layer on.
  • the memory cell structure in this embodiment is basically similar to that in FIG. 1, except that a first interface layer is provided between the ferroelectric layer and the channel region, and a second interface layer is provided between the ferroelectric layer and the gate. Interface layer.
  • the first interface layer can be used to control the growth of ferroelectric materials, such as lattice orientation control or defect distribution.
  • the second interface layer is used to isolate the mutual diffusion and interface damage between the metal gate and the storage layer.
  • the material of the first interface layer may be SiO 2 , SiN, SiON, AlO x , TiO 2 , HfO x or a combination thereof.
  • the material of the first interface layer may be SiO 2 ;
  • the thickness of an interface layer can be 0.3nm ⁇ 3nm; the material of the first interface layer is adjusted according to the ferroelectric layer material to be grown, for example, when the ferroelectric layer material is HfO x , the corresponding first interface layer material can be SiON; for example, when the ferroelectric layer material is SBT or PZT, the corresponding first interface layer material can be HfO x or AlO x .
  • the material of the second interface layer may be SiO 2 , SiN, SiON, AlO x , TiO 2 or HfO x .
  • the second interface layer material may be AlO x; thickness of the second interface layer may be 1nm ⁇ 10nm; second interface material layer is adjusted according to the ferroelectric layer and a gate material, for example, when the ferroelectric layer When the material is HfO x , the corresponding second interface layer material can be a SiO 2 /SiN/SiO 2 laminate; for example, when the ferroelectric layer material is SBT or PZT, the corresponding first interface layer material can be HfO x or AlO x .
  • FIG. 4 The working principle of the storage unit in the fusion memory of the foregoing embodiment can be referred to as shown in FIG. 4.
  • FIG 4 is a schematic diagram of the fusion memory implemented in the present disclosure.
  • the threshold voltage V T in the charge trap mode, when the gate voltage V G gradually increases, the threshold voltage V T also gradually increases.
  • the scan voltage Is -5V the corresponding threshold voltage V T is about -1.5V; when the scan voltage gradually rises and turns to a positive value, such as point B, the scan voltage is 1V, at this time the threshold voltage V T is about -1.1V, and Compared with point A, the threshold is increased.
  • points C and D are in charge trapping mode; when the voltage rises to 4V, the voltage exceeds the ferroelectric reversal voltage generated in the ferroelectric layer, and ferroelectric reversal occurs at this time. The threshold voltage drops. When the scan voltage is increased again, the threshold voltage V T gradually drops, and the ferroelectric reversal mode is entered.
  • the fusion memory includes a plurality of memory cells, each memory cell bulk substrate; source and drain above the substrate The channel region extending between the electrode and the source and drain, and the ferroelectric layer and the gate stacked on the channel region.
  • the channel region and the ferroelectric layer here may not include other semiconductor layers, or may include the above-mentioned first interface layer, and the ferroelectric layer and the channel may include a second interface layer or two Therefore, the storage unit here can be the structure described in any of the embodiments in FIGS. 1-3.
  • the writing method for converged storage in this embodiment includes:
  • the source and the gate are respectively set to be grounded or floating.
  • FIG. 5 is a schematic diagram of a writing method for a converged memory according to an embodiment of the present disclosure.
  • the source and drain terminals of the memory cell are maintained at zero potential (such as grounded) or floating, and the block is maintained at zero potential (such as grounded).
  • a first voltage is applied to the gate terminal, The first voltage is less than the flipping voltage of the ferroelectric flip-up polarization flip.
  • the operating state can refer to the charge trap mode in Figure 4, which is completed in the low-voltage region (less than the flipping voltage).
  • the first voltage is applied to cause the electrons to charge and discharge, thereby causing the threshold voltage to change.
  • the change process is faster and can be Reaching a programming speed of 20ns, which is faster than traditional DRAM and has a lower voltage.
  • FIGS. 7A-7C at the same time, as shown in FIG. 7A, when an electric field is applied to a memory cell (that is, a transistor containing a ferroelectric layer), the central atom in the crystal in the ferroelectric layer stays in a low-energy state along the electric field. After the electric field is removed, the central atom remains in a low energy state; when the first voltage is applied, the ferroelectric domain does not flip (the first voltage is in the non-inverted voltage interval). As shown in Fig. 7B, the first voltage in the forward direction can be controlled to be 3V and the pulse time is 20nm. During this process, the threshold value changes, that is, data writing is realized; by comparing with the existing DRAM, as shown in Fig.
  • the threshold voltage is still lower than that of traditional DRAM, and it has a retention time of more than 1,000 seconds at 85°C.
  • the speed is equivalent to that of DRAM, and the retention characteristics are much better than that of prior art DRAM.
  • the writing method of the fusion memory may further include a writing method 52 as shown in FIG. 5, applying a second voltage between the gate and the block of at least one memory cell, and the second The voltage is greater than the reversal voltage at which the polarization reversal of the ferroelectric layer occurs; and the source electrode is in a grounded state and the gate electrode is in a positive voltage state.
  • the operation state can refer to the ferroelectric flip mode in Figure 4, which is completed in the high voltage region (greater than the flip voltage), and the second voltage is applied to cause the ferroelectric domain flip.
  • the programming voltage of this process is still less than that of the traditional FLASH, and The speed is also faster, up to 20ns programming speed.
  • the second voltage for the application of the second voltage, referring to FIGS. 8A-8C, an electric field is applied to the memory cell (that is, a transistor containing a ferroelectric layer).
  • the ferroelectric domain is reversed.
  • the second voltage is greater than the flip voltage.
  • the second voltage in the forward direction can be controlled to be 6V and the pulse time is 20nm.
  • the threshold value changes, that is, data writing is realized, and ferroelectric domain flipping occurs simultaneously; by comparing with the existing FLASH, As shown in Figures 8B and 8C, after many cycles, the threshold voltage is still lower than the traditional FLASH, and the retention time and speed are equivalent to the FLASH, and the programming voltage is much smaller than the traditional FLASH.
  • the writing method of this embodiment further includes reading the data written into the memory cell. For example, as shown in FIG. 7C, a smaller reading voltage (for example -0.7V) can be applied to realize data reading. Take, the threshold voltage does not change at this time.
  • a smaller reading voltage for example -0.7V
  • FIG. 6 is a schematic diagram of an erasing method for a converged memory according to an embodiment of the present disclosure.
  • the source and drain terminals of the memory cell are maintained at zero potential (such as grounded) or floating, and the block is maintained at zero potential (such as grounded).
  • a negative value is applied to the gate terminal.
  • the absolute value of the third voltage is less than the flipping voltage of the ferroelectric flip-up polarization.
  • This operating state can refer to the charge trapping mode in Figure 4, which is completed in the low voltage region (less than the flip voltage).
  • the application of the third voltage causes the electrons to charge and discharge, thereby causing the threshold voltage to change.
  • the change process is faster and can be
  • the erasing speed reaches 20ns, which is faster than traditional DRAM, and the voltage is also lower.
  • FIGS. 7A-7C at the same time, as shown in FIG. 7A, when an electric field is applied to a memory cell (that is, a transistor containing a ferroelectric layer), the central atom in the crystal in the ferroelectric layer stays in a low-energy state along the electric field. After the electric field is removed, the central atom remains in a low energy state; when the third voltage is applied, the ferroelectric domain is not inverted (the third voltage is in the non-inverted voltage interval). As shown in Figure 7B, the third voltage that can be controlled in the forward direction is -4V, and the pulse time is 20nm.
  • a memory cell that is, a transistor containing a ferroelectric layer
  • the central atom in the crystal in the ferroelectric layer stays in a low-energy state along the electric field. After the electric field is removed, the central atom remains in a low energy state; when the third voltage is applied, the ferroelectric domain is not inverted (the third voltage is in the non-inverted voltage interval).
  • the threshold value changes, that is, data erasure is achieved; compared with the existing DRAM, as shown in Figures 7B and 7C It can be seen that after 10 12 cycles or more, the threshold voltage is still lower than that of traditional DRAM, and the retention time of 85 degrees is more than 1000 seconds, the speed is equivalent to DRAM, and the retention characteristics are much better than traditional DRAM.
  • the erasing method of the fusion memory may further include an erasing method as shown by 62 in FIG. 6, applying a fourth voltage between the gate and the block of at least one memory cell, and the fourth
  • the absolute value of the voltage is greater than the flipping voltage at which the ferroelectric layer undergoes polarization reversal; and the block is in a zero voltage (such as a grounded state), the gate is in a negative voltage state, the drain is in a grounded or floating state, and the source is in a positive voltage state.
  • the operating state can refer to the ferroelectric flip mode in Figure 4, which is completed in the high voltage region (greater than the flip voltage).
  • the fourth voltage for the application of the fourth voltage, referring to FIGS. 8A-8C, an electric field is applied to the memory cell (that is, a transistor containing a ferroelectric layer).
  • the fourth voltage is applied, the ferroelectric domain is reversed.
  • the absolute value of the fourth voltage is greater than the switching voltage).
  • the fourth reverse voltage can be controlled to be -6V, and the pulse time is 20nm.
  • the threshold value changes, that is, data erasure is realized, and ferroelectric domain flipping occurs at the same time; compared with the existing FLASH
  • FIG. 8B and FIG. 8C after many cycles, the threshold voltage is still lower than that of traditional FLASH, and the retention time and speed are equivalent to FLASH, and the erase voltage is much smaller than that of traditional FLASH.
  • a memory includes a plurality of memory cells, and each memory cell contains a deep-level defect dielectric layer, so that the memory cell can work in a charge trap mode. Therefore, the The memory has the function of DRAM, while the operating voltage is much lower than that of traditional DRAM, and the storage and erasure speed is fast.
  • FIG. 9A is a schematic cross-sectional view of a memory cell in a converged memory according to an embodiment of the present disclosure.
  • a fusion type memory is provided in FIG. 9A, including a plurality of memory cells 91, wherein the memory cell 10 includes: a bulk substrate; a source and a drain above the bulk substrate and between the source and drain regions An extended channel region; a deep-level defect dielectric layer located on the channel region; and a gate located on the deep-level defect dielectric layer.
  • the memory cell in this embodiment includes a channel region and a deep-level defect dielectric layer above, which are in direct contact.
  • the deep-level defect dielectric layer can be in charge trapping mode. And work in the polarization flip mode.
  • the deep-level defect dielectric layer in FIG. 9A uses a deep-level defect dielectric layer as the gate dielectric between the gate and the channel.
  • the memory can use a large number of lattice defects in deep-level defect materials for charge storage, so that it can work in a charge trapping mode, and store data by trapping and releasing charges.
  • the deep-level defect dielectric layer referred to in the embodiments of the present disclosure refers to dielectric layer materials with a charge trap energy level of 1 eV or more, such as SiN, ferroelectric materials, and the like.
  • the material of the ferroelectric layer can be doped HfO x , ZrO x , PZT, BFO or BST, more preferably HfO x ;
  • the doping species can be Si, Zr, Hf, Al, Y , Gd, La, Sr, Ti, and/or N, etc.
  • the preferred doping is Zr; the doping content is between 10% and 75%.
  • the ferroelectric layer has a thickness of 3 nm to 10 nm; the length of the channel is 5 nm to 200 nm, and the width of the channel is 5 nm to 500 nm.
  • the above-mentioned block, source, drain, and gate can be configured according to the existing memory cell arrangement, and the corresponding preparation process can also be performed with reference to the existing process flow and participation.
  • the fusion memory further includes a control circuit, and includes a gate control sub-circuit connected to each memory cell, for individually applying a specific first voltage to the gate, so that the deep level below the gate
  • the defective dielectric layer traps electrons and changes the threshold voltage during charging or discharging.
  • the control circuit can also be integrated in the read-write circuit of the memory to control the corresponding voltage pulse value during the read-write process.
  • the read-write circuit writes the content into the accessed storage unit with the first voltage according to the CPU's read-write instruction; or reads information from the accessed storage unit.
  • the absolute value of the first voltage should be less than the reversal voltage required for the polarization reversal of the deep-level defect material in the deep-level defect dielectric layer. As the first voltage rises, the deep-level defect dielectric layer captures The more electrons, the threshold voltage of the memory cell will gradually rise.
  • the source region and the drain region can be kept in a floating state, or adjusted to the corresponding state (positive voltage, negative voltage) according to the working state of the memory (writing, erasing or reading). Voltage or ground).
  • the specific adjustment method refer to the above-mentioned embodiment in the writing method for converged memory.
  • the fusion memory of the embodiments of the present disclosure may use the word line, bit line, and source line architecture known in the prior art to configure the memory cell array.
  • the word line is coupled to the gate of the corresponding memory cell
  • the bit line is coupled to the drain of the corresponding memory cell
  • the source line is coupled to the source of the corresponding ferroelectric memory cell.
  • the fusion memory of the embodiments of the present disclosure further includes a readout circuit for reading out the information stored in each memory cell, which can read out the deep-level defect polarization inversion or the deep-level defect dielectric layer trapping respectively.
  • a small read voltage for example, -0.7V, 0V or 0.7V is applied to read the information in the memory cell.
  • FIG. 9B is a schematic cross-sectional view of a memory cell in another fusion memory according to an embodiment of the present disclosure.
  • a fusion memory is provided in FIG. 9B, including a plurality of memory cells 92, wherein the memory cell 92 includes: a bulk substrate; a source and a drain above the bulk substrate and between the source and drain regions The extended channel region; the first interface layer is located on the channel; the deep-level defect dielectric layer is located on the first interface layer; the gate is located on the deep-level defect dielectric layer.
  • the memory cell structure in this embodiment is basically similar to that in FIG. 9A, except that the first interface layer is provided between the deep-level defect dielectric layer and the channel region.
  • the first interface layer can be used to control the growth of deep-level defect materials, such as lattice orientation control or defect distribution.
  • the material of the first interface layer may be SiO 2 , SiN, SiON, AlO x , TiO 2 , HfO x or a combination thereof.
  • the material of the first interface layer may be SiO 2 ;
  • the thickness of an interface layer can be 0.3nm ⁇ 3nm; the material of the first interface layer is adjusted according to the ferroelectric layer material to be grown, for example, when the ferroelectric layer material is HfO x , the corresponding first interface layer material can be SiON; for example, when the ferroelectric layer material is SBT or PZT, the corresponding first interface layer material can be HfO x or AlO x .
  • FIG. 9C is a schematic cross-sectional view of a memory cell in another converged memory according to an embodiment of the present disclosure.
  • a fusion memory is provided in FIG. 9C, which includes a plurality of memory cells 93, wherein the memory cell 30 includes: a bulk substrate; source and drain above the bulk substrate and between the source and drain regions The extended channel region; the first interface layer is located on the channel; the deep-level defect dielectric layer is located on the first interface layer; the second interface layer is located on the deep-level defect dielectric layer; the gate, Located above the second interface layer.
  • the memory cell structure in this embodiment is basically similar to that in FIG. 9A, except that a first interface layer is provided between the deep-level defective dielectric layer and the channel region, the deep-level defective dielectric layer and the gate A second interface layer is arranged between.
  • the first interface layer can be used to control the growth of deep-level defect materials, such as lattice orientation control or defect distribution.
  • the second interface layer is used to isolate the mutual diffusion and interface damage between the metal gate and the storage layer.
  • the material of the first interface layer may be SiO 2 , SiN, SiON, AlO x , TiO 2 , HfO x or a combination thereof.
  • the material of the first interface layer may be SiO 2 ;
  • the thickness of an interface layer can be 0.3nm ⁇ 3nm; the material of the first interface layer is adjusted according to the ferroelectric layer material to be grown, for example, when the ferroelectric layer material is HfO x , the corresponding first interface layer material can be SiON; for example, when the ferroelectric layer material is SBT or PZT, the corresponding first interface layer material can be HfO x or AlO x .
  • the material of the second interface layer may be SiO 2 , SiN, SiON, AlO x , TiO 2 or HfO x .
  • the second interface layer material may be AlO x; thickness of the second interface layer may be 1nm ⁇ 10nm; second interface material layer is adjusted according to the ferroelectric layer and a gate material, for example, when the ferroelectric layer When the material is HfO x , the corresponding second interface layer material can be a SiO 2 /SiN/SiO 2 laminate; for example, when the ferroelectric layer material is SBT or PZT, the corresponding first interface layer material can be HfO x or AlO x .
  • FIG. 4 is a schematic diagram of the principle of the fusion memory implemented in the present disclosure.
  • the threshold voltage V T in the charge trap mode, when the gate voltage V G gradually increases, the threshold voltage V T also gradually increases. At point A, the scan voltage Is -5V, the corresponding threshold voltage V T is about -1.5V; when the scan voltage gradually rises and turns to a positive value, such as point B, the scan voltage is 1V, at this time the threshold voltage V T is about -1.1V, and Compared with point A, the threshold is increased, similarly, points C and D are in charge trapping mode.
  • a neural network computing system which includes:
  • the arithmetic array includes arithmetic units, and each arithmetic unit includes: a source terminal, a drain terminal, a gate, and a threshold voltage adjustment layer under the gate;
  • the gates of the arithmetic units in each column of the arithmetic array are connected together, and each column is used to determine the weight according to the threshold voltage adjusted by the threshold voltage adjustment layer;
  • the threshold voltage adjustment layer is a ferroelectric layer.
  • the traditional synaptic device at both ends of the memristor or three-terminal transistor is simulated.
  • Synaptic devices are generally connected to each other in a parallel NOR structure.
  • the calculation is completed by the way of current convergence.
  • the current generated by each terminal is measured in 10uA
  • the maximum parallel number of input X is about hundreds of magnitudes (the maximum current of Y terminal at the summary is about several mA)
  • the current generated by each terminal In terms of 1uA, the maximum parallel number of input X is about thousands of magnitudes.
  • the problem with this connection method is that the training power consumption is large and the number of parallelism is limited.
  • This type of structure has problems such as large operating current and high power consumption training, which limits the number of parallels.
  • the neural network operation system proposed by the embodiment of the present disclosure includes an operation array, wherein the operation units summarized by the array include a threshold voltage adjustment layer, and the adjustment layer material is a ferroelectric layer.
  • the arithmetic array includes arithmetic units, and each arithmetic unit includes: a source terminal, a drain terminal, and a gate, as well as a threshold voltage adjustment layer under the gate, and a channel region extending between the source and drain regions ,
  • the threshold voltage adjustment layer is located above the channel region; the gates of the arithmetic units of each column of the arithmetic array are connected together, and each column is used to adjust the weight according to the threshold voltage adjusted by the threshold voltage adjustment layer; the threshold voltage adjustment layer is Ferroelectric layer.
  • Figure 13 shows a three-terminal threshold-regulated synaptic device.
  • the threshold voltage is regulated by the modulation layer, so that the source-drain resistance can be regulated and used for synapses in neural networks.
  • the arithmetic units and the arithmetic units (synapses and synapses) in each row are connected in series.
  • X is an input terminal
  • the weight training is realized by applying a voltage to the X terminal.
  • the current during training is mainly the leakage current of the Gate terminal (in the order of pA), and the power consumption is small; optional, for the set first
  • the threshold voltage of the arithmetic unit in n rows and m columns can be determined by simultaneously applying voltage on the m-th column of the input terminal X and the n-th row of the array, that is, to jointly adjust the threshold voltage of the arithmetic unit to achieve a specific row and column Weight input.
  • V n is read, and the magnitude of V n is proportional to the sum of the synaptic resistance values of each row in series.
  • the current value when the structure is read is a constant value, and the number of parallels is not limited, which is conducive to building a super large-scale neural network.
  • V n represents the total output voltage of the nth row, i ranges from 1 to m, R m represents the current of the nth row and mth column, ⁇ is the transconductance of the transistor;
  • Xm is the gate terminal of the mth column (Corresponding to the input value of the neural network), Vth m is the threshold voltage of the arithmetic unit in the mth column and the nth row.
  • the gates of each column of the arithmetic array are used to input the value to be calculated, and the arithmetic units of each row of the arithmetic array are connected in series to output the calculated values of the arithmetic units of each row. output value.
  • the arithmetic units in each row are also connected in series with a summation circuit for adding and summing the operation results of each unit to form an output voltage value. That is, add up the output i ⁇ R m of each drain terminal in the above formula to obtain Vn.
  • the rear end of the summation circuit of each row further includes an analog-to-digital conversion circuit for converting the output voltage value of each row into the output value of the corresponding digital signal.
  • the ferroelectric layer material is doped HfOx, ZrOx, PZT, BFO or BST.
  • each arithmetic unit in the arithmetic array is constructed in a 3D stacking manner.
  • the absolute value of the voltage applied to the gate of each arithmetic unit is configured to be greater than the switching voltage at which the ferroelectric layer undergoes polarization inversion.
  • FIG. 14 is a block diagram of a neural network computing system according to an embodiment of the disclosure.
  • a typical neural network computing system 1400 may include an arithmetic array 1401, and may also include a control circuit 1402 and a reading circuit 1403.
  • the control circuit 1402 can control the arithmetic array to input and weight the weights of the arithmetic units in the array.
  • Value training adjustment you can control the grid voltage of the column where the arithmetic unit is located and/or the voltage of the row where the arithmetic unit is located), control the neural network operation (by inputting the voltage corresponding to the input value in the neural network at the X terminal), and control Read neural network calculation results (input a read current at the source terminal, output the total current/voltage at the end of each row in the series, and then determine the corresponding value through the summing circuit and analog-to-digital conversion circuit and output it to the reading circuit 1403) .

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Neurology (AREA)
  • Molecular Biology (AREA)
  • General Health & Medical Sciences (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Evolutionary Computation (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • Artificial Intelligence (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

一种融合型存储器，包括多个存储器单元（10），其中，所述存储器单元（10）包括：块体衬底；块体衬底上方的源极和漏极以及在源极和漏极区域之间延伸的沟道区；铁电层，位于沟道区之上；栅极，位于铁电层之上。该融合型存储器使存储单元能够在电荷俘获模式以及极化翻转模态下工作，因此，该融合型存储器兼具DRAM和NAND的功能，融合了两者的优点。

Description

融合型存储器 技术领域
本公开涉及存储器领域，进一步涉及一种融合型存储器。
背景技术
传统DRAM(动态随机存取存储器)采用1 T1C(1Transistor-1Capacitor，1晶体管-1电容器)的存储单元结构，当连接至晶体管栅极的字线选通时，晶体管选通，可以从位线上读取存储在电容器上的位信息；传统NAND则采用浮置栅极(floating gate)或者电荷俘获结构；它们一种是实现动态随机存储，一种是实现非易失性存储，所以说这两类存储器的制备工艺差别巨大，无法在一款片上芯片(SOC)里同时集成，因此无法融合两种存储器的优点，使得SOC芯片的存储容量和计算性能受到限制。
神经网络中，传统的突触器件两端忆阻器或三端晶体管模拟实现，突触器件一般采用并行NOR结构相互连接，在经过权值训练后，采用电流汇聚的方式来完成运算。该类结构存在操作电流大，功耗训练功耗大等问题，使并行数受限。
发明内容
有鉴于此，本公开的目的在于提供一种融合性存储器，以融合上述两种存储器的优点。
根据本公开的一方面，提供一种融合型存储器，包括多个存储器单元，其中，所述存储器单元包括：
块体衬底；
块体衬底上方的源极和漏极以及在源极和漏极区域之间延伸的沟 道区；
铁电层，位于沟道区之上；
栅极，位于铁电层之上。
根据本公开的另一方面，提供一种融合型存储器，包括多个存储器单元，其中，所述存储器单元包括：
块体衬底；
块体衬底上方的源极和漏极以及在源极和漏极区域之间延伸的沟道区；
第一界面层，位于沟道之上；
铁电层，位于第一界面层之上；
栅极，位于铁电层之上。
根据本公开的再一方面，提供一种融合型存储器，包括多个存储器单元，其中，所述存储器单元包括：
块体衬底；
块体衬底上方的源极和漏极以及在源极和漏极区域之间延伸的沟道区；
第一界面层，位于沟道之上；
铁电层，位于第一界面层之上；
第二界面层，位于铁电层之上；
栅极，位于第二界面层之上。
在进一步的实施方案中，所述铁电层材料为掺杂的HfO x，ZrO x，PZT，BFO或BST。
在进一步的实施方案中，铁电层层中的掺杂元素为Si，Zr，Hf，Al，Y，Gd，La，Sr，Ti，和/或N。
在进一步的实施方案中，还包括栅极电压控制器，该控制器电性连接至所述存储单元的栅极，用于控制栅极电压工作在第一电压，所述第一电压的绝对值小于铁电层发生极化翻转的翻转电压。
在进一步的实施方案中，还包括栅极电压控制器，该控制器电性连接至所述存储单元的栅极，用于控制栅极电压工作在第二电压，所述第 二电压的绝对值大于铁电层发生极化翻转的翻转电压。
在进一步的实施方案中，所述多个存储器单元形成3D堆叠结构
本公开的融合型存储器使存储单元能够在电荷俘模式以及极化翻转模态下工作，因此，该存储器兼具DRAM和NAND的功能，融合了两者的优点。
本公开的栅极电压控制器，能控制栅极电压工作在第一电压和第二电压，以使存储器分别工作电荷俘模式以及极化翻转模态，具有高效性以及灵活性。
附图说明
图1是本公开实施例的一种融合型存储器中存储器单元的截面示意图。
图2是本公开实施例的另一种融合型存储器中存储器单元的截面示意图。
图3是本公开实施例的再一种融合型存储器中存储器单元的截面示意图。
图4是本公开实施的融合型存储器的原理示意图。
图5是本公开实施例的用于融合型存储器的写入方法的示意图。
图6是本公开实施例的用于融合型存储器的擦除方法的示意图。
[根据细则26改正18.04.2019]　
图7A、7B和7C分别为本公开实施例的融合型存储器电荷俘获模式下的电压扫描曲线图、写入擦除示意图和读取示意图。
图8A、8B和8C分别为本公开实施例的融合型存储器铁电翻转模式下的单周期操作、多周期操作，以及写入擦除示意图。
图9A-9C分别为本公开实施例三种存储器的存储单元的截面示意图。
图10为一种神经网络运算装置的原理示意图。
图11为神经元构成示意图。
图12为本公开实施例的神经网路运算系统的原理示意图。
图13为图12中的神经网路运算系统中的一存储单元的示意图。
图14为本公开实施例的神经网络运算系统的方框图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开作进一步的详细说明。在下文中，将提供一些实施例以详细说明本公开的实施方案。本公开的优点以及功效将通过本公开下述内容而更为显著。在此说明所附附图简化过且做为例示用。附图中所示的组件数量、形状及尺寸可依据实际情况而进行修改，且组件的配置可能更为复杂。本公开中也可进行其他方面的实践或应用，且不偏离本公开所定义的精神及范畴的条件下，可进行各种变化以及调整。
本公开中的“之上”、“上方”、“之下”等用语，除非特别说明，是指存储器中的一半导体层结构位于另一半导体层结构的直接接触的上部，或者直接接触的下部，也就是说采用“之上”或“之下”进行描述时两个半导体层为直接接触，例如，“铁电层，位于沟道区之上”表示铁电层位于沟道区直接接触的上部；本公开中所指的“块体”，是指可以参与形成一个或多个存储单元的衬底或者阱材料。
根据本公开实施例的一方面，提供一种融合型存储器，包括多个存储单元，各存储单元中包含有铁电层，使存储单元能够在电荷俘模式以及极化翻转模态下工作，因此，该存储器兼具DRAM和NAND的功能，融合了两者的优点。
图1是本公开实施例的一种融合型存储器中存储器单元的截面示意图。图1中提供一种融合型存储器，包括多个存储器单元10，其中，存储器单元10包括：块体衬底；块体衬底上方的源极和漏极以及在源极和漏极区域之间延伸的沟道区；铁电层，位于沟道区之上；以及栅极，位于铁电层之上。
该实施例中的存储器单元包括沟道区和之上的铁电层，两者直接接触，通过调整施加于栅极的电压大小，可以使铁电层能够在电荷俘模式以及极化翻转模态下工作。
其中，图1中的铁电层在栅极和沟道之间用铁电层作为栅介质。该存储器可以工作在两种模式：一方面利用铁电材料中大量的晶格缺陷做电荷存储，使其可以工作在电荷俘获模式，通过俘获和释放电荷来存储数据；另一方面也可以工作在铁电翻转模式，通过极化翻转来存储数据。
在一些实施例中，该铁电层的材料可以是掺杂的HfO x，ZrO x,PZT,BFO或者BST，比较优选的为HfO x；掺杂种类可以是Si，Zr，Hf，Al，Y，Gd，La，Sr，Ti，和/或N等，优选的掺杂为Zr；掺杂含量介于10％～75％
在一些实施例中，该铁电层的厚度3nm～10nm；沟道的长度为5nm～200nm，沟道的宽度为5nm～500nm。
一些实施例中，上述的块体、源极、漏极和栅极可以按照现有的存储单元设置方式予以配置，相应的制备工艺也可以参照现有的工艺流程和参与予以执行。
在一些实施例中，融合型存储器中还包括控制电路，以及包括连接至各存储单元的栅极控制子电路，用于单独施加特定的第一电压至栅极，使栅极下方的铁电层俘获电子，在充电或者放电过程中改变阈值电压。该控制电路也可以集成于存储器的读写电路中，在读写过程中控制相应的电压脉冲值。读写电路根据CPU的读写指令，把内容以第一电压写入被访问的存储单元；或者从被访问的存储单元读出信息。该第一电压的绝对值应当小于铁电层中的铁电材料发生极化反转所需的翻转电压值，随着第一电压的上升，铁电层俘获的电子越多，存储单元的阈值电压会逐步上升。
在一些实施例中，该控制电路还用于单独施加特定的第二电压至栅极，使栅极电荷实现极化翻转，相应的改变了阈值电压，该阈值电压随着第二电压的增大，逐渐下降。读写电路根据CPU的读写指令，把内容以第二电压写入被访问的存储单元；或者从被访问的存储单元读出信息。该第二电压的绝对值应当大于铁电层中的铁电材料发生极化反转所需 的翻转电压值。
一些实施例中，根据存储器产品的要求，源极区和漏极区可以保持浮置状态，或者根据存储器的工作状态(写入、擦除或者读取)调整为对应的状态(正电压、负电压或者接地)。具体的调整方式可以参照下述的用于融合型存储器的写入方法实施例。
在一些实施例中，在一特定的程序中，上述控制电路能够控制施加于栅极的电压处于第一电压或者第二电压，也就是可以在一项进程同时出现两种电压模式，这样能够发挥DRAM和传统flash的两者的各自优势。
一些实施例中，本公开实施例的融合型存储器可以使用现有技术已知的字线、位线和源极线架构来设置存储单元阵列。字线耦合到相应的存储单元的栅极，位线耦合到相应的存储单元漏极，并且源极线耦合到相应的Fe存储单元源极。
一些实施例中，本公开实施例的融合型存储器还包括读出电路，用于读出各存储单元储存的信息，可以分别读出在极化翻转或者铁电层俘获电子模态下，通过施加较小的读出电压(例如0.6V)，以读出存储单元中的信息。
图2是本公开实施例的另一种融合型存储器中存储器单元的截面示意图。图2中提供一种融合型存储器，包括多个存储器单元20，其中，存储器单元20包括：块体衬底；块体衬底上方的源极和漏极以及在源极和漏极区域之间延伸的沟道区；第一界面层，位于沟道之上；铁电层，位于第一界面层之上；栅极，位于铁电层之上。
该实施例中的存储器单元结构与图1中的基本类似，不同之处仅在于在铁电层和沟道区之间设置有第一界面层。该第一界面层可以用于控制铁电材料的生长，如晶格取向控制或者缺陷分布。
在一些实施例中，该第一界面层的材料可以是SiO 2，SiN，SiON，AlO x，TiO 2或者HfO x，作为优选的，第一界面层材料可以是SiO 2；该第一界面层的厚度可以为0.3nm～3nm；第一界面层的材料根据需生长的铁电层材料而进行调整，例如当铁电层材料为HfO x时，对应的第一界 面层材料可以是SiON；例如当铁电层材料为SBT时，对应的第一界面层材料可以是HfO x或AlO x。
图3是本公开实施例的又一种融合型存储器中存储器单元的截面示意图。图3中提供一种融合型存储器，包括多个存储器单元30，其中，存储器单元30包括：块体衬底；块体衬底上方的源极和漏极以及在源极和漏极区域之间延伸的沟道区；第一界面层，位于沟道之上；铁电层，位于第一界面层之上；第二界面层，位于铁电层之上；栅极，位于第二界面层之上。
该实施例中的存储器单元结构与图1中的基本类似，不同之处仅在于在铁电层和沟道区之间设置有第一界面层，铁电层和栅极之间设置有第二界面层。该第一界面层可以用于控制铁电材料的生长，如晶格取向控制或者缺陷分布。该第二界面层用于隔绝金属栅与存储层之间的相互扩散和界面损伤。
在一些实施例中，该第一界面层的材料可以是SiO 2，SiN，SiON，AlO x，TiO 2，HfO x或者其组合，作为优选的，第一界面层材料可以是SiO 2；该第一界面层的厚度可以为0.3nm～3nm；第一界面层的材料根据需生长的铁电层材料而进行调整，例如当铁电层材料为HfO x时，对应的第一界面层材料可以是SiON；例如当铁电层材料为SBT或PZT时，对应的第一界面层材料可以是HfO x或AlO x。
在一些实施例中，该第二界面层材料可以是SiO 2，SiN，SiON，AlO x，TiO 2或者HfO x。作为优选的，第二界面层材料可以是AlO x；该第二界面层的厚度可以为1nm～10nm；第二界面层的材料根据铁电层以及栅极材料而进行调整，例如当铁电层材料为HfO x时，对应的第二界面层材料可以是SiO 2/SiN/SiO 2叠层；例如当铁电层材料为SBT或PZT时，对应的第一界面层材料可以是HfO x或AlO x。
上述实施例的融合型存储器中存储单元的工作原理可以参照图4所示。
图4是本公开实施的融合型存储器的原理示意图，如图4所示，在电荷捕获模式下，当栅极电压V G逐渐增加，阈值电压V T也逐渐增加， 在A点时，扫描电压为-5V，相应的阈值电压V T约为-1.5V；当扫描电压逐渐上升并转变为正值时，如B点，扫描电压为1V，此时阈值电压V T约为-1.1V，与A点时相比，阈值增大，类似的如C和D点，均处于电荷捕捉模式；当电压上升至4V，该电压超过铁电层内产生铁电翻转电压，此时发生铁电翻转，阈值电压下降，当再增加扫描电压时，阈值电压V T逐步下降，此时进入铁电翻转模式。
根据本公开实施例的另一方面，还提供一种用于融合型存储器的写入方法，该融合性存储器包括多个存储单元，各存储单元块体衬底；衬底上方的源极、漏极和源极漏极之间延伸的沟道区，以及沟道区上堆叠的铁电层和栅极。应当注意的是，这里的沟道区与铁电层之间可以不包含其他半导体层，也可以包含上述的第一界面层，且铁电层与沟道之间可以包括第二界面层或者两者直接接触，所以这里的存储单元可以是图1-3任一实施例所述描述的结构。本实施例的融合型存储的写入方法包括：
在至少一个的存储单元的栅极和块体之间施加第一电压，第一电压小于铁电层发生极化翻转的翻转电压；以及将
源极和栅极分别设置为接地或者为浮置状态。
图5是本公开实施例的用于融合型存储器的写入方法的示意图。图5中51所示，分别在存储单元的源极和漏极端保持零电位(如接地)或者为浮置状态，块体保持零电位(如接地)，此外，在栅极端施加第一电压，该第一电压小于铁电翻身极化翻转的翻转电压。该操作状态可参考图4中的电荷俘获模式，其在低电压区(小于翻转电压)完成，通过施加第一电压，引起电子充放电，从而引起阈值电压的变化，该变化过程较快，可达到20ns级编程速度，比传统的DRAM相比，速度更快，且电压也较低。
同时参考图7A-7C，如图7A所示，当电场被施加到存储单元(也就是含铁电层的晶体管)，铁电层中的结晶体中的中心原子顺着电场停留于低能态位置，在移去电场后，中心原子在低能态保持；当施加第一 电压时，铁电畴无翻转(第一电压位于非翻转的电压区间)。如图7B所示，可以控制正向的第一电压为3V，脉冲时间20nm，该过程中产生阈值变化，即实现数据的写入；通过与现有的DRAM比较，如图7B和图7C可知，其经过10 12以上的循环，阈值电压仍然小于传统的DRAM，且在85℃有1000秒以上的保持时间，速度与DRAM相当，保持特性大幅优于现有技术的DRAM。
在一些实施例中，融合型存储器的写入方法还可以包括如图5中示意的写入方式52，在至少一个的存储单元的栅极和块体之间施加第二电压，所述第二电压大于铁电层发生极化翻转的翻转电压；且源极为接地状态，栅极为正电压状态。该操作状态可参考图4中的铁电翻转模式，其在高电压区(大于翻转电压)完成，通过施加第二电压，引起铁电畴翻转，该过程的编程电压仍然小于传统的FLASH，且速度也较快，可达到20ns级编程速度。
在一些实施例中，对于第二电压的施加，参考图8A-8C所示，电场被施加到存储单元(也就是含铁电层的晶体管)，当施加第二电压时，铁电畴反转(第二电压大于翻转电压)。如图8B所示，可以控制正向的第二电压为6V，脉冲时间20nm，该过程中产生阈值变化，即实现数据的写入，同时产生铁电畴翻转；通过与现有的FLASH比较，如图8B和图8C可知，其经过多次的循环，阈值电压仍然小于传统的FLASH，且保持时间，速度与FLASH相当，编程电压远小于传统FLASH。
在一些实施例中，该实施例的写入方法还包括对写入存储单元的数据进行读取，例如图7C所示，可以施加较小的读取电压(例如-0.7V)，实现数据读取，此时阈值电压不发生变化。
图6是本公开实施例的用于融合型存储器的擦除方法的示意图。图6中61所示，分别在存储单元的源极和漏极端保持零电位(如接地)或者为浮置状态，块体保持零电位(如接地)，此外，在栅极端施加负值的第三电压，该第三电压的绝对值小于铁电翻身极化翻转的翻转电压。该操作状态可参考图4中的电荷俘获模式，其在低电压区(小于翻转电压)完成，通过施加第三电压，引起电子充放电，从而引起阈值电压的 变化，该变化过程较快，可达到20ns级擦除速度，比传统的DRAM相比，速度更快，且电压也较低。
同时参考图7A-7C，如图7A所示，当电场被施加到存储单元(也就是含铁电层的晶体管),铁电层中的结晶体中的中心原子顺着电场停留于低能态位置，在移去电场后，中心原子在低能态保持；当施加第三电压时，铁电畴无反转(第三电压位于非翻转的电压区间)。如图7B所示，可以控制正向的第三电压为-4V，脉冲时间20nm，该过程中产生阈值变化，即实现数据的擦除；通过与现有的DRAM比较，如图7B和图7C可知，其经过10 12以上的循环，阈值电压仍然小于传统的DRAM，且85度1000秒以上的保持时间，速度与DRAM相当，保持特性大幅优于传统DRAM。
在一些实施例中，融合型存储器的擦除方法还可以包括如图6中62示意的擦除方式，在至少一个的存储单元的栅极和块体之间施加第四电压，所述第四电压绝对值大于铁电层发生极化翻转的翻转电压；且块体为零电压(如接地状态)，栅极为负电压状态，漏极为接地或者浮置状态，源极为正电压状态。该操作状态可参考图4中的铁电翻转模式，其在高电压区(大于翻转电压)完成，通过施加第四电压，引起铁电池畴翻转，该过程的擦除电压仍然小于传统的FLASH，且速度也较快，可达到20ns级擦除速度。
在一些实施例中，对于第四电压的施加，参考图8A-8C所示，电场被施加到存储单元(也就是含铁电层的晶体管)，当施加第四电压时，铁电畴反转(第四电压绝对值大于翻转电压)。如图8B所示，可以控制反向的第四电压为-6V，脉冲时间20nm，该过程中产生阈值变化，即实现数据的擦除，同时产生铁电畴翻转；通过与现有的FLASH比较，如图8B和图8C可知，其经过多次的循环，阈值电压仍然小于传统的FLASH，且保持时间，速度与FLASH相当，擦除电压远小于传统FLASH。
根据本公开实施例的再一方面，提供一种存储器，该存储器包括多个存储单元，各存储单元中包含有深能级缺陷介质层，使存储单元能够 在电荷俘模式下工作，因此，该存储器具有DRAM的功能，同时操作电压远小于传统DRAM，且存储和擦除速度快。
图9A是本公开实施例的一种融合型存储器中存储器单元的截面示意图。图9A中提供一种融合型存储器，包括多个存储器单元91，其中，存储器单元10包括：块体衬底；块体衬底上方的源极和漏极以及在源极和漏极区域之间延伸的沟道区；深能级缺陷介质层，位于沟道区之上；以及栅极，位于深能级缺陷介质层之上。
该实施例中的存储器单元包括沟道区和之上的深能级缺陷介质层，两者直接接触，通过调整施加于栅极的电压大小，可以使深能级缺陷介质层能够在电荷俘模式以及极化翻转模态下工作。
其中，图9A中的深能级缺陷介质层在栅极和沟道之间用深能级缺陷介质层作为栅介质。该存储器可以利用深能级缺陷材料中大量的晶格缺陷做电荷存储，使其可以工作在电荷俘获模式，通过俘获和释放电荷来存储数据。
本公开实施例中所指的深能级缺陷介质层是指电荷陷阱能级1eV以上的介质层材料，如SiN，铁电材料等。
在一些实施例中，该铁电层的材料可以是掺杂的HfO x，ZrO x,PZT,BFO或者BST，比较优选的为HfO x；掺杂种类可以是Si，Zr，Hf，Al，Y，Gd，La，Sr，Ti，和/或N等，优选的掺杂为Zr；掺杂含量介于10％～75％。
在一些实施例中，该铁电层的厚度3nm～10nm；沟道的长度为5nm～200nm，沟道的宽度为5nm～500nm。
一些实施例中，上述的块体、源极、漏极和栅极可以按照现有的存储单元设置方式予以配置，相应的制备工艺也可以参照现有的工艺流程和参与予以执行。
在一些实施例中，融合型存储器中还包括控制电路，以及包括连接至各存储单元的栅极控制子电路，用于单独施加特定的第一电压至栅极，使栅极下方的深能级缺陷介质层俘获电子，在充电或者放电过程中改变阈值电压。该控制电路也可以集成于存储器的读写电路中，在读写过程中控制相应的电压脉冲值。读写电路根据CPU的读写指令，把内容以第 一电压写入被访问的存储单元；或者从被访问的存储单元读出信息。该第一电压的绝对值应当小于深能级缺陷介质层中的深能级缺陷材料发生极化反转所需的翻转电压值，随着第一电压的上升，深能级缺陷介质层俘获的电子越多，存储单元的阈值电压会逐步上升。
一些实施例中，根据存储器产品的要求，源极区和漏极区可以保持浮置状态，或者根据存储器的工作状态(写入、擦除或者读取)调整为对应的状态(正电压、负电压或者接地)。具体的调整方式可以参照上述的用于融合型存储器的写入方法中的实施例。
一些实施例中，本公开实施例的融合型存储器可以使用现有技术已知的字线、位线和源极线架构来设置存储单元阵列。字线耦合到相应的存储单元的栅极，位线耦合到相应的存储单元漏极，并且源极线耦合到相应的铁电存储单元源极。
一些实施例中，本公开实施例的融合型存储器还包括读出电路，用于读出各存储单元储存的信息，可以分别读出在深能级缺陷极化翻转或者深能级缺陷介质层俘获电子模态下，通过施加较小的读出电压(例如-0.7V，0V或0.7V)，以读出存储单元中的信息。
图9B是本公开实施例的另一种融合型存储器中存储器单元的截面示意图。图9B中提供一种融合型存储器，包括多个存储器单元92，其中，存储器单元92包括：块体衬底；块体衬底上方的源极和漏极以及在源极和漏极区域之间延伸的沟道区；第一界面层，位于沟道之上；深能级缺陷介质层，位于第一界面层之上；栅极，位于深能级缺陷介质层之上。
该实施例中的存储器单元结构与图9A中的基本类似，不同之处仅在于在深能级缺陷介质层和沟道区之间设置有第一界面层。该第一界面层可以用于控制深能级缺陷材料的生长，如晶格取向控制或者缺陷分布。
在一些实施例中，该第一界面层的材料可以是SiO 2，SiN，SiON，AlO x，TiO 2，HfO x或者其组合，作为优选的，第一界面层材料可以是SiO 2；该第一界面层的厚度可以为0.3nm～3nm；第一界面层的材料根据需生长的铁电层材料而进行调整，例如当铁电层材料为HfO x时，对应 的第一界面层材料可以是SiON；例如当铁电层材料为SBT或PZT时，对应的第一界面层材料可以是HfO x或AlO x。
图9C是本公开实施例的又一种融合型存储器中存储器单元的截面示意图。图9C中提供一种融合型存储器，包括多个存储器单元93，其中，存储器单元30包括：块体衬底；块体衬底上方的源极和漏极以及在源极和漏极区域之间延伸的沟道区；第一界面层，位于沟道之上；深能级缺陷介质层，位于第一界面层之上；第二界面层，位于深能级缺陷介质层之上；栅极，位于第二界面层之上。
该实施例中的存储器单元结构与图9A中的基本类似，不同之处仅在于在深能级缺陷介质层和沟道区之间设置有第一界面层，深能级缺陷介质层和栅极之间设置有第二界面层。该第一界面层可以用于控制深能级缺陷材料的生长，如晶格取向控制或者缺陷分布。该第二界面层用于隔绝金属栅与存储层之间的相互扩散和界面损伤。
在一些实施例中，该第一界面层的材料可以是SiO 2，SiN，SiON，AlO x，TiO 2，HfO x或者其组合，作为优选的，第一界面层材料可以是SiO 2；该第一界面层的厚度可以为0.3nm～3nm；第一界面层的材料根据需生长的铁电层材料而进行调整，例如当铁电层材料为HfO x时，对应的第一界面层材料可以是SiON；例如当铁电层材料为SBT或PZT时，对应的第一界面层材料可以是HfO x或AlO x。
在一些实施例中，该第二界面层材料可以是SiO 2，SiN，SiON，AlO x，TiO 2或者HfO x。作为优选的，第二界面层材料可以是AlO x；该第二界面层的厚度可以为1nm～10nm；第二界面层的材料根据铁电层以及栅极材料而进行调整，例如当铁电层材料为HfO x时，对应的第二界面层材料可以是SiO 2/SiN/SiO 2叠层；例如当铁电层材料为SBT或PZT时，对应的第一界面层材料可以是HfO x或AlO x。
上述实施例的融合型存储器中存储单元的工作原理可以参照图4所示的电荷捕捉模式部分。图4是本公开实施的融合型存储器的原理示意图，如图4所示，在电荷捕获模式下，当栅极电压V G逐渐增加，阈值电压V T也逐渐增加，在A点时，扫描电压为-5V，相应的阈值电压V T 约为-1.5V；当扫描电压逐渐上升并转变为正值时，如B点，扫描电压为1V，此时阈值电压V T约为-1.1V，与A点时相比，阈值增大，类似的如C和D点，均处于电荷捕捉模式。
根据本公开又一实施例的内容，提供一种神经网络运算系统，其中，包括：
运算阵列，包括运算单元，各运算单元包括：源极端、漏极端和栅极，以及栅极下方的阈值电压调整层；
运算阵列的每列运算单元的栅极接在一起，各列用于依据阈值电压调整层调整的阈值电压以确定权值；
阈值电压调整层为铁电层。
首先，如图10所示，一种神经网络运算装置中，神经网络中，传统的突触器件两端忆阻器或三端晶体管模拟实现，突触器件一般采用并行NOR结构相互连接，在经过权值训练后，采用电流汇聚的方式来完成运算。结合图10和图11所示，输出端Y的电流值为输入端X的电压值乘Y＝X×G以相应交叉端点突触的权值(电导)的求和值
Figure PCTCN2019073434-appb-000001
如图10中所示，每个端点所产生的电流以10uA计，输入X最大的并行数约为数百量级(汇总处Y端电流最大值约几mA)，每个端点所产生的电流以1uA计，输入X最大的并行数约为数千量级，这种连接方式的问题是训练功耗大，并行数受限。该类结构存在操作电流大，功耗训练功耗大等问题，使并行数受限。
基于上述陈述，如图12所示，本公开实施例提出的神经网络运算系统，包括运算阵列，其中阵列汇总的运算单元包括阈值电压调整层，该调整层材料为铁电层。
如图13所示，运算阵列包括运算单元，各运算单元包括：源极端、漏极端和栅极，以及栅极下方的阈值电压调整层，以及源极和漏极区域 之间延伸的沟道区，所述阈值电压调整层位于沟道区上方；运算阵列的每列运算单元的栅极接在一起，各列用于依据阈值电压调整层调整的阈值电压以调整权值；阈值电压调整层为铁电层。图13所示的为三端阈值调控突触器件，通过调制层调控阈值电压，使源漏电阻获得调控，从而用于神经网络中的突触。
图12中，各行的运算单元与运算单元(突触与突触)之间以串联的方式相互连。其中，X为一输入端，权值的训练通过在X端上施加电压实现，训练时的电流主要为Gate端的漏电流(pA量级)，功耗小；可选的，对于设定的第n行m列的运算单元的阈值电压的确定，可以通过同时在输入端X的第m列和阵列的第n行上同时施加电压，即以联合调整该运算单元的阈值电压，实现特定行列的权值输入。训练完毕后，通过在每条行线上施加一固定电流i，读取电压值V n，V n的大小与每行串联的突触电阻值和成正比。该结构读取时的电流值为一恒定值，并行数不受限制，有利于构建超大规模神经网络。
Figure PCTCN2019073434-appb-000002
上述公式中，V n表示第n行的总输出电压，i取值为1至m，R m表示第n行第m列的电流，β为晶体管的跨导；Xm为第m列的栅极端的输入(对应于神经网络的输入值)，Vth m为第m列第n行运算单元的阈值电压。
在一些实施例中，上述运算阵列的每列的栅极用于输入待运算值，所述运算阵列的每行的运算单元的串接在一起，用于输出每行的运算单元各自运算后的输出值。
在一些实施例中，每行的运算单元还串接有求和电路，用于对各单元运算结果进行加和形成输出电压值。也就是对上述公式中各漏极端的输出i×R m进行加和，求出Vn。
在一些实施例中，每行的求和电路后端还包括模数转换电路，用于 将各行的输出电压值转换为对应数字信号的输出值。
在一些实施例中，所述铁电层材料为掺杂的HfOx，ZrOx，PZT，BFO或BST。
在一些实施例中，所述运算阵列中的各运算单元采用3D堆叠方式构成。
在一些实施例中，所述施加于各运算单元栅极的电压绝对值配置为大于铁电层发生极化翻转的翻转电压。
图14为本公开实施例的神经网络运算系统的方框图。如图14所示，典型的神经网络运算系统1400可以包括运算阵列1401，还可以包括控制电路1402以及读取电路1403，其中控制电路1402可以控制运算阵列进行阵列中运算单元权值的输入以及权值的训练调整(可以通过控制运算单元所在列的栅极电压和/或运算单元所在行的电压)，控制进行神经网络运算(通过在X端输入神经网络中输入值对应的电压)，以及控制读取神经网络运算结果(在源极端输入一读取电流，在串行的各行最后输出总电流/电压，再通过求和电路和模数转换电路确定相应的数值并输出至读取电路1403)。
尽管本公开可以描述许多细节，但是这些不应该被解释为对所请求保护的发明或可以请求保护的发明的范围有所限制，而是作为特定实施例的特殊特征的描述。在单独实施例的上下文的本公开档中所描述的某些特征，也可以在单个实施例中组合实现。相反地，在单个实施例的上下文中所描述的各种特征，也可以在多个实施例中单独地或以任何合适的子组合来实现。再者，虽然上文可以将特征描述为在某些组合中作用并且甚至最初的权利要求范围所述，但是在一些情况下可以从所要求的组合中删除一个或多个特征，并且所请求保护的组合可以针对子组合或子组合的变异。类似地，虽然在附图中以特定次序来描述操作，但这不应被理解为该被要求按所示的特定次序或按顺序的次序来执行这样的操作，或者不应被理解该被要求执行所有示出的操作以实现期望的结果。
以上所述的具体实施例，对本公开的目的、技术方案和有益效果进 行了进一步详细说明，应理解的是，以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (8)

  1. 一种融合型存储器，包括多个存储器单元，其中，所述存储器单元包括：
    块体衬底；
    块体衬底上方的源极和漏极以及在源极和漏极区域之间延伸的沟道区；
    铁电层，位于沟道区之上；
    栅极，位于铁电层之上。
  2. 一种融合型存储器，包括多个存储器单元，其中，所述存储器单元包括：
    块体衬底；
    块体衬底上方的源极和漏极以及在源极和漏极区域之间延伸的沟道区；
    第一界面层，位于沟道之上；
    铁电层，位于第一界面层之上；
    栅极，位于铁电层之上。
  3. 一种融合型存储器，包括多个存储器单元，其中，所述存储器单元包括：
    块体衬底；
    块体衬底上方的源极和漏极以及在源极和漏极区域之间延伸的沟道区；
    第一界面层，位于沟道之上；
    铁电层，位于第一界面层之上；
    第二界面层，位于铁电层之上；
    栅极，位于第二界面层之上。
  4. 根据权利要求1-3任一所述的融合型存储器，其特征在于，所述铁电层材料为掺杂的HfO x，ZrO x，PZT，BFO或BST。
  5. 根据权利要求1-3任一所述的融合型存储器，其特征在于，铁电层层中的掺杂元素为Si，Zr，Hf，Al，Y，Gd，La，Sr，Ti，和/或N。
  6. 根据权利要求1-3任一所述的融合型存储器，其特征在于，还包括栅极电压控制器，该控制器电性连接至所述存储单元的栅极，用于控制栅极电压工作在第一电压，所述第一电压的绝对值小于铁电层发生极化翻转的翻转电压。
  7. 根据权利要求1-3任一所述的融合型存储器，其特征在于，还包括栅极电压控制器，该控制器电性连接至所述存储单元的栅极，用于控制栅极电压工作在第二电压，所述第二电压的绝对值大于铁电层发生极化翻转的翻转电压。
  8. 根据权利要求1-3任一所述的融合型存储器，其特征在于，所述多个存储器单元形成3D堆叠结构。
PCT/CN2019/073434 2019-01-28 2019-01-28 融合型存储器 WO2020154843A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2019/073434 WO2020154843A1 (zh) 2019-01-28 2019-01-28 融合型存储器
US17/424,998 US11776607B2 (en) 2019-01-28 2019-01-28 Fusion memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/073434 WO2020154843A1 (zh) 2019-01-28 2019-01-28 融合型存储器

Publications (1)

Publication Number Publication Date
WO2020154843A1 true WO2020154843A1 (zh) 2020-08-06

Family

ID=71839854

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/073434 WO2020154843A1 (zh) 2019-01-28 2019-01-28 融合型存储器

Country Status (2)

Country Link
US (1) US11776607B2 (zh)
WO (1) WO2020154843A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11545506B2 (en) * 2020-11-13 2023-01-03 Sandisk Technologies Llc Ferroelectric field effect transistors having enhanced memory window and methods of making the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040057274A1 (en) * 2002-09-19 2004-03-25 Klaus Dimmler Ferroelectric transistor for storing two data bits
US20050054166A1 (en) * 2003-09-09 2005-03-10 Sharp Laboratories Of America, Inc. Conductive metal oxide gate ferroelectric memory transistor
CN103165172A (zh) * 2011-12-09 2013-06-19 中国科学院微电子研究所 混合存储器件及其控制方法、制备方法
CN106537509A (zh) * 2014-07-23 2017-03-22 纳姆实验有限责任公司 电荷存储铁电存储器混合体和擦除方案

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5563081A (en) * 1992-03-23 1996-10-08 Rohm Co., Inc. Method for making a nonvolatile memory device utilizing a field effect transistor having a ferroelectric gate film
US5666305A (en) * 1993-03-29 1997-09-09 Olympus Optical Co., Ltd. Method of driving ferroelectric gate transistor memory cell
US6122191A (en) 1996-05-01 2000-09-19 Cypress Semiconductor Corporation Semiconductor non-volatile device including embedded non-volatile elements
US5969380A (en) * 1996-06-07 1999-10-19 Micron Technology, Inc. Three dimensional ferroelectric memory
JP3627640B2 (ja) 2000-09-22 2005-03-09 松下電器産業株式会社 半導体メモリ素子
US8304823B2 (en) * 2008-04-21 2012-11-06 Namlab Ggmbh Integrated circuit including a ferroelectric memory cell and method of manufacturing the same
EP3038141B1 (en) * 2014-12-23 2019-08-28 IMEC vzw Method of reading a memory cell of a vertical ferroelectric memory device
CN107924952A (zh) 2015-04-24 2018-04-17 Neo半导体公司 双功能混合存储单元
KR20190008048A (ko) * 2017-07-14 2019-01-23 에스케이하이닉스 주식회사 강유전성 메모리 소자
KR20190115508A (ko) * 2018-03-15 2019-10-14 에스케이하이닉스 주식회사 강유전성 메모리 장치
KR102578816B1 (ko) * 2018-03-16 2023-09-15 에스케이하이닉스 주식회사 강유전성 메모리 장치
US10403631B1 (en) * 2018-08-13 2019-09-03 Wuxi Petabyte Technologies Co., Ltd. Three-dimensional ferroelectric memory devices
US11251036B2 (en) * 2018-12-28 2022-02-15 Imec Vzw Semiconductor devices and methods of manufacturing semiconductor devices
KR20210085460A (ko) * 2019-12-30 2021-07-08 삼성전자주식회사 강유전성의 커패시터, 트랜지스터, 메모리 소자 및 강유전성의 커패시터의 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040057274A1 (en) * 2002-09-19 2004-03-25 Klaus Dimmler Ferroelectric transistor for storing two data bits
US20050054166A1 (en) * 2003-09-09 2005-03-10 Sharp Laboratories Of America, Inc. Conductive metal oxide gate ferroelectric memory transistor
CN103165172A (zh) * 2011-12-09 2013-06-19 中国科学院微电子研究所 混合存储器件及其控制方法、制备方法
CN106537509A (zh) * 2014-07-23 2017-03-22 纳姆实验有限责任公司 电荷存储铁电存储器混合体和擦除方案

Also Published As

Publication number Publication date
US20220093150A1 (en) 2022-03-24
US11776607B2 (en) 2023-10-03

Similar Documents

Publication Publication Date Title
US20200272343A1 (en) Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements
Jiang et al. Next-generation ferroelectric domain-wall memories: principle and architecture
US8891276B2 (en) Memory array with local bitlines and local-to-global bitline pass gates and gain stages
US20170323681A1 (en) Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
US8565003B2 (en) Multilayer cross-point memory array having reduced disturb susceptibility
US10566056B2 (en) Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
JP2008146740A (ja) 半導体記憶装置
JP2008016098A (ja) 半導体記憶装置
US10607678B2 (en) Apparatus and method for controlling erasing data in ferroelectric memory cells
US11347401B2 (en) Memory device including mixed non-volatile memory cell types
CN112101539B (zh) 一种存算一体电路及人工智能芯片
WO2020154839A1 (zh) 神经网络运算系统
CN109860190B (zh) 融合型存储器
WO2020154843A1 (zh) 融合型存储器
WO2020154844A1 (zh) 融合型存储器的写入、擦除方法
CN109887532B (zh) 融合型存储器的写入、擦除方法
CN109829540B (zh) 神经网络运算系统
WO2020154845A1 (zh) 存储器
CN109801977A (zh) 存储器
CN102800359B (zh) 一种半导体存储器件
CN216250002U (zh) 一种数据存储结构
WO2022110327A1 (zh) 神经元网络单元
US20230289577A1 (en) Neural network system, high density embedded-artificial synaptic element and operating method thereof
Bui Demonstration on Ferroelectric-gate Thin Film Transistor NAND-type Array with Disturbance-free Operation
CN117156861A (zh) 一种电荷俘获型可编程单电容非易失性存储器及其制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19913009

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19913009

Country of ref document: EP

Kind code of ref document: A1