WO2020150887A1 - 发光扫描驱动单元、阵列基板与输出发光扫描信号的方法 - Google Patents

发光扫描驱动单元、阵列基板与输出发光扫描信号的方法 Download PDF

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Publication number
WO2020150887A1
WO2020150887A1 PCT/CN2019/072646 CN2019072646W WO2020150887A1 WO 2020150887 A1 WO2020150887 A1 WO 2020150887A1 CN 2019072646 W CN2019072646 W CN 2019072646W WO 2020150887 A1 WO2020150887 A1 WO 2020150887A1
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Prior art keywords
pull
transistor
light
emitting
scan
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English (en)
French (fr)
Inventor
颜尧
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to PCT/CN2019/072646 priority Critical patent/WO2020150887A1/zh
Priority to CN201980073531.4A priority patent/CN113261048B/zh
Priority to US17/424,885 priority patent/US20220093046A1/en
Publication of WO2020150887A1 publication Critical patent/WO2020150887A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present invention relates to the field of display driving, in particular to scanning driving technology in image display.
  • the scanning driving circuit is required to provide the gate scanning signal and the light-emitting scanning signal to cooperate with the data driving circuit to provide the image data signal to drive the pixel array arranged in the image display area to perform image display.
  • gate scan drive circuits, light-emitting scan drive circuits, and pixel arrays have been fabricated on an array substrate, also known as GOA (Gateon Array, gate drive array substrate) and EOA ( Emission on Array) circuit.
  • Each scan driving circuit includes a plurality of scan driving units, which are usually designed in a cascade form to sequentially output the shifted scan signals to the pixel array.
  • each scan driving unit includes a GOA circuit and an EOA circuit.
  • GOA circuit and EOA circuit in the process of actually driving the pixel unit to perform the image display work, the phenomenon that the pixel unit consumes a lot of power may occur.
  • a light-emitting scan driving unit with lower power consumption is provided.
  • an array substrate including the aforementioned light-emitting scan driving unit.
  • the embodiment of the present invention discloses a light-emitting scan driving unit, and the light-emitting scan driving unit includes:
  • the pull-up control unit is configured to receive a first clock signal, and transmit the high-level reference voltage to the pull-up node according to the first clock signal in a scan period to control the pull-up point to a high state ;
  • a pull-up output unit which is electrically connected to the pull-up node, and when the pull-up point is in a high level state, transmits the received high reference voltage to the light-emitting scan terminal and outputs it as a light-emitting scan signal;
  • the pull-down control unit is electrically connected to the pull-down node and the pull-up node, and is configured to control the pull-up node to be in a low state and control the pull-down node to be in a high state during two non-overlapping time periods in one scan period Flat state
  • the pull-down output unit is electrically connected to the pull-down node and the light-emitting scan terminal, and is used to output the received low-level reference voltage to the light-emitting scan terminal when the pull-down node is in a high-level state. Luminous scanning signal output.
  • An embodiment of the present invention discloses an array substrate.
  • the array substrate includes a pixel unit and a scan drive circuit.
  • the scan drive circuit includes a plurality of scan drive units cascaded with each other.
  • the scan drive unit includes a gate scan line drive unit. And the aforementioned light-emitting scan driving unit.
  • the gate scan driving unit is used to output a gate scan signal, and the pixel unit emits light on the received data signal and performs image display under the driving of the gate scan signal and the light emission scan signal.
  • the embodiment of the present invention also discloses a method for outputting the light-emitting scan signal using the aforementioned light-emitting scan driving unit, which includes:
  • the high-level gate scan signal is provided to the pull-down control unit to control the pull-down node to be in a high-level state.
  • the pull-down output unit outputs the received low-level reference voltage to the light-emitting scanning terminal;
  • the pull-up output unit transmits the high-level reference voltage to the light-emitting scan terminal;
  • the pull-down control unit Corresponding to the data loading period of the pixel unit, provide the gate scan signal of a high level to the pull-down control unit to control the pull-down node to be in a high-level state, when the pull-down node is in a high-level state
  • the pull-down output unit outputs the received low-level reference voltage to the light-emitting scanning terminal
  • a first clock signal is provided to the pull-up control unit to control the pull-up node to be in a high-level state, and when the pull-up node is in a high-level state, the The pull-up output unit outputs the received high-level reference voltage to the light-emitting scanning terminal.
  • the light-emitting scan driving unit provides low-level light-emitting scan signals. Therefore, during the initialization period, the light-emitting scan signals can be controlled and received.
  • the pixel transistor of the driving voltage is in the off state, which can effectively ensure that the driving voltage terminal and the initialization voltage terminal are in an electrical disconnection state, and the two cannot form a conductive path, thereby effectively reducing the power consumption of each transistor and the capacitor device.
  • FIG. 1 is a schematic diagram of the layout structure of a scan driving circuit in an embodiment of the present invention
  • FIG. 2 is a schematic diagram of the circuit structure of the pixel unit shown in FIG. 1;
  • FIG. 3 is a schematic diagram of the working stage of the pixel unit shown in FIG. 2;
  • FIG. 4 is a schematic diagram of the circuit structure of the light-emitting scan driving unit shown in FIG. 1;
  • FIG. 5 is a working timing diagram of the light-emitting scan driving circuit shown in FIGS. 1 and 4;
  • FIGS. 1 and 4 are schematic diagrams of a flow chart of the light-emitting scan driving circuit shown in FIGS. 1 and 4 outputting light-emitting scan signals;
  • FIG. 7 is a working timing diagram of the pixel unit shown in FIG. 2.
  • the transistors used in all embodiments of the present invention are all N-type thin film transistors (Thin-filmtransistor, TFT) made by indium gallium zinc oxide (IGZO) or low temperature polysilicon (Low Temperature Poly-Silicon, LTPS). ). Of course, in other modified embodiments, the transistors can also be P-type thin film transistors, but not limited to this.
  • the pixel unit is an Organic Light-Emitting Diode (OLED) display unit.
  • FIG. 1 is a schematic diagram of the layout structure of the array substrate AY in an embodiment of the present invention.
  • the array substrate AY includes a pixel matrix 200 disposed in the display area and a scan driving circuit 100 disposed in the non-display area.
  • the scan driving circuit 100 is used to provide the pixel matrix 200 with scan pulse signals.
  • the scan driving circuit 100 includes a plurality of scan driving units 10 cascaded with each other, and the plurality of scan driving units 10 cascaded with each other are respectively connected to a plurality of sets of scan lines, and are used to sequentially provide multiple sets of scan lines in the pixel array 200
  • the scan signal wherein each group of scan lines includes a gate scan line Gk and a light-emitting scan line Ek, and k is any positive integer greater than 1 and less than 2N+2.
  • each scan driving unit 10 provides a gate scan signal and a light emitting scan signal to the corresponding gate scan line and light emitting scan line.
  • each scanning driving unit 10 outputs a gate scanning signal and a light-emitting scanning signal of one scanning period to a group of scanning lines connected to the scanning driving unit 10 in the driving and displaying of one frame of image.
  • each scan driving unit 10 includes a gate scan driving unit GOA and an emission scan driving unit EOA.
  • the gate scan driving unit GOA is used to output a gate scan signal
  • the light emitting scan driving unit EOA is used to output a light emitting scan signal.
  • the plurality of pixel units P in each row are driven by the gate scan signal and the light-emitting scan signal to perform light-emitting display according to the image data to be displayed, thereby displaying the image to be displayed.
  • the multiple scan driving units 10 are defined as two parts, which are respectively disposed on opposite sides of the pixel array 200.
  • each row of pixel units P corresponds to a scan driving unit 10, a gate scan line Gk and a light-emitting scan line Ek, and two adjacent gate scan lines and scan driving units corresponding to the light-emitting scan line are respectively disposed at The opposite sides of the pixel array 200, that is, the scan driving units 10 corresponding to the odd-numbered and even-numbered scan lines are respectively located on the opposite sides of the pixel array 200.
  • the gate scan driving units GOA1, GOA3, GOA5, GOA7..., GOA(N-2), GOAN, GOA(N+2)... is located on the right side of the pixel array 200; the gate scan lines G2, G4, G6...corresponding to the scan driving units GOA2, GOA4, GOA6, GOA8..., GOA(N-3 ), GOA(N-1), GOA(N+1)... are located on the left side of the pixel array 200.
  • EOA1, EOA3, EOA5, EOA7..., EOA(N-2), EOAN, EOA(N+2 ),... are located on the right side of the pixel array 200;
  • the even-numbered rows of light-emitting scan lines E2, E4, E6... correspond to the light-emitting scan driving units EOA2, EOA4, EOA6, EOA8..., EOA(N-3), EOA(N -1), EOA(N+1)... are located on the left side of the pixel array 200.
  • each scan driving unit 10 includes a driving enable terminal EN, a clock signal terminal CK, a gate scanning terminal Og, and a light-emitting scanning terminal Oe.
  • the driving enable terminal EN in each scan driving unit 10 is used to receive the start voltage STV and provide the start voltage STV to the gate scan driving unit GOA in the scan driving unit 10.
  • the clock signal terminal CK is used to receive multiple clock signals provided by the outside.
  • the clock signal terminal in each scan driving unit 10 includes a first clock signal terminal ECK (FIG. 4) and a second clock signal terminal ECKB ( Fig. 4), and two clock signals of the first clock signal ECKi and the second clock signal ECKBj are respectively received from the two clock signal terminals, where i is a positive integer less than 8 and j is a positive integer less than 4.
  • the gate scanning driving unit GOA outputs a gate scanning signal to the corresponding gate scanning line Gk through the gate scanning terminal Og
  • the light-emitting scanning driving unit EOA outputs a light-emitting scanning signal to the corresponding light-emitting scanning line Ek through the light-emitting scanning terminal Oe.
  • the gate scan driving unit 10 in the scan driving unit 10 at the first position The drive enable terminal EN of GOA1 is connected to the start voltage terminal STV-R to receive the start voltage STV (not labeled).
  • the gate scan terminal Og is connected to the first scan line G1 and also electrically connected to the drive enable of GOA3. End EN, and so on.
  • the drive enable terminal EN of GOA2 is connected to the start voltage terminal STV-L to receive the start voltage STV, and the gate scan terminal Og is connected to the second scan line G2 while also being combined It is electrically connected to the drive enable terminal EN of GOA4, and so on.
  • each adjacent 8 light-emitting scan driving units EOA is a group according to the arranged position, and respectively receives the first scan clock signals ECK1-ECK8 with 8 adjacent scan periods, and each adjacent 4 A group of the light-emitting scan driving unit EOA receives the second scan clock signals ECKB1-ECKB4 adjacent to 4 scan periods.
  • the four light-emitting scan driving units EOA are set as a group on the left and right sides according to the arrangement position, and respectively receive four first scan clock signals ECKi and two second scan clock signals ECKBj.
  • FIG. 2 is a schematic diagram of the circuit structure of any pixel unit P in the pixel matrix 200 shown in FIG. 1.
  • the pixel matrix 200 includes a plurality of pixel units P arranged in an array for performing image display.
  • any pixel unit P in the nth row has a 4T2C driving circuit structure composed of 4 transistors and 2 capacitors to drive an OLED display.
  • the pixel unit P includes a first pixel transistor TP1, a second pixel transistor TP2, a third pixel transistor TP3, a fourth pixel transistor TP4, a driving capacitor CP1, and an auxiliary capacitor CP2.
  • the gate of the first pixel transistor TP1 is electrically connected to the gate scanning line Gn, the drain is electrically connected to the data line (not labeled) to receive the data signal Vdata/Vref, and the source is electrically connected to the second pixel transistor The gate of TP2.
  • the gate of the third pixel transistor TP3 is electrically connected to the light-emitting scan line En, the drain is electrically connected to the driving voltage terminal ELVDD, and the source is electrically connected to the drain of the second pixel transistor TP2.
  • the source of the second pixel transistor TP2 is electrically connected to the anode terminal Anode of the light emitting element OLED.
  • the gate of the fourth pixel transistor TP4 is electrically connected to the gate scanning line Gn-1, the drain is electrically connected to the initialization voltage terminal Vinitial, and the source is electrically connected to the anode terminal Anode of the light-emitting element OLED.
  • the initialization voltage terminal Vinitial is used to provide the initialization voltage Vini.
  • the driving capacitor CP1 is electrically connected between the anode terminal Anode of the light-emitting element OLED and the gate of the second pixel transistor TP2.
  • the auxiliary capacitor CP2 is electrically connected between the anode terminal Anode of the light-emitting element OLED and the high-voltage driving terminal ELVDD.
  • the cathode of the light-emitting element OLED is electrically connected to the low-voltage driving terminal ELVSS.
  • each pixel unit P in the nth row it is necessary to perform the selection of the pixel unit by receiving gate scan signals from the gate scan lines Gn and Gn-1, and at the same time receive the light-emitting scan signal through the self-luminous scan line En to execute the image data Vdata Loading. That is, each pixel unit P needs the cooperation of at least three scanning signals to accurately perform the correct display of image data.
  • the pixel unit P includes an initialization period (Initial) t1, a compensation period (Com) t2, and a data loading period (Data ) t3 and the emission period (Emission) t4, that is, the initialization period t1, the compensation period t2, the data loading period t3, and the emission period t4 are continuous in time without interval and no overlap.
  • one scanning period of the pixel unit P is a working period of the pixel unit P in the process of displaying one frame of image.
  • FIG. 3 is a schematic diagram of the working stage of the pixel unit P. Now, the working process of the pixel unit P will be described in detail with reference to FIGS. 2 and 3.
  • the gate scan signals provided by the gate scan lines Gn and Gn-1 are both at a high level, and the initialization voltage Vini is provided to the anode terminal Anode of the light-emitting element OLED to perform initialization for the light-emitting element OLED and the driving capacitor. It is ensured that the remaining electrical signals in the pixel unit P in the previous scan period are discharged cleanly.
  • the compensation time period t2 it is necessary to provide a compensation voltage to the anode terminal Anode of the light-emitting element OLED to compensate for the offset of the threshold voltage Vth of each transistor in the pixel unit P and the aging offset of the light-emitting element OLED itself to ensure the pixel unit The correct display of P for the current image data and the consistency of the display of all pixel units P.
  • the image data Vdata to be displayed is loaded to the anode terminal Anode of the light emitting element OLED.
  • the icon symbol Vdata/Vref indicates that the image data Vdata and the reference voltage Vref are provided alternately in two adjacent time periods.
  • Dn-2, Dn-1, Dn, Dn+1, Dn+2 indicate that the The image data of the row.
  • the light-emitting element OLED emits light according to the image data Vdata to perform image display.
  • the initialization time period t1, the compensation time period t2, and the data loading time period t3 of the scan period of the pixel unit P in the n-1th row and the light emission in one scanning period of the pixel unit P in the nth row coincides in time.
  • FIG. 4 is a schematic diagram of the circuit structure of the light-emitting scan driving unit EOAN in any scan driving unit 10 shown in FIG. 1, and N is a positive integer.
  • the light emission scan driving unit EOA includes a pull-up control unit 11, a pull-up output unit 12, a pull-down control unit 13, and a pull-down output unit 14.
  • the pull-up control unit 11 is configured to receive the first clock signal ECKi, and transmit a high level to the pull-up node PU according to the first clock signal ECKi in one scan period to control the pull-up node PU to be high. Ping state.
  • the pull-up output unit 12 is electrically connected to the pull-up node PU, and is in a conductive state when the pull-up point PU is in a high-level state, so that the high-level reference voltage VGH received from the high-reference voltage terminal EVGH Transmitted to the light-emitting scanning terminal Oe.
  • the pull-down control unit 14 is electrically connected to the pull-down node PD and the pull-up node PU, and is configured to control the pull-up node PU to be at a low level in each of two non-overlapping time periods within one scan period State and control the pull-down node PD to be in a high level state.
  • controlling the pull-up node PU to be in a low level state and controlling the pull-down node PD to be in a high level state in each of two non-overlapping time periods within one scan period refers to two Control the pull-up node PU to be in a low level state and control the pull-down node PD to be in a high level state simultaneously in each of the non-overlapping time periods.
  • the high voltage reference state is that the voltage of the node is high and is sufficient to drive the corresponding transistor in the on state, for example, VGH is 5V
  • the low voltage reference state is that the voltage of the node is low. The voltage is not enough to maintain the transistor in the on state, for example, VGL is 0V.
  • the pull-down output unit 13 is electrically connected to the pull-down node PD and the light-emitting scanning terminal Oe, and is used for when the pull-down node PD is in a high-level state, the low-level reference received from the low-reference voltage terminal EVGL
  • the voltage VGL is output to the light-emitting scanning terminal Oe. Therefore, under the control of the pull-down control unit 13, a pulse (Pulse) at a low level is output through the light-emitting scanning terminal Oe during the two non-overlapping time periods.
  • two non-overlapping time periods in a scanning period in the low-level state of the light-emitting scan signal output by the light-emitting scan driving unit EOA are the initialization time period t1 and The data loading time period t3, and the time length of the initialization time period t1 is greater than the time length of the data loading time period t3.
  • the light-emitting scanning unit EOA can provide two non-overlapping low-level reference voltages in one scanning period, then, in the initialization period t1, the third pixel transistor TP3 in the pixel unit P is in an off state, even at a high level.
  • the gate scan signals provided by the gate scan lines Gn and Gn-1 are at a high level, and the driving voltage terminal ELVDD connected to the third pixel transistor TP3 in the pixel unit P is between the initialization voltage terminal Vinitial of the fourth pixel transistor TP4 In the open state, the two cannot form a conductive path, thereby effectively reducing the power consumption of each transistor and capacitive device.
  • the pull-up control unit 11 includes a first transistor M1, the gate and drain of the first transistor M1 are electrically connected to each other and receive the first clock signal ECKi, and the source of the first transistor M1 is electrically connected to the Pull up the node PU.
  • the pull-up output unit 12 includes a second transistor M2 and a first capacitor C1, the gate of the second transistor M2 is electrically connected to the pull-up node PU, and the drain of the second transistor M2 is electrically connected to a high reference voltage
  • the terminal EVGH receives the high reference voltage VGH, and the source of the second transistor M2 is electrically connected to the light-emitting scanning terminal Oe.
  • the first capacitor C1 is electrically connected between the pull-up node PU and the light-emitting scanning terminal Oe.
  • the pull-down output unit 13 includes a third transistor M3, the gate of the third transistor M3 is electrically connected to the pull-down node PD, the source of the third transistor M3 is electrically connected to the light-emitting scanning terminal Oe, and the third transistor M3 The drain of M3 is electrically connected to the low reference voltage terminal EVGL and receives the low level reference voltage VGL.
  • the pull-down control unit 14 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9.
  • the gate and drain of the fourth transistor M4 are electrically connected to each other and receive the second clock signal ECKBj, and the source of the fourth transistor M4 is electrically connected to the pull-up node PU.
  • the gate and drain of the seventh transistor M7 are electrically connected to each other and receive a gate scan signal corresponding to the gate scan line GN, and the source of the seventh transistor M7 is electrically connected to the gate of the fifth transistor M5.
  • the drain of the fifth transistor M5 is electrically connected to the gate of the seventh transistor M7 and receives the gate scan signal corresponding to the gate scan line GN, and the drain of the fifth transistor M5 is electrically connected to the pull-down node PD.
  • the gate of the sixth transistor M6 receives the second clock signal ECKBj, the drain of the sixth transistor M6 is electrically connected to the low reference voltage terminal EVGL and receives the low level reference voltage VGL, the sixth transistor M6 The source of the transistor M6 is electrically connected to the pull-down node PD.
  • the gate of the eighth transistor M8 receives the second clock signal ECKBj, the source of the eighth transistor M8 is electrically connected to the gate of the fifth transistor M5, and the drain of the eighth transistor M8 is electrically connected
  • the low reference voltage terminal EVGL also receives the low reference voltage VGL.
  • the second clock signal ECKBj cooperates with the fourth transistor M4, the sixth transistor M6, and the eighth transistor M8 to ensure that the pull-up node PU is in the low-parameter voltage state during the corresponding time period (compensation time period t2). It is reliably in the high level state, so that the light-emitting scanning terminal Oe accurately outputs the high reference voltage in the corresponding period.
  • the gate scan signal corresponding to the gate scan line GN cooperates with the fifth transistor M5 and the seventh transistor M7 to ensure that the pull-down node PD is in the high-parameter voltage state during the corresponding period.
  • the gate of the ninth transistor M9 is electrically connected to the pull-down node PD, the source of the ninth transistor M9 is electrically connected to the pull-up node PU, and the drain of the ninth transistor M9 is electrically connected to the The low reference voltage terminal EVGL and receives the low reference voltage VGL.
  • the ninth transistor M9 is used to ensure that when the pull-down node PD is in the high-parameter voltage state, the pull-up node PU is reliably in the low-level state, so that the light-emitting scanning terminal Oe accurately outputs the low-level state in the corresponding period Reference voltage.
  • FIGS. 5-6 where FIG. 5 is a working timing diagram of all the light-emitting scan driving units EOA shown in 1, 4, and FIG. 6 is a flow of outputting the light-emitting scan signal by all the light emitting scan driving units EOA shown in 1 and 4 Schematic.
  • the symbols in the figure represent the corresponding signals received in FIG. 4.
  • the light-emitting scanning unit EOA1 sorted in the first position is taken as an example to illustrate the working process.
  • the gate scan signal output by the gate scan line G1 is at a high level
  • the first clock signal ECK1 is at a low level
  • the second clock signal ECK1 is also at a low level
  • the pull-up control unit 11 The first transistor M1 is in the off state.
  • the seventh transistor M7 and the fifth transistor M5 are in the on state under the control of the gate scan signal output by the gate scan line G1.
  • the pull-down node PD corresponds to the gate
  • the gate scan signal output by the pole scan line G1 is in a high level state
  • the third transistor M3 in the pull-down output unit 13 is in a conductive state under the control of the pull-down node PD high level, thereby transmitting the low-level reference voltage VGL
  • the light-emitting scanning unit EOA1 outputs a low-level light-emitting scanning signal during the initialization period t1.
  • the sixth transistor M6 and the eighth transistor M8 in the pull-down control unit 14 are turned off under the low level control of the second clock signal ECKB1, and the ninth transistor M9 is turned on under the high level control of the pull-down node PD. Therefore, the low-level reference voltage VGL is transmitted to the pull-up node PU, so that the second transistor M2 in the pull-up unit 12 is in an off state, and the high-level reference voltage VGH is prevented from being transmitted to the light-emitting scan terminal Oe.
  • the gate scan signal output by the gate scan line G1 is at a high level
  • the first clock signal ECK1 is at a low level
  • the second clock signal ECKB1 is at a high level.
  • the fourth transistor M4 is in a conducting state, thereby pulling the pull-up node PU to a high level state.
  • the second transistor M2 in the pull-up unit 12 is in a conducting state, and the high-level reference voltage The VGH is transmitted to the light-emitting scanning terminal Oe, so that the light-emitting scanning unit EOA1 outputs a high-level light-emitting scanning signal during the compensation period t2.
  • the sixth transistor M6 and the eighth transistor M8 in the pull-down control unit 14 are controlled to be turned on at the high level of the second clock signal ECKB1, thereby transmitting the low-level reference voltage VGL to the pull-down node PD, so that the pull-down The node PD is in a low-level state, and the third transistor M3 in the pull-down output unit 13 is in a cut-off state, thereby stopping the transmission of the low-level reference voltage VGL to the light-emitting scan terminal Oe.
  • the ninth transistor M9 is in an off state under the control of the pull-down node PD.
  • the gate scan signal output by the gate scan line G1 is at a high level
  • the first clock signal ECK1 is at a low level
  • the second clock signal ECKB1 is at a low level.
  • the low-level reference voltage VGL is transmitted to the light-emitting scanning terminal Oe, that is, the light-emitting scanning unit EOA1 outputs a low-level light-emitting scanning signal during the data loading period t3.
  • the gate scan signal output by the gate scan line G1 is at a low level
  • the first clock signal ECK1 is at a high level
  • the second clock signal ECKB1 is at a low level.
  • the first transistor M1 is in a conductive state
  • the pull-up node PU is pulled up to a high-level state
  • the second transistor M2 is in a conductive state
  • the high-level reference voltage VGH is transmitted to the light-emitting scan terminal Oe Therefore, the light-emitting scanning unit EOA1 outputs a high-level light-emitting scanning signal in the light-emitting period t4.
  • the transistors in the pull-down control unit 14 and the pull-down output unit 13 are all in the off state, thereby stopping the transmission of the low-level reference voltage VGL to the light-emitting scanning terminal Oe, ensuring that the light-emitting scanning terminal Oe outputs accurate high-level light. Scan signal.
  • the luminescence scanning signal output by the luminescence scanning unit EOA1 includes two low-level reference voltage phases separated by a certain period of time in a scanning period, that is, during the initialization period t1 and data respectively in a scanning period
  • the loading time period t3 outputs a low level
  • the compensation time period t2 and the light emitting time period t4 output a high level, so as to effectively ensure that the pixel unit P loads the image data correctly, and can effectively reduce the power consumption of the pixel unit.
  • FIG. 7 is a working timing diagram of the pixel unit P shown in FIG. 2, where the pixel unit P is driven by the light-emitting scan signal output by the light-emitting scan driving unit EOAN shown in 4. Specifically, As shown in Figures 2 and 6:
  • the gate scan signals provided by the gate scan lines Gn and Gn-1 are both high voltages, and the light-emitting scan signals provided by the light-emitting scan lines En are low, then in the pixel unit P, the transistor TP3 is in the off state, the transistors TP1 and TP4 are in the on state, and the initialization voltage Vinitial is provided to the anode terminal Anode of the light emitting element OLED to perform initialization for the light emitting element OLED and the driving capacitor CP1.
  • the drive voltage terminal ELVDD and the initialization voltage terminal Vintial are in an electrically disconnected state, that is, no conductive path is formed between the drive voltage terminal ELVDD and the initialization voltage terminal Vintial.
  • the electronic components will not be in a conductive working state, but are in a non-power-consuming working state.
  • the auxiliary capacitor CP2 is in a non-conductive state. Therefore, it is in a non-working state, so the power consumption of the electronic components in the pixel unit P is reduced during this time period.
  • the gate scan signal provided by the gate scan line Gn is at a high level
  • the gate scan signal provided by the gate scan line Gn-1 is at a low level
  • the light emission provided by the light-emitting scan line En The scan signal is high.
  • the first pixel transistor TP1 and the third pixel TP3 in the pixel unit P are in the on state
  • the fourth pixel transistor TP4 is in the off state.
  • the threshold voltage of each transistor in the pixel unit P is performed on the anode terminal Anode of the light-emitting element OLED Vth offset and compensation of the aging offset of the light-emitting element OLED itself.
  • the gate scan signal provided by the gate scan line Gn is at a high level
  • the gate scan signal provided by the gate scan line Gn-1 is at a low level
  • the gate scan signal provided by the light-emitting scan line En The light-emitting scan signal is low.
  • the first pixel transistor TP1 in the pixel unit P is in an on state
  • the third pixel transistor TP3 and the fourth pixel transistor TP4 are in an off state
  • the data signal Vdata is loaded to the light through the first and second pixel transistors TP1 and TP2 and the driving capacitor CP1.
  • the gate scan signals provided by the two adjacent gate scan lines Gn-1 and Gn are at low level
  • the light-emitting scan signal provided by the light-emitting scan line En is at high level
  • the second pixel transistor TP2 and the third pixel transistor TP3 in P are in the on state
  • the first pixel transistor TP1 and the fourth pixel transistor TP4 are in the off state
  • the driving voltage provided by the driving voltage terminal ELVDD drives the light-emitting element according to the data signal Vdata
  • the OLED performs light emission to perform image display.

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Abstract

一种发光扫描驱动单元(EOA)，包括上拉控制单元(11)、上拉输出单元(12)、下拉控制单元(14)及下拉输出单元(13)。上拉控制单元(11)接收到第一时钟信号(ECKi)时将高电平参考电压传输至上拉节点(PU)以控制上拉点(PU)为高电平状态，同时上拉输出单元(12)在其为高电平状态时将高电平参考电压传输至发光扫描端(Oe)并作为发光扫描信号输出。下拉控制单元(14)电性连接下拉节点(PD)与上拉节点(PU)，在一个扫描周期内在两个不重叠的时间段控制上拉节点(PU)处于低电平状态及控制下拉节点(PD)处于高电平状态，下拉输出单元(13)在下拉节点(PD)处于高电平状态时将低电平参考电压输出至发光扫描端(Oe)。

Description

发光扫描驱动单元、阵列基板与输出发光扫描信号的方法 技术领域
本发明涉及一种显示驱动领域，具体涉及图像显示中的扫描驱动技术。
背景技术
对于自发光显示面板图像显示过程中，需要扫描驱动电路提供栅极扫描信号与发光扫描信号配合数据驱动电路提供图像数据信号驱动设置在图像显示区的像素阵列执行图像显示。近年来，为了提高显示面板的集成度，将栅极扫描驱动电路、发光扫描驱动电路与像素阵列一并制作于阵列基板上，亦称为GOA(Gateon Array，栅极驱动阵列基板)与EOA(Emission on Array)电路。
每个扫描驱动电路中包括多个扫描驱动单元，通常被设计成级联形式以依次输出移位后的扫描信号至像素阵列。其中，每个扫描驱动单元均包括一个GOA电路与一个EOA电路。但是现有的GOA电路与EOA电路在实际驱动像素单元执行图像显示工作的过程中会发生像素单元的功耗较大的现象。
发明内容
为解决前述问题，提供一种功耗较小的发光扫描驱动单元。
进一步，还提供一种包括前述发光扫描驱动单元的阵列基板。
本发明实施例公开了一种发光扫描驱动单元，所述发光扫描驱动单元包括：
上拉控制单元，用于接收第一时钟信号，并且在一个扫描周期内依据所述第一时钟信号将所述高电平参考电压传输至上拉节点以控制所述上拉点为高电平状态；
上拉输出单元，电性连接所述上拉节点，并且当所述上拉点为高电平状态时，将接收的高参考电压传输至发光扫描端并作为发光扫描信号输出；
下拉控制单元，电性连接下拉节点与所述上拉节点，用于在一个扫描周期内在两个不重叠的时间段控制所述上拉节点处于低电平状态以及控制所述下拉节点处于高电平状态；
下拉输出单元，电性连接于所述下拉节点以及所述发光扫描端，用于在所 述下拉节点处于高电平状态时，将接收的低电平参考电压输出至所述发光扫描端并作为发光扫描信号输出。
本发明实施例公开了一种阵列基板，所述阵列基板包括像素单元与扫描驱动电路，所述扫描驱动电路包括多个相互级联的扫描驱动单元，所述扫描驱动单元包括栅扫描线驱动单元以及前述的发光扫描驱动单元。所述栅极扫描驱动单元用于输出栅极扫描信号，所述像素单元在所述栅极扫描信号与发光扫描信号驱动下对接收的数据信号发光并且执行图像显示。
本发明实施例还公开一种采用前述发光扫描驱动单元输出所述发光扫描信号方法，包括：
对应像素单元的初始化时间段，提供高电平的所述栅极扫描信号至所述下拉控制单元以控制所述下拉节点处于高电平状态，当所述下拉节点处于高电平状态时，所述下拉输出单元将接收的低电平参考电压输出至所述发光扫描端；
对应所述像素单元的补偿时间段，提供高电平的所述第二时钟信号至所述下拉控制单元以控制所述下拉节点处于低电平状态以及控制所述上拉节点处于高电平状态，当所述上拉节点处于高电平状态时，所述上拉输出单元将所述高电平参考电压传输至发光扫描端；
对应所述像素单元的数据加载时间段，提供高电平的所述栅极扫描信号至所述下拉控制单元以控制所述下拉节点处于高电平状态，当所述下拉节点处于高电平状态时，所述下拉输出单元将接收的低电平参考电压输出至所述发光扫描端；
对应所述像素单元的发光时间段，提供第一时钟信号至所述上拉控制单元以控制所述上拉节点处于高电平状态，当所述上拉节点处于高电平状态时，所述上拉输出单元将接收的高电平参考电压输出至所述发光扫描端。
相较于现有技术，在像素单元对应的初始化时间段与数据加载时间段，发光扫描驱动单元均提供低电平的发光扫描信号，因此，在初始化时间段时，发光扫描信号能够控制与接收驱动电压的像素晶体管处于截止状态，从而能够有效保证驱动电压端与初始化电压端之间处于电性断路状态，也是二者无法形成导电通路，从而有效降低各个晶体管与电容器件的功耗。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一实施例中扫描驱动电路的布局结构示意图；
图2为如图1所示像素单元的电路结构示意；
图3为图2所示像素单元的工作阶段示意图；
图4为如图1所示发光扫描驱动单元的电路结构示意；
图5为图1、4所示发光扫描驱动电路的工作时序图；
图6为图1、4所示发光扫描驱动电路输出发光扫描信号的流程图示意图；
图7为图2所示像素单元的工作时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
下面结合附图，具体说明发光扫描驱动单元与包含有发光扫描驱动单元的阵列基板的电路结构及其工作过程。
本发明所有实施方式中采用的晶体管均为通过铟镓锌氧化物工艺(indium gallium zinc oxide,IGZO)或者低温多晶硅(Low Temperature Poly-Silicon，LTPS)制作的N型薄膜晶体管(Thin-filmtransistor，TFT)。当然，在其他变更实施例中，晶体管还可以为P型薄膜晶体管，并不以此为限，像素单元为有机发光二极管(Organic Light-Emitting Diode,OLED)显示单元。
请参阅图1，其为本发明一实施例中阵列基板AY布局结构示意图。
如图1所示，阵列基板AY包括设置于显示区内的像素矩阵200以及设置于非显示区的扫描驱动电路100，其中，扫描驱动电路100用于为像素矩阵200提 供扫描脉冲信号。
扫描驱动电路100包括相互级联的多个扫描驱动单元10，所述相互级联的多个扫描驱动单元10与多组扫描线分别连接，用于依次向像素阵列200中的多组扫描线提供扫描信号，其中，每一组扫描线包括一条栅极扫描线Gk与一条发光扫描线Ek，k为大于1小于2N+2的任意一个正整数。对应地，每个扫描驱动单元10向与其对应的栅极扫描线与发光扫描线提供栅极扫描信号与发光扫描信号。其中，每个扫描驱动单元10在一帧图像的驱动显示中输出一个扫描周期的栅极扫描信号与发光扫描信号至与该扫描驱动单元10连接的一组扫描线。
本实施例中，每个扫描驱动单元10包括栅极扫描驱动单元GOA与发光扫描驱动单元EOA。其中，栅极扫描驱动单元GOA用于输出栅极扫描信号，而发光扫描驱动单元EOA用于输出发光扫描信号。每一行中的多个像素单元P在栅极扫描信号与发光扫描信号配合驱动下依据待显示的图像数据进行发光显示，从而显示所述待显示图像。
多个扫描驱动单元10定义为两部分，分别设置于像素阵列200的相对两侧。具体地，每一行像素单元P分别对应一个扫描驱动单元10、一条栅极扫描线Gk与发光扫描线Ek，并且相邻的两条栅极扫描线与发光扫描线对应的扫描驱动单元分别设置于像素阵列200的相对两侧，也即是奇数行、偶数行扫描线对应的扫描驱动单元10分别位于像素阵列200的相对两侧。例如，以栅极扫描线来说，奇数行的栅极扫描线G1、G3、G5……对应的栅极扫描驱动单元GOA1、GOA3、GOA5、GOA7……、GOA(N-2)、GOAN、GOA(N+2)、……位于像素阵列200的右边；偶数行的栅极扫描线G2、G4、G6……对应的扫描驱动单元GOA2、GOA4、GOA6、GOA8……、GOA(N-3)、GOA(N-1)、GOA(N+1)……位于像素阵列200的左边。以发光扫描线来说，奇数行的发光扫描线E1、E3、E5……对应的发光扫描驱动单元EOA1、EOA3、EOA5、EOA7……、EOA(N-2)、EOAN、EOA(N+2)、……位于像素阵列200的右边；偶数行的发光扫描线E2、E4、E6……对应的发光扫描驱动单元EOA2、EOA4、EOA6、EOA8……、EOA(N-3)、EOA(N-1)、EOA(N+1)……位于像素阵列200的左边。
其中，每个扫描驱动单元10包括驱动使能端EN、时钟信号端CK、栅极扫描端Og与发光扫描端Oe。发光扫描端相互级联时，奇数行扫描线对应的扫描 驱动单元依次级联，而偶数行扫描线对应的扫描驱动单元10依次相互级联。其中，每个扫描驱动单元10中的驱动使能端EN用于接收启动电压STV，并且将启动电压STV提供给该扫描驱动单元10中的栅极扫描驱动单元GOA。时钟信号端CK用于接收外部提供的多个时钟信号，本实施例中，每个扫描驱动单元10中的时钟信号端包括第一时钟信号端ECK(图4)与第二时钟信号端ECKB(图4)，并且自该两个时钟信号端分别接收第一时钟信号ECKi与第二时钟信号ECKBj两个的时钟信号，其中，i为小于8的正整数，j为小于4的正整数。栅极扫描驱动单元GOA通过栅极扫描端Og输出栅极扫描信号至对应的栅极扫描线Gk，发光扫描驱动单元EOA通过发光扫描端Oe输出发光扫描信号至对应的发光扫描线Ek。
具体的，以奇数行扫描线对应的扫描驱动单元10为例，即以图1中的右边的多个扫描驱动单元10为例，处于第一位置的扫描驱动单元10中的栅极扫描驱动单元GOA1的驱动使能端EN与启动电压端STV-R连接以接收启动电压STV(未标示)，栅极扫描端Og连接第一个扫描线G1的同时还一并电性连接GOA3的驱动使能端EN，以此类推。对应地，对于左边的多个扫描驱动单元10，GOA2的驱动使能端EN连接启动电压端STV-L以接收启动电压STV，栅极扫描端Og连接第二个扫描线G2的同时还一并电性连接GOA4的驱动使能端EN，以此类推。
扫描驱动电路100中按照排列的位置每相邻的8个发光扫描驱动单元EOA为一组，且分别接收8个扫描周期相邻的第一扫描时钟信号ECK1-ECK8，同时每相邻的4个发光扫描驱动单元EOA一组分别接收4个扫描周期相邻的第二扫描时钟信号ECKB1-ECKB4。本实施例中，左右两侧则按照排列位置将4个发光扫描驱动单元EOA设为一组，分别接收4个第一扫描时钟信号ECKi以及2个第二扫描时钟信号ECKBj。
具体地，请参阅图2，其为图1所示的像素矩阵200中任意一个像素单元P的电路结构示意图。所述像素矩阵200包括若干呈阵列分布、用于执行图像显示的像素单元P。如图2所示，第n行中任意一个像素单元P为包括4个晶体管与2个电容构成的4T2C驱动OLED显示的驱动电路结构。
具体地，像素单元P包括第一像素晶体管TP1、第二像素晶体管TP2、第三 像素晶体管TP3、第四像素晶体管TP4、驱动电容CP1以及辅助电容CP2。
其中，第一像素晶体管TP1的栅极电性连接至栅极扫描线Gn，漏极电性连接至数据线(未标示)以接收数据信号Vdata/Vref，源极电性连接至第二像素晶体管TP2的栅极。
第三像素晶体管TP3的栅极电性连接至发光扫描线En，漏极电性连接至驱动电压端ELVDD，源极电性连接至第二像素晶体管TP2的漏极。
第二像素晶体管TP2的源极电性连接至发光元件OLED的阳极端Anode。
第四像素晶体管TP4的栅极电性连接至栅极扫描线Gn-1，漏极电性连接至初始化电压端Vinitial，源极电性连接至发光元件OLED的阳极端Anode。其中，初始化电压端Vinitial用于提供初始化电压Vini。
驱动电容CP1电性连接在发光元件OLED的阳极端Anode与第二像素晶体管TP2的栅极之间。
辅助电容CP2电性连接在发光元件OLED的阳极端Anode与高压驱动端ELVDD之间。
发光元件OLED的阴极电性连接低压驱动端ELVSS。
对于第n行中的像素单元P，需要通过自栅极扫描线Gn与Gn-1接收栅极扫描信号来执行像素单元的选择，同时通过自发光扫描线En接收发光扫描信号来执行图像数据Vdata的加载。也即是，每个像素单元P至少需要三个扫描信号的配合才能够准确执行图像数据的正确显示。
同时，为了准确执行图像数据的显示，像素单元P在一个扫描周期内包括在时间上连续无间隔的间断的初始化时间段(Initial)t1、补偿时间段(Com)t2、数据加载时间段(Data)t3以及发光时间段(Emission)t4，也即是说，初始化时间段t1、补偿时间段t2、数据加载时间段t3以及发光时间段t4在时间上连续无间隔并且无重叠。其中，所述像素单元P的一个扫描周期为显示一帧图像的过程中，像素单元P的工作周期。
请参阅图3，其为像素单元P的工作阶段示意图，现结合图2与图3具体说明像素单元P的工作过程。
在初始化时间段t1，栅极扫描线Gn与Gn-1提供的栅极扫描信号均为高电 平，初始化电压Vini提供至发光元件OLED阳极端Anode，以针对发光元件OLED以及驱动电容执行初始化，保证像素单元P中的残留的前一次扫描周期中的电信号释放干净。
在补偿时间段t2，提供需要提供补偿电压至发光元件OLED的阳极端Anode，以补偿由于像素单元P中各晶体管阈值电压Vth偏移以及发光元件OLED本身的老化偏移进行补偿，以保证像素单元P的针对当前图像数据的正确显示以及全部像素单元P显示的一致性。
在数据加载时间段t3，待显示的图像数据Vdata加载至发光元件OLED的阳极端Anode。其中，图标符号Vdata/Vref表示图像数据Vdata与参考电压Vref在相邻的2个时间段交替提供，同时，Dn-2、Dn-1、Dn、Dn+1、Dn+2则表示提供到不同行的图像数据。
在发光时间段t4，在待显示的图像数据Vdata加载完成以后，发光元件OLED则依据图像数据Vdata进行发光从而执行图像显示。
需要说明的是，第n行中的像素单元P中一个扫描周期中的初始化时间段t1、补偿时间段t2与第n-1行中的像素单元P的扫描周期的数据加载时间段t3以及发光时间段t4在时间上重合。
具体地，请参阅图4，其为图1所示任意一个扫描驱动单元10中发光扫描驱动单元EOAN的电路结构示意图，N为正整数。
如图4所示，发光扫描驱动单元EOA包括上拉控制单元11、上拉输出单元12、下拉控制单元13、下拉输出单元14。
其中，上拉控制单元11用于接收第一时钟信号ECKi，并且在一个扫描周期内依据所述第一时钟信号ECKi将高电平传输至上拉节点PU以控制所述上拉节点PU为高电平状态。
上拉输出单元12电性连接所述上拉节点PU，并且当所述上拉点PU为高电平状态时处于导通状态，以将从高参考电压端EVGH接收的高电平参考电压VGH传输至发光扫描端Oe。
下拉控制单元14，电性连接下拉节点PD与所述上拉节点PU，用于在一个扫描周期内在两个不重叠的时间段中的每一个时间段控制所述上拉节点PU处 于低电平状态以及控制所述下拉节点PD处于高电平状态。
较佳地，所述两个不重叠的时间段的时间长度不同。其中，在一个扫描周期内在两个不重叠的时间段中的每一个时间段控制所述上拉节点PU处于低电平状态以及控制所述下拉节点PD处于高电平状态指的是，两个不重叠的时间段中的每一个时间段内同时控制所述上拉节点PU处于低电平状态以及控制所述下拉节点PD处于高电平状态。
本实施例中，所述高电压参考状态为所述节点的电压为高电平并且足以驱动对应的晶体管处于导通状态，例如VGH为5V，低电压参考状态则为所述节点的电压为低电压且不足以将晶体管维持在导通状态，例如VGL为0V。
下拉输出单元13，电性连接于所述下拉节点PD以及所述发光扫描端Oe，用于在所述下拉节点PD处于高电平状态时，将从低参考电压端EVGL接收的低电平参考电压VGL输出至所述发光扫描端Oe。从而对应下拉控制单元13的控制下在该两个不重叠的时间段通过发光扫描端Oe输出处于低电平的脉冲(Pulse)。
本实施例中，如图3-4所示，发光扫描驱动单元EOA输出的发光扫描信号中处于低电平状态的在一个扫描周期内两个不重叠的时间段依次分别为初始化时间段t1与数据加载时间段t3，且所述述初始化时间段t1的时间长度大于所述数据加载时间段t3的时间长度。
由于发光扫描单元EOA能够在一个扫描周期中提供两个不重叠的低电平参考电压，那么，在初始化时间段t1，像素单元P中的第三像素晶体管TP3处于截止状态，即使在高电平的栅极扫描线Gn与Gn-1提供的栅极扫描信号处于高电平，像素单元P中与第三像素晶体管TP3连接的驱动电压端ELVDD与第四像素晶体管TP4初始化电压端Vinitial之间为断路状态，也是二者无法形成导电通路，从而有效降低各个晶体管与电容器件的功耗。
更为具体地，如图4所示：
上拉控制单元11包括第一晶体管M1，第一晶体管M1的栅极与漏极相互电性连接并且接收所述第一时钟信号ECKi，所述第一晶体管M1的源极电性连接至所述上拉节点PU。
上拉输出单元12包括第二晶体管M2与第一电容C1，所述第二晶体管M2的栅极电性连接所述上拉节点PU，所述第二晶体管M2的漏极电性连接至高参考电压端EVGH以接收高参考电压VGH，所述第二晶体管M2的源极电性连接所述发光扫描端Oe。所述第一电容C1电性连接于所述上拉节点PU与所述发光扫描端Oe之间。
下拉输出单元13包括第三晶体管M3，所述第三晶体管M3的栅极电性连接所述下拉节点PD，第三晶体管M3的源极电性连接所述发光扫描端Oe，所述第三晶体管M3的漏极电性连低参考电压端EVGL并且接收所述低电平参考电压VGL。
下拉控制单元14包括第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8与第九晶体管M9。
第四晶体管M4的栅极与漏极相互电性连接并且接收所述第二时钟信号ECKBj，所述第四晶体管M4的源极电性于所述上拉节点PU。
第七晶体管M7的栅极与漏极相互电性连接并且接收栅极扫描线GN对应的栅极扫描信号，所述第七晶体管M7的源极电性连接所述第五晶体管M5的栅极。
第五晶体管M5漏极电性连接所述第七晶体管M7的栅极并且接收栅极扫描线GN对应的栅极扫描信号，所述第五晶体管M5的漏极电性连接所述下拉节点PD。
第六晶体管M6的栅极接收所述第二时钟信号ECKBj，所述第六晶体管M6的漏极电性连接所述低参考电压端EVGL并且接收所述低电平参考电压VGL，所述第六晶体管M6的源极电性连接所述下拉节点PD。
第八晶体管M8的栅极接收所述第二时钟信号ECKBj，所述第八晶体管M8的源极电性连接所述第五晶体管M5的栅极，所述第八晶体管M8的漏极电性连接所述低参考电压端EVGL并且接收所述低电平参考电压VGL。
所述第二时钟信号ECKBj配合第四晶体管M4、第六晶体管M6以及第八晶体管M8用于保证在对应的时间段(补偿时间段t2)下拉节点PD处于低参电压状态时，上拉节点PU可靠地处于高电平状态，从而使得发光扫描端Oe准确地在相应的时段输出高参考电压。
栅极扫描线GN对应的栅极扫描信号配合第五晶体管M5与第七晶体管M7保证在对应的时段下拉节点PD处于高参电压状态。
所述第九晶体管M9的栅极电性连接所述下拉节点PD，所述第九晶体管M9的源极电性连接所述上拉节点PU，所述第九晶体管M9的漏极电性连接所述低参考电压端EVGL并且接收所述低电平参考电压VGL。其中，所述第九晶体管M9用于保证当下拉节点PD处于高参电压状态时，上拉节点PU可靠地处于低电平状态，从而使得发光扫描端Oe准确地在相应的时段输出低电平参考电压。
请参阅图5-6，其中，图5为1、4所示全部发光扫描驱动单元EOA的工作时序图，图6为1、4所示全部发光扫描驱动单元EOA输出所述发光扫描信号的流程示意图。其中，图中的符号表示为图4中所接收的相应的信号。本实施例中，以排序在第一位置的发光扫描单元EOA1为例说明其工作过程。
其中，对于发光扫描单元EOA1在第一帧图像扫描期间1stFrame时，
在初始化时间段t1，栅极扫描线G1输出的栅极扫描信号为处于高电平，第一时钟信号ECK1为低电平，第二时钟信号ECKB1也处于低电平，则上拉控制单元11中第一晶体管M1处于截止状态，下拉控制单元14中，第七晶体管M7与第五晶体管M5在栅极扫描线G1输出的栅极扫描信号控制下处于导通状态，则下拉节点PD则对应栅极扫描线G1输出的栅极扫描信号处于高电平状态，下拉输出单元13中第三晶体管M3则在下拉节点PD高电平的控制下处于导通状态，从而将低电平参考电压VGL传输至发光扫描端Oe，从而在初始化时间段t1发光扫描单元EOA1输出低电平的发光扫描信号。
与此同时，下拉控制单元14中第六晶体管M6与第八晶体管M8在第二时钟信号ECKB1低电平控制处于截止状态，第九晶体管M9则在下拉节点PD高电平的控制下处于导通状态，从而将低电平参考电压VGL传输至上拉节点PU，使得上拉单元12中的第二晶体管M2处于截止状态，防止高电平参考电压VGH传输至发光扫描端Oe。
在补偿时间段t2，栅极扫描线G1输出的栅极扫描信号为处于高电平，第一时钟信号ECK1为低电平，第二时钟信号ECKB1处于高电平。下拉控制单元14中，第四晶体管M4处于导通状态，从而将上拉节点PU拉高至高电平状态， 对应地，上拉单元12中第二晶体管M2处于导通状态，高电平参考电压VGH传输至发光扫描端Oe，从而在补偿时间段t2发光扫描单元EOA1输出高电平的发光扫描信号。
与此同时，下拉控制单元14中的第六晶体管M6与第八晶体管M8在第二时钟信号ECKB1高电平控制处于导通状态，从而将低电平参考电压VGL传输至下拉节点PD，使得下拉节点PD处于低电平状态，下拉输出单元13中的第三晶体管M3处于截止状态，从而停止将低电平参考电压VGL传输至发光扫描端Oe。
第九晶体管M9在下拉节点PD的控制下处于截止状态。
在数据加载时间段t3，栅极扫描线G1输出的栅极扫描信号为处于高电平，第一时钟信号ECK1为低电平，第二时钟信号ECKB1处于低电平，那么则与初始化时间段t1相同，低电平参考电压VGL传输至发光扫描端Oe，也即是在数据加载时间段t3发光扫描单元EOA1输出低电平的发光扫描信号。
在发光时间段t4，栅极扫描线G1输出的栅极扫描信号为处于低电平，第一时钟信号ECK1为高电平，第二时钟信号ECKB1处于低电平。上拉控制单元11中第一晶体管M1处于导通状态，则上拉节点PU则被拉高至高电平状态，第二晶体管M2处于导通状态，高电平参考电压VGH传输至发光扫描端Oe，从而在发光时间段t4发光扫描单元EOA1输出高电平的发光扫描信号。
与此同时，下拉控制单元14以及下拉输出单元13中各晶体管均处于截止状态，从而停止将低电平参考电压VGL传输至发光扫描端Oe，保证发光扫描端Oe输出准确的高电平的发光扫描信号。
至此，明显可见，发光扫描单元EOA1输出的发光扫描信号在一个扫描周期内包括两个相互间隔一定时长的低电平参考电压阶段，也即是在一个扫描周期内分别在初始化时间段t1与数据加载时间段t3输出低电平，而在补偿时间段t2与发光时间段t4输出高电平，以有效保证像素单元P正确加载图像数据，并且能够有效降低像素单元的功耗。
第二帧图像扫描期间2stFrame与第一帧图像扫描期间1stFrame工作过程以及显示原理相同。
请一并参阅图2、7，其中图7为图2所示像素单元P的工作时序图，其中， 像素单元P采用如4所示发光扫描驱动单元EOAN输出的发光扫描信号驱动，具体的，如图2、6所示：
在步骤601的初始化时间段t1，栅极扫描线Gn与Gn-1提供的栅极扫描信号均为高电压，发光扫描线En提供的发光扫描信号为低电平，则像素单元P中，晶体管TP3处于截止状态，晶体管TP1、TP4处于导通状态，初始化电压Vinitial提供至发光元件OLED阳极端Anode，以针对发光元件OLED以及驱动电容CP1执行初始化。此时间段中，驱动电压端ELVDD与初始化电压端Vintial之间为电性断路状态，也即是驱动电压端ELVDD与初始化电压端Vintial之间不会形成导电通路，那么在两个端点之间的电子元件就不会处于导电的工作状态，而均处于非耗电的工作状态，例如当驱动电压端ELVDD与初始化电压端Vintial之间未形成导电通路时，辅助电容CP2就处于非导通状态，从而处于非工作状态，故而在此时间段降低了像素单元P中电子元器件的功耗。
在步骤602的补偿时间段t2，栅极扫描线Gn提供的栅极扫描信号为高电平，栅极扫描线Gn-1提供的栅极扫描信号为低电平，发光扫描线En提供的发光扫描信号为高电平。像素单元P中的第一像素晶体管TP1、第三像素TP3处于导通状态，第四像素晶体管TP4处于截止状态，此时间段则对发光元件OLED的阳极端Anode执行像素单元P中各晶体管阈值电压Vth偏移以及发光元件OLED本身的老化偏移的补偿。
在步骤603的数据加载时间段t3，栅极扫描线Gn提供的栅极扫描信号为高电平，栅极扫描线Gn-1提供的栅极扫描信号为低电平，发光扫描线En提供的发光扫描信号为低电平。像素单元P中的第一像素晶体管TP1处于导通状态，第三像素晶体管TP3、第四像素晶体管TP4处于截止状态，数据信号Vdata通过第一、二像素晶体管TP1、TP2以及驱动电容CP1加载至发光元件OLED的阳极端Anode。
在步骤604的发光时间段t4，相邻的两个栅极扫描线Gn-1、Gn提供的栅极扫描信号为低电平，发光扫描线En提供的发光扫描信号为高电平，像素单元P中的第二像素晶体管TP2、第三像素晶体管TP3处于导通状态，第一像素晶体管TP1、第四像素晶体管TP4处于截止状态，驱动电压端ELVDD提供的驱动电压则依据数据信号Vdata驱动发光元件OLED执行发光从而进行图像显示。
需要说明的是，其他像素单元的工作过程前述像素单元的工作过程相同，在此不再赘述。
本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (18)

  1. 一种发光扫描驱动单元，其特征在于，所述发光扫描驱动单元用于输出发光扫描信号，包括：
    上拉控制单元，用于接收第一时钟信号，并且在一个扫描周期内依据所述第一时钟信号将高电平参考电压传输至上拉节点以控制所述上拉点为高电平状态；
    上拉输出单元，电性连接所述上拉节点，并且当所述上拉节点为高电平状态时，将接收的高电平参考电压传输至发光扫描端并作为所述发光扫描信号输出；
    下拉控制单元，电性连接下拉节点与所述上拉节点，用于在一个扫描周期内在两个不重叠的时间段中的每一个时间段控制所述上拉节点处于低电平状态以及控制所述下拉节点处于高电平状态；
    下拉输出单元，电性连接于所述下拉节点以及所述发光扫描端，用于在所述下拉节点处于高电平状态时，将接收的低电平参考电压输出至所述发光扫描端并作为所述发光扫描信号输出。
  2. 根据权利要求1所述的发光扫描驱动单元，其特征在于，每一个所述扫描周期包括自时间上连续且无间断的初始化时间段、补偿时间段、数据加载时间段以及发光时间段，其中，所述两个不重叠时间段为所述初始化时间段与所述数据加载时间段，所述初始化时间段与所述数据加载时间段时间长度不同。
  3. 根据权利要求2所述的发光驱动扫描单元，其特征在于，所述初始化时间段的时间长度大于所述数据加载时间段的时间长度。
  4. 根据权利要求2所述的发光扫描驱动单元，其特征在于，所述第一时钟信号为在所述发光时间段提供至所述上拉控制单元，所述下拉控制单元还用于在所述补偿时间段接收第二时钟信号，并且依据所述第二时钟信号控制所述上拉点为高电平状态。
  5. 根据权利要求2所述的发光扫描驱动单元，其特征在于，所述上拉控制单元包括第一晶体管，所述第一晶体管的栅极与漏极相互电性连接并且接收所述第一时钟信号，所述第一晶体管的源极电性连接至所述上拉节点。
  6. 根据权利要求5所述的发光扫描驱动单元，其特征在于，所述上拉输出单元包括第二晶体管与第一电容，所述第二晶体管的栅极电性连接所述上拉节点，所述第二晶体管的漏极电性连接至高电压参考端以接收高电平参考电压，所述第二晶体管的源极电性连接所述发光扫描端，所述第一电容电性连接于所述上拉节点与所述发光扫描端之间。
  7. 根据权利要求6所述的发光扫描驱动单元，其特征在于，所述下拉输出单元包括第三晶体管，所述第三晶体管的栅极电性连接所述下拉节点，所述第三晶体管的源极电性连接所述发光扫描端，所述第三晶体管的漏极电性连接低参考电压端并且接收所述低电平参考电压。
  8. 根据权利要求7所述的发光扫描驱动单元，其特征在于，所述下拉控制单元包括第四晶体管、第五晶体管、第六晶体管、第七晶体管与第八晶体管，
    所述第四晶体管的栅极与漏极相互电性连接并且接收所述第二时钟信号，所述第四晶体管的源极电性于所述上拉节点，
    所述第七晶体管的栅极与漏极相互电性连接并且接收栅极扫描信号，所述第七晶体管的源极电性连接所述第五晶体管的栅极，
    所述第五晶体管漏极电性连接所述第七晶体管的栅极，所述第五晶体管的漏极电性连接所述下拉节点，
    所述第六晶体管的栅极接收所述第二时钟信号，所述第六晶体管的漏极电性连接所述低参考电压端并且接收所述低电平参考电压，所述第六晶体管的源极电性连接所述下拉节点；
    所述第八晶体管的栅极接收所述第二时钟信号，所述第八晶体管的源极电性连接所述第五晶体管的栅极，所述第八晶体管的漏极电性连接所述低参考电压端并且接收所述低电平参考电压。
  9. 根据权利要求8所述的发光扫描驱动单元，其特征在于，所述下拉控制单元包括还包括第九晶体管，所述第九晶体管的栅极电性连接所述下拉节点，所述第九晶体管的源极电性连接所述上拉节点，所述第九晶体管的漏极电性连接所述低参考电压端并且接收所述低电平参考电压。
  10. 一种阵列基板，所述阵列基板包括像素单元与扫描驱动电路，其特征在于，所述扫描驱动电路包括多个相互级联的扫描驱动单元，所述扫描驱动单元包括栅极扫描驱动单元以及权利要求1-9任意一项所述的发光扫描驱动单元，所述栅极扫描驱动单元用于输出栅极扫描信号，所述像素单元在所述栅极扫描信号与发光扫描信号驱动下对接收的数据信号发光并且执行图像显示。
  11. 根据权利要求10所述的阵列基板，其特征在于，所述像素单元包括第一像素晶体管、第二像素晶体管、第三像素晶体管、第四像素晶体管、驱动电容，
    所述第一像素晶体管的栅极电性连接至栅极扫描线，所述第一像素晶体管的漏极电性连接至数据线以接收数据信号，所述第一像素晶体管的源极电性连接至所述第二像素晶体管的栅极；
    所述第三像素晶体管的栅极电性连接至发光扫描线，所述第三像素晶体管的漏极电性连接至驱动电压端，所述第三像素晶体管的源极电性连接至所述第二像素晶体管的漏极；
    所述第二像素晶体管的源极电性连接至发光元件的阳极端；
    所述第四像素晶体管的栅极电性连接至所述栅极扫描线相邻的另一栅极扫描线，所述第四像素晶体管的漏极电性连接至初始化电压端，所述第四像素晶体管的源极电性连接至所述发光元件的阳极端；
    所述驱动电容电性连接在所述发光元件的阳极端与所述第二像素晶体管的栅极之间。
  12. 根据权利要求11所述的阵列基板，其特征在于，所述像素单元还包括辅助电容，所述辅助电容电性连接所述发光元件的阳极端与高压驱动端之间。
  13. 根据权利要求12所述的阵列基板，其特征在于，所述像素单元在一个扫描周期中初始化时间段自所述相邻的两个栅极扫描线接收到均处于高电平的栅极扫描信号，以及自所述发光扫描端接收到处于低电平的发光扫描信号，从而控制所述第一像素晶体管与第四像素晶体管处于导通状态，以对所述像素单元进行初始化，所述第三像素晶体管处于截止状态以保证所述高压驱动端与所述初始化电压端之间处于电性断路。
  14. 根据权利要求13所述的阵列基板，其特征在于，
    所述像素单元在补偿时间段，所述栅极扫描线提供的栅极扫描信号为高电平，自所述相邻的另一个栅极扫描线提供的栅极扫描信号为低电平，所述发光扫描线提供的发光扫描信号为高电平，以控制所述第一像素晶体管、所述第三像素晶体管处于导通状态，所述第四像素晶体管处于截止状态，对所述像素单元执行补偿；
    所述像素单元在数据加载时间段，发光扫描线提供的发光扫描信号为低电平，以控制所述第一晶体管处于导通状态，所述第一像素晶体管、所述第四像素处于截止状态，以保证所述数据信号通过第二像素晶体管加载至对发光元件的阳极端。
  15. 根据权利要求14所述的像素单元，其特征在于，
    所述像素单元在发光时间段，所述相邻的两条栅极扫描线提供的栅极扫描信号均为低电平，所述发光扫描线提供的发光扫描信号为高电平，以控制所述第二像素晶体管、所述第三像素晶体管处于导通状态，所述第一像素晶体管、所述第四像素晶体管处于截止状态，自所述驱动电压端配合所述数据信号驱动所述发光元件行发光显示。
  16. 根据权利要求15所述的像素单元，其特征在于，每一个所述扫描周 期包括自时间上连续且无间断的所述初始化时间段、所述补偿时间段、所述数据加载时间段以及所述发光时间段。
  17. 一种采用如权利要求1-9任意一项所述的发光扫描驱动单元输出所述发光扫描信号的方法，其特征在于，包括：
    对应像素单元的初始化时间段，提供高电平的所述栅极扫描信号至所述下拉控制单元以控制所述下拉节点处于高电平状态，当所述下拉节点处于高电平状态时，所述下拉输出单元将接收的低电平参考电压输出至所述发光扫描端；
    对应所述像素单元的补偿时间段，提供高电平的所述第二时钟信号至所述下拉控制单元以控制所述下拉节点处于低电平状态以及控制所述上拉节点处于高电平状态，当所述上拉节点处于高电平状态时，所述上拉输出单元将所述高电平参考电压传输至发光扫描端；
    对应所述像素单元的数据加载时间段，提供高电平的所述栅极扫描信号至所述下拉控制单元以控制所述下拉节点处于高电平状态，当所述下拉节点处于高电平状态时，所述下拉输出单元将接收的低电平参考电压输出至所述发光扫描端；
    对应所述像素单元的发光时间段，提供第一时钟信号至所述上拉控制单元以控制所述上拉节点处于高电平状态，当所述上拉节点处于高电平状态时，所述上拉输出单元将接收的高电平参考电压输出至所述发光扫描端。
  18. 根据权利要求17所述的输出所述发光扫描信号的方法，其特征在于，对应所述像素单元的补偿时间段与数据加载时间段，维持所述栅极扫描信号处于高电平，对应所述像素单元的发光时间段，所述栅极扫描信号处于低电平。
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