WO2020147200A1 - 自对准表面沟道场效应晶体管的制备方法及功率器件 - Google Patents

自对准表面沟道场效应晶体管的制备方法及功率器件 Download PDF

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WO2020147200A1
WO2020147200A1 PCT/CN2019/080067 CN2019080067W WO2020147200A1 WO 2020147200 A1 WO2020147200 A1 WO 2020147200A1 CN 2019080067 W CN2019080067 W CN 2019080067W WO 2020147200 A1 WO2020147200 A1 WO 2020147200A1
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layer
gate
metal
metal layer
source
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PCT/CN2019/080067
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English (en)
French (fr)
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王元刚
吕元杰
冯志红
蔚翠
周闯杰
何泽召
宋旭波
梁士雄
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中国电子科技集团公司第十三研究所
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Priority to US16/964,726 priority Critical patent/US11189696B2/en
Publication of WO2020147200A1 publication Critical patent/WO2020147200A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • This application belongs to the technical field of microwave power devices, and in particular relates to a method for preparing a self-aligned surface channel field effect transistor and a power device.
  • surface channel devices have great advantages in high speed and high limit, they have attracted much attention in the high frequency field.
  • surface channel materials include p-type surface channels formed by hydrogen plasma treatment of diamond, and two-dimensional materials such as graphene, BN, black phosphorus, and GaN.
  • the characteristics of surface channel devices are greatly affected by the surface state.
  • the self-aligned process developed in recent years has effectively solved the above-mentioned problems.
  • the self-aligned process can only realize the device structure of the gate-source and the gate-drain with equal spacing, and it is difficult to take into account the breakdown voltage and the saturation current.
  • the purpose of this application is to provide a method for preparing a self-aligned surface-channel field effect transistor to solve the technical problems in the prior art that the gate is between the source and the drain and the breakdown voltage is generally low.
  • the technical solution adopted in this application is to provide a method for preparing a self-aligned surface channel field effect transistor, which includes the following steps:
  • Preparing a second photoresist layer exposing and developing to form at least one gate area pattern, the gate area pattern being biased toward the source metal layer;
  • wet etching to remove the first metal mask layer and the second metal mask layer between the source metal layer and the drain metal layer, and the source metal layer and the drain metal layer are corrosion stop layers;
  • the second photoresist layer is stripped off.
  • An under-gate dielectric layer is deposited on the surface channel epitaxial layer, and the gate metal layer is deposited on the under-gate dielectric layer.
  • the dielectric layer under the gate is a single-layer dielectric
  • the dielectric layer under the gate is a multilayer dielectric.
  • two layers of the second photoresist layer are prepared, exposed and developed to form at least one gate area pattern, and the gate area pattern is biased toward the source metal layer.
  • the structures of the gate region patterns are the same;
  • the structure of at least one of the gate region patterns is different from the structure of other gate region patterns;
  • each gate region pattern is different.
  • the structure of the gate metal layer is one or more gate combinations of straight gate, T-type gate, TT-type gate, TTT-type gate, U-type gate and Y-type gate.
  • the metal type of the first metal mask layer and the second metal mask layer are the same and different from the metal type of the source metal layer and the drain metal layer;
  • the metal types of the first metal mask layer and the second metal mask layer are different, and are different from the metal types of the source metal layer and the drain metal layer.
  • first metal mask layer, the second metal mask layer, the source metal layer, the drain metal layer and the gate metal layer are all a single layer of metal;
  • At least one single-layer metal and one multi-layer metal are included.
  • a passivation layer is prepared.
  • the application also provides a power device, which is prepared by the method.
  • the preparation method of the self-aligned surface channel field effect transistor provided by the present application is gate biased source or biased drain preparation, that is, the gate is not between the source and drain, and the gate biased source device can take into account the saturation current, increase the breakdown voltage of the device, and obtain high Power density.
  • FIG. 1 is a first structural schematic diagram of a manufacturing method of a self-aligned surface channel field effect transistor provided by an embodiment of the application;
  • FIG. 2 is a second structural diagram of a method for manufacturing a self-aligned surface-channel field effect transistor provided by an embodiment of the application.
  • 1- surface channel epitaxial layer 2- source metal layer; 3- second metal mask layer; 4- second photoresist layer; 5- gate metal layer; 6-gate region pattern; 7- drain metal layer; 8-first metal mask layer; 9-first photoresist layer; 10-lower gate dielectric layer.
  • the preparation method of the self-aligned surface channel field effect transistor includes the following steps:
  • a first metal mask layer 8 is deposited on the surface trench epitaxial layer 1, see a in FIGS. 1 and 2;
  • a first photoresist layer 9 is prepared on the first metal mask layer 8, see b in FIGS. 1 and 2;
  • a second metal mask layer 3 is deposited on the source metal layer 2, the drain metal layer 7 and the first metal mask layer 8, see e in FIGS. 1 and 2;
  • the drain metal layer 7 is a corrosion stop layer
  • a gate metal layer 5 is deposited on the gate region pattern 6, see h in FIGS. 1 and 2;
  • the second photoresist layer 4 is stripped off.
  • the preparation method of the self-aligned surface channel field effect transistor is that the gate metal layer 5 is prepared towards the source metal layer 2 or the drain metal layer 7, rather than between the source and drain, that is, the source metal
  • the layer 2 and the drain metal layer 7 are distributed asymmetrically with respect to the gate metal layer 5.
  • the gate biased source device can take into account the saturation current, effectively increase the breakdown voltage and working voltage, and increase the power density of the device; and the T-shaped gate helps Taking into account the characteristics of gate parasitic capacitance and gate resistance, the frequency characteristics of the device are improved.
  • the mesa isolation process can be performed after any of the above steps, and the function is to separate the device prepared in this application from other parts.
  • each photoresist layer is developed through one exposure and one time, or multiple exposure and one time development, or multiple exposure and multiple development to form a corresponding area pattern, and the number of each photoresist layer is an integer greater than or equal to 1.
  • the field effect transistor when the gate is biased toward the source, that is, when the effective gate-source spacing is smaller than the effective gate-drain spacing, the field effect transistor can take into account the saturation current and provide breakdown voltage and working voltage.
  • the effective gate-source spacing can also be greater than the effective gate-drain spacing of devices.
  • FIGS. 1 to 2 Please refer to FIGS. 1 to 2 together, as a specific embodiment of the preparation method of the self-aligned surface channel field effect transistor provided by the present application, before the gate metal layer 5 is deposited at the gate region pattern 6: An under-gate dielectric layer 10 is deposited on the surface channel epitaxial layer 1, and the gate metal layer 5 is deposited on the under-gate dielectric layer 10.
  • the under-gate dielectric layer 10 is a single-layer dielectric; or, the under-gate dielectric Layer 10 is a multilayer medium.
  • two layers of the second photoresist layer 4 are prepared, exposed and developed to form at least one gate region pattern 6.
  • the gate region pattern 6 is biased toward the source metal layer 2.
  • the structure of the gate region patterns 6 is the same or, the structure of at least one of the gate region patterns 6 is different from the structure of the other gate region patterns 6; or, the structure of each of the gate region patterns 6 is different.
  • the structure and size of the graphics may or may not be the same, depending on actual needs.
  • the structure of the gate metal layer 5 is a straight gate, a T-type gate, and a TT-type gate. , TTT-type gate, U-type gate and Y-type gate in one or more combinations.
  • the gate metal layer 5 in FIG. 1 is a straight gate
  • the gate metal layer 5 in FIG. 2 is a T-shaped gate.
  • the second photolithography layer is two layers. The structure of the gate metal layer 5 and The number is determined according to the structure and number of the gate etching window pattern of photolithography.
  • the metal types of the first metal mask layer 8 and the second metal mask layer 3 are the same, and It is different from the metal types of the source metal layer 2 and the drain metal layer 7; or, the metal types of the first metal mask layer 8 and the second metal mask layer 3 are different, and are still different from those of the The source metal layer 2 and the drain metal layer 7 have different metal types.
  • the drain metal layer 7 and the gate metal layer 5 are both single-layer metals; or, both are multilayer metals; or, they include at least one single-layer metal and one multilayer metal.
  • the metal types are all metals commonly used in the preparation of existing semiconductor devices.
  • a passivation layer is prepared to protect the device, and the passivation layer is a single layer or multiple layers. Layer medium.
  • the surface channel epitaxial layer 11 is a diamond p-type surface channel, or is graphene, BN, black phosphorus, GaN
  • the substrate used is diamond, SiC, GaN, sapphire, Si, Au, quartz, SiO 2 , SiN, copper and other materials, or a composite substrate of a combination of multiple materials.
  • the application also provides a power device, which is prepared by the method.
  • a power device which is prepared by the method.
  • the gate metal layer 5 is biased toward the source metal layer 2, rather than between the source and drain, that is, the source metal layer 2 and the drain metal layer 7 are distributed asymmetrically with respect to the gate metal layer 5, and the gate is biased toward the source
  • the device can take into account the saturation current, effectively increase the breakdown voltage and the working voltage, and increase the power density of the device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本申请提供了一种自对准表面沟道场效应晶体管的制备方法及功率器件，属于微波功率器件领域，包括：淀积第一金属掩膜层；制备第一光刻胶层；形成源区域图形和漏区域图形；在源区域图形和漏区域图形部位淀积源金属层和漏金属层；剥离去除第一光刻胶；淀积第二金属掩膜层；制备第二光刻胶层，曝光、显影，形成至少一个栅区域图形，栅区域图形偏向源金属层；湿法腐蚀去除源金属层和漏金属层之间的第一金属掩膜层和第二金属掩膜层；在栅区域图形处淀积栅金属层；剥离去除第二光刻胶层。本申请提供的自对准表面沟道场效应晶体管的制备方法，栅偏源制备，可以兼顾饱和电流，提高器件击穿电压，获得高功率密度。

Description

自对准表面沟道场效应晶体管的制备方法及功率器件 技术领域
本申请属于微波功率器件技术领域，尤其涉及一种自对准表面沟道场效应晶体管的制备方法及功率器件。
 背景技术
由于表面沟道器件在高速、高限域性等方面具有较大优势，在高频领域备受关注。目前常用的表面沟道材料包括氢等离子体处理金刚石形成的p型表面沟道，以及石墨烯、BN、黑磷、GaN等二维材料。表面沟道器件特性受表面态影响大，近些年开发的自对准工艺，有效解决了上述问题。但是自对准工艺仅能实现栅源和栅漏等间距器件结构，难以兼顾击穿电压和饱和电流。
 技术问题
本申请的目的在于提供一种自对准表面沟道场效应晶体管的制备方法，以解决现有技术中存在的栅在源漏中间、击穿电压普遍较低的技术问题。
 技术解决方案
为实现上述目的，本申请采用的技术方案是：提供一种自对准表面沟道场效应晶体管的制备方法，包括以下步骤：
在表面沟道外延层上淀积第一金属掩膜层；
在第一金属掩膜层上制备第一光刻胶层；
曝光、显影，形成源区域图形和漏区域图形；
湿法腐蚀去除所述源区域图形和所述漏区域图形部位的第一金属掩膜层；
在所述源区域图形和所述漏区域图形部位淀积源金属层和漏金属层；
剥离去除第一光刻胶；
在所述源金属层、所述漏金属层和所述第一金属掩膜层上淀积第二金属掩膜层；
制备第二光刻胶层，曝光、显影，形成至少一个栅区域图形，所述栅区域图形偏向所述源金属层；
湿法腐蚀去除所述源金属层和所述漏金属层之间的第一金属掩膜层和第二金属掩膜层，并且源金属层和漏金属层为腐蚀终止层；
在所述栅区域图形处淀积栅金属层；
剥离去除第二光刻胶层。
进一步地，在所述栅区域图形处淀积栅金属层之前：
所述表面沟道外延层上淀积栅下介质层，所述栅金属层淀积在所述栅下介质层上。
进一步地，所述栅下介质层为单层介质；
或者，所述栅下介质层为多层介质。
进一步地，制备两层所述第二光刻胶层，曝光、显影，形成至少一个栅区域图形，所述栅区域图形偏向所述源金属层。
进一步地，当所述栅区域图形的数量为两个或两个以上时，所述栅区域图形的结构相同；
或者，至少一个所述栅区域图形的结构与其他的所述栅区域图形的结构不同；
或者，各所述栅区域图形的结构均不相同。
进一步地，所述栅金属层的结构为直栅、T型栅、TT型栅、TTT型栅、U型栅和Y型栅中的一种或多种栅组合。
进一步地，所述第一金属掩膜层和所述第二金属掩膜层的金属类型相同，且与所述源金属层和所述漏金属层的金属类型不同；
或者，所述第一金属掩膜层和所述第二金属掩膜层的金属类型不同，且与所述源金属层和所述漏金属层的金属类型不同。
进一步地，所述第一金属掩膜层、所述第二金属掩膜层、所述源金属层、所述漏金属层和所述栅金属层均为单层金属；
或者，均为多层金属；
或者，至少包括一个单层金属和一个多层金属。
进一步地，制备所述栅金属层之后，制备钝化层。
本申请还提供一种功率器件，利用所述的方法制备。
 有益效果
本申请提供的自对准表面沟道场效应晶体管的制备方法的栅偏源或偏漏制备，也即栅不在源漏中间，其中栅偏源器件可以兼顾饱和电流，提高器件击穿电压，获得高功率密度。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的自对准表面沟道场效应晶体管的制备方法的结构示意图一；
图2为本申请实施例提供的自对准表面沟道场效应晶体管的制备方法的结构示意图二。
其中，图中各附图标记：
1-表面沟道外延层；2-源金属层；3-第二金属掩膜层；4-第二光刻胶层；5-栅金属层；6-栅区域图形；7-漏金属层；8-第一金属掩膜层；9-第一光刻胶层；10-栅下介质层。
本申请的实施方式
为了使本申请所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
请一并参阅图1及图2，现对本申请提供的自对准表面沟道场效应晶体管的制备方法进行说明。所述自对准表面沟道场效应晶体管的制备方法，包括以下步骤：
在表面沟道外延层1上淀积第一金属掩膜层8，参见图1和图2中a；
在第一金属掩膜层8上制备第一光刻胶层9，参见图1和图2中b；
曝光、显影，形成源区域图形和漏区域图形，参见图1和图2中c；
湿法腐蚀去除所述源区域图形和所述漏区域图形部位的第一金属掩膜层8；
在所述源区域图形和所述漏区域图形部位淀积源金属层2和漏金属层7，参见图1和图2中d；
剥离去除第一光刻胶；
在所述源金属层2、所述漏金属层7和所述第一金属掩膜层8上淀积第二金属掩膜层3，参见图1和图2中e；
制备第二光刻胶层4，曝光、显影，形成至少一个栅区域图形6，所述栅区域图形6偏向所述源金属层2，参见图1和图2中f；
湿法腐蚀去除所述源金属层2和所述漏金属层7之间的第一金属掩膜层8和第二金属掩膜层3，参见图1和图2中g，并且源金属层2和漏金属层7为腐蚀终止层；
在所述栅区域图形6处淀积栅金属层5，参见图1和图2中h；
剥离去除第二光刻胶层4。
本申请提供的自对准表面沟道场效应晶体管的制备方法，与现有技术相比，栅金属层5偏向源金属层2或漏金属层7制备，而不是在源漏中间，也即源金属层2和漏金属层7相对于栅金属层5为非对称分布，其中栅偏源器件能够兼顾饱和电流，有效提高击穿电压和工作电压，提高器件的功率密度；并且T型栅有助于兼顾栅寄生电容和栅电阻特性，提高器件频率特性。
其中，台面隔离工艺可以在上述的任一步骤之后进行，作用是将本申请制备的器件与其他的部分分隔。
其中，各光刻胶层通过一次曝光一次显影，或者多次曝光一次显影，或者多次曝光多次显影，形成对应的区域图形，各光刻胶的层数为大于等于1的整数。
本实施例中，当栅偏向源时，也即有效栅源间距小于有效栅漏间距时，场效应晶体管能够兼顾饱和电流，提供击穿电压和工作电压。当然，有效栅源间距还可以大于有效栅漏间距的器件。
请一并参阅图1至图2，作为本申请提供的自对准表面沟道场效应晶体管的制备方法的一种具体实施方式，在所述栅区域图形6处淀积栅金属层5之前：所述表面沟道外延层1上淀积栅下介质层10，所述栅金属层5淀积在所述栅下介质层10上。
请参阅图1至图2，作为本申请提供的自对准表面沟道场效应晶体管的制备方法的一种具体实施方式，所述栅下介质层10为单层介质；或者，所述栅下介质层10为多层介质。
参阅图2，作为本申请提供的自对准表面沟道场效应晶体管的制备方法的一种具体实施方式，制备两层所述第二光刻胶层4，曝光、显影，形成至少一个栅区域图形6，所述栅区域图形6偏向所述源金属层2。
作为本申请提供的自对准表面沟道场效应晶体管的制备方法的一种具体实施方式，当所述栅区域图形6的数量为两个或两个以上时，所述栅区域图形6的结构相同；或者，至少一个所述栅区域图形6的结构与其他的所述栅区域图形6的结构不同；或者，各所述栅区域图形6的结构均不相同。图形的结构、尺寸可以完全相同也可以不完全相同，根据实际需要而定。
请参阅图1及图2，作为本申请提供的自对准表面沟道场效应晶体管的制备方法的一种具体实施方式，所述栅金属层5的结构为直栅、T型栅、TT型栅、TTT型栅、U型栅和Y型栅中的一种或多种栅组合。本实施例图1中的栅金属层5为直栅，图2中的栅金属层5为T型栅，为制备T型栅，第二光刻层为两层，栅金属层5的结构和数量根据光刻的栅腐蚀窗口图形的结构和数量而定。
其中，作为本申请提供的自对准表面沟道场效应晶体管的制备方法的一种具体实施方式，所述第一金属掩膜层8和所述第二金属掩膜层3的金属类型相同，且与所述源金属层2和所述漏金属层7的金属类型不同；或者，所述第一金属掩膜层8和所述第二金属掩膜层3的金属类型不同，且仍与所述源金属层2和所述漏金属层7的金属类型不同。
作为本申请提供的自对准表面沟道场效应晶体管的制备方法的一种具体实施方式，所述第一金属掩膜层8、所述第二金属掩膜层3、所述源金属层2、所述漏金属层7和所述栅金属层5均为单层金属；或者，均为多层金属；或者，至少包括一个单层金属和一个多层金属。金属类型均为现有半导体器件制备常规使用的金属。
作为本申请提供的自对准表面沟道场效应晶体管的制备方法的一种具体实施方式，制备所述栅金属层5之后，制备钝化层，对器件进行保护，钝化层为单层或者多层介质。
作为本申请提供的自对准表面沟道场效应晶体管的制备方法的一种具体实施方式，所述表面沟道外延层11为金刚石p型表面沟道，或者为石墨烯、BN、黑磷、GaN等二维材料，所用衬底为金刚石、SiC、GaN、蓝宝石、Si、Au、石英、SiO 2、SiN、铜等材料，或者为多种材料组合的复合衬底。
本申请还提供一种功率器件，利用所述的方法制备。本申请制备的功率器件，由于栅金属层5偏向源金属层2，而不是在源漏中间，也即源金属层2和漏金属层7相对于栅金属层5为非对称分布，栅偏源器件能够兼顾饱和电流，有效提高击穿电压和工作电压，提高器件的功率密度。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 自对准表面沟道场效应晶体管的制备方法，其特征在于，包括以下步骤：
    在表面沟道外延层上淀积第一金属掩膜层；
    在第一金属掩膜层上制备第一光刻胶层；
    曝光、显影，形成源区域图形和漏区域图形；
    湿法腐蚀去除所述源区域图形和所述漏区域图形部位的第一金属掩膜层；
    在所述源区域图形和所述漏区域图形部位淀积源金属层和漏金属层；
    剥离去除第一光刻胶；
    在所述源金属层、所述漏金属层和所述第一金属掩膜层上淀积第二金属掩膜层；
    制备第二光刻胶层，曝光、显影，形成至少一个栅区域图形，所述栅区域图形偏向所述源金属层；
    湿法腐蚀去除所述源金属层和所述漏金属层之间的第一金属掩膜层和第二金属掩膜层，并且源金属层和漏金属层为腐蚀终止层；
    在所述栅区域图形处淀积栅金属层；
    剥离去除第二光刻胶层。
  2. 如权利要求1所述的自对准表面沟道场效应晶体管的制备方法，其特征在于：在所述栅区域图形处淀积栅金属层之前：
    所述表面沟道外延层上淀积栅下介质层，所述栅金属层淀积在所述栅下介质层上。
  3. 如权利要求2所述的自对准表面沟道场效应晶体管的制备方法，其特征在于：所述栅下介质层为单层介质；
    或者，所述栅下介质层为多层介质。
  4. 如权利要求1所述的自对准表面沟道场效应晶体管的制备方法，其特征在于：制备两层所述第二光刻胶层，曝光、显影，形成至少一个栅区域图形，所述栅区域图形偏向所述源金属层或偏向所述漏金属层。
  5. 如权利要求1所述的自对准表面沟道场效应晶体管的制备方法，其特征在于：当所述栅区域图形的数量为两个或两个以上时，所述栅区域图形的结构相同；
    或者，至少一个所述栅区域图形的结构与其他的所述栅区域图形的结构不同；
    或者，各所述栅区域图形的结构均不相同。
  6. 如权利要求1所述的自对准表面沟道场效应晶体管的制备方法，其特征在于：所述栅金属层的结构为直栅、T型栅、TT型栅、TTT型栅、U型栅和Y型栅中的一种或多种栅组合。
  7. 如权利要求1所述的自对准表面沟道场效应晶体管的制备方法，其特征在于：所述第一金属掩膜层和所述第二金属掩膜层的金属类型相同，且与所述源金属层和所述漏金属层的金属类型不同；
    或者，所述第一金属掩膜层与所述第二金属掩膜层的金属类型不同，且与所述源金属层和所述漏金属层的金属类型不同。
  8. 如权利要求1所述的自对准表面沟道场效应晶体管的制备方法，其特征在于：所述第一金属掩膜层、所述第二金属掩膜层、所述源金属层、所述漏金属层和所述栅金属层均为单层金属；
    或者，均为多层金属；
    或者，至少包括一个单层金属和一个多层金属。
  9. 如权利要求1所述的自对准表面沟道场效应晶体管的制备方法，其特征在于：制备所述栅金属层之后，制备钝化层。
  10. 功率器件，其特征在于：利用如权利要求1-9任一项所述的方法制备。
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