WO2020146994A1 - Puce et son procédé de fabrication - Google Patents

Puce et son procédé de fabrication Download PDF

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Publication number
WO2020146994A1
WO2020146994A1 PCT/CN2019/071682 CN2019071682W WO2020146994A1 WO 2020146994 A1 WO2020146994 A1 WO 2020146994A1 CN 2019071682 W CN2019071682 W CN 2019071682W WO 2020146994 A1 WO2020146994 A1 WO 2020146994A1
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Prior art keywords
chip
porous silicon
substrate
layer
silicon structure
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PCT/CN2019/071682
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English (en)
Chinese (zh)
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陆斌
沈健
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN201980000113.2A priority Critical patent/CN111699551B/zh
Priority to PCT/CN2019/071682 priority patent/WO2020146994A1/fr
Publication of WO2020146994A1 publication Critical patent/WO2020146994A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices

Definitions

  • the embodiments of the present application relate to information security technology, and in particular to a chip and a method for manufacturing the chip.
  • the embodiments of the present application provide a chip and a method for manufacturing the chip to solve the problem of low reliability of the self-destructing chip in the prior art.
  • an embodiment of the present application provides a chip
  • the chip body includes:
  • the device layer which is located on the substrate
  • Porous silicon structure the porous silicon structure is arranged on the substrate, and the porous silicon structure is used to react with the chemical capping solution to destroy the chip body.
  • the substrate has at least one reserved area, and the porous silicon structure is arranged in the reserved area and is exposed at least outside the substrate.
  • the reserved area includes a receiving cavity provided on the substrate, and the porous silicon structure is provided in the receiving cavity.
  • the chip body further includes an insulating passivation layer, the insulating passivation layer is located on the substrate, and the insulating passivation layer covers the device layer.
  • the insulating passivation layer has a first opening, and the first opening is in communication with the accommodating cavity on the substrate.
  • the chip body further includes a conductive interconnection layer, the conductive interconnection layer is located on the substrate, and the insulating passivation layer covers the conductive interconnection layer.
  • the porous silicon structure is a porous silicon layer formed in a reserved area.
  • the porous silicon structure is a porous silicon chip arranged in the containing cavity.
  • the porous silicon layer is located on the side of the substrate away from the device layer.
  • the porous silicon structure is located outside the device layer.
  • the porous silicon structure is distributed on the four corners of the chip body.
  • the accommodating cavity is located in the region of the chip body corresponding to the dicing lane.
  • the accommodating cavity is located on the side of the substrate away from the device layer.
  • the gap between the accommodating cavity and the porous silicon wafer is filled with an organic material that can be dissolved in a chemical capping solution.
  • the porous silicon layer is covered with an organic material that can be dissolved in a chemical capping solution.
  • the holes of the porous silicon structure are filled with an oxidant.
  • the chip body further includes a pad, the pad is located in the insulating passivation layer, and the insulating passivation layer has a second opening, and the second opening is connected to the pad .
  • the thickness of the porous silicon structure is 1 ⁇ m to 200 ⁇ m.
  • the chip provided in the embodiment of the present application has a substrate resistivity of 1-20 ⁇ cm.
  • the chip provided in the embodiment of the present application further has a conductive layer on the substrate, and the conductive layer is located on the side of the substrate that is away from the porous silicon structure.
  • the chip further includes a packaging structure, and the packaging structure is used for packaging the chip body.
  • the chip provided in the embodiment of the present application has a silicon substrate as the substrate.
  • an embodiment of the present application provides a method for manufacturing a chip, including the following steps:
  • a porous silicon structure is fabricated on the substrate to obtain a chip body; wherein, the porous silicon structure is used to react with a chemical capping solution to destroy the chip body.
  • the method for manufacturing a chip provided by the embodiment of the present application, fabricating a porous silicon structure on a substrate to obtain a chip body specifically includes:
  • the porous silicon structure is arranged in the reserved area, and the porous silicon structure is exposed at least outside the substrate.
  • the method for manufacturing a chip provided in the embodiment of the present application, arranging the porous silicon structure in the reserved area specifically includes: etching the porous silicon layer in the reserved area.
  • the method for manufacturing a chip provided in the embodiment of the present application, arranging the porous silicon structure in a reserved area specifically includes:
  • An embodiment of the application provides a chip and a method for manufacturing the chip.
  • Nitric acid as a chemical decap solution reacts with the porous silicon structure to destroy the chip body, thereby preventing the information stored in the chip from being maliciously deciphered and stolen, preventing reverse engineering of the chip manufacturing process, and preventing the analysis of the structural parameters and material components of the chip. In this way, the security of the chip is improved in all aspects.
  • FIG. 1 is a schematic structural diagram of a chip provided in Embodiment 1 of the application;
  • FIG. 2 is a diagram of the position between the area of the dicing lane and the insulating passivation layer in a chip provided in the first embodiment of the application;
  • FIG. 3 is a schematic structural diagram of a chip provided in Embodiment 2 of the application.
  • FIG. 4 is a schematic structural diagram of a chip provided in Embodiment 3 of the application.
  • FIG. 5 is a schematic structural diagram of a porous silicon chip in a chip provided in Embodiment 3 of the application
  • FIG. 6 is a schematic structural diagram of a chip provided in Embodiment 4 of the application.
  • FIG. 7 is a flowchart of a method for manufacturing a chip provided in Embodiment 5 of the application.
  • FIG. 8 is a schematic structural diagram of the package of the chip body in a method for manufacturing a chip provided in the fifth embodiment of the application.
  • 10 chip body; 101—substrate; 1011—accommodating cavity; 1012—porous silicon layer; 1013—porous silicon wafer; 1014—organic material; 102—device layer; 103—conductive interconnection layer; 104—insulating passivation layer 1041—the first opening; 1042—the second opening; 105—the area of the cutting track; 106—the conductive layer; 20—single crystal silicon; 30—the base; 40—metal lead; 50—lead frame; 60—plastic packaging material .
  • FIG. 1 is a schematic structural diagram of a chip provided in Embodiment 1 of the application.
  • the chip provided in this embodiment includes a chip body 10, which includes a substrate 101, a device layer 102, and a porous silicon structure.
  • the device layer 102 is located on a substrate 101 and the porous silicon structure is disposed on the substrate 101.
  • the porous silicon structure is used to react with the chemical capping solution to destroy the chip body 10.
  • the substrate 101 in this embodiment is a silicon substrate, and the material of the substrate 101 can also be germanium, gallium arsenide, silicon-on-insulator or other semiconductor materials.
  • the material of the substrate 101 is not limited in this embodiment. .
  • the chip body 10 further includes an insulating passivation layer 104, the insulating passivation layer 104 is located on the substrate 101, and the insulating passivation layer 101 covers the device layer 102.
  • the chip body 10 further includes a conductive interconnection layer 103, the conductive interconnection layer 103 is located on the substrate 101, and the insulating passivation layer 104 covers the conductive interconnection layer 103.
  • the specific layout in the device layer 102 and the connection mode of the insulating passivation layer 104, the device layer 102 and the conductive interconnection layer 103 can be specifically designed according to chips with different functions, which are not limited in this embodiment.
  • nitric acid which is commonly used for chemical lid opening, can effectively remove the plastic packaging material covering the chip body 10 without damaging the chips, so nitric acid soaking is the most common chemical lid opening method.
  • a porous silicon structure is provided on the substrate 101, so that after the nitric acid removes the molding compound covering the chip, it comes into contact with the porous silicon structure and produces a violent reaction, thereby destroying the chip body 10 and reaching the chip The purpose of destruction.
  • the substrate 101 has at least one reserved area, and the porous silicon structure is arranged in the reserved area and is exposed at least outside the substrate 101. Further, the reserved area includes a receiving cavity 1011 provided on the substrate 101, and the porous silicon structure is provided in the receiving cavity 1011.
  • the porous silicon structure is disposed in the accommodating cavity 1011 on the substrate 101, and after the nitric acid removes the plastic packaging material covering the chip body 10, the nitric acid passes through and is exposed to at least the accommodating outside of the substrate 101.
  • the cavity 1011 enters the porous silicon structure and reacts with the porous silicon structure to destroy the chip body 10, thereby preventing the information stored in the chip from being maliciously stolen, preventing reverse engineering of the chip manufacturing process, and preventing the analysis of the structural parameters and material composition of the chip , In order to improve the security of the chip.
  • the porous silicon structure is a porous silicon layer 1012 formed in a reserved area.
  • the porous silicon layer 1012 is etched in the reserved area, and the porous silicon layer 1012 can be prepared by electrochemical etching.
  • the specific preparation method of chemical etching is not limited in this embodiment.
  • the resistivity of the substrate 101 is 1-20 ⁇ cm
  • the thickness of the porous silicon layer 1012 is 1 ⁇ m-200 ⁇ m. In this way, the porous silicon layer 1012 on the substrate 101 can better react with nitric acid to damage the chip body 10.
  • the porosity of the porous silicon layer 1012 is 20-80%
  • the pore diameter of the pores in the porous silicon layer 1012 is on the order of nm
  • the thickness, porosity, and pore size of the porous silicon layer 1012 can be adjusted during chemical etching.
  • the composition of the etching solution, the current density and the reaction time are adjusted, which is not limited in this embodiment.
  • the substrate 101 further has a conductive layer 106, and the conductive layer 106 is located on the side of the substrate 101 that is away from the porous silicon layer 1012.
  • the conductive layer may be a P-type or N-type heavily doped region formed by doping the substrate, or may be a metal layer or a heavily doped silicon layer obtained by a material deposition process.
  • a P-type heavily doped layer can be formed on the back of the substrate 101 through an ion implantation process in advance, and the P-type heavily doped layer and the porous silicon layer 1012 relatively.
  • the P-type heavily doped layer is used to enhance the electrical contact quality between the substrate 101 and the etching solution during electrochemical corrosion, otherwise a current loop cannot be formed.
  • the conductive layer 106 is formed on the entire back of the substrate 101, or a part of the back of the substrate 101 has a conductive layer 106, as long as the back of the substrate 101 has a conductive layer 106 opposite to the porous silicon layer 1012, This embodiment is not limited here.
  • the pores of the porous silicon layer 1012 are filled with an oxidant.
  • the oxidant can be sulfur, Ca(ClO 4 ) 2 , NH 4 ClO 4 , LiClO 4 , NaClO 4 , KClO 4 , Ca(NO 3 ) 2 , NH 4 NO 3 , KNO 3 or Gd(NO 3 ) 3
  • One or more of the oxidants are used to further enhance the reactivity of the porous silicon layer 1012.
  • the porous silicon layer 1012 filled with oxidant will burst when irradiated by the laser, thereby increasing the chip's ability to prevent the laser from being opened.
  • the insulating passivation layer 104 has a first opening 1041, and the first opening 1041 is in communication with the accommodating cavity 1011 on the substrate 101.
  • the chip body 10 further includes a pad, the pad is located in the insulating passivation layer 104, the insulating passivation layer 104 has a second opening 1042, and the second opening 1042 is connected to the pad.
  • the porous silicon layer 1012 is covered with an organic material 1014 that can be dissolved in a chemical capping solution.
  • the chip further includes a packaging structure, and the packaging structure is used to package the chip body 10.
  • the package structure may include a base 30, metal leads 40, a lead frame 50 and a plastic encapsulation material 60.
  • the chip body 10 is pasted on the base 30, and the pads of the chip body 10 and the lead frame 50 are connected with the metal leads 40, and the plastic is sealed Material 60 covers the entire structure.
  • FIG. 2 is a position diagram between the area of the dicing lane and the insulating passivation layer in a chip provided in Embodiment 1 of the application.
  • the accommodating cavity 1011 is located in the area 105 of the chip body 10 corresponding to the dicing lane.
  • the porous silicon structure may also be located outside the device layer 102.
  • the porous silicon structure can also be distributed at the four corners of the chip body 10.
  • FIG. 3 is a schematic structural diagram of a chip provided in Embodiment 2 of the application.
  • the porous silicon layer 1012 is located on the side of the substrate 101 away from the device layer 102.
  • the porous silicon layer 1012 and the insulating passivation layer 104 are respectively located on the back and the front of the substrate 101, and the first opening 1041 on the insulating passivation layer 104 is opposite to the receiving cavity 1011 on the substrate 101.
  • the conductive layer 106 is a P-type heavily doped layer, and the P-type heavily doped layer on the substrate 101 is located in the substrate 101 at the first opening 1041.
  • the first opening 1041 needs to be provided on the insulating passivation layer 104 to determine the location of the porous silicon layer 1012 to be etched. Due to the lateral scooping effect of the electrochemical corrosion, the distance between the edge of the chip device layer 102 and the porous silicon layer 1012 needs to be increased to prevent damage to the chip. Therefore, in this embodiment, the corrosion area of the porous silicon layer 1012 is changed to the side opposite to the device layer 102, which can avoid this problem and obtain a chip with a smaller size.
  • the porous silicon layer 1012 is disposed on the side of the substrate 101 away from the device layer 102. In this way, while improving the security of the chip, the size of the final chip is reduced.
  • FIG. 4 is a schematic structural diagram of a chip provided in Embodiment 3 of this application
  • FIG. 5 is a schematic structural diagram of a porous silicon chip in a chip provided in Embodiment 3 of this application.
  • the porous silicon structure is a porous silicon chip 1013 arranged in a containing cavity 1011.
  • the accommodating cavity 1011 is a groove, which can be made on the substrate 101 by a photolithography process, and the groove is in communication with the first opening 1041.
  • the porous silicon wafer 1013 is separately manufactured by additional wafers.
  • the porous silicon wafer 1013 may be all porous silicon, or may include porous silicon and part of single crystal silicon 20. Due to the relatively large unevenness of the electrochemical etching process, the production of the porous silicon wafer 1013 alone can better control the chip yield. Chip raise the chip.
  • the gap between the accommodating cavity 1011 and the porous silicon wafer 1013 is filled with an organic material 1014 that is soluble in the chemical capping solution.
  • the organic material 1014 may be a resin material.
  • the porous silicon layer 1012 is etched in the reserved area on the substrate 101. Due to the unevenness of the electrochemical corrosion, the yield of the chip may be affected. Therefore, in the chip provided in this embodiment, a porous silicon wafer 1013 is separately fabricated, and a groove made on the substrate 101 has the porous silicon wafer 1013 arranged in the groove. Due to the relatively large unevenness of the electrochemical etching process, the production of the porous silicon wafer 1013 alone can better control the chip yield.
  • FIG. 6 is a schematic structural diagram of a chip provided in the fourth embodiment of the application.
  • the porous silicon wafer 1013 is located on the side of the substrate 101 away from the device layer 102.
  • the porous silicon wafer 1013 and the device layer 102 are respectively located on two opposite sides of the substrate 101.
  • the first opening 1041 is not provided on the insulating passivation layer 104.
  • the accommodating cavity 1011 is located on the side of the substrate 101 away from the device layer 102
  • FIG. 7 is a flowchart of a method for manufacturing a chip provided in Embodiment 5 of the application. As shown in FIG. 7, an embodiment of the present application provides a method for manufacturing a chip, including the following steps:
  • a silicon wafer is selected as the substrate 101, and a device layer 102, a conductive interconnection layer 103, and an insulating passivation layer 104 are formed on the substrate 101 using a semiconductor manufacturing process.
  • a conductive layer 106 is formed on the substrate 101, and the conductive layer 106 is located on the side of the substrate 101 away from the porous silicon layer 1012.
  • a first opening 1041 is provided on the insulating passivation layer 104.
  • a photolithography process can be used to provide a first opening 1041 on the insulating passivation layer 104 in a specific area of the chip to expose the silicon substrate 101.
  • the first opening 1041 is located at the four corners of the chip, and the first opening 1041 may also be located in the middle of the chip.
  • the shape of the first opening 1041 can be any geometric figure, which is not limited in this embodiment.
  • S102 Fabricate a porous silicon layer 1012 on the substrate 101 to obtain the chip body 10; wherein the porous silicon structure is used to react with the chemical capping solution to destroy the chip body 10.
  • At least one reserved area is provided on the substrate 101, and the porous silicon layer 1012 is etched in the reserved area.
  • the silicon wafer is placed in an electrochemical reaction device, and the porous silicon layer 1012 is etched at the position of the first opening 1041 on the insulating passivation layer 104 (that is, the porous silicon layer is etched at the position of the cavity 1011 on the substrate 101). 1012).
  • the porosity and pore size of the porous silicon layer 1012, as well as the thickness of the porous silicon layer 1012 are adjusted by controlling the composition of the etching solution in the electrochemical reaction device, the current density and the reaction time.
  • the thickness of the porous silicon layer 1012 is controlled to be 1 ⁇ m to 200 ⁇ m,
  • the porosity of the porous silicon layer 1012 is controlled to be 20% to 80%, and the pore diameter of the pores in the porous silicon layer 1012 is controlled to the nm level.
  • the porous silicon layer 1012 is covered with an organic material 1014 that is soluble in a chemical capping solution.
  • the pores of the porous silicon layer 1012 are filled with an oxidant.
  • the oxidant can be sulfur, Ca(ClO 4 ) 2 , NH 4 ClO 4 , LiClO 4 , NaClO 4 , KClO 4 , Ca(NO 3 ) 2 , NH 4 NO 3 , KNO 3 or Gd(NO 3 ) 3 One or more of.
  • a second opening 1042 is provided on the insulating passivation layer 104, and the second opening 1042 is connected to the pad.
  • a photolithography process is used to open a second opening 1042 on the passivation insulating layer 104 in an area corresponding to the pad to expose the pad.
  • the surface where the metal layer 106 is formed on the substrate 101 is ground and polished to thin the silicon wafer to the required thickness, and then the silicon wafer is cut into individual small pieces along the area 105 of the chip dicing path. chip.
  • the chip body 10 is packaged by a packaging structure.
  • FIG. 8 is a schematic structural diagram of the package of the chip body in a method for manufacturing a chip provided in the fifth embodiment of the application.
  • the chip body 10 is pasted on the base 30, the pads of the chip body 10 and the lead frame 50 are connected with metal leads 40, and the entire structure is covered with a plastic encapsulating material 60.
  • Other packaging methods can also be used, which is not limited in this embodiment.
  • the embodiment of the present application provides a method for manufacturing a chip, which corresponds to the chip provided in the second embodiment above.
  • the embodiment of the application provides a method for manufacturing a chip, which includes the following steps:
  • a silicon wafer is selected as the substrate 101, and a device layer 102, a conductive interconnection layer 103 and an insulating passivation layer 104 are formed on the substrate 101 by using a semiconductor process to realize the pre-designed function of the chip.
  • the first opening 1041 is provided on the insulating passivation layer 104, and the specific method for setting the first opening 1041 is the same as that of the fifth embodiment, and this embodiment will not be repeated here.
  • a P-type heavily doped layer is formed in the substrate 101 at the first opening 1041.
  • the side of the silicon wafer opposite to the device layer 102 is thinned to a desired thickness.
  • S202 Fabricate a porous silicon layer 1012 on the substrate 101 to obtain the chip body 10; wherein the porous silicon structure is used to react with the chemical capping solution to destroy the chip body 10.
  • a reserved area is provided on the thinned side of the substrate 101, and the porous silicon layer 1012 is etched in the reserved area.
  • the specific growth method of the porous silicon layer 1012 is the same as that of the fifth embodiment, which will not be repeated in this embodiment.
  • the pores of the porous silicon layer 1012 are filled with an oxidant.
  • the oxidant can be sulfur, Ca(ClO 4 ) 2 , NH 4 ClO 4 , LiClO 4 , NaClO 4 , KClO 4 , Ca(NO 3 ) 2 , NH 4 NO 3 , KNO 3 or Gd(NO 3 ) 3 One or more of.
  • a second opening 1042 is provided on the insulating passivation layer 104, and the second opening 1042 is connected to the pad.
  • a photolithography process is used to open a second opening 1042 on the passivation insulating layer 104 in an area corresponding to the pad to expose the pad.
  • the area 105 along the chip dicing lane cuts the silicon wafer into individual small chips.
  • the chip body 10 is packaged by a packaging structure.
  • packaging of the chip body 10 is the same as that of the fifth embodiment, and this embodiment will not be repeated here.
  • the embodiment of the present application provides a method for manufacturing a chip, which corresponds to the chip provided in the third embodiment.
  • the embodiment of the application provides a method for manufacturing a chip, which includes the following steps:
  • a silicon wafer is selected as the substrate 101, and the device layer 102, the conductive interconnection layer 103 and the insulating passivation layer 104 are formed on the substrate 101 to realize the pre-designed function of the chip, wherein the insulating passivation layer 104 covers The device layer 102 and the conductive interconnection layer 103.
  • the first opening 1041 is provided on the insulating passivation layer 104, and the specific method for setting the first opening 1041 is the same as that of the fifth embodiment, and this embodiment will not be repeated here.
  • a second opening 1042 is provided on the insulating passivation layer 104, and the second opening 1042 is connected to the pad. Specifically, a photolithography process is used to open a second opening 1042 on the passivation insulating layer 104 in an area corresponding to the pad to expose the pad.
  • S302 Fabricate a porous silicon layer 1012 on the substrate 101 to obtain the chip body 10; wherein, the porous silicon structure is used to react with the chemical capping solution to destroy the chip body 10.
  • a groove is provided on the substrate 101 as the accommodating cavity 1011, the accommodating cavity 1011 is connected to the first opening 1041, and the manufactured porous silicon wafer 1013 is put into the accommodating cavity 1011 through the first opening 1041 Inside.
  • the gap between the accommodating cavity 1011 and the porous silicon wafer 1013 is filled with an organic material 1014 that can be dissolved in a chemical capping solution.
  • the side of the silicon wafer opposite to the device layer 102 is reduced to a desired thickness, and the silicon wafer is cut into individual small chips along the area 105 of the chip dicing lane.
  • the chip body 10 is packaged by a packaging structure.
  • packaging of the chip body 10 is the same as that of the fifth embodiment, and this embodiment will not be repeated here.
  • the embodiment of the present application provides a method for manufacturing a chip, which corresponds to the chip provided in the fourth embodiment.
  • the embodiment of the application provides a method for manufacturing a chip, which includes the following steps:
  • a silicon wafer is selected as the substrate 101, and the device layer 102, the conductive interconnection layer 103, and the insulating passivation layer 104 are formed on the substrate 101 using a semiconductor processing technology to realize the pre-designed function of the chip;
  • a second opening 1042 is provided on the layer 104, and the second opening 1042 is connected to the pad.
  • a photolithography process is used to open a second opening 1042 on the passivation insulating layer 104 in the region corresponding to the pad to expose the pad; the side of the silicon wafer opposite to the device layer 102 is thinned to a desired thickness.
  • S402 Fabricate a porous silicon layer 1012 on the substrate 101 to obtain the chip body 10; wherein, the porous silicon structure is used to react with the chemical capping solution to destroy the chip body 10.
  • a groove is provided on the substrate 101 as the containing cavity 1011, and the containing cavity 1011 is opposite to the device layer 102, and the manufactured porous silicon wafer 1013 is put into the containing cavity 1011 through the first opening 1041.
  • the gap between the accommodating cavity 1011 and the porous silicon wafer 1013 is filled with an organic material 1014 that can be dissolved in a chemical capping solution.
  • the area 105 along the chip dicing lane cuts the silicon wafer into individual small chips.
  • the chip body 10 is packaged by a packaging structure.
  • the packaging of the chip body 10 is basically the same as that of the fifth embodiment above, and this embodiment will not be repeated here.
  • the chip described in each embodiment of the present application may be an integrated circuit in CMOS process or other semiconductor processes, such as a chip containing a memory circuit, or a microelectromechanical (MEMS) chip.
  • the MEMS chip includes a substrate, and a microstructure and sensor layer processed on the substrate.
  • the device layer may be an integrated circuit layer, a microstructure, or a sensor layer, etc., various structures that can realize various signal detection, control, storage, physical quantity conversion and other functions.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

L'invention concerne une puce et son procédé de fabrication. La puce comprend un corps de puce (10). Le corps de puce (10) comprend : un substrat (101), une couche de dispositif (102) et une structure de silicium poreux. La couche de dispositif (102) est située sur le substrat (101). La structure de silicium poreux est disposée sur le substrat (101) et est utilisée pour réagir avec la solution de décapsulage chimique pour endommager le corps de puce (10). Selon la puce, l'acide nitrique en tant que solution de décapsulage chimique réagit avec la structure de silicium poreux pour endommager le corps de puce, les informations stockées dans la puce sont protégées contre le craquage et le vol, et la sécurité de la puce est améliorée.
PCT/CN2019/071682 2019-01-15 2019-01-15 Puce et son procédé de fabrication WO2020146994A1 (fr)

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CN201980000113.2A CN111699551B (zh) 2019-01-15 2019-01-15 芯片及芯片的制造方法
PCT/CN2019/071682 WO2020146994A1 (fr) 2019-01-15 2019-01-15 Puce et son procédé de fabrication

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