WO2020143469A1 - 显示面板、显示面板的制造方法和显示装置 - Google Patents

显示面板、显示面板的制造方法和显示装置 Download PDF

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Publication number
WO2020143469A1
WO2020143469A1 PCT/CN2019/128732 CN2019128732W WO2020143469A1 WO 2020143469 A1 WO2020143469 A1 WO 2020143469A1 CN 2019128732 W CN2019128732 W CN 2019128732W WO 2020143469 A1 WO2020143469 A1 WO 2020143469A1
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semiconductor layer
layer
active switch
forming
display panel
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PCT/CN2019/128732
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English (en)
French (fr)
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卓恩宗
莫琼花
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惠科股份有限公司
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Priority to US17/298,015 priority Critical patent/US11791416B2/en
Publication of WO2020143469A1 publication Critical patent/WO2020143469A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel, a method of manufacturing the display panel, and a display device.
  • the display device is a liquid crystal display device (Liquid Crystal Display, LCD) or an organic electroluminescence display device (Organic Light-Emitting Display, OLED) is provided with an active switch (Thin Film Transistor, TFT), the performance of the active switch is greatly Affects the performance of the display device.
  • the active switch can be set in the display area (AA area) for controlling the display of the pixels, or can be set in the non-display area such as the gate drive circuit (Gate On Array, GOA) area as the drive circuit Part.
  • Active switches can be divided into amorphous silicon active switches, low temperature poly-silicon (LTPS) active switches and oxide semiconductor active switches by the material of the active layer.
  • amorphous silicon active switches are widely used in the display field, their large size is not easy to achieve narrow borders, and their power consumption is also large.
  • the purpose of the present application is to provide a display panel, a manufacturing method of the display panel, and a display device that take into consideration both the reduction of the frame and the reduction of power consumption.
  • the present application discloses a method for manufacturing a display panel, including forming a first active switch containing a first semiconductor layer in a display area of the display panel, and forming a second active switch containing a second semiconductor layer in a non-display area of the display panel In the step; wherein, in the step, the material of the formed first semiconductor layer is oxide, the material of the formed second semiconductor layer is polysilicon, and the first semiconductor layer and the second semiconductor layer are formed On the same floor.
  • the present application also discloses a display panel including a substrate, the substrate is divided into a display area and a non-display area; the display area includes a first active switch, the first active switch includes a first semiconductor layer, the first A semiconductor layer is composed of an oxide material; the non-display area includes a second active switch, the second active switch includes a second semiconductor layer, the second semiconductor layer is composed of a polysilicon material; the first semiconductor layer and The second semiconductor layer is disposed on the same layer.
  • the present application also discloses a display device including a display panel and a driving circuit for driving the display panel.
  • the display panel is divided into a display area and a non-display area, and includes a substrate.
  • the substrate includes a first active switch and A second active switch, the first active switch is formed in the display area, the first active switch includes a first semiconductor layer, the first semiconductor layer is composed of an oxide material; the second active switch is formed in In the non-display area, the second active switch includes a second semiconductor layer, and the second semiconductor layer is made of polysilicon material; the first semiconductor layer and the second semiconductor layer are disposed on the same layer.
  • This application can reduce the power consumption of the circuit in the display area while achieving a narrow bezel.
  • first semiconductor layer and the second semiconductor layer after applying the first semiconductor layer and the second semiconductor layer to one layer, only two insulating layers are needed The layer is separated from other conductive layers, and if the first semiconductor layer and the second semiconductor layer are made different layers, the first one needs an insulating layer to make the two semiconductor layers have different heights, and at least two more insulating layers The one semiconductor layer and the second semiconductor layer are separated from other conductive layers, so this application can also reduce the manufacturing process of the insulating layer and improve the production efficiency.
  • FIG. 1 is a schematic diagram of a method for manufacturing a display panel according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of a method of manufacturing a display panel according to another embodiment of the present application.
  • FIG. 3 is a schematic diagram of a method of manufacturing a display panel according to another embodiment of the present application.
  • FIG. 4 is a schematic diagram of a method of manufacturing a display panel according to another embodiment of the present application.
  • FIG. 5 is a schematic diagram of a display panel according to another embodiment of the present application.
  • FIG. 6 is a schematic diagram of a display panel according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a display device according to another embodiment of the present application.
  • first and second are used only for descriptive purposes and cannot be understood as indicating relative importance, or implicitly indicating the number of technical features indicated.
  • the features defined as “first” and “second” may expressly or implicitly include one or more of the features; “multiple” means two or more.
  • the term “comprising” and any variations thereof are meant to be non-exclusive and one or more other features, integers, steps, operations, units, components, and/or combinations thereof may be present or added.
  • connection should be understood in a broad sense, such as fixed connection, detachable connection, or integral connection; may be mechanical connection It can also be an electrical connection; it can be directly connected, indirectly connected through an intermediary, or connected within two components.
  • an embodiment of the present application discloses a method of manufacturing a display panel 200, including forming a first active switch 410 including a first semiconductor layer 411 in the display area 400 of the display panel 200, and displaying The step of forming the second active switch 510 including the second semiconductor layer 511 in the non-display area 500 of the panel 200; wherein, in the above step, the material of the first semiconductor layer 411 is oxide, and the second semiconductor layer 511 is formed The material is polysilicon, and the first semiconductor layer 411 and the second semiconductor layer 511 are formed on the same layer.
  • the polysilicon mentioned in this application can be formed by a laser method, so it can be called low-temperature polysilicon, so the second active switch 510 can also be called a low-temperature polysilicon active switch.
  • this application combines the active switch of polysilicon and the active switch of oxide semiconductor to achieve the active switch of oxide semiconductor After the display area 400, the electron mobility in the active switch of the oxide semiconductor can reach 20-50 times that of the amorphous active switch, and the higher the mobility, the smaller the resistivity, and the lower the power consumption when passing the same current.
  • the display also has a more refined display effect than the previous display; the amorphous silicon display is even in When displaying a still picture, the data will be constantly refreshed, which naturally forms a continuous operation of the screen, thereby making the screen a large power-consuming user.
  • the oxide display screen uses a mode in which the current is switched between ON and OFF when displaying a still picture, which means that the oxide display screen does not constantly refresh, but the current is intermittently turned on and off. The picture we see from the screen when refreshing can actually be understood as the "cache content" of the previously displayed picture. In this way, the power consumption of the oxide display screen can be greatly reduced to one-fifth or even one-tenth; in summary, the active switch of the oxide semiconductor can reduce the power consumption.
  • the electron mobility in the active switch of polysilicon is more than 10 times that of the active switch of the oxide semiconductor, which means that the active switch of polysilicon only needs a smaller number to achieve the original purpose, so the active switch of polysilicon
  • the small size reduces the area of the non-display area 500, which can meet the needs of the market with narrow bezels. Based on this, the present application can reduce the power consumption of the display area 400 while achieving a narrow bezel.
  • the second semiconductor layer 511 is a different layer.
  • an insulating layer is required to make the two semiconductor layers have different heights. At least two insulating layers are needed to separate the first semiconductor layer 411 and the second semiconductor layer 511 from other conductive layers. Open, so this application can also reduce the manufacturing process of the insulating layer and improve production efficiency.
  • a first active switch 410 containing a first semiconductor layer 411 is formed in the display area 400 of the display panel 200, and a second semiconductor layer is formed in the non-display area 500 of the display panel 200
  • the step of the second active switch 510 of 511 includes the following steps:
  • step A forming a second semiconductor layer in the non-display area; wherein, step A includes:
  • step A1 forming an undoped second semiconductor layer in the non-display area; wherein, step A1 includes:
  • A11 forming a substrate
  • step A12 forming a polysilicon layer on the substrate; wherein, step A12 includes:
  • A121 An amorphous silicon layer is formed on the substrate
  • A122 Convert the amorphous silicon layer into a polycrystalline silicon layer
  • A13 forming a first photoresist on the polysilicon layer, etching the polysilicon layer to form a second semiconductor layer in the non-display area;
  • A14 Strip the first photoresist
  • step A2 heavily doped and lightly doped the undoped second semiconductor layer to form an intrinsic layer, a first doped layer, and a second doped layer; wherein, step A2 includes:
  • A21 forming a second photoresist on the second semiconductor layer, the second photoresist is shorter than the second semiconductor layer;
  • A22 heavily doping the second semiconductor layer, and forming the first doped layer by the portion not blocked by the second photoresist;
  • A23 Stripping the second photoresist, and forming a third photoresist shorter than the second photoresist on the second semiconductor layer, wherein the part of the second semiconductor layer covered by the third photoresist is an intrinsic layer;
  • A24 Lightly doping the second semiconductor layer, forming a second doped layer between the first doped layer and the intrinsic layer;
  • A25 Strip the third photoresist
  • the source and drain of the first active switch 410 formed in step D communicate with the first semiconductor layer 411 formed in step B, respectively, and the source and drain of the second active switch 510 formed in step D are respectively connected with The second semiconductor layer 511 formed in step A is connected.
  • the second semiconductor layer 511 composed of polysilicon material is formed first, and then the first semiconductor layer 411 composed of oxide is formed. Since the structure in the second semiconductor layer 511 is relatively complicated, it needs to be doped in addition to etching As a result, the second semiconductor layer 511 with a complicated structure is processed first to avoid the first semiconductor layer 411 from affecting it, and the process efficiency of the second semiconductor layer 511 can be improved.
  • the second semiconductor layer 511 may not be doped in step A, that is, only step A1 is performed in step A, and step A2 is not performed, which does not affect the function of the second active switch 510. In this solution, the doping step is reduced and the manufacturing efficiency is improved.
  • step A1 may also be to first form an amorphous silicon layer on the substrate 310, then form a photoresist on the amorphous silicon, and then etch the amorphous silicon layer to form a second in the non-display area 500 The semiconductor layer 511 is finally stripped of photoresist.
  • Wet stripping the polysilicon layer can be etched using dry etching, and hydrogen bromide (HBr) can be used as the etching gas
  • the amorphous silicon can be etched using dry etching, which can be etched with fluorine or chlorine based plasma, Such as CH 4 , CHF 3 , SF 6 , NF 3 , Cl 2 , CF 2 Cl 2 and SiCl 4 .
  • a step is further included between step A11 and step A12: forming a buffer layer on the substrate.
  • the substrate 310 is generally made of glass and contains metal impurities. If there is no buffer layer 320, the metal impurities will run on the active layer, which may cause a short circuit and affect the yield of the display panel.
  • the method for converting the amorphous silicon layer into a polycrystalline silicon layer may be a laser method, and the amorphous silicon is subjected to solid phase crystallization (SPC) to convert the amorphous silicon into polycrystalline silicon to form polycrystalline silicon; in addition, an excimer Laser annealing (ELA) can also play a role in converting the amorphous silicon layer into a polysilicon layer.
  • SPC solid phase crystallization
  • ELA excimer Laser annealing
  • the embodiment of the present application further discloses a manufacturing method of the display panel 200, including the steps of:
  • A1 forming an undoped second semiconductor layer in the non-display area
  • step A2 heavily doped and lightly doped the undoped second semiconductor layer to form an intrinsic layer, a first doped layer, and a second doped layer; wherein, step A2 includes:
  • A26 forming a fourth photoresist on the second gate, the fourth photoresist is shorter than the second semiconductor layer and longer than the second gate;
  • the second semiconductor layer is heavily doped, and the second semiconductor layer not blocked by the fourth photoresist forms the first doped layer; the part blocked by the second gate is an intrinsic layer;
  • A28 Stripping the fourth photoresist and lightly doping the second semiconductor layer, forming a portion between the intrinsic layer and the first doped layer as the second doped layer;
  • the source and drain of the first active switch 410 formed in step D communicate with the first semiconductor layer 411 formed in step B, respectively, and the source and drain of the second active switch 510 formed in step D are respectively connected with The second semiconductor layer 511 formed in step A is connected.
  • the gate electrode is used to replace a photoresist when doping the second semiconductor layer 511, which reduces the process time of the photoresist.
  • the power of the ion arrangement process needs to be increased here to ensure that the doped components can enter the second semiconductor layer 511.
  • the embodiment of the present application further discloses a manufacturing method of the display panel 200, including the steps of:
  • step B includes:
  • the oxide semiconductor layer is etched into the first semiconductor layer
  • step A forming a second semiconductor layer in the non-display area; wherein, step A includes:
  • A1 forming an undoped second semiconductor layer in the non-display area
  • A2 heavily doped and lightly doped the undoped second semiconductor layer to form an intrinsic layer, a first doped layer and a second doped layer;
  • A3 Strip the fifth photoresist
  • the first semiconductor layer 411 composed of an oxide material is formed first, and then the second semiconductor layer 511 composed of a polysilicon material is formed. Since the material of the first semiconductor is similar to the material of the general transparent electrode layer 370, it is relatively fragile. , so forming the first semiconductor layer 411 on the substrate 310 is beneficial to the forming of the first semiconductor; in addition, after the first semiconductor layer 411 is completed, the fifth Photoresist, wait until the second semiconductor layer 511 is converted, etched out and doped, and then stripped, so that the fifth photoresist can also block the laser light, etching solution and doping elements. It is advantageous for the first semiconductor layer 411 to remain as it is.
  • the embodiment of the present application further discloses a manufacturing method of the display panel 200, including the steps of:
  • the oxide semiconductor layer is etched into the first semiconductor layer
  • A1 forming an undoped second semiconductor layer in the non-display area
  • A3 Strip the fifth photoresist
  • A2 heavily doped and lightly doped the undoped second semiconductor layer to form an intrinsic layer, a first doped layer and a second doped layer;
  • D Synchronously form the second insulating layer of the first active switch and the second active switch; and, simultaneously form the source and drain of the first active switch and the second active switch.
  • the present application discloses a display panel 200, which is divided into a display area 400 and a non-display area 500, including a substrate 300, and the substrate 300 includes; a first active The switch 410 is formed in the display area 400, the first active switch 410 includes a first semiconductor layer 411, and the first semiconductor layer 411 is composed of an oxide material; the second active switch 510, formed in the non-display area 500, the second active switch 510 The second semiconductor layer 511 is included, and the second semiconductor layer 511 is made of polysilicon material; wherein, the first semiconductor layer 411 and the second semiconductor layer 511 are disposed on the same layer.
  • the first active switch 410 includes a first thin film transistor
  • the second active switch 510 includes a second thin film transistor
  • the first thin film transistor and the second thin film transistor are high-level conductive thin film transistors.
  • the first semiconductor may be IGZO (Indium Gallium Zinc Oxide), In2O3 (Indium oxide), IZO (Indium Zinc Oxide) and IGZO (Indium gallium oxide zinc) oxide, at least one of indium gallium zinc oxide), where the first semiconductor can be selected as the IGZO semiconductor, because the technology of using IGZO as a semiconductor is more mature, so the first thin film transistor is also an IGZO thin film transistor.
  • the second thin film transistor is an LTPS (Low Temperature Poly-silicon) thin film transistor.
  • the first thin film transistor includes a first gate 412
  • the second thin film transistor includes a second gate 512
  • the first gate 412 and the second gate 512 are disposed on the same layer.
  • the two grids are arranged on the same layer.
  • the substrate 300 includes a substrate 310, a first semiconductor layer 411 is disposed between the first gate 412 and the substrate 310, and the second semiconductor layer 511 is disposed between the second gate 512 and the substrate 310 between.
  • the first thin-film transistor and the second thin-film transistor adopt a top-gate structure, which can prevent external light from irradiating the polysilicon, generating photocurrent, and affecting the display effect.
  • the first gate 412 and the second gate 512 can also be between the substrate 310 and the semiconductor layer, which can reduce the influence of the backlight on the polysilicon; and the first gate 412 and the second gate 512 may not To achieve the same level, not limited here.
  • the substrate 300 includes a buffer layer 320 disposed between the substrate 310 and the first semiconductor layer 41.
  • the first thin film transistor includes a first source 413 and a first drain 414
  • the second thin film transistor includes a second source 513 and a second drain 514
  • the first source 413, the first drain 414, the second source electrode 513 and the second drain electrode 514 are disposed on the same layer.
  • the source and drain of the first thin-film transistor and the second thin-film transistor are arranged in the same layer.
  • the first source 413 and the first drain 414 can be formed through a photomask process 2.
  • the second source electrode 513 and the second drain electrode 514 are processed at the same time, reducing process steps and improving manufacturing efficiency.
  • the substrate 300 includes a first via 331, a second via 332, a third via 333, and a fourth via 334.
  • the first source 413 passes through the first via 331 and the first semiconductor layer 411 Is connected to the other end of the first semiconductor layer 411 through the second via 332; the second source 513 is connected to one end of the second semiconductor layer 511 through the third via 333, the second drain
  • the pole 514 is connected to the other end of the second semiconductor layer 511 through the fourth via 334; wherein the position of the first gate 412 corresponds to the position of the first semiconductor layer 411, and the width of the first gate 412 is smaller than that of the first semiconductor layer
  • the width of 411, the position of the second gate 512 corresponds to the position of the second semiconductor layer 511, and the width of the second gate 512 is smaller than the width of the second semiconductor layer 511.
  • the width of the first gate 412 is smaller than the width of the first semiconductor layer 411, and the width of the second gate 512 is smaller than the width of the second semiconductor layer 511, so that the first via 331 and the second via 332 are processed , The third via 333 and the fourth via 334 will not be interfered.
  • the second semiconductor layer 511 includes two first doped layers 5111, two second doped layers 5112 and intrinsic layers 5113, two first doped layers 5111, two second doped
  • the arrangement of layer 5112 and intrinsic layer 5113 is first doped layer 5111, second doped layer 5112, intrinsic layer 5113, second doped layer 5112 and first doped layer 5111, and third via 333 and The fourth via 334 corresponds to the first doped layer 5111, and the width of the second gate 512 is equal to the width of the intrinsic layer 5113.
  • the second gate 512 when the second semiconductor layer 511 is doped, the second gate 512 can act as a photoresist to prevent the intrinsic layer 5113 from being doped, so the intrinsic layer 5113 and the second gate 512 The widths are equal, which can reduce one photoresist process when forming the first doped layer 5111 and the second doped layer 5112.
  • the first doped layer 5111 is a heavily doped layer
  • the second doped layer 5112 is a lightly doped layer
  • both the first doped layer 5111 and the second doped layer 5112 are doped with phosphorus.
  • the substrate 300 further includes a first insulating layer 340, a second insulating layer 350, a third insulating layer 360, a fifth via 335, and a transparent electrode layer 370;
  • the buffer layer 320 is disposed on Above the substrate 310, the first semiconductor layer 411 and the second semiconductor layer 511 are disposed above the buffer layer 320, the first insulating layer 340 is disposed above the first semiconductor layer 411 and the second semiconductor layer 511, and the first gate 412 and the second gate 512 are disposed above the first insulating layer 340, the second insulating layer 350 can be disposed above the first gate 412 and the second gate 512, the first source 413, the first drain 414 , The second source electrode 513 and the second drain electrode 514 are disposed above the second insulating layer 350, the first via hole 331 communicates with the first source electrode 413 and the first semiconductor layer 411, and the second via hole 332 communicates with the first drain electrode 414 and the first semiconductor layer 4
  • a display device 100 including the above-described display panel 200 and a driving circuit 600 that drives the display panel 200.
  • the technical solution of the present application can be widely used in various display panels, such as twisted nematic (TN) display panel, in-plane switching (IPS) display panel, vertical alignment type (Vertical Alignment, VA) ) Display panel, multi-quadrant vertical alignment (Multi-Domain Vertical Alignment, MVA) display panel, of course, it can also be other types of display panels, such as organic light-emitting diode (Organic Light-Emitting Diode, OLED) display panel, both The above scheme is applicable.
  • TN twisted nematic
  • IPS in-plane switching
  • VA Vertical Alignment
  • MVA multi-quadrant vertical alignment
  • OLED Organic Light-Emitting Diode

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Abstract

本申请公开了一种显示面板、显示面板的制造方法和显示装置，包括在显示面板(200)的显示区(400)形成含有第一半导体层(411)的第一主动开关(410)，并在显示面板(200)的非显示区(500)形成含有第二半导体层(511)的第二主动开关(510)的步骤；其中，形成的第一半导体层(411)的材料为氧化物，形成的第二半导体层(511)的材料为多晶硅，且第一半导体层(411)和第二半导体层(511)形成在同一层。

Description

显示面板、显示面板的制造方法和显示装置
本申请要求于2019年1月11日提交中国专利局，申请号为CN201910024973.1，申请名称为“一种显示面板、显示面板的制造方法和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板、显示面板的制造方法和显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
显示装置无论是液晶显示装置(Liquid Crystal Display，LCD)，还是有机电致发光显示装置(Organic Light-Emitting Display，OLED)都设置有主动开关(Thin Film Transistor，TFT)，主动开关的性能极大地影响着显示装置的性能。在显示装置中，主动开关可以设置在显示区域(AA区)，用于对像素的显示进行控制，也可以设置在非显示区域例如栅极驱动电路(Gate On Array，GOA)区域作为驱动电路的一部分。主动开关可以通过有源层的材料分为非晶硅主动开关、低温多晶硅(Low Temperature Poly-silicon，LTPS)主动开关和氧化物半导体主动开关。
非晶硅主动开关虽然被广泛应用于显示领域，但是其体积较大不易实现窄边框，且其功耗也较大。
发明内容
本申请的目的是提供一种的兼顾减小边框和降低功耗的显示面板、显示面板的制造方法和显示装置。
本申请公开了一种显示面板的制造方法，包括在显示面板的显示区形成含有第一半导体层的第一主动开关，并在显示面板的非显示区形成含有第二半导体层的第二主动开关的步骤中；其中，所述的步骤中，形成的第一半导体层的材料为氧化物，形成的第二半导体层的材料为多晶硅，且所述第一半导体层和所述第二半导体层形成在同一层。
本申请还公开了一种显示面板,包括基板，所述基板划分为显示区和非显示区；所述显示区包括第一主动开关，所述第一主动开关包括第一半导体层，所述第一半导体层由氧化物材料构成；所述非显示区包括第二主动开关，所述第二主动开关包括第二半导体层，所述第二半导体层由多晶硅材料构成；所述第一半导体层和所述第二半导体层设置在同一层。
本申请还公开了一种显示装置，包括显示面板和用于驱动所述显示面板的驱动电路，所述显示面板划分为显示区和非显示区，包括基板，所述基板包括第一主动开关和第二主动开关，所述第一主动开关形成在所述显示区，所述第一主动开关包括第一半导体层，所述第一半导体层由氧化物材料构成；所述第二主动开关形成在所述非显示区，所述第二主动开关包括第二半导体层，所述第二半导体层由多晶硅材料构成；所述第一半导体层和所述第二半导体层设置在同一层。
本申请在实现窄边框的同时，可以降低显示区中电路的功耗，另外本申请将第一半导体层和第二半导体层做到一层后，只需要两道绝缘层就能将两个半导体层与其它导电层隔开，而如果将第一半导体层和第二半导体层做到不同层，那个首先要一道绝缘层使两个半导体层高度不一，另外起码还需要两道绝缘层将第一半导体层、第二半导体层与其它导电层隔开，所以本申请还可以减少绝缘层的制程，提高生产效率。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请的一实施例的一种显示面板制造方法的示意图；
图2是本申请的另一实施例的显示面板制造方法的示意图；
图3是本申请的另一实施例的显示面板制造方法的示意图；
图4是本申请的另一实施例的显示面板制造方法的示意图；
图5是本申请的另一实施例的一种显示面板的示意图；
图6是本申请的一实施例的一种显示面板的示意图；
图7是本申请的另一实施例的一种显示装置的示意图。
具体实施方式
需要理解的是，这里所使用的术语、公开的具体结构和功能细节，仅仅是为了描述具体实施例，是代表性的，但是本申请可以通过许多替换形式来具体实现，不应被解释成仅受限于这里所阐述的实施例。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示相对重要性，或者隐含指明所指示的技术特征的数量。由此，除非另有说明，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征；“多个”的含义是两个或 两个以上。术语“包括”及其任何变形，意为不排他的包含，可能存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
另外，“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系的术语，是基于附图所示的方位或相对位置关系描述的，仅是为了便于描述本申请的简化描述，而不是指示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
下面参考附图和可选的实施例对本申请作进一步说明。
如图1至图4所示，本申请实施例公开了一种显示面板200的制造方法，包括在显示面板200的显示区400形成含有第一半导体层411的第一主动开关410，并在显示面板200的非显示区500形成含有第二半导体层511的第二主动开关510的步骤；其中，上述步骤中，形成的第一半导体层411的材料为氧化物，形成的第二半导体层511的材料为多晶硅，且第一半导体层411和第二半导体层511形成在同一层。
其中本申请中提到的多晶硅可以通过镭射方法形成，所以可称为低温多晶硅，因此第二主动开关510也可称为低温多晶硅主动开关。
本方案中，相对于只含一种类型的主动开关或含有非晶硅主动开关的方案来说，本申请结合多晶硅的主动开关和氧化物半导体的主动开关，将氧化物半导体的主动开关做到显示区400后，氧化物半导体的主动开关中电子迁移率能够达到非晶主动开关的20-50倍，而迁移率越高，电阻率越小，通过相同电流时，功耗也就越小，这对显示屏的低功耗表现，有着非常大的作用；同时，基于极高的电子迁移率，显示屏也要比以往的显示屏具备更加精细的显示效果；非晶硅型显示屏即便在显示静止画面时，也会不断地进行数据的刷新，这自然也就形成了屏幕不间断的在运作，从而使屏幕成为了耗电大户。而氧化物型显示屏在显示静止画面时采用了电流在ON与OFF之间切换的模式，也就是说氧化物型显示屏并非不断地进行刷新，而是间歇性的开启、关闭电流，当未刷新时我们从屏幕中看到的画面其实可以理解为此前显示的画面的“缓存内容”。这样一来氧化物型显示屏的耗电可以大幅度缩减至五分之一甚至十分之一；综上，氧化物半导体的主动开关有降低功耗的作用。
多晶硅的主动开关中电子迁移率是氧化物半导体的主动开关中电子迁移率的10倍以上，意味着多晶硅的主动开关只需要较少的数量就能达到原来的目的，所以由于多晶硅的主 动开关的尺寸较小，因而减小了非显示区500的面积，从而可以满足市场窄边框的需求。基于此，本申请在实现窄边框的同时，可以降低显示区400的功耗。
另外本申请将第一半导体层411和第二半导体层511做到一层后，只需要两道绝缘层就能将两个半导体层与其它导电层隔开，而如果将第一半导体层411和第二半导体层511做到不同层，那个首先要一道绝缘层使两个半导体层高度不一，另外起码还需要两道绝缘层将第一半导体层411、第二半导体层511与其它导电层隔开，所以本申请还可以减少绝缘层的制程，提高生产效率。
在一实施例中，如图1所示，在显示面板200的显示区400形成含有第一半导体层411的第一主动开关410，并在显示面板200的非显示区500形成含有第二半导体层511的第二主动开关510的步骤中，包括以下步骤：
A：在非显示区形成第二半导体层；其中，步骤A包括：
A1：在非显示区形成未掺杂的第二半导体层；其中，步骤A1包括：
A11：形成衬底；
A12：在衬底上形成一层多晶硅层；其中，步骤A12包括：
A121：在衬底上形成一层非晶硅层；
A122：将非晶硅层转化为多晶硅层；
A13：在多晶硅层上形成第一光刻胶，蚀刻多晶硅层在非显示区形成第二半导体层；
A14：剥离第一光刻胶；
A2：对未掺杂的第二半导体层进行重掺杂和轻掺杂，形成本征层、第一掺杂层和第二掺杂层；其中，步骤A2包括：
A21：在第二半导体层上形成第二光刻胶，第二光刻胶短于第二半导体层；
A22：对第二半导体层重掺杂，将未被第二光刻胶遮挡的部分形成第一掺杂层；
A23：剥离第二光刻胶，并在第二半导体层上形成比第二光刻胶短的第三光刻胶，其中第二半导体层被第三光刻胶覆盖的部分为本征层；
A24：对第二半导体层进行轻掺杂，在第一掺杂层和本征层之间形成第二掺杂层；
A25：剥离第三光刻胶；
B：在显示区形成第一半导体层；
C：同步形成第一主动开关和第二主动开关的第一绝缘层；以及，同步形成第一主动开关和第二主动开关的第一栅极、第二栅极；
D：同步形成第一主动开关和第二主动开关的第二绝缘层；以及，同步形成第一主动开关和第二主动开关的源极、漏极；
其中，步骤D中形成的第一主动开关410的源极、漏极分别与步骤B中形成的第一半导体层411连通，步骤D中形成的第二主动开关510的源极、漏极分别与步骤A中形成的第二半导体层511连通。
本方案中，先形成由多晶硅材料构成的第二半导体层511，再形成由氧化物构成的第一半导体层411，由于第二半导体层511中的结构比较复杂，除了要蚀刻外还要进行掺杂，所以先把结构复杂的第二半导体层511加工完，避免第一半导体层411对其影响，能够提高第二半导体层511的制程效率。
在一实施例中，步骤A中可以不对第二半导体层511进行掺杂，也就是只步骤A中只进行步骤A1，不进行步骤A2，这样也不影响第二主动开关510的作用。本方案中，减少掺杂步骤，提高制作效率。
在一实施例中，步骤A1还可以是先在衬底310上形成一层非晶硅层，然后在非晶硅上形成光刻胶，然后蚀刻非晶硅层在非显示区500形成第二半导体层511，最后剥离光刻胶。
在上述实施例中，光刻胶的剥离方式采用干法剥离和湿法剥离都行，常用DMSO:MEA＝7.3(质量比)的比例混合成的无色、透明但是有刺激性气味的剥离液进行湿法剥离；对多晶硅层的蚀刻方法可以采用干蚀刻，可以采用溴化氢(HBr)作为蚀刻气体；非晶硅的蚀刻方式可采用干蚀刻，可用氟基或氯基的等离子刻蚀，如CH 4，CHF 3，SF 6,NF 3,Cl 2，CF 2Cl 2和SiCl 4。
在一实施例中，步骤A11和步骤A12之间还包括步骤：在衬底上形成一层缓冲层。本方案中，衬底310一般为玻璃材质，其中含有有金属杂质，如果没有缓冲层320的话，金属杂质会跑到有源层上，可能导致短路，影响显示面板的良率。
在步骤A122中，将非晶硅层转化为多晶硅层的方法可以为镭射法，将非晶硅进行固相结晶化处理(SPC)使其中的非晶硅转变为多晶硅以形成多晶硅；另外准分子激光退火(ELA)也能起到将非晶硅层转化为多晶硅层的作用。
作为本申请的另一个实施例，如图2所示，本申请实施例还公开了一种显示面板200的制造方法，包括步骤：
A1：在非显示区形成未掺杂的第二半导体层；
B：在显示区形成第一半导体层；
C：同步形成第一主动开关和第二主动开关的第一绝缘层，以及同步形成第一主动开关和第二主动开关的第一栅极、第二栅极；
A2：对未掺杂的第二半导体层进行重掺杂和轻掺杂，形成本征层、第一掺杂层和第二掺杂层；其中，步骤A2包括：
A26：在第二栅极上形成第四光刻胶，第四光刻胶比第二半导体层短，并且长于第二栅极；
A27：对第二半导体层进行重掺杂，未被第四光刻胶遮挡的第二半导体层形成第一掺杂层；其中被第二栅极挡住的部分为本征层；
A28：剥离第四光刻胶，并对第二半导体层进行轻掺杂，将本征层和第一掺杂层之间的部分形成第二掺杂层；
D：同步形成第一主动开关和第二主动开关的第二绝缘层；以及，同步形成第一主动开关和第二主动开关的源极、漏极；
其中，步骤D中形成的第一主动开关410的源极、漏极分别与步骤B中形成的第一半导体层411连通，步骤D中形成的第二主动开关510的源极、漏极分别与步骤A中形成的第二半导体层511连通。
本方案中，对第二半导体层511掺杂时利用栅极替代一道光刻胶，减少了光刻胶的制程时间。上述实施例中，由于要隔着一层绝缘层对第二半导体层511进行掺杂，这里需要增加离子布置制程的功率，保证掺杂的成分能够进入到第二半导体层511中。
作为本申请的另一个实施例，如图3所示，本申请实施例还公开了一种显示面板200的制造方法，包括步骤：
B：在显示区形成第一半导体层；其中，步骤B包括：
B1：形成衬底；
B2：在衬底上形成一层氧化物半导体层；
B3：在氧化物半导体层上形成第五光刻胶；
B4：将氧化物半导体层蚀刻成第一半导体层；
A：在非显示区形成第二半导体层；其中，步骤A包括：
A1：在非显示区形成未掺杂的第二半导体层；
A2：对未掺杂的第二半导体层进行重掺杂和轻掺杂，形成本征层、第一掺杂层和第二掺杂层；
A3：剥离第五光刻胶；
C：同步形成第一主动开关和第二主动开关的第一绝缘层，以及同步形成第一主动开关和第二主动开关的第一栅极、第二栅极；
D：同步形成第一主动开关和第二主动开关的第二绝缘层；以及同步形成第一主动开关和第二主动开关的源极、漏极。
本方案中，先形成由氧化物材料构成的第一半导体层411，再形成由多晶硅材料构成的 第二半导体层511，由于第一半导体的材质与一般透明电极层370的材质相近，自身较脆弱，所以需要一个平整的环境，所以先在衬底310上形成第一半导体层411有利于第一半导体的成型；另外，在第一半导体层411步骤制作完成后，先不剥离其上方的第五光刻胶，等到第二半导体层511先进行转化、蚀刻出和掺杂完后再剥离，这样的话第五光刻胶还能起到阻挡镭射光、刻蚀液和掺杂元素的作用，有利于第一半导体层411保持原状。
作为本申请的另一个实施例，如图4所示，本申请实施例还公开了一种显示面板200的制造方法，包括步骤：
B1：形成衬底；
B2：在衬底上形成一层氧化物半导体层；
B3：在氧化物半导体层上形成第五光刻胶；
B4：将氧化物半导体层蚀刻成第一半导体层；
A1：在非显示区形成未掺杂的第二半导体层；
A3：剥离第五光刻胶；
C：同步形成第一主动开关和第二主动开关的第一绝缘层，以及同步形成第一主动开关和第二主动开关的第一栅极、第二栅极；
A2：对未掺杂的第二半导体层进行重掺杂和轻掺杂，形成本征层、第一掺杂层和第二掺杂层；
D：同步形成第一主动开关和第二主动开关的第二绝缘层；以及，同步形成第一主动开关和第二主动开关的源极、漏极。
作为本申请的另一个实施例，如图5和图6所示，本申请公开了一种显示面板200，划分为显示区400和非显示区500，包括基板300，基板300包括；第一主动开关410，形成在显示区400，第一主动开关410包括第一半导体层411，第一半导体层411由氧化物材料构成；第二主动开关510，形成在非显示区500，第二主动开关510包括第二半导体层511，第二半导体层511由多晶硅材料构成；其中，第一半导体层411和第二半导体层511设置在同一层。其中，所述第一主动开关410包括第一薄膜晶体管，所述第二主动开关510包括第二薄膜晶体管，所述第一薄膜晶体管和第二薄膜晶体管为高电平导通的薄膜晶体管。
本申请将两种主动开关的半导体做到一层后，只需要上下两道绝缘层来隔绝半导体层，如果不将两种主动开关的半导体做到一层，那么最少需要三层绝缘层才能隔绝半导体层，所以本申请还可以减少制程步骤。
在一实施例中，第一半导体可以为IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)、In2O3(Indium oxide，氧化铟)、IZO(Indium Zinc Oxide，氧化铟锌)以及 IGZO(Indium gallium zinc oxide，氧化铟镓锌)中的至少一种，这里可选第一半导体为IGZO半导体，因为将IGZO作为半导体的技术更加成熟，所以第一薄膜晶体管也是IGZO薄膜晶体管。另外，第二薄膜晶体管为LTPS(Low Temperature Poly-silicon，低温多晶硅)薄膜晶体管。
在一实施例中，如图6所示，第一薄膜晶体管包括第一栅极412，第二薄膜晶体管包括第二栅极512，第一栅极412与第二栅极512设置在同一层。本方案中，将两种栅极设置在同一层，在成型栅极时，可以通过一道光罩制程将第一栅极412和第二栅极512同时加工完成，减少制程步骤，提高制作效率。
在一实施例中，基板300包括衬底310，第一半导体层411设置在第一栅极412和衬底310之间，所述第二半导体层511设置在第二栅极512与衬底310之间。本方案中，第一薄膜晶体管和第二薄膜晶体管采取顶栅结构，可以防止外界光线照射到多晶硅上，产生光电流，影响显示效果。当然，第一栅极412和第二栅极512还可以都做到衬底310和半导体层之间，能够减少背光源对多晶硅的影响；而且第一栅极412与第二栅极512可以不做到同一层，在此不做限定。
在一实施例中，基板300包括缓冲层320，缓冲层320设置在衬底310和第一半导体层41之间。
在一实施例中，第一薄膜晶体管包括第一源极413和第一漏极414，第二薄膜晶体管包括第二源极513和第二漏极514，第一源极413、第一漏极414、第二源极513和第二漏极514设置在同一层。本方案中，将第一薄膜晶体管和第二薄膜晶体管的源、漏极设置在同一层，在成型源、漏极时，可以通过一道光罩制程将第一源极413、第一漏极414、第二源极513和第二漏极514同时加工完成，减少制程步骤，提高制作效率。
在一实施例中，基板300包括第一过孔331、第二过孔332、第三过孔333和第四过孔334，第一源极413通过第一过孔331与第一半导体层411的一端连接，第一漏极414通过第二过孔332与第一半导体层411的另一端连接；第二源极513通过第三过孔333与第二半导体层511的一端连接，第二漏极514通过第四过孔334与第二半导体层511的另一端连接；其中第一栅极412的位置与第一半导体层411的位置对应，且第一栅极412的宽度小于第一半导体层411的宽度，第二栅极512的位置与第二半导体层511的位置对应，且第二栅极512的宽度小于第二半导体层511的宽度。
本方案中，第一栅极412的宽度小于第一半导体层411的宽度，第二栅极512的宽度小于第二半导体层511的宽度，这样在加工第一过孔331、第二过孔332、第三过孔333和第四过孔334时，不会被干涉到。
在一实施例中，第二半导体层511包括两个第一掺杂层5111、两个第二掺杂层5112和本征层5113，两个第一掺杂层5111、两个第二掺杂层5112和本征层5113的排列方式为第一掺杂层5111、第二掺杂层5112、本征层5113、第二掺杂层5112和第一掺杂层5111，第三过孔333和第四过孔334与第一掺杂层5111对应，第二栅极512的宽度与本征层5113的宽度相等。本方案中，在对第二半导体层511进行掺杂时，第二栅极512可以充当光刻胶的作用，防止本征层5113被掺杂，所以令本征层5113与第二栅极512的宽度相等，可以在形成第一掺杂层5111和第二掺杂层5112时减少一道光刻胶的制程。其中，第一掺杂层5111为重掺杂层，第二掺杂层5112为轻掺杂层，第一掺杂层5111和第二掺杂层5112中掺杂的都是磷元素。
在一实施例中，如图6所示，基板300还包括第一绝缘层340，第二绝缘层350、第三绝缘层360、第五过孔335和透明电极层370；缓冲层320设置在衬底310的上方，第一半导体层411和第二半导体层511设置在缓冲层320的上方，第一绝缘层340设置在第一半导体层411和第二半导体层511的上方，第一栅极412和第二栅极512设置在第一绝缘层340的上方，第二绝缘层350能设置在第一栅极412和第二栅极512的上方，第一源极413、第一漏极414、第二源极513和第二漏极514设置在第二绝缘层350的上方，第一过孔331连通第一源极413和第一半导体层411，第二过孔332连通第一漏极414和第一半导体层411，第三过孔333连通第二源极513和第二半导体层511，第四过孔334连通第二漏极514和第二半导体层511，第三绝缘层360设置在第一源极413、第一漏极414、第二源极513和第二漏极514的上方，透明电极层370设置在第三绝缘层360的上方，第五过孔335连通透明电极层370和第一漏极414。
如图7所示，作为本申请的另一实施例，公开了一种显示装置100，包括上述显示面板200和驱动显示面板200的驱动电路600。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的技术方案可以广泛用于各种显示面板，如扭曲向列型(Twisted Nematic，TN)显示面板、平面转换型(In-Plane Switching，IPS)显示面板、垂直配向型(Vertical Alignment，VA)显示面板、多象限垂直配向型(Multi-Domain Vertical Alignment，MVA)显示面板，当然，也可以是其他类型的显示面板，如有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，均可适用上述方案。
以上内容是结合具体的可选的实施方式对本申请所作的详细说明，不能认定本申请的具 体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (19)

  1. 一种显示面板的制造方法，包括在显示面板的显示区形成含有第一半导体层的第一主动开关，并在显示面板的非显示区形成含有第二半导体层的第二主动开关的步骤；
    其中，形成的第一半导体层的材料为氧化物，形成的第二半导体层的材料为多晶硅，且所述第一半导体层和所述第二半导体层形成在同一层。
  2. 如权利要求1所述的一种显示面板的制造方法，其中，所述在显示面板的显示区形成含有第一半导体层的第一主动开关，并在显示面板的非显示区形成含有第二半导体层的第二主动开关的步骤中，包括以下步骤：
    在非显示区形成第二半导体层；
    在显示区形成第一半导体层；
    同步形成第一主动开关和第二主动开关的第一绝缘层，同步形成第一主动开关和第二主动开关的第一栅极、第二栅极；以及
    同步形成第一主动开关和第二主动开关的第二绝缘层，同步形成第一主动开关和第二主动开关的源极、漏极；
    其中，所述同步形成第一主动开关和第二主动开关的第二绝缘层，同步形成第一主动开关和第二主动开关的源极、漏极的步骤中，形成的所述第一主动开关的源极、漏极分别与所述第一主动开关的所述第一半导体层连通，形成的所述第二主动开关的源极、漏极分别与所述第二主动开关的所述第二半导体层连通。
  3. 如权利要求2所述的一种显示面板的制造方法，其中，所述在非显示区形成所述第二半导体层的步骤中，包括以下步骤：
    形成衬底；
    在衬底上形成一层非晶硅层；
    将非晶硅层转化为多晶硅层；
    在多晶硅层上形成第一光刻胶，蚀刻多晶硅层在非显示区形成第二半导体层；
    剥离第一光刻胶；以及
    对未掺杂的所述第二半导体层进行重掺杂和轻掺杂，形成本征层、第一掺杂层和第二掺杂层。
  4. 如权利要求3所述的一种显示面板的制造方法，其中，所述对未掺杂的所述第二半导体层进行重掺杂和轻掺杂，形成本征层、第一掺杂层和第二掺杂层的步骤中，包括以下步骤：
    在第二半导体层上形成第二光刻胶，所述第二光刻胶短于所述第二半导体层；
    对第二半导体层重掺杂，将未被第二光刻胶遮挡的部分形成第一掺杂层；
    剥离第二光刻胶，并在第二半导体层上形成比第二光刻胶短的第三光刻胶，其中第二半导体层被第三光刻胶覆盖的部分为本征层；
    对第二半导体层进行轻掺杂，在第一掺杂层和本征层之间形成第二掺杂层；以及
    剥离第三光刻胶。
  5. 如权利要求3所述的一种显示面板的制造方法，其中，所述将非晶硅层转化为多晶硅层的步骤包括：
    通过镭射工艺将非晶硅层转化为多晶硅层。
  6. 如权利要求2所述的一种显示面板的制造方法，其中，所述同步形成第一主动开关和第二主动开关的第一绝缘层，以及同步形成第一主动开关和第二主动开关的第一栅极、第二栅极的步骤后，包括以下步骤：
    在第二栅极上形成第四光刻胶，所述第四光刻胶比所述第二半导体层短，并且长于第二栅极；
    对第二半导体层进行重掺杂，未被第四光刻胶遮挡的第二半导体层形成第一掺杂层；其中被第二栅极挡住的部分为本征层；以及
    剥离第四光刻胶，并对所述第二半导体层进行轻掺杂，将所述本征层和所述第一掺杂层之间的部分形成第二掺杂层。
  7. 如权利要求3所述的一种显示面板的制造方法，其中，所述形成衬底的步骤后，还包括步骤：在衬底上形成缓冲层。
  8. 如权利要求1所述的一种显示面板的制造方法，其中，所述在显示面板的显示区形成含有第一半导体层的第一主动开关，并在显示面板的非显示区形成含有第二半导体层的第二主动开关的步骤中，包括以下步骤：
    在显示区形成第一半导体层；
    在非显示区形成第二半导体层；
    同步形成第一主动开关和第二主动开关的第一绝缘层，同步形成第一主动开关和第二主动开关的第一栅极、第二栅极；以及
    同步形成第一主动开关和第二主动开关的第二绝缘层，同步形成第一主动开关和第二主动开关的源极、漏极；
    其中，所述同步形成第一主动开关和第二主动开关的第二绝缘层，同步形成第一主动开关和第二主动开关的源极、漏极的步骤中，形成的所述第一主动开关的源极、漏极分别与所述第一主动开关的所述第一半导体层连通，形成的所述第二主动开关的源极、漏极分别与所述第二主动开关的所述第二半导体层连通。
  9. 如权利要求8所述的一种显示面板的制造方法，其中，所述在显示区形成第一半导体层的步骤中，包括以下步骤：
    形成衬底；
    在所述衬底上形成一层氧化物半导体层；
    在所述氧化物半导体层上形成第五光刻胶；以及
    将所述氧化物半导体层蚀刻成第一半导体层。
  10. 如权利要求9所述的一种显示面板的制造方法，其中，所述在非显示区形成第二半导体层的步骤中，包括以下步骤：
    在非显示区形成未掺杂的第二半导体层；
    在第二半导体层上形成第二光刻胶，所述第二光刻胶短于所述第二半导体层；
    对第二半导体层重掺杂，将未被第二光刻胶遮挡的部分形成第一掺杂层；
    剥离第二光刻胶，并在第二半导体层上形成比第二光刻胶短的第三光刻胶，其中第二半导体层被第三光刻胶覆盖的部分为本征层；
    对第二半导体层进行轻掺杂，在第一掺杂层和本征层之间形成第二掺杂层；
    剥离第三光刻胶；以及
    剥离第五光刻胶。
  11. 一种显示面板，划分为显示区和非显示区，包括基板，所述基板包括；
    第一主动开关，形成在所述显示区，所述第一主动开关包括第一半导体层，所述第一半导体层由氧化物材料构成；以及
    第二主动开关，形成在所述非显示区，所述第二主动开关包括第二半导体层，所述第二半导体层由多晶硅材料构成；
    其中，所述第一半导体层和所述第二半导体层设置在同一层。
  12. 如权利要求11所述的一种显示面板，其中，所述第一主动开关包括第一薄膜晶体管，所述第二主动开关包括第二薄膜晶体管，所述第一薄膜晶体管和第二薄膜晶体管为高电平导通的薄膜晶体管。
  13. 如权利要求11所述的一种显示面板，其中，所述第二半导体层为铟镓锌氧化物半导体层，所述第二半导体层为低温多晶硅半导体层。
  14. 如权利要求12所述的一种显示面板，其中，所述第一薄膜晶体管包括第一栅极，所述第二薄膜晶体管包括第二栅极，所述第一栅极与所述第二栅极设置在同一层。
  15. 如权利要求14所述的一种显示面板，其中，所述基板包括衬底，所述第一半导体层设置在所述第一栅极与所述衬底之间，所述第二半导体层设置在所述第二栅极与所述衬底之间。
  16. 如权利要求12所述的一种显示面板，其中，所述第一薄膜晶体管包括第一源极和第一漏极，所述第二薄膜晶体管包括第二源极和第二漏极，所述第一源极、第一漏极、第二源极和第二漏极设置在同一层。
  17. 如权利要求16所述的一种显示面板，其中，所述基板包括第一过孔、第二过孔、第三过孔和第四过孔；
    所述第一源极通过所述第一过孔与所述第一半导体层的一端连接，所述第一漏极通过所述第二过孔与所述第一半导体层的另一端连接；所述第二源极通过所述第三过孔与所述第二半导体层的一端连接，所述第二漏极通过所述第四过孔与所述第二半导体层的另一端连接；
    所述第一栅极的位置与所述第一半导体层的位置对应，且所述第一栅极的宽度小于所述第一半导体层的宽度，所述第二栅极的位置与所述第二半导体层的位置对应，且所述第二栅极的宽度小于所述第二半导体层的宽度。
  18. 如权利要求14所述的一种显示面板，其中，所述第二半导体层包括两个第一掺杂层、两个第二掺杂层和本征层；
    所述第一掺杂层为重掺杂层，两个所述第一掺杂层分别设置在所述本征层的两端；
    所述第二掺杂层为轻掺杂层，两个所述第二掺杂层分别设置在所述本征层与两个所述第一掺杂层之间。
  19. 一种显示装置，包括显示面板和用于驱动所述显示面板的驱动电路，所述显示面板划分为显示区和非显示区，包括基板，所述基板包括；
    第一主动开关，形成在所述显示区，所述第一主动开关包括第一半导体层，所述第一半导体层由氧化物材料构成；以及
    第二主动开关，形成在所述非显示区，所述第二主动开关包括第二半导体层，所述第二半导体层由多晶硅材料构成；
    其中，所述第一半导体层和所述第二半导体层设置在同一层。
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