WO2020143339A1 - 输出电路和芯片 - Google Patents

输出电路和芯片 Download PDF

Info

Publication number
WO2020143339A1
WO2020143339A1 PCT/CN2019/120207 CN2019120207W WO2020143339A1 WO 2020143339 A1 WO2020143339 A1 WO 2020143339A1 CN 2019120207 W CN2019120207 W CN 2019120207W WO 2020143339 A1 WO2020143339 A1 WO 2020143339A1
Authority
WO
WIPO (PCT)
Prior art keywords
pull
output
threshold nmos
stage circuit
thin
Prior art date
Application number
PCT/CN2019/120207
Other languages
English (en)
French (fr)
Inventor
田凯
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP19909127.3A priority Critical patent/EP3910633A4/en
Publication of WO2020143339A1 publication Critical patent/WO2020143339A1/zh
Priority to US17/172,319 priority patent/US11295804B2/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Definitions

  • the invention relates to a semiconductor memory, in particular to an output circuit and a chip.
  • LPDDR4 Low Power Double Data Rate SDRAM 4
  • LPDDR4X Low Power Double Data Rate SDRAM 4
  • LVSTL Low Voltage Swing Terminated Logic
  • the present invention provides an output circuit and a chip to at least solve the above technical problems in the prior art.
  • an output circuit including:
  • a first-stage circuit the first-stage circuit is used to read serial data inside the memory and divide the serial data into a plurality of voltage signals of a set rate level;
  • the second-stage circuit is connected to the first-stage circuit, and the second-stage circuit is used to receive a plurality of voltage signals output from the first-stage circuit, generate a plurality of voltage signals, and generate a voltage signal for each Assign transmission paths;
  • the third stage circuit is connected to the second stage circuit.
  • the third stage circuit is used to receive a plurality of voltage signals output by the second stage circuit and distribute each received voltage signal according to the ZQ calibration signal. Transmission path
  • the fourth-stage circuit is connected to the third-stage circuit.
  • the fourth-stage circuit includes a pull-up circuit and a pull-down circuit, and the pull-up circuit and the pull-down circuit both include a plurality of thin gate low-threshold NMOS transistors connected in parallel
  • the fourth-stage circuit is configured to receive a plurality of voltage signals output by the third-stage circuit, and generate an output voltage signal of the output circuit according to the received voltage signals.
  • the pull-up circuit includes a plurality of parallel pull-up branches, and each of the pull-up branches includes a first thin-gate low-threshold NMOS transistor with the same structure, and the first thin-gate The drain of the low-threshold NMOS tube is connected to the power supply voltage, the gate of the first thin-gate low-threshold NMOS tube receives the pull-up voltage signal output by the third-stage circuit; the first of the pull-up branch The source of a thin gate low-threshold NMOS tube is connected as a data output (DQ).
  • DQ data output
  • the pull-down circuit includes a plurality of pull-down branches connected in parallel, and each of the pull-down branches includes a second thin-gate low-threshold NMOS transistor with the same structure, and the second thin-gate low-threshold NMOS tube
  • the source of the tube is grounded, the drain of the second thin gate low threshold NMOS tube is connected to the source of the first thin gate low threshold NMOS tube, the gate of the second thin gate low threshold NMOS tube
  • the pull-down voltage signal output by the third stage circuit is a plurality of pull-down branches connected in parallel, and each of the pull-down branches includes a second thin-gate low-threshold NMOS transistor with the same structure, and the second thin-gate low-threshold NMOS tube
  • the source of the tube is grounded, the drain of the second thin gate low threshold NMOS tube is connected to the source of the first thin gate low threshold NMOS tube, the gate of the second thin gate low threshold NMOS tube.
  • the third-stage circuit is further used to output multiple pull-up ZQ calibration signals during ZQ calibration;
  • Each of the pull-up branches includes a plurality of third thin-gate low-threshold NMOS tubes, and each of the third thin-gate low-threshold NMOS tubes in each of the pull-up branches and the first thin-gate low-threshold NMOS tube Parallel connection; the gate of the third thin gate low-threshold NMOS tube receives the pull-up ZQ calibration signal, and the third thin gate low-threshold NMOS tube is used to adjust the pull-up branch according to the pull-up ZQ calibration signal
  • the equivalent resistance is RZQ (reference resistance).
  • the third-stage circuit is also used to output multiple pull-down ZQ calibration signals during ZQ calibration;
  • Each of the pull-down branches includes a plurality of fourth thin-gate low-threshold NMOS tubes, and the fourth thin-gate low-threshold NMOS tubes in each of the pull-down branches are connected in parallel with the second thin-gate low-threshold NMOS tubes.
  • the gate of the fourth thin gate low threshold NMOS tube receives the pull-down ZQ calibration signal, and the fourth thin gate low threshold NMOS tube is used to adjust the equivalent resistance of the pull-down branch to RZQ according to the pull-down ZQ calibration signal .
  • the ratios of the equivalent width-to-length ratios of the plurality of third thin gate low threshold NMOS transistors and the plurality of fourth thin gate low threshold NMOS transistors are sequentially increased.
  • the pull-up circuit further includes a pull-up switch module.
  • the pull-up switch module includes the same number of thick gate high-threshold NMOS transistors as the first thin gate low-threshold NMOS transistors.
  • the drain of the thick gate high threshold NMOS tube is connected to the power supply voltage
  • the source of the thick gate high threshold NMOS tube is connected to the drain of the first thin gate low threshold NMOS tube
  • the thick gate high threshold NMOS tube gate The pole is used to receive the high voltage threshold signal output by the third stage circuit.
  • each of the pull-up branches further includes at least one first low voltage calibration MOS tube, and the first low voltage calibration MOS tube is connected in parallel with the first thin gate low threshold NMOS tube.
  • the gate of the first low-voltage calibration MOS tube is connected to the third-stage circuit, and the first low-voltage calibration MOS tube is used for conducting when receiving a low-voltage signal.
  • each of the pull-down branches further includes at least one second low voltage calibration MOS tube, the second low voltage calibration MOS tube and the second thin gate low threshold NMOS tube are connected in parallel, the The gate of the second low-voltage calibration MOS tube is connected to the third-stage circuit, and the second low-voltage calibration MOS tube is used for conducting when receiving a low-voltage signal.
  • a first fixed-value resistor is connected in series between the source connection terminal of the first thin-gate low-threshold NMOS tube and the first low-voltage calibration MOS tube and the data output terminal, a plurality of the A second fixed-value resistor is connected in series between the source connection end of the third thin-gate low-threshold NMOS tube and the data output end;
  • a third fixed-value resistor is connected in series between the source connection end of the second thin gate low threshold NMOS tube and the second low voltage calibration MOS tube and the data output terminal, and a plurality of the fourth thin gate low threshold NMOS tubes
  • a fourth fixed-value resistor is connected in series between the source connection end of the tube and the data output end.
  • the first-stage circuit includes a first pull-up control module and a first pull-down control module with the same structure, and the first pull-up control module and the first pull-down control module are both It is used to delay the read data signal and divide it into data signals including multiple rate levels for output.
  • the second-stage circuit includes:
  • a second pull-down control module is used to receive the data signal output by the first pull-down control module, and select one according to the pull-down drive setting intensity and the ODT (On Die Terminator, on-chip termination resistor) on signal Path output data signal;
  • ODT On Die Terminator, on-chip termination resistor
  • a second pull-up control module is configured to receive the data signal output by the first pull-up control module, and select a path to output the data signal according to the pull-up drive setting intensity;
  • a pull-up switch control module is used to receive a switch enable signal and multiplex the pull-up drive setting intensity to control the switch of each path in the second pull-up control module.
  • the third-stage circuit includes a third pull-up control module and a third pull-down control module having the same structure
  • the input terminal of the third pull-up control module is connected to the second pull-up control module and the ZQ calibration value, and the output terminal of the third pull-up control module is connected to the gate of the first thin gate low threshold NMOS tube
  • the third pull-up control module is used to convert the received data signal and ZQ calibration value to the same rate of the pull-up voltage signal and the received data signal corresponding to the pull-up ZQ calibration signal;
  • the input terminal of the third pull-down control module is connected to the second pull-down control module and the ZQ calibration value, and the output terminal of the third pull-down control module is connected to the gate of the second thin gate low threshold NMOS tube;
  • the third pull-down control module is used to convert the received data signal and the ZQ calibration value into the pull-down voltage signal and the pull-down ZQ calibration signal corresponding to the received data signal at the same rate.
  • the present invention provides a chip including the output circuit described in the above embodiment.
  • the pull-up circuit eliminates the limitation of the threshold voltage on the minimum operating power supply voltage, and is compatible with two or more different high-speed data transmission standards, realizing the same chip in two outputs Working in environments with different levels improves efficiency and saves resources.
  • 1 is a schematic diagram of connection of an output circuit in an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a fourth-stage circuit in an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a pull-up branch in a pull-up circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a pull-down branch in a pull-down circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a first-stage circuit in an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a pull-down control module in a second-stage circuit according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of a pull-up control module in a second-stage circuit according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a pull-up switch module in a second-stage circuit according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a third-stage circuit in an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a pull-up control sub-module (pull-down control sub-module) in a third-level circuit according to an embodiment of the present invention.
  • the first aspect of this embodiment provides an output circuit.
  • the output circuit includes a first-stage circuit 100, a second-stage circuit 200, a third-stage circuit 300, and a fourth-stage circuit 400.
  • the first stage circuit 100 is used to read the serial data inside the memory and divide the serial data into a plurality of voltage signals of a set rate level.
  • the second-stage circuit 200 is connected to the first-stage circuit 100.
  • the second-stage circuit 200 is used to receive a plurality of voltage signals output from the first-stage circuit 100, generate a plurality of voltage signals, and allocate a transmission path for each generated voltage signal .
  • the third-stage circuit 300 is connected to the second-stage circuit 200.
  • the third-stage circuit 300 is used to receive a plurality of voltage signals output by the second-stage circuit 200, and allocate a transmission path to each received voltage signal according to the ZQ calibration signal.
  • the third stage circuit 300 is also used to adjust the voltage slew rate of the data signal to control the voltage slew rate of the fourth stage circuit 400.
  • the fourth-stage circuit 400 is connected to the third-stage circuit 300. As shown in FIG. 2, the fourth-stage circuit 400 includes a pull-up circuit 410 and a pull-down circuit 420, and the pull-up circuit 410 and the pull-down circuit 420 each include a plurality of thin gates connected in parallel. Low-threshold NMOS tube.
  • the fourth-stage circuit 400 is used to receive multiple voltage signals output from the third-stage circuit 300 and generate output voltage signals of the output circuit according to the received voltage signals.
  • the pull-up circuit 410 and the pull-down circuit 420 The thin-gate low-threshold NMOS tube is used to eliminate the limitation of the minimum operating power supply voltage by turning on the threshold voltage of the MOS tube.
  • the thin-gate low-threshold NMOS tube in the pull-up circuit 410 and the pull-down circuit 420 speeds up the response speed of the output circuit and obtains a larger current per unit area, eliminating the limitation of the minimum operating power supply voltage by the turn-on threshold voltage, and is compatible with two One or more different high-speed data transmission standards enable the same chip to work in two environments with different output levels.
  • the pull-up circuit 410 includes a plurality of pull-up branches 411 connected in parallel, and each pull-up branch 411 includes a first thin-gate low-threshold NMOS transistor 411a.
  • the drain of the thin-gate low-threshold NMOS transistor 411a is connected to the power supply voltage.
  • the gate of the first thin-gate low-threshold NMOS transistor 411a receives the pull-up voltage signal output by the third-stage circuit 300; the first thin of each pull-up branch 411
  • the sources of the gate low threshold NMOS transistor 411a are all connected as data output terminals.
  • the pull-down circuit 420 includes a plurality of pull-down branches 421 connected in parallel, each pull-down branch 421 includes a second thin gate low threshold NMOS transistor 421a, and the second thin gate is low
  • the source of the threshold NMOS tube 421a is grounded
  • the drain of the second thin gate low threshold NMOS tube 421a is connected to the source of the first thin gate low threshold NMOS tube 411a
  • the gate of the second thin gate low threshold NMOS tube 421a receives the first The pull-down voltage signal output by the three-stage circuit 300.
  • the thin-gate low-threshold NMOS transistors are used in the pull-up circuit 410 and the pull-down circuit 420, which eliminates the limitation of the minimum operating power supply voltage of the output threshold of the output transistor in the CMOS structure, so that the fourth stage circuit 400 meets various output voltage standards.
  • the third stage circuit 300 is also used to output multiple pull-up ZQ calibration signals during ZQ calibration.
  • each pull-up branch 411 includes a plurality of third thin gate low threshold NMOS transistors 411c, and the third thin gate low threshold NMOS transistor 411c in each pull up branch 411 is the same as the first thin gate low threshold NMOS tubes 411a are connected in parallel; the gate of the third thin gate low threshold NMOS tube 411c receives the pull-up ZQ calibration signal, and the third thin gate low threshold NMOS tube 411c is used to adjust the pull-up branch 411 according to the pull-up ZQ calibration signal
  • the effective resistance is RZQ.
  • the third stage circuit 300 is also used to output multiple pull-down ZQ calibration signals during ZQ calibration.
  • each pull-down branch 421 includes a plurality of fourth thin gate low-threshold NMOS transistors 421c, and the fourth thin gate low-threshold NMOS transistor 421c in each pull-down branch 421 is connected to the second thin-gate low-threshold NMOS transistor 421c. 421a is connected in parallel.
  • the gate of the fourth thin gate low threshold NMOS transistor 421c receives the pull-down ZQ calibration signal.
  • the fourth thin gate low threshold NMOS transistor 421c is used to adjust the equivalent resistance of the pull-down branch to RZQ according to the pull-down ZQ calibration signal.
  • the ratios of the equivalent width-to-length ratios of the plurality of third thin gate low threshold NMOS transistors 411c and the plurality of fourth thin gate low threshold NMOS transistors 421c are sequentially increased.
  • the third stage circuit 300 is also used to output six pull-up ZQ calibration signals Zq ⁇ 0>, Zq ⁇ 1>, Zq during ZQ calibration ⁇ 2>, Zq ⁇ 3>, Zq ⁇ 4> and Zq ⁇ 5>.
  • Each pull-up branch 411 includes six third thin gate low-threshold NMOS transistors 411c.
  • the gate of a third thin gate low threshold NMOS transistor 411c is connected to one of the pull-up ZQ calibration signals Zq ⁇ 5:0>.
  • the third stage circuit 300 is also used to output six pull-down ZQ calibration signals Zq ⁇ 0>, Zq ⁇ 1>, Zq ⁇ 2>, Zq ⁇ 3>, Zq ⁇ 4> and Zq ⁇ 5>.
  • Each pull-down branch 421 includes six fourth thin gate low threshold NMOS transistors 421c.
  • the gate of a fourth thin-gate low-threshold NMOS transistor 411c is connected to one of the pull-down ZQ calibration signals Zq ⁇ 5:0>.
  • the ratio of the equivalent width-to-length ratio of the six third thin gate low-threshold NMOS transistors 411c and the six fourth thin gate low-threshold NMOS transistors 421c are 1:2:4:8:16 :32.
  • the pull-down drive strength ie, equivalent pull-down output resistance
  • RZQ/1 to RZQ/6 the pull-down output stage
  • each pull-down The equivalent resistance of the branch is adjusted to RZQ, and a preferred value of RZQ includes 240 ⁇ .
  • each pull-up branch 411 and pull-down branch 421 are connected in parallel on each pull-up branch 411 and pull-down branch 421 to perform ZQ calibration, which effectively adjusts the equivalent resistance of the pull-up branch 410 and the pull-down branch 420 to the reference resistance.
  • the pull-up branch 410 further includes a pull-up switch module 430.
  • the pull-up switch module 430 includes a thick gate high-threshold NMOS tube 431, a drain of the thick gate high-threshold NMOS tube 431 is connected to the power supply voltage, and a source of the thick gate high-threshold NMOS tube 431 is connected to the first thin gate low-threshold NMOS tube 411a.
  • the drain is connected, and the gate of the thick gate high threshold NMOS transistor 431 is used to receive the high voltage threshold signal output by the third stage circuit 300.
  • the pull-up branch 410 uses the first thin gate low threshold NMOS tube 411a
  • the thick gate high threshold NMOS tube 431 is connected between the power supply voltage and the first thin gate low threshold NMOS tube 411a, which can effectively reduce static leakage Current.
  • the pull-up switch module 430 is calibrated together. And each branch in parallel will not affect the accuracy and linearity of the on-resistance.
  • each pull-up branch 410 further includes at least one first low voltage calibration MOS tube 411b, a first low voltage calibration MOS tube 411b and a first thin gate low threshold NMOS tube 411a
  • the gate of the first low-voltage calibration MOS tube 411b is connected to the third stage circuit, and the first low-voltage calibration MOS tube 411b is used for conducting when receiving a low-voltage signal.
  • each pull-down branch 420 further includes at least one second low voltage calibration MOS tube 421b, and the second low voltage calibration MOS tube 421b is connected in parallel with the second thin gate low threshold NMOS tube 421a
  • the gate of the second low voltage calibration MOS tube 421b is connected to the third stage circuit 300, and the second low voltage calibration MOS tube 421b is used to turn on when receiving a low voltage signal.
  • the low voltage signal and the pull-up/pull-down voltage signal received by the first low-voltage calibration MOS tube 411b and the second low-voltage calibration MOS tube 421b are homologous signals.
  • the first low-voltage calibration MOS tube 411b and the second low-voltage calibration MOS tube 421b are both thin-gate low-threshold NMOS tubes, and thin-gate low-threshold NMOS tubes are used in parallel in the pull-up/pull-down circuit for correction. Effectively prevent the equivalent resistance in the pull-up/pull-down circuit from changing greatly, and completely rely on ZQ calibration to narrow the calibration range.
  • a first fixed-value resistor 411d is connected in series between the source connection end of the first thin-gate low-threshold NMOS tube 411a and the first low-voltage calibration MOS tube 411b, and the data output terminal.
  • a plurality of third thin-gate low-threshold NMOS transistors 411c have a second fixed-value resistor 411e connected in series between the source terminal and the data output terminal DQ;
  • a third fixed value resistor 421d is connected in series between the source connection end of the second thin gate low threshold NMOS tube 421a and the second low voltage calibration MOS tube 421b and the data output terminal, and a plurality of fourth thin gates
  • a fourth fixed value resistor 421e is connected in series between the source connection end of the low-threshold NMOS transistor 421c and the data output end.
  • a resistor is connected in series with the MOS tube in the pull-up circuit 410 or the pull-down circuit 420, so that when adjusting the setting of the ZQ calibration signal, the accuracy and linearity of the MOS tube in the pull-up circuit 410 or the pull-down circuit 420 can be adjusted. Keep it better.
  • the first-stage circuit 100 includes a first pull-up control module 110 and a first pull-down control module 120 having the same structure, and the first pull-up control module 110 and the first pull-down control module
  • the control modules 120 are used to delay the read data signals and divide them into data signals including multiple rate levels for output.
  • the first pull-up control module 110 and the first pull-down control module 120 each include three delay units 130. Both the first pull-up control module 110 and the first pull-down control module 120 are used to pass the read serial data through three delay units 130, and are divided into data signals including three speed levels of fast, medium, and slow, that is, output Fast signal Dataout ⁇ 0>, medium signal Dataout ⁇ 1>, slow signal Dataout ⁇ 2>.
  • drive tubes with different drive strengths are used as the delay unit 130 for delay to generate data signals with different rate levels.
  • the driver tubes in the circuit are prevented from being opened at the same time, and large noise interference is generated on the power and ground terminals of the output stage.
  • the signals divided into different rate levels can partially control the output stage signal. Voltage conversion rate.
  • the second stage circuit includes: a second pull-up control module 220, a second pull-down control module 210, and a pull-up switch control module 230.
  • the second pull-up control module 220 is used to receive the data signal output by the first pull-up control module 110 and select a path to output the data signal according to the pull-up drive setting intensity;
  • the second pull-down control module 210 is used to receive the data signal output by the first pull-down control module 120, and select a path to output the data signal according to the pull-down driving setting intensity and the ODT on signal;
  • the pull-up switch control module 230 is used to receive a switch enable signal and multiplex the pull-up drive setting strength to control the switch of each path in the second pull-up control module 220.
  • the second pull-down control module 210 includes four pull-down path units 210a, and the pull-down path unit 210a includes a first NAND gate 211, a second NAND gate 212, and a third AND NAND gate 213, an input terminal of the first NAND gate 211 is a driving strength setting terminal, an input terminal of the second NAND gate 212 is an ODT (output high level) opening signal terminal, and another input terminal of the second NAND gate 212 An input terminal is an ODT setting terminal; the output terminals of the first NAND gate and the second NAND gate 212 are connected to an input terminal of the third NAND gate 213, and the output terminal of the third NAND gate 213 outputs a data signal; two The other input terminal of the first NAND gate 211 in the pull-down path unit 210a receives the fast data signal Datain ⁇ 0> output by the first pull-down control module 120, and the corresponding output terminal of the third NAND gate 213 outputs the fast data signal Dataout
  • the ODT mode When the memory is in the read data mode, the ODT mode is closed, the ODT open signal terminal (Odten) is 0, and the output data signal (Dataout ⁇ 3:0>) is controlled by the drive strength setting terminal (Drive ⁇ 2:0>).
  • the ODT mode When the memory is in the write data mode, the ODT mode is turned on and the ODT turn-on signal terminal (Odten) is 1, then the output data signal (Dataout ⁇ 3:0>) is controlled by the ODT setting terminal (Odt ⁇ 2:0>).
  • the second pull-up control module 220 includes four pull-up path units 220a, and the pull-up path unit 220a includes a fourth NAND gate 221 and a first inverter 222, An input terminal of the fourth NAND gate 221 is a driving strength setting terminal. The output terminal of the fourth NAND gate 221 is connected to the input terminal of the first inverter 222. The output terminal of the first inverter 222 outputs a data signal.
  • the other input terminal of the fourth NAND gate 221 in the pull-up path unit 220a receives the fast data signal Datain ⁇ 0> output by the first pull-up control module 110, and corresponds to the output terminal of the first inverter 222 to output the fast data signal Dataout ⁇ 0> and Dataout ⁇ 1>; the other input terminal of the fourth NAND gate 221 in the remaining two pull-up path units 220a receives the medium data signal Datain ⁇ 1> and the slow data signal output by the first pull-up control module 110 Datain ⁇ 2>, corresponding to the middle data signal Dataout ⁇ 2> and the slow data signal Dataout ⁇ 3> output from the output end of the first inverter 222.
  • the output data signal (Dataout ⁇ 3:0>) of the second pull-up control module 220 is controlled by the drive strength setting end (Drive ⁇ 2:0>); the ODT in the memory is pulled down to ground, The pull-up control module 220 is not controlled by ODT.
  • the pull-up switch control module 230 includes a plurality of pull-up switch units 230a.
  • the pull-up switch unit 230a includes a fifth NAND gate 231 and a second inverter 232.
  • One input terminal of the five NAND gate 231 is the switch enable signal terminal (Swen), the other input terminal of the fifth NAND gate 231 is the pull-up drive strength setting terminal (Drive ⁇ 2:0>), and the fifth NAND gate
  • the output terminal of the gate 231 is connected to the input terminal of the second inverter 232, the output terminal of the second inverter 232 outputs a data signal (Dataout ⁇ 3:0>), and the pull-up drive strength is set to the multiplexed pull-up control module 220
  • the medium driving strength is set so that one pull-up switch unit 230a correspondingly controls one pull-up path unit 220a.
  • the memory multiplexes the drive strength setting end (Drive ⁇ 2:0>) of the pull-up control module 220 to control the pull-up switch unit 230a, that is, the pull-up switch unit 230a controls the pull-up path unit 220a.
  • the third stage circuit 300 includes a third pull-up control module 310 and a third pull-down control module 320 having the same structure.
  • the third pull-up control module 310 and the third pull-down control module 320 have the same structure.
  • the input terminal of the third pull-up control module 310 is connected to the second pull-up control module 210, and the output terminal of the third pull-up control module 310 is connected to the gate of the first thin gate low threshold NMOS tube 411a
  • the input terminal of the third pull-down control module 320 is connected to the second pull-down control module 220, and the output terminal of the third pull-down control module 320 is connected to the gate of the second thin-gate low-threshold NMOS transistor 421a;
  • the pull-down control module 320 is used to convert the received data signal Datainx to a pull-down voltage signal Dataout0main at the same rate and the pull-down ZQ calibration signal DataoutxZq ⁇ n:0> corresponding to the received data signal.
  • the third pull-up control module 310 is used to receive two fast data signals and medium and slow data signals Datain ⁇ 3:0 received from the second pull-up control module 220. >Convert to the pull-up voltage signal Dataout0main and the pull-up ZQ calibration signal Dataout ⁇ 3:0>Zq ⁇ 5:0> corresponding to the received data signal (Datain and Dataout only represent the input and output status of the data signal).
  • the third pull-down control module 320 is used to convert the two fast data signals received from the second pull-down control module 210 and the medium and slow data signals Datain ⁇ 3:0> It is the pull-down voltage signal Dataout0main of the same rate and the pull-down ZQ calibration signal Dataout ⁇ 3:0>Zq ⁇ 5:0> of the corresponding data signal.
  • Dataout ⁇ 3:0>Zq ⁇ 5:0> is the ZQ calibration signal Zq ⁇ 5:0> input to the fourth stage circuit 400.
  • the third pull-up control module 310 includes four pull-up control sub-modules 330.
  • the pull-up control sub-module 330 includes seven sixth NAND gates 331 and seven third inverters 332, an input of the sixth NAND gate 331 receives the output of the second pull-up control module 220
  • One of the data information Datain the other input of the first sixth NAND gate 311 is connected to the reference signal EN, and the other input of the remaining six sixth NAND gates 331 is connected to the ZQ calibration value Zqcal ⁇ 5:0>
  • the output terminal of a sixth NAND gate 331 is connected to the input terminal of a third inverter 332; the seven third inverters 332 sequentially output a pull-up voltage signal Dataoutmain and a pull-up ZQ calibration signal DataoutZq ⁇ 5:0 >.
  • the output terminals of the four pull-up control sub-modules 330 that receive fast, medium, and slow data signals in the third pull-up control module 310 and the gates of the six first thin-gate low-threshold NMOS transistors 411a in the pull-up circuit 410 follow 1 :2:2:1 or 2:1:2:1 ratio to ensure that fast data signals are connected to the gates of three first thin gate low-threshold NMOS transistors 411a, and middle data signals are connected to two first The gate of the thin gate low threshold NMOS transistor 411a, the slow data signal is connected to the gate of a first thin gate low threshold NMOS transistor 411a.
  • the third pull-down control module 320 includes four pull-down control sub-modules 340.
  • the pull-down control sub-module 340 and the pull-up control sub-module 330 have the same structure.
  • the pull-down control sub-module 340 includes seven sixth NAND gates 331 and seven third inverters 332, an input terminal of the sixth NAND gate 331 receives an output from the second pull-down control module 210 Data information Datain, the other input terminal of the first sixth NAND gate 311 is connected to the reference signal EN, and the other input terminal of the remaining six sixth NAND gates 331 is connected to the ZQ calibration value Zqcal ⁇ 5:0>, a first The output terminal of the six NAND gate 331 is connected to the input terminal of a third inverter 332; the seven third inverters 332 sequentially output the pull-down voltage signal Dataoutmain and the pull-down ZQ calibration signal DataoutZq ⁇ 5:0>.
  • the output terminals of the four pull-down control sub-modules 340 in the third pull-down control module 320 that receive fast, medium, and slow data signals and the gates of the six second thin-gate low-threshold NMOS transistors 421a in the pull-down circuit 420 are 1:2: Connect at a ratio of 2:1 or 2:1:2:1 to ensure that fast data signals are connected to the gates of three second thin gate low threshold NMOS transistors 421a, and middle data signals are connected to two second thin gates low
  • the gate of the threshold NMOS transistor 421a, the slow data signal is connected to the gate of a second thin gate low threshold NMOS transistor 421a.
  • this embodiment allocates and selects the transmission path of the data signal, and at the same time, the third inverter 332 with adjustable voltage conversion rate adjusts the voltage conversion rate of the output signal of the third stage circuit 300 to control the fourth stage voltage 400 conversion rate.
  • the present invention provides a chip including the output circuit of the above embodiment.
  • the chip of this embodiment optimizes the control of various parameters under the condition of meeting JEDEC, and meets the requirements of two different memory data output environments.
  • first and second are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • the features defined with “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more, unless otherwise specifically limited.
  • the terms “installation”, “connected”, “connected”, “fixed” and other terms should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection , Or integrated; it can be mechanical connection, electrical connection, or communication; it can be directly connected, or it can be indirectly connected through an intermediary, it can be the connection between two components or the interaction between two components .
  • installation can be a fixed connection or a detachable connection , Or integrated; it can be mechanical connection, electrical connection, or communication; it can be directly connected, or it can be indirectly connected through an intermediary, it can be the connection between two components or the interaction between two components .
  • the first feature “above” or “below” the second feature may include the direct contact of the first and second features, or may include the first and second features Not direct contact but contact through other features between them.
  • the first feature is “above”, “above” and “above” the second feature includes that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is higher in level than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is less horizontal than the second feature.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)

Abstract

一种输出电路和芯片，输出电路包括第一级电路（100）、第二级电路（200）、第三级电路（300）和第四级电路（400）。第一级电路（100）用于将读取存储器内部的串行数据，并将串行数据分成设定速率等级的电压信号；第二级电路（200）用于接收第一级电路（100）输出的电压信号，并为电压信号分配传输路径；第三级电路（300）用于接收第二级电路（200）输出的电压信号，并根据ZQ校准信号为每一个接收到的电压信号分配传输路径；第四级电路（400）包括上拉电路（410）和下拉电路（420），上拉电路（410）和下拉电路（420）均包括薄栅低阈值NMOS管，第四级电路（400）用于接收第三级电路（300）输出的电压信号，生成输出电路的输出电压信号。通过消除开启阈值电压对最低工作电源电压的限制，可以兼容多种不同的高速数据输出端口，提高效率。

Description

输出电路和芯片
本申请要求于2019年01月07日提交中国专利局、申请号为201910012322.0、发明名称为“输出电路和芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体存储器，具体涉及一种输出电路和芯片。
背景技术
在LPDDR4(Low Power Double Data Rate SDRAM 4)和LPDDR4X的应用中，都是采用了LVSTL(Low Voltage Swing Terminated Logic)的高速接口标准，并且都可由内存控制器设置不同的输出下拉驱动能力和输出高电平。但是，由于两者数据输出端口的电压不同，无法在同一芯片中应用LPDDR4和LPDDR4X。因此，给芯片应用和设计造成困扰。
发明内容
本发明提供一种输出电路和芯片，以至少解决现有技术中的以上技术问题。
为达到上述目的，本发明提供了一种输出电路，包括：
第一级电路，所述第一级电路用于读取存储器内部的串行数据，并将所述串行数据分成多个设定速率等级的电压信号；
第二级电路，与所述第一级电路连接，所述第二级电路用于接收所述第一级电路输出的多个电压信号，生成多个电压信号，并为每一个生成的电压信号分配传输路径；
第三级电路，与所述第二级电路连接，所述第三级电路用于接收所述第二级电路输出的多个电压信号，并根据ZQ校准信号为每一个接收到的电压信号分配传输路径；
第四级电路，与所述第三级电路连接，所述第四级电路包括上拉电路和下拉电路，所述上拉电路和所述下拉电路均包括多个并联的薄栅低阈值 NMOS管，所述第四级电路用于接收所述第三级电路输出的多个电压信号，并根据接收到的电压信号生成所述输出电路的输出电压信号。
在一种可实施方式中，所述上拉电路包括多个并联的上拉支路，各所述上拉支路均包括结构相同的第一薄栅低阈值NMOS管，所述第一薄栅低阈值NMOS管的漏极与电源电压连接，所述第一薄栅低阈值NMOS管的栅极接收所述第三级电路输出的上拉电压信号；各所述上拉支路的所述第一薄栅低阈值NMOS管的源极均连接作为数据输出端(DQ)。
在一种可实施方式中，所述下拉电路包括多个并联的下拉支路，各所述下拉支路均包括结构相同的第二薄栅低阈值NMOS管，所述第二薄栅低阈值NMOS管的源极接地，所述第二薄栅低阈值NMOS管的漏极与所述第一薄栅低阈值NMOS管的源极连接，所述第二薄栅低阈值NMOS管的栅极接收所述第三级电路输出的下拉电压信号。
在一种可实施方式中，所述第三级电路还用于在ZQ校准时输出多个上拉ZQ校准信号；
各所述上拉支路均包括多个第三薄栅低阈值NMOS管，各所述上拉支路中所述第三薄栅低阈值NMOS管均与所述第一薄栅低阈值NMOS管并联；所述第三薄栅低阈值NMOS管的栅极接收所述上拉ZQ校准信号，所述第三薄栅低阈值NMOS管用于根据上拉ZQ校准信号，调整所述上拉支路的等效电阻为RZQ(参考电阻)。
在一种可实施方式中，所述第三级电路还用于在ZQ校准时输出多个下拉ZQ校准信号；
各所述下拉支路均包括多个第四薄栅低阈值NMOS管，各所述下拉支路中所述第四薄栅低阈值NMOS管均与所述第二薄栅低阈值NMOS管并联，所述第四薄栅低阈值NMOS管的栅极接收所述下拉ZQ校准信号，所述第四薄栅低阈值NMOS管用于根据下拉ZQ校准信号，调整所述下拉支路的等效电阻为RZQ。
在一种可实施方式中，多个所述第三薄栅低阈值NMOS管和多个所述第四薄栅低阈值NMOS管的等效宽长比的比例均依次递增。
在一种可实施方式中，所述上拉电路还包括上拉开关模块，所述上拉 开关模块包括与所述第一薄栅低阈值NMOS管数量相同的厚栅高阈值NMOS管，所述厚栅高阈值NMOS管的漏极与电源电压连接，所述厚栅高阈值NMOS管的源极与所述第一薄栅低阈值NMOS管的漏极连接，所述厚栅高阈值NMOS管栅极用于接收所述第三级电路输出的高电压阈值信号。
在一种可实施方式中，各所述上拉支路还包括至少一个第一低电压校准MOS管，所述第一低电压校准MOS管与所述第一薄栅低阈值NMOS管并联，所述第一低电压校准MOS管的栅极与所述第三级电路连接，所述第一低电压校准MOS管用于在接收低电压信号时导通。
在一种可实施方式中，各所述下拉支路还包括至少一个第二低电压校准MOS管，所述第二低电压校准MOS管与所述第二薄栅低阈值NMOS管并联，所述第二低电压校准MOS管的栅极与所述第三级电路连接，所述第二低电压校准MOS管用于在接收低电压信号时导通。
在一种可实施方式中，所述第一薄栅低阈值NMOS管和第一低电压校准MOS管源极连接端与所述数据输出端之间串联有第一定值电阻，多个所述第三薄栅低阈值NMOS管的源极连接端与所述数据输出端之间串联有第二定值电阻；
所述第二薄栅低阈值NMOS管和第二低电压校准MOS管的源极连接端与所述数据输出端之间串联有第三定值电阻，多个所述第四薄栅低阈值NMOS管的源极连接端与所述数据输出端之间串联有第四定值电阻。
在一种可实施方式中，所述第一级电路包括结构相同的第一上拉控制模块和第一下拉控制模块，所述第一上拉控制模块和所述第一下拉控制模块均用于将读取的数据信号进行延时，分成包括多个速率等级的数据信号输出。
在一种可实施方式中，所述第二级电路包括：
第二下拉控制模块，所述第二下拉控制模块用于接收所述第一下拉控制模块输出的数据信号，并根据下拉驱动设置强度和ODT(On Die Terminator，片上终端电阻)开启信号选择一路径输出数据信号；
第二上拉控制模块，所述第二上拉控制模块用于接收所述第一上拉控 制模块输出的数据信号，并根据上拉驱动设置强度选择一路径输出数据信号；
上拉开关控制模块，所述上拉开关控制模块用于接收开关使能信号和复用上拉驱动设置强度，以控制所述第二上拉控制模块中每一个路径的开关。
在一种可实施方式中，所述第三级电路包括具有相同结构的第三上拉控制模块和第三下拉控制模块；
所述第三上拉控制模块的输入端与第二上拉控制模块和ZQ校准值连接，所述第三上拉控制模块的输出端与所述第一薄栅低阈值NMOS管的栅极连接；所述第三上拉控制模块用于将接收的数据信号和ZQ校准值转化为同一速率的所述上拉电压信号和接收数据信号对应的所述上拉ZQ校准信号；
所述第三下拉控制模块的输入端与第二下拉控制模块和ZQ校准值连接，所述第三下拉控制模块的输出端与所述第二薄栅低阈值NMOS管的栅极连接；所述第三下拉控制模块用于将接收的数据信号和ZQ校准值转化为同一速率的所述下拉电压信号和接收数据信号对应的所述下拉ZQ校准信号。
为达到上述目的，本发明提供了一种芯片，包括上述实施方式所述的输出电路。
本发明采用上述技术方案，具有如下优点：通过上拉电路消除开启阈值电压对最低工作电源电压的限制，可以兼容两种或以上的不同的高速数据传输标准，实现了同一个芯片在两种输出电平不同的环境下工作，提高效率，节省资源。
上述概述仅仅是为了说明书的目的，并不意图以任何方式进行限制。除上述描述的示意性的方面、实施方式和特征之外，通过参考附图和以下的详细描述，本发明进一步的方面、实施方式和特征将会是容易明白的。
附图说明
在附图中，除非另外规定，否则贯穿多个附图相同的附图标记表示相 同或相似的部件或元素。这些附图不一定是按照比例绘制的。应该理解，这些附图仅描绘了根据本发明公开的一些实施方式，而不应将其视为是对本发明范围的限制。
图1为本发明实施例中输出电路的连接示意图；
图2为本发明实施例中第四级电路的结构示意图；
图3为本发明实施例中上拉电路中一上拉支路的结构示意图；
图4为本发明实施例中下拉电路中一下拉支路的结构示意图；
图5为本发明实施例中第一级电路的结构示意图；
图6为本发明实施例中第二级电路中下拉控制模块的结构示意图；
图7为本发明实施例中第二级电路中上拉控制模块的结构示意图；
图8为本发明实施例中第二级电路中上拉开关模块的结构示意图；
图9为本发明实施例中第三级电路的结构示意图；以及
图10为本发明实施例中第三级电路中上拉控制子模块(下拉控制子模块)的结构示意图。
附图标记：
100 第一级电路；
110 第一上拉控制模块；
120 第一下拉控制模块；
130 延时单元；
200 第二级电路；
210 第二下拉控制模块；
210a 下拉路径单元；
211 第一与非门；
212 第二与非门；
213 第三与非门
220 第二上拉控制模块；
220a 上拉路径单元；
221 第四与非门；
222 第一反相器；
230 上拉开关控制模块；
230a 上拉开关单元；
231 第五与非门；
232 第二反相器；
300 第三级电路；
310 第三上拉控制模块；
320 第三下拉控制模块；
330 上拉控制子模块；
340 下拉控制子模块；
331 第六与非门；
332 第三反相器；
400 第四级电路；
410 上拉电路；
411 上拉支路；
411a 第一薄栅低阈值NMOS管；
411b 第一低电压校准MOS管；
411c 第三薄栅低阈值NMOS管；
411d 第一定值电阻；
411e 第二定值电阻；
420 下拉电路；
421 下拉支路；
421a 第二薄栅低阈值NMOS管；
421b 第二低电压校准MOS管；
421c 第四薄栅低阈值NMOS管；
421d 第三定值电阻；
421e 第四定值电阻；
430 上拉开关电路；
431 厚栅高阈值NMOS管。
具体实施方式
在下文中，仅简单地描述了某些示例性实施例。正如本领域技术人员可认识到的那样，在不脱离本发明的精神或范围的情况下，可通过各种不同方式修改所描述的实施例。因此，附图和描述被认为本质上是示例性的而非限制性的。
本实施例第一方面提供了一种输出电路。
参见图1所示，输出电路包括第一级电路100、第二级电路200、第三级电路300以及第四级电路400。
第一级电路100用于读取存储器内部的串行数据，并将串行数据分成多个设定速率等级的电压信号。
第二级电路200与第一级电路100连接，第二级电路200用于接收第一级电路100输出的多个电压信号，生成多个电压信号，并为每一个生成的电压信号分配传输路径。
第三级电路300与第二级电路200连接，第三级电路300用于接收第二级电路200输出的多个电压信号，并根据ZQ校准信号为每一个接收到的电压信号分配传输路径。第三级电路300还用于调整数据信号的电压转换速率控制第四级电路400的电压转换速率。
第四级电路400与第三级电路300连接，参见图2所示，第四级电路400包括上拉电路410和下拉电路420，上拉电路410和下拉电路420均包括多个并联的薄栅低阈值NMOS管，第四级电路400用于接收第三级电路300输出的多个电压信号，并根据接收到的电压信号生成输出电路的输出电压信号，上拉电路410和下拉电路420中的薄栅低阈值NMOS管用于消除开启MOS管阈值电压对最低工作电源电压的限制。
本实施例通过上拉电路410和下拉电路420中的薄栅低阈值NMOS管加快输出电路的响应速度和获得更大的单位面积电流，消除开启阈值电压对最低工作电源电压的限制，可以兼容两种或以上的不同的高速数据传输标准，实现了同一个芯片在两种输出电平不同的环境下工作。
在一种实施例中，参见图2和3所示，上拉电路410包括多个并联的 上拉支路411，各上拉支路411均包括第一薄栅低阈值NMOS管411a，第一薄栅低阈值NMOS管411a的漏极与电源电压连接，第一薄栅低阈值NMOS管411a的栅极接收第三级电路300输出的上拉电压信号；各上拉支路411的第一薄栅低阈值NMOS管411a的源极均连接作为数据输出端。
在一种实施例中，参见图2和4所示，下拉电路420包括多个并联的下拉支路421，各下拉支路421均包括第二薄栅低阈值NMOS管421a，第二薄栅低阈值NMOS管421a的源极接地，第二薄栅低阈值NMOS管421a的漏极与第一薄栅低阈值NMOS管411a的源极连接，第二薄栅低阈值NMOS管421a的栅极接收第三级电路300输出的下拉电压信号。
本实施例上拉电路410和下拉电路420中使用薄栅低阈值NMOS管，消除了CMOS结构中输出管开启阈值电压最低工作电源电压的限制，使第四级电路400满足多种输出电压标准。
在一种实施例中，第三级电路300还用于在ZQ校准时输出多个上拉ZQ校准信号。
参见图3所示，各上拉支路411均包括多个第三薄栅低阈值NMOS管411c，各上拉支路411中第三薄栅低阈值NMOS管411c均与第一薄栅低阈值NMOS管411a并联；第三薄栅低阈值NMOS管411c的栅极接收上拉ZQ校准信号，第三薄栅低阈值NMOS管411c用于根据上拉ZQ校准信号，调整上拉支路411的等效电阻为RZQ。
在一种实施例中，第三级电路300还用于在ZQ校准时输出多个下拉ZQ校准信号。
参见图4所示，各下拉支路421均包括多个第四薄栅低阈值NMOS管421c，各下拉支路421中第四薄栅低阈值NMOS管421c均与第二薄栅低阈值NMOS管421a并联，第四薄栅低阈值NMOS管421c的栅极接收下拉ZQ校准信号，第四薄栅低阈值NMOS管421c用于根据下拉ZQ校准信号，调整下拉支路的等效电阻为RZQ。
进一步地，多个第三薄栅低阈值NMOS管411c和多个第四薄栅低阈值NMOS管421c的等效宽长比的比例均依次递增。
基于上述实施例，参见图3所示，在一种具体实施例中，第三级电路 300还用于在ZQ校准时输出六个上拉ZQ校准信号Zq<0>、Zq<1>、Zq<2>、Zq<3>、Zq<4>和Zq<5>。
各上拉支路411均包括六个第三薄栅低阈值NMOS管411c。一个第三薄栅低阈值NMOS管411c的栅极接入上拉ZQ校准信号Zq<5:0>中一个校准信号。
参见图4所示，第三级电路300还用于在ZQ校准时输出六个下拉ZQ校准信号Zq<0>、Zq<1>、Zq<2>、Zq<3>、Zq<4>和Zq<5>。
各下拉支路421均包括六个第四薄栅低阈值NMOS管421c。一个第四薄栅低阈值NMOS管411c的栅极接入下拉ZQ校准信号Zq<5:0>中一个校准信号。
在一种具体实施例中，六个第三薄栅低阈值NMOS管411c和六个第四薄栅低阈值NMOS管421c的等效宽长比的比例均为1:2:4:8:16:32。
根据JEDEC规范，输出电路的下拉驱动强度(即等效下拉输出电阻)有六种选择，从RZQ/1到RZQ/6，由于采用下拉输出级为六个同样结构的支路并联，每个下拉支路的等效电阻均调整为RZQ，且RZQ的一种较佳选值包括240Ω，根据JEDEC的规范，上拉电路对应六种ODT的阻值，为了控制VOH＝VDDQ/3，上拉输出级也为六个同样结构的支路并联，每个上拉支路的等效电阻也均调整为RZQ。
本实施例在每个上拉支路411和下拉支路421上均并联六个薄栅低阈值NMOS管进行ZQ校准，有效使上拉支路410和下拉支路420的等效电阻调整到参考电阻。
在一种实施例中，参见图1所示，上拉支路410还包括上拉开关模块430。
上拉开关模块430包括厚栅高阈值NMOS管431，厚栅高阈值NMOS管431的漏极与电源电压连接，厚栅高阈值NMOS管431的源极与第一薄栅低阈值NMOS管411a的漏极连接，厚栅高阈值NMOS管431栅极用于接收第三级电路300输出的高电压阈值信号。当上拉支路410采用第一薄栅低阈值NMOS管411a时，采用厚栅高阈值NMOS管431连接在电源电压与第一薄栅低阈值NMOS管411a之间，可以有效减小静态的漏电流。 又为了减小厚栅高阈值NMOS管431的较大的等效电阻对上拉开关电路430的影响。在ZQ校准时，包括上拉开关模块430一起校准。并且每条支路并联时不会影响导通电阻的准确性及线性度。
在一种实施例中，参见图3所示，各上拉支路410还包括至少一个第一低电压校准MOS管411b，第一低电压校准MOS管411b与第一薄栅低阈值NMOS管411a并联，第一低电压校准MOS管411b的栅极与第三级电路连接，第一低电压校准MOS管411b用于在接收低电压信号时导通。
在一种实施例中，参见图4所示，各下拉支路420还包括至少一个第二低电压校准MOS管421b，第二低电压校准MOS管421b与第二薄栅低阈值NMOS管421a并联，第二低电压校准MOS管421b的栅极与第三级电路300连接，第二低电压校准MOS管421b用于在接收低电压信号时导通。
第一低电压校准MOS管411b和第二低电压校准MOS管421b接受的低电压信号与上拉/下拉电压信号为同源信号。
在一种具体实施例中，第一低电压校准MOS管411b和第二低电压校准MOS管421b均为薄栅低阈值NMOS管，在上拉/下拉电路中并联薄栅低阈值NMOS进行矫正，有效防止在上拉/下拉电路中等效电阻变化较大，完全依赖ZQ校准，缩小校准范围。
在一种实施例中，参见图3所示，第一薄栅低阈值NMOS管411a和第一低电压校准MOS管411b源极连接端与数据输出端之间串联有第一定值电阻411d，多个第三薄栅低阈值NMOS管411c的源极连接端与数据输出端DQ之间串联有第二定值电阻411e；
参见图4所示，第二薄栅低阈值NMOS管421a和第二低电压校准MOS管421b的源极连接端与数据输出端之间串联有第三定值电阻421d，多个第四薄栅低阈值NMOS管421c的源极连接端与数据输出端之间串联有第四定值电阻421e。
本实施例上拉电路410或者下拉电路420中的MOS管上分别串联一个电阻，这样，在调整ZQ校准信号的设置时，上拉电路410或者下拉电路420中的MOS管的精度和线性度能够保持的更好。
在一种实施例中，参见图5所示，第一级电路100包括结构相同的第一上拉控制模块110和第一下拉控制模块120，第一上拉控制模块110和第一下拉控制模块120均用于将读取的数据信号进行延时，分成包括多个速率等级的数据信号输出。
在一种具体实施例中，参见图5所示，第一上拉控制模块110和第一下拉控制模块120均包括三个延时单元130。第一上拉控制模块110和第一下拉控制模块120均用于将读取的串行数据通过三个延时单元130，分成包括快、中、慢三个速率等级的数据信号输出，即快信号Dataout<0>，中信号Dataout<1>，慢信号Dataout<2>。
本实施例使用不同驱动强度的驱动管作为延时单元130进行延时，以产生速率等级不同的数据信号。这样，当数据信号传到第四级电路400时，防止电路中驱动管同时打开，在输出级的电源和接地端上产生大的噪音干扰，同时分成速率等级不同的信号可以部分控制输出级信号的电压转换速率。
在一种实施例中，第二级电路包括：第二上拉控制模块220、第二下拉控制模块210以及上拉开关控制模块230。
参见图7所示，第二上拉控制模块220用于接收第一上拉控制模块110输出的数据信号，并根据上拉驱动设置强度选择一路径输出数据信号；
参见图6所示，第二下拉控制模块210用于接收第一下拉控制模块120输出的数据信号，并根据下拉驱动设置强度和ODT开启信号选择一路径输出数据信号；
参见图8所示，上拉开关控制模块230用于接收开关使能信号和复用上拉驱动设置强度，以控制第二上拉控制模块220中每一个路径的开关。
在一种具体实施例中，参见图6所示，第二下拉控制模块210包括四个下拉路径单元210a，下拉路径单元210a包括第一与非门211、第二与非门212和第三与非门213，第一与非门211的一输入端为驱动强度设置端，第二与非门212的一输入端为ODT(输出高电平)开启信号端，第二与非门212的另一输入端为ODT设置端；第一与非和第二与非门212的输出端均与第三与非门213的一输入端连接，第三与非门213的输出端输出数据 信号；两个下拉路径单元210a中第一与非门211的另一输入端接收第一下拉控制模块120输出的快数据信号Datain<0>，对应的第三与非门213的输出端输出快数据信号Dataout<0>和Dataout<1>；其余两个下拉路径单元210a中第一与非门211的另一输入端接收第一下拉控制模块120输出的中数据信号Datain<1>和慢数据信号Datain<2>，对应的第三与非门213的输出端输出中数据信号Dataout<2>和慢数据信号Dataout<3>。
在存储器处于读数据模式时，ODT模式关闭，ODT开启信号端(Odten)为0，输出数据信号(Dataout<3:0>)由驱动强度设置端(Drive<2:0>)控制。
在存储器处于写数据模式时，ODT模式开启，ODT开启信号端(Odten)为1，则输出数据信号(Dataout<3:0>)由ODT设置端(Odt<2:0>)控制。
不同的输出强度和不同的快慢速度的组合，对小的驱动强度，则输出快打开，要用快信号；对大的驱动强度，要减小噪音，用快慢组合信号。
在一种具体实施例中，参见图7所示，第二上拉控制模块220包括四个上拉路径单元220a，上拉路径单元220a包括第四与非门221和第一反相器222，第四与非门221的一输入端为驱动强度设置端，第四与非门221的输出端与第一反相器222的输入端连接，第一反相器222输出端输出数据信号，两个上拉路径单元220a中第四与非门221的另一输入端接收第一上拉控制模块110输出的快数据信号Datain<0>，对应第一反相器222输出端输出快数据信号Dataout<0>和Dataout<1>；其余两个上拉路径单元220a中第四与非门221的另一输入端接收第一上拉控制模块110输出的中数据信号Datain<1>和慢数据信号Datain<2>，对应第一反相器222输出端输出中数据信号Dataout<2>和慢数据信号Dataout<3>。
当存储器处于读数据模式时，第二上拉控制模块220的输出数据信号(Dataout<3:0>)由驱动强度设置端(Drive<2:0>)控制；存储器中ODT是下拉接地的，上拉控制模块220不受ODT控制。
在一种具体实施例中，参见图8所示，上拉开关控制模块230包括多个上拉开关单元230a，上拉开关单元230a包括第五与非门231和第二反相器232，第五与非门231的一输入端为开关使能信号端(Swen)，第五与 非门231的另一输入端为上拉驱动强度设置端(Drive<2:0>)，第五与非门231的输出端与第二反相器232的输入端连接，第二反相器232输出端输出数据信号(Dataout<3:0>)，上拉驱动强度设置为复用上拉控制模块220中驱动强度设置，以使一个上拉开关单元230a对应控制一个上拉路径单元220a。
存储器复用了上拉控制模块220的驱动强度设置端(Drive<2:0>)来控制上拉开关单元230a，即一路上拉开关单元230a控制一路上拉路径单元220a。
在一种实施例中，参见图9所示，第三级电路300包括具有相同结构的第三上拉控制模块310和第三下拉控制模块320。在一种实施例中，第三上拉控制模块310和第三下拉控制模块320具有相同结构。
参见图9所示，第三上拉控制模块310的输入端与第二上拉控制模块210连接，第三上拉控制模块310的输出端与第一薄栅低阈值NMOS管411a的栅极连接；第三上拉控制模块310用于将接收的数据信号Datain x转化为同一速率的上拉电压信号Dataout0main和对应接收数据信号的上拉ZQ校准信号DataoutxZq<n:0>其中，x≥0，n≥1；图9中，x＝0，1，2，3，n＝5。
参见图9所示，第三下拉控制模块320的输入端与第二下拉控制模块220连接，第三下拉控制模块320的输出端与第二薄栅低阈值NMOS管421a的栅极连接；第三下拉控制模块320用于将接收的数据信号Datain x转化为同一速率的下拉电压信号Dataout0main和对应接收数据信号的下拉ZQ校准信号DataoutxZq<n:0>，图9中，x＝0，1，2，3，n＝5。
在一种具体实施例中，参见图9所示，第三上拉控制模块310用于将从第二上拉控制模块220接收的两个快数据信号和中、慢数据信号Datain<3:0>转化为上拉电压信号Dataout0main和对应接收数据信号的上拉ZQ校准信号Dataout<3:0>Zq<5:0>(Datain和Dataout仅表示该数据信号的输入和输出状态)。
在一种具体实施例中，参见图9所示，第三下拉控制模块320用于将从第二下拉控制模块210接收的两个快数据信号和中、慢数据信号Datain<3:0>转化为同一速率的下拉电压信号Dataout0main和对应数据信号 的下拉ZQ校准信号Dataout<3:0>Zq<5:0>。Dataout<3:0>Zq<5:0>即为输入第四级电路400中的ZQ校准信号Zq<5:0>。
在一种具体实施例中，参见图9所示，第三上拉控制模块310包括四个上拉控制子模块330。参见图10所示，上拉控制子模块330包括七个第六与非门331和七个第三反相器332，第六与非门331的一输入端接收第二上拉控制模块220输出的一数据信息Datain，第一个第六与非门311的另一输入端连接基准信号EN，其余六个第六与非门331的另一输入端连接ZQ校准值Zqcal<5:0>，一个第六与非门331的输出端连接一个第三反相器332的输入端；七个所述第三反相器332依次输出上拉电压信号Dataoutmain以及上拉ZQ校准信号DataoutZq<5:0>。
第三上拉控制模块310中接收快、中、慢数据信号的四个上拉控制子模块330的输出端与上拉电路410中六个第一薄栅低阈值NMOS管411a的栅极按照1:2:2:1或者2:1:2:1的比例进行连接，以保证快数据信号接入三个第一薄栅低阈值NMOS管411a的栅极，中数据信号接入两个第一薄栅低阈值NMOS管411a的栅极，慢数据信号接入一个第一薄栅低阈值NMOS管411a的栅极。
在一种具体实施例中，参见图9所示，第三下拉控制模块320包括四个下拉控制子模块340。下拉控制子模块340和上拉控制子模块330具有相同结构。
参见图10所示，下拉控制子模块340包括七个第六与非门331和七个第三反相器332，第六与非门331的一输入端接收第二下拉控制模块210输出的一数据信息Datain，第一个第六与非门311的另一输入端连接基准信号EN，其余六个第六与非门331的另一输入端连接ZQ校准值Zqcal<5:0>，一个第六与非门331的输出端连接一个第三反相器332的输入端；七个所述第三反相器332依次输出下拉电压信号Dataoutmain以及下拉ZQ校准信号DataoutZq<5:0>。
第三下拉控制模块320中接收快、中、慢数据信号的四个下拉控制子模块340的输出端与下拉电路420中六个第二薄栅低阈值NMOS管421a的栅极按照1:2:2:1或者2:1:2:1的比例进行连接，以保证快数据信号接入 三个第二薄栅低阈值NMOS管421a的栅极，中数据信号接入两个第二薄栅低阈值NMOS管421a的栅极，慢数据信号接入一个第二薄栅低阈值NMOS管421a的栅极。
本实施例根据ZQ校准值的设置，分配选择数据信号的传输路径，同时通过电压转换速率可调的第三反相器332调整第三级电路300输出信号的电压转换速率来控制第四级电压400转换速率。
为达到上述目的，本发明提供了一种芯片，包括上述实施方式的输出电路。
本实施例的芯片在满足JEDEC的条件下，优化了各参数的控制，满足了应用于两种不同存储器数据输出环境的要求。
以上，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到其各种变化或替换，这些都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接，还可以是通信； 可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度小于第二特征。
上文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，上文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。

Claims (14)

  1. 一种输出电路，其特征在于，包括：
    第一级电路，所述第一级电路用于读取存储器内部的串行数据，并将所述串行数据分成多个设定速率等级的电压信号；
    第二级电路，与所述第一级电路连接，所述第二级电路用于接收所述第一级电路输出的多个电压信号，生成多个电压信号，并为每一个生成的电压信号分配传输路径；
    第三级电路，与所述第二级电路连接，所述第三级电路用于接收所述第二级电路输出的多个电压信号，并根据ZQ校准信号为每一个接收到的电压信号分配传输路径；以及
    第四级电路，与所述第三级电路连接，所述第四级电路包括上拉电路和下拉电路，所述上拉电路和所述下拉电路均包括多个并联的薄栅低阈值NMOS管，所述第四级电路用于接收所述第三级电路输出的多个电压信号，并根据接收到的电压信号生成所述输出电路的输出电压信号。
  2. 如权利要求1所述的输出电路，其特征在于，所述上拉电路包括多个并联的上拉支路，各所述上拉支路均包括结构相同的第一薄栅低阈值NMOS管，所述第一薄栅低阈值NMOS管的漏极与电源电压连接，所述第一薄栅低阈值NMOS管的栅极接收所述第三级电路输出的上拉电压信号；各所述上拉支路的所述第一薄栅低阈值NMOS管的源极均连接作为数据输出端。
  3. 如权利要求2所述的输出电路，其特征在于，所述下拉电路包括多个并联的下拉支路，各所述下拉支路均包括结构相同的第二薄栅低阈值NMOS管，所述第二薄栅低阈值NMOS管的源极接地，所述第二薄栅低阈值NMOS管的漏极与所述第一薄栅低阈值NMOS管的源极连接，所述第二薄栅低阈值NMOS管的栅极接收所述第三级电路输出的下拉电压信号。
  4. 如权利要求3所述的输出电路，其特征在于，所述第三级电路还用 于在ZQ校准时输出多个上拉ZQ校准信号；
    各所述上拉支路均包括多个第三薄栅低阈值NMOS管，各所述上拉支路中所述第三薄栅低阈值NMOS管均与所述第一薄栅低阈值NMOS管并联；所述第三薄栅低阈值NMOS管的栅极接收所述上拉ZQ校准信号，所述第三薄栅低阈值NMOS管用于根据上拉ZQ校准信号，调整所述上拉支路的等效电阻为RZQ。
  5. 如权利要求4所述的输出电路，其特征在于，所述第三级电路还用于在ZQ校准时输出多个下拉ZQ校准信号；
    各所述下拉支路均包括多个第四薄栅低阈值NMOS管，各所述下拉支路中所述第四薄栅低阈值NMOS管均与所述第二薄栅低阈值NMOS管并联，所述第四薄栅低阈值NMOS管的栅极接收所述下拉ZQ校准信号，所述第四薄栅低阈值NMOS管用于根据下拉ZQ校准信号，调整所述下拉支路的等效电阻为RZQ。
  6. 如权利要求5所述的输出电路，其特征在于，多个所述第三薄栅低阈值NMOS管和多个所述第四薄栅低阈值NMOS管的等效宽长比的比例均依次递增。
  7. 如权利要求5所述的输出电路，其特征在于，所述上拉电路还包括上拉开关模块，所述上拉开关模块包括与所述第一薄栅低阈值NMOS管对应数目的厚栅高阈值NMOS管，所述厚栅高阈值NMOS管的漏极与电源电压连接，所述厚栅高阈值NMOS管的源极与所述第一薄栅低阈值NMOS管的漏极一一对应连接，所述厚栅高阈值NMOS管栅极用于接收所述第三级电路输出的高电压阈值信号。
  8. 如权利要求7所述的输出电路，其特征在于，各所述上拉支路还包括至少一个第一低电压校准MOS管，所述第一低电压校准MOS管与所述第一薄栅低阈值NMOS管并联，所述第一低电压校准MOS管的栅极与所述第三级电路连接，所述第一低电压校准MOS管用于在接收低电压信号时导通。
  9. 如权利要求8所述的输出电路，其特征在于，各所述下拉支路还包括至少一个第二低电压校准MOS管，所述第二低电压校准MOS管与所述第二薄栅低阈值NMOS管并联，所述第二低电压校准MOS管的栅极与所述第三级电路连接，所述第二低电压校准MOS管用于在接收低电压信号时导通。
  10. 如权利要求7所述的输出电路，其特征在于，所述第一薄栅低阈值NMOS管和第一低电压校准MOS管源极连接端与所述数据输出端之间串联有第一定值电阻，多个所述第三薄栅低阈值NMOS管的源极连接端与所述数据输出端之间串联有第二定值电阻；
    所述第二薄栅低阈值NMOS管和第二低电压校准MOS管的源极连接端与所述数据输出端之间串联有第三定值电阻，多个所述第四薄栅低阈值NMOS管的源极连接端与所述数据输出端之间串联有第四定值电阻。
  11. 如权利要求3-10任一项所述的输出电路，其特征在于，所述第一级电路包括结构相同的第一上拉控制模块和第一下拉控制模块，所述第一上拉控制模块和所述第一下拉控制模块均用于将读取的数据信号进行延时，分成包括多个速率等级的数据信号输出。
  12. 如权利要求11所述的输出电路，其特征在于，所述第二级电路包括：
    第二下拉控制模块，所述第二下拉控制模块用于接收所述第一下拉控制模块输出的数据信号，并根据下拉驱动设置强度和ODT开启信号选择一路径输出数据信号；
    第二上拉控制模块，所述第二上拉控制模块用于接收所述第一上拉控制模块输出的数据信号，并根据上拉驱动设置强度选择一路径输出数据信号；以及
    上拉开关控制模块，所述上拉开关控制模块用于接收开关使能信号和复用上拉驱动设置强度，以控制所述第二上拉控制模块中每一个路径的开关。
  13. 如权利要求12所述的输出电路，其特征在于，所述第三级电路包括具有相同结构的第三上拉控制模块和第三下拉控制模块；
    所述第三上拉控制模块的输入端与第二上拉控制模块和ZQ校准值连接，所述第三上拉控制模块的输出端与所述第一薄栅低阈值NMOS管的栅极连接；所述第三上拉控制模块用于将接收的数据信号和ZQ校准值转化为同一速率的所述上拉电压信号和接收数据信号对应的所述上拉ZQ校准信号；
    所述第三下拉控制模块的输入端与第二下拉控制模块和ZQ校准值连接，所述第三下拉控制模块的输出端与所述第二薄栅低阈值NMOS管的栅极连接；所述第三下拉控制模块用于将接收的数据信号和ZQ校准值转化为同一速率的所述下拉电压信号和接收数据信号对应的所述下拉ZQ校准信号。
  14. 一种芯片，其特征在于，包括如权利要求1-13任一项所述的输出电路。
PCT/CN2019/120207 2019-01-07 2019-11-22 输出电路和芯片 WO2020143339A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP19909127.3A EP3910633A4 (en) 2019-01-07 2019-11-22 OUTPUT CIRCUIT AND CHIP
US17/172,319 US11295804B2 (en) 2019-01-07 2021-02-10 Output circuit and chip

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910012322.0A CN111415689A (zh) 2019-01-07 2019-01-07 输出电路和芯片
CN201910012322.0 2019-01-07

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/172,319 Continuation US11295804B2 (en) 2019-01-07 2021-02-10 Output circuit and chip

Publications (1)

Publication Number Publication Date
WO2020143339A1 true WO2020143339A1 (zh) 2020-07-16

Family

ID=71493999

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/120207 WO2020143339A1 (zh) 2019-01-07 2019-11-22 输出电路和芯片

Country Status (4)

Country Link
US (1) US11295804B2 (zh)
EP (1) EP3910633A4 (zh)
CN (1) CN111415689A (zh)
WO (1) WO2020143339A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112526581A (zh) * 2020-11-26 2021-03-19 重庆邮电大学 一种适用于辐射检测前端读出电路的时间甄别器
CN117831590B (zh) * 2024-01-04 2024-05-28 上海奎芯集成电路设计有限公司 多模式存储器驱动电路和多协议接口兼容型phy芯片
CN117555843B (zh) * 2024-01-09 2024-04-09 凌思微电子(杭州)有限公司 Io接口电路及芯片

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7714618B2 (en) * 2007-12-13 2010-05-11 Macronix International Co. Ltd Output driver circuit with output preset circuit and controlling method thereof having lower power consumption
CN102487240A (zh) * 2010-12-01 2012-06-06 中芯国际集成电路制造(上海)有限公司 电压转换速率控制电路和输出电路
US20170092348A1 (en) * 2013-10-07 2017-03-30 Samsung Electronics Co., Ltd. Signaling method using constant reference voltage and devices thereof
CN107947784A (zh) * 2017-10-20 2018-04-20 上海华力微电子有限公司 一种高性能输出驱动电路
CN108305647A (zh) * 2017-01-11 2018-07-20 中芯国际集成电路制造(上海)有限公司 输出驱动器和存储器的读电路
CN209045167U (zh) * 2019-01-07 2019-06-28 长鑫存储技术有限公司 输出电路和芯片

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552596B2 (en) * 2001-08-10 2003-04-22 Micron Technology, Inc. Current saving mode for input buffers
JP2015050691A (ja) * 2013-09-03 2015-03-16 マイクロン テクノロジー， インク． 半導体装置
JP2015076655A (ja) * 2013-10-07 2015-04-20 マイクロン テクノロジー， インク． 半導体装置
CN104064158B (zh) * 2014-07-17 2016-05-04 深圳市华星光电技术有限公司 具有自我补偿功能的栅极驱动电路
US10145892B2 (en) * 2016-08-22 2018-12-04 International Business Machines Corporation Increasing the resolution of on-chip measurement circuits
JP6899259B2 (ja) * 2017-05-17 2021-07-07 ラピスセミコンダクタ株式会社 半導体装置及びデータドライバ
CN107909959B (zh) * 2018-01-02 2020-05-12 京东方科技集团股份有限公司 移位寄存器单元、其驱动方法、栅极驱动电路及显示装置
US10614870B2 (en) * 2018-05-10 2020-04-07 Micron Technology, Inc. Low power method and system for signal slew rate control
CN208384966U (zh) * 2018-08-08 2019-01-15 北京京东方显示技术有限公司 一种移位寄存器、栅极驱动电路和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7714618B2 (en) * 2007-12-13 2010-05-11 Macronix International Co. Ltd Output driver circuit with output preset circuit and controlling method thereof having lower power consumption
CN102487240A (zh) * 2010-12-01 2012-06-06 中芯国际集成电路制造(上海)有限公司 电压转换速率控制电路和输出电路
US20170092348A1 (en) * 2013-10-07 2017-03-30 Samsung Electronics Co., Ltd. Signaling method using constant reference voltage and devices thereof
CN108305647A (zh) * 2017-01-11 2018-07-20 中芯国际集成电路制造(上海)有限公司 输出驱动器和存储器的读电路
CN107947784A (zh) * 2017-10-20 2018-04-20 上海华力微电子有限公司 一种高性能输出驱动电路
CN209045167U (zh) * 2019-01-07 2019-06-28 长鑫存储技术有限公司 输出电路和芯片

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3910633A4 *

Also Published As

Publication number Publication date
EP3910633A4 (en) 2022-03-09
US20210166748A1 (en) 2021-06-03
EP3910633A1 (en) 2021-11-17
US11295804B2 (en) 2022-04-05
CN111415689A (zh) 2020-07-14

Similar Documents

Publication Publication Date Title
WO2020143339A1 (zh) 输出电路和芯片
KR100904482B1 (ko) 온 다이 터미네이션 장치의 캘리브래이션 회로
US8736306B2 (en) Apparatuses and methods of communicating differential serial signals including charge injection
KR101290080B1 (ko) 프리엠퍼시스 회로 및 이를 구비한 차동 전류 신호전송 시스템
US7800416B2 (en) Data output buffer circuit
KR102430328B1 (ko) 데이터를 나타내는 다중 레벨 신호에 추가 구동을 제공하기 위한 장치 및 방법
US8749269B2 (en) CML to CMOS conversion circuit
JP4402185B2 (ja) インピーダンスコントロール回路
US20150333753A1 (en) Io and pvt calibration using bulk input technique
US7982493B1 (en) Semiconductor integrated circuit for controlling output driving force
US8441283B2 (en) Integrated circuit
JPH11186895A (ja) ヒステリシス入力バッファ
US9647666B1 (en) Transmitter and semiconductor device
US10135442B2 (en) Current-mode logic circuit
US8749266B2 (en) Data output circuit responsive to calibration code and on die termination code
US7759994B2 (en) Skew signal generation circuit and semiconductor memory device having the same
CN209045167U (zh) 输出电路和芯片
CN109783421B (zh) 高速信号驱动装置
US20220231891A1 (en) Apparatuses and methods for pre-emphasis control
US9838011B2 (en) Integrated circuit chip and its impedance calibration method
US8045399B2 (en) Data output circuit in a semiconductor memory apparatus
US9847777B2 (en) Signal potential converter
US20110050290A1 (en) Output driver circuit
US20240242747A1 (en) Off-chip driving device and driving capability enhancement method thereof
US7505752B1 (en) Receiver for differential and reference-voltage signaling with programmable common mode

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19909127

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2019909127

Country of ref document: EP

Effective date: 20210809