WO2020136821A1 - Circuit de pompe de charge et dispositif à semi-conducteurs - Google Patents

Circuit de pompe de charge et dispositif à semi-conducteurs Download PDF

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Publication number
WO2020136821A1
WO2020136821A1 PCT/JP2018/048203 JP2018048203W WO2020136821A1 WO 2020136821 A1 WO2020136821 A1 WO 2020136821A1 JP 2018048203 W JP2018048203 W JP 2018048203W WO 2020136821 A1 WO2020136821 A1 WO 2020136821A1
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Prior art keywords
charge pump
transistor
node
voltage
pump circuit
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PCT/JP2018/048203
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English (en)
Japanese (ja)
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明夫 上村井
晃嗣 大江
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三菱電機株式会社
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Priority to PCT/JP2018/048203 priority Critical patent/WO2020136821A1/fr
Priority to JP2020562061A priority patent/JP7134255B2/ja
Publication of WO2020136821A1 publication Critical patent/WO2020136821A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a charge pump circuit and a semiconductor device including the charge pump circuit.
  • Patent Document 1 Charge pumps described in Japanese Patent Laid-Open No. 2003-33006 (Patent Document 1) and Japanese Patent Laid-Open No. 2006-67764 (Patent Document 2) as a circuit for obtaining an output voltage obtained by boosting the input voltage of the input terminal at the output terminal. Circuits are known.
  • the charge pump circuit outputs an output voltage obtained by boosting the input voltage by charging/discharging a capacitor by switching on/off of a plurality of switching elements connected in series between an input terminal and an output terminal according to a clock signal. It is generated at the terminal.
  • the output voltage can be reduced to 0 V (ground voltage) by supplying current from the input terminal to the output terminal via the parasitic diodes of the plurality of switch elements in the operation stop state.
  • 0 V ground voltage
  • the output voltage of the charge pump circuit is used as a power supply, a leak current is generated by applying the voltage.
  • Patent Document 1 in a charge pump circuit, a transistor for cutting off the supply of an input voltage and a transistor for forcibly fixing an output voltage to a ground voltage are additionally arranged, and both transistors respond to a reset signal.
  • a configuration for operating the above is disclosed. As a result, when the operation of the charge pump circuit is stopped, the current from the input terminal to the output terminal is cut off, and the output voltage is fixed to the ground voltage.
  • Patent Document 2 a mechanism for switching the connection destination of the back gate of the switch element connected between the input terminal and the connection terminal is provided, and the polarity of the parasitic diode is set between the operation of the charge pump circuit and the operation stop thereof. It is described that the inversion reduces the current consumption when the operation is stopped.
  • a plurality of switch elements connected in series between the input terminal and the output terminal are composed of N-channel transistors. Therefore, when the operation of the charge pump circuit is stopped, if the N-channel transistor is turned off in response to the decrease in the gate voltage, the polarity of the parasitic diode is inverted to cut off the current path passing through the back gate. The current from the terminal to the output terminal can be cut off.
  • the gate voltage needs to be at the output voltage level in order to turn off the P-channel transistors when the charge pump circuit operates.
  • the output voltage is lowered to the ground voltage when the operation is stopped, there is a concern that the P-channel transistor cannot be turned off and the current from the input terminal to the output terminal cannot be cut off.
  • the present invention has been made to solve such a problem, and its main purpose is to interrupt the current supply from the input terminal to the output terminal and discharge the output terminal in the operation stop state. It is to provide a structure of a charge pump circuit.
  • the discharge element discharges the output terminal by turning on when the operation of the charge pump circuit is stopped.
  • a plurality of 1st P type transistors are connected in series between an input terminal and an output terminal, and constitute a plurality of switch elements, respectively.
  • the plurality of switch drive circuits selectively select one of the reference voltage and the output voltage for each control electrode of the plurality of first P-type transistors according to one of the complementary first and second clocks. It outputs and controls ON/OFF of a plurality of switch elements, respectively.
  • the first terminal of the capacitor is connected to a connection point of two adjacent switch elements among the plurality of switch elements.
  • the voltage selection circuit selectively outputs one of the reference voltage and the input voltage to the second terminal of the capacitor according to the first or second clock.
  • the back gate disconnection switch element includes a back gate of at least one first P-type transistor of the plurality of first P-type transistors and an output terminal of two main electrodes of the first P-type transistor. Connected to the main electrode on the side.
  • the back gate disconnection switch drive circuit turns on the back gate disconnection switch element in the boosting operation state, and turns off the back gate disconnection switch element in the operation stop state.
  • the second P-type transistor forming the back gate disconnecting switch element includes a first main electrode connected to the back gate of the first P-type transistor, and a main electrode on the output terminal side of the first P-type transistor. A second main electrode connected. The back gate of the second P-type transistor is connected to the first main electrode.
  • at least one first switch drive circuit corresponding to at least one first P-type transistor to which the back gate disconnection switch element is connected has at least one first switch drive circuit in the operation stop state of the charge pump circuit. , And outputs the input voltage to the control electrode of the first P-type transistor.
  • the input voltage is supplied to the gate of the first P-type transistor by the first switch drive circuit and the parasitic diode formed in the second P-type transistor. It is possible to cut off the current from the input terminal to the output terminal. At the same time, the output terminal can be discharged to reduce the output voltage to the ground voltage.
  • FIG. 7 is a circuit diagram illustrating a configuration of a charge pump circuit according to a comparative example.
  • FIG. It is a wave form diagram of the clock signal input into a charge pump circuit.
  • 3 is a chart illustrating a boosting operation of the charge pump circuit shown in FIG. 1.
  • 3 is a circuit diagram illustrating a configuration example of a charge pump circuit according to the first embodiment.
  • FIG. 5 is a conceptual cross-sectional view for explaining a current cutoff structure of a switch element in the charge pump shown in FIG. 4.
  • 3 is a table for explaining the behavior of the charge pump circuit according to the first embodiment in an operation stop state and a boost operation state.
  • 6 is a flowchart illustrating a control process at the start of the boosting operation of the charge pump circuit according to the first embodiment.
  • FIG. 1 is a wave form diagram of the clock signal input into a charge pump circuit.
  • 3 is a chart illustrating a boosting operation of the charge pump circuit shown in FIG. 1.
  • 3 is
  • FIG. 9 is a circuit diagram illustrating a configuration of a charge pump circuit according to a first modification of the first embodiment.
  • FIG. 9 is a circuit diagram illustrating a configuration of a charge pump circuit according to a second modification of the first embodiment.
  • FIG. 6 is a circuit diagram illustrating a configuration example of a charge pump circuit according to the second embodiment.
  • FIG. 11 is a waveform diagram of a clock signal input to the charge pump circuit shown in FIG. 10.
  • 11 is a chart illustrating the operation of the charge pump circuit shown in FIG. 10. It is a schematic block diagram of a semiconductor device including a charge pump circuit according to the present embodiment.
  • Embodiment 1 (Explanation of Comparative Example) First, the configuration of a general charge pump circuit will be described as a comparative example of this embodiment.
  • FIG. 1 is a circuit diagram illustrating the configuration of a charge pump circuit according to a comparative example.
  • the basic circuit operation (boost operation) of the charge pump circuit 100 according to the comparative example is the same as that of the charge pump circuit according to the present embodiment described later, but The charge pump circuit 100 has a problem similar to that of Patent Document 1 with respect to the function of interrupting the short-circuit current when the output terminal is grounded.
  • a charge pump circuit 100 constitutes an input terminal 5, an output terminal 10, and a “plurality of switch elements” connected in series between the input terminal 5 and the output terminal 10.
  • P-channel type (also simply referred to as P-type) transistors PMOS5 and PMOS6, switch drive circuits 11 and 12, an inverter 20, inverter drive circuits 13 and 14, and a capacitor C1 are provided.
  • the voltage of the input terminal 5 will be referred to as the input voltage VIN
  • the voltage of the output terminal 10 will be referred to as the output voltage VOUT.
  • Each of the clock signals CLK1 to CLK4 shown in FIG. 1 is a logic high level (hereinafter, referred to as “H level”) and a logic low level (hereinafter, “L level”) during the operation period of the charge pump circuit 100. ”) is repeated at regular intervals.
  • the transistor PMOS5 is electrically connected between the node Np0 connected to the input terminal 5 and the node Np1.
  • the gate of the transistor PMOS5 is connected to the output node N3 of the switch drive circuit 11.
  • the transistor PMOS5 has the parasitic diode D9 of the polarity shown in FIG. 1 by connecting the back gate to the node Np1.
  • the transistor PMOS6 is electrically connected between the node Np1 and the node Np2 connected to the output terminal 10.
  • the gate of the transistor PMOS6 is connected to the output node N4 of the switch drive circuit 12.
  • the transistor PMOS6 has a parasitic diode D10 having the polarity shown in FIG. 1 by connecting the back gate to the node Np2.
  • the switch drive circuit 11 has a P-type transistor PMOS1 and an N-channel type (also simply referred to as N-type) transistor NMOS1 which are connected in series via a node N3 between a node Np2 and a ground node Ng.
  • the clock signal CLK1 is commonly input to the gates of the transistors PMOS1 and NMOS1.
  • Ground node Ng supplies a reference voltage (typically, ground voltage GND).
  • the switch drive circuit 12 includes a P-type transistor PMOS2 and an N-type transistor NMOS2 that are connected in series between the node Np2 and the ground node Ng via the node N4.
  • the clock signal CLK2 is commonly input to the gates of the transistors PMOS2 and NMOS2.
  • the switch drive circuits 11 and 12 configure an inverter that uses the output voltage VOUT and the ground voltage GND as power supplies and receives the clock signals CLK1 and CLK2 as inputs.
  • the transistors PMOS1 and NMOS1 have parasitic diodes D1 and D2 having the polarities shown in FIG. 1 by connecting their back gates to the node Np2 and the ground node Ng, respectively.
  • the transistors PMOS2 and NMOS2 have parasitic diodes D3 and D4 of the polarity shown in FIG. 1 by connecting their back gates to the node Np2 and the ground node Ng, respectively.
  • the inverter 20 has a P-type transistor PMOS7 and an N-type transistor NMOS5 connected in series via a node N2 between a node Np0 (input voltage VIN) and a ground node Ng (ground voltage GND).
  • the node N2 is connected to the node Np1 via the capacitor C1.
  • the gate of the transistor PMOS7 is connected to the output node of the inverter drive circuit 13 to which the clock signal CLK3 is input.
  • the gate of the transistor NMOS5 is connected to the output node of the inverter drive circuit 14 to which the clock signal CLK4 is input.
  • the transistors PMOS7 and NMOS5 have parasitic diodes D11 and D12 having the polarities shown in FIG. 1 by connecting their back gates to the node Np0 and the ground node Ng, respectively.
  • the inverter drive circuit 13 includes a P-type transistor PMOS3 and a P-type transistor PMOS3 connected in series between the node Np0 (input voltage VIN) and the ground node Ng (ground voltage GND) via an output node connected to the gate of the transistor PMOS7. It has an N-type transistor NMOS3.
  • the clock signal CLK3 is commonly input to the gates of the transistors PMOS3 and NMOS3.
  • the inverter drive circuit 14 is connected in series between the node Np0 (input voltage VIN) and the ground node Ng (ground voltage GND) via an output node connected to the gate of the transistor NMOS5, and is of a P-type. It has a transistor PMOS4 and an N-type transistor NMOS4. The clock signal CLK4 is commonly input to the gates of the transistors PMOS4 and NMOS4.
  • the inverter drive circuits 13 and 14 constitute an inverter that receives the clock signals CLK3 and CLK4 as inputs using the input voltage VIN and the ground voltage GND as power sources.
  • the transistors PMOS3 and NMOS3 have parasitic diodes D5 and D6 of the polarity shown in FIG. 1 by connecting their back gates to the node Np0 and the ground node Ng, respectively.
  • the transistors PMOS4 and NMOS4 have parasitic diodes D7 and D8 having the polarities shown in FIG. 1 by connecting their back gates to the node Np0 and the ground node Ng, respectively.
  • FIG. 2 is a waveform diagram of clock signals CLK1 to CLK4 input to the charge pump circuit 100.
  • the clock signal CLK1 and the clock signals CLK2 to CLK4 have opposite phases, and the clock signals CLK2 to CLK4 have the same phase.
  • a time difference (so-called dead time) is provided between the edges of the clock signals CLK1 to CLK4 to prevent a shoot-through current due to simultaneous conduction of a plurality of transistors.
  • the dead time is normally several (ns) to several tens (ns), but in FIG. 2, the dead time is exaggerated with respect to the clock period.
  • FIG. 3 shows a chart for explaining the boosting operation of the charge pump circuit 100.
  • the charge pump circuit 100 alternately repeats the states 1 and 2 shown in FIG. 3 according to the clock signals CLK1 to CLK4 based on the complementary reference clocks CLKa and CLKb.
  • the switch drive circuit 11 outputs the L level voltage (ground voltage GND) to the node N3.
  • the switch drive circuit 12 outputs an H level voltage (output voltage VOUT) to the node N4.
  • the inverter drive circuits 13 and 14 output the input voltage VIN
  • the transistor PMOS7 turns off while the transistor NMOS5 turns on. Therefore, inverter 20 connects node N2 to ground node Ng.
  • the node Np1 is connected to the input terminal 5 (input voltage VIN) but disconnected from the output terminal 10.
  • the clock signal CLK1 (reference clock CLKa) is at L level, while the clock signals CLK2 to CLK4 (reference clock CLKb) are at H level. Therefore, the node N3, that is, the gate voltage of the transistor PMOS5 becomes the output voltage VOUT, and the node N4, that is, the gate voltage of the transistor PMOS6 becomes the ground voltage GND. Thereby, in the plurality of switch elements, the transistor PMOS6 is turned on, while the transistor PMOS5 is turned off.
  • the inverter drive circuits 13 and 14 output the ground voltage GND
  • the transistor PMOS7 turns on while the transistor NMOS5 turns off. Therefore, the inverter 20 connects the node N2 to the node Np0.
  • the node Np1 is disconnected from the input terminal 5 (input voltage VIN) and is connected to the output terminal 10.
  • the capacitor C1 is connected between the input terminal 5 (node Np0) and the node Np1. Therefore, the output voltage VOUT at the output terminal 10 becomes the sum of the input voltage VIN and the capacitor voltage V(C1), that is, twice the input voltage VIN.
  • the charge pump circuit 100 can execute the boosting operation of outputting the output voltage VOUT that is twice the input voltage VIN by alternately repeating the states 1 and 2 according to the clock signals CLK1 to CLK4.
  • the transistor PMOS5 is turned on while the transistor PMOS6 is turned off.
  • the transistor PMOS5 in the on state and the parasitic diode D10 of the transistor PMOS6 in the off state form a current path from the input terminal 5 to the output terminal 10.
  • the output voltage VOUT becomes a voltage lower than the input voltage VIN by the amount of forward voltage drop due to the parasitic diode D10.
  • the transistor PMOS6 is turned on while the transistor PMOS5 is turned off.
  • the transistor PMOS6 in the on state and the parasitic diode D9 of the transistor PMOS5 in the off state form a current path from the input terminal 5 to the output terminal 10.
  • the output voltage VOUT becomes a voltage lower than the input voltage VIN by the amount of forward voltage drop due to the parasitic diode D9.
  • the parasitic diodes D) and D10 form a current path from the input terminal 5 to the output terminal 10. At this time, the output voltage VOUT becomes a voltage lower than the input voltage VIN by the sum of the amount of voltage drop in the forward direction due to the parasitic diodes D9 and D10.
  • FIG. 4 is a circuit diagram illustrating a configuration example of the charge pump circuit according to the first embodiment.
  • charge pump circuit 101 performs the same boosting operation as charge pump circuit 100 according to the comparative example, and changes from input terminal 5 to output terminal 10 in the operation stop state. It has a current interruption function.
  • the charge pump circuit 101 according to the first embodiment is different from the charge pump circuit 100 of the comparative example in that the transistor PMOS13 connected to the back gate of the transistor PMOS5, which is a switch element, and the switch driving that controls ON/OFF of the transistor PMOS13.
  • the circuit 30 and an N-type transistor NMOS7 corresponding to one example of the "discharging element" are further provided.
  • the charge pump circuit 101 includes a switch drive circuit 21 instead of the switch drive circuit 12 in the charge pump circuit 100 of the comparative example.
  • the switch drive circuit 21 controls ON/OFF of the transistor PMOS6 which is a switch element to which the transistor PMOS13 is connected.
  • the configuration of the other parts of the charge pump circuit 101 according to the first embodiment is similar to that of the charge pump circuit 100 (FIG. 1) according to the comparative example, and therefore detailed description will not be repeated.
  • the transistors PMOS5 and PMOS6 correspond to one embodiment of the "first P-type transistor” that constitutes the "plurality of switch elements", and the transistor PMOS13 is the "back gate disconnection switch element". This corresponds to one example of the "second P-type transistor" to be configured.
  • the switch drive circuit 30 corresponds to an example of the "back gate disconnection switch element drive circuit”.
  • the node Np1 corresponds to a “connection point” between two adjacent switch elements, and the inverter drive circuits 13 and 14 and the inverter 20 constitute an example of a “voltage selection circuit”.
  • the transistor PMOS13 is connected between the back gate of the transistor PMOS6 and the main electrode (source in FIG. 4) on the output terminal 10 side of the two main electrodes (source and drain) of the transistor PMOS6.
  • FIG. 5 shows a conceptual cross-sectional view of the transistors PMOS6 and PMOS13 for explaining the current cutoff structure of the charge pump circuit 101.
  • N-well 61 and N-well 71 are formed on P-type substrate 60.
  • the transistor PMOS6 has P+ regions 62 and 63 and an N+ region 65 formed in the N well 61.
  • the P+ regions 62 and 63 correspond to the first and second main electrodes (one of the source and the drain) of the transistor PMOS6.
  • the N+ region 65 corresponds to the back gate of the transistor PMOS6.
  • the transistor PMOS6 further has a gate 64 corresponding to a control electrode, which is formed immediately above the channel region between the P+ regions 62 and 63 via an insulating film.
  • the transistor PMOS 13 has P+ regions 72 and 73 formed in the N well 71, a gate 74, and an N+ region 75.
  • the P+ regions 72 and 73 correspond to the first and second main electrodes (one of the source and the drain) of the transistor PMOS 13, and the N+ region 75 corresponds to the back gate of the transistor PMOS 13.
  • the gate 64 corresponds to the control electrode of the transistor PMOS13.
  • the P+ region 63 is connected to the node Np2 (that is, the output terminal 10), and the P+ region 62 is connected to the node Np1 connected to the capacitor C1.
  • Gate 64 is connected to node N4 that receives the output of switch drive circuit 21.
  • the P+ region 62 and the P+ region 63 correspond to one example of the "main electrode”, and in particular, the P+ region 63 corresponds to the "main electrode” on the output terminal 10 side.
  • the P+ region 73 is connected to the node Np2 (that is, the P+ region 63 of the transistor PMOS6), and the gate 74 is connected to the node N5 receiving the output of the switch drive circuit 30.
  • the P+ region 72 is connected to the N+ region 75 and the N+ region 75 of the transistor PMOS6.
  • a PN junction between the P+ region 73 connected to the output terminal 10 and the N well 71 forms a parasitic diode.
  • a P+ region 62 connected to the node Np1 and a PN junction between the N well 61 form a parasitic diode.
  • the bodies (back gates) of the PMOS 6 and the PMOS 13 are electrically connected to each other. That is, in the transistor PMOS13 which is one example of the "second P-type transistor", the P+ region 72 corresponds to one example of the "first main electrode”, and the P+ region 73 is the "second main electrode”. N+ region 75 corresponds to one example of the “back gate”.
  • a path formed by the parasitic diode D10 of the PMOS 6, the bodies (back gates) of the PMOS 6 and the PMOS 13, and the parasitic diode D23 of the PMOS 13 is formed between the main electrodes of the transistor PMOS6.
  • the parasitic diodes D10 and D23 are connected in series with opposite polarities by the connection relationship described in FIG.
  • the switch drive circuit 30 has a P-type transistor PMOS14 and an N-type transistor NMOS11 connected in series via a node N5 between a node Np0 and a ground node Ng.
  • the control signal EN is commonly input to the gates of the transistors PMOS14 and NMOS11.
  • the control signal EN is set to the H level in the boosting operation state of the charge pump circuit, while being set to the L level in the operation stop state.
  • the switch drive circuit 30 constitutes an inverter that receives the control signal EN as an input from the input voltage VIN and the ground voltage GND as power sources.
  • the transistors PMOS14 and NMOS11 have parasitic diodes D24 and D25 having the polarities shown in FIG. 1 by connecting their back gates to the node Np1 and the ground node Ng, respectively.
  • the output node N5 of the switch drive circuit 30 is connected to the gate of the transistor PMOS13.
  • the switch drive circuit 21 further includes transistors PMOS11 and PMOS12 in addition to the inverter-connected transistors PMOS2 and NMOS2 similar to the switch drive circuit 12 of FIG.
  • the transistor PMOS11 is connected between the node Np0 (input voltage VIN) and the node Ns corresponding to the source of the transistor PMOS2.
  • the transistor PMOS12 is connected between the node Np2 (output voltage VOUT) and the node Ns (transistor PMOS2).
  • a control signal EN is input to the gate of the transistor PMOS11.
  • the control signal ENB which is the inverted logic level of the control signal EN is input to the gate of the transistor PMOS12. That is, the control signal ENB is set to the H level in the operation stop state, while it is set to the L level in the boosting operation state of the charge pump circuit.
  • the transistors PMOS11 and NMOS12 have parasitic diodes D21 and D22 having the polarities shown in FIG. 1 by commonly connecting the back gate to the node Ns.
  • the switch drive circuit 21 operates as an inverter having the output voltage VOUT as a power supply voltage when the transistor PMOS12 is turned on in the boosting operation state of the charge pump circuit 101.
  • the switch drive circuit 21 operates as an inverter that uses the input voltage VIN as the power supply voltage.
  • the output node N4 of the inverter is connected to the gate of the transistor PMOS6.
  • clock signals CLK1 to CLK4 (FIG. 2) as those in the charge pump circuit 100 of the comparative example are input to the switch drive circuits 11 and 21 and the inverter drive circuits 13 and 14 of the charge pump circuit 101, respectively.
  • the transistor NMOS7 is connected between the output terminal 10 (node Np2) and the ground node Ng.
  • the output signal of the logic gate 80 is input to the gate of the transistor NMOS7.
  • Logic gate 80 outputs a logical product (AND) operation result of control signal ENB and an inverted signal of precharge signal PR.
  • the precharge signal PR has an L level by default, and is set to an H level in a precharge period described later.
  • the transistor PMOS11 is turned on, while the transistor PMOS12 is turned off.
  • the input voltage VIN is supplied to the node Ns by the transistor PMOS11. Therefore, by fixing the clock signal CLK2 to the L level, the input voltage VIN can be output to the node N4, that is, the gate of the transistor PMOS6, via the transistor PMOS2. Accordingly, the transistor PMOS6 can be turned off by setting the gate to a high voltage with respect to the source connected to the node Np2 (output terminal 10).
  • the function of the "first switch drive circuit” is realized by the switch drive circuit 21 among the plurality of switch drive circuits 11 and 21.
  • the transistors PMOS11 and PMOS12 form an example of a "voltage switching circuit”
  • the inverter formed by the transistors PMOS2 and NMOS2 forms an example of a "signal transmission circuit”.
  • the node Ns corresponds to an example of “power supply node”
  • the ground node Ng corresponds to an example of “reference voltage node”.
  • the switch drive circuit 30 outputs the input voltage VIN to the node N5 by turning on the transistor PMOS14. As a result, the transistor PMOS13 is kept off together with the transistor PMOS6. At this time, the current path passing through the body (back gate) of the transistor PMOS6 is blocked by the reverse voltage blocking by the parasitic diode D23 of the transistor PMOS13, which is a "back gate disconnecting switch element". Thereby, even if the transistor PMOS5 is turned on, the current path from the input terminal 5 to the output terminal 10 can be cut off.
  • FIG. 7 is a flowchart illustrating a control process at the start of the boosting operation of the charge pump circuit 101 according to the first embodiment.
  • the control process shown in FIG. 7 can be executed by a control circuit (not shown) that outputs the clock signals CLK1 to CLK4 and the control signals EN and ENB.
  • the control circuit can be provided outside the charge pump circuit 101.
  • the control circuit can be arranged inside the charge pump circuit 101. In this case, for example, the control circuit outputs the clock signals CLK1 to CLK4 and the control signals EN and ENB by inputting the operation and stop instructions of the charge pump circuit 101 and the reference clocks CLKa and CLKb to the control circuit. It is possible to adopt a configuration that does.
  • the output terminal 10 is disconnected from the ground node Ng by turning off the transistor NMOS7. Further, the switch driving circuit 21 outputs the ground voltage GND to the node N4, so that the transistor PMOS6 is turned on. Before the precharge, the output voltage VOUT is lowered to the ground voltage GND, so that the transistor PMOS5 is turned on regardless of the clock signal CLK1. Therefore, when the transistor PMOS6 is turned on, the output terminal 10 is precharged with the input voltage VIN.
  • the precharge completion determination at S100 is executed. For example, the precharge in S100 is continued until the predetermined time Txp elapses from the start of charging in S100 (when NO is determined in S110). When the time Txp has elapsed, the completion of precharge is determined (when YES is determined in S110), and the process proceeds to S120.
  • the determination in S120 can be realized by measuring the elapsed time using a timer or the like, but the completion of precharge is determined based on the detection value of a voltage sensor (not shown) arranged at the output terminal 10. May be.
  • control signal EN is changed from the L level to the H level and the control signal ENB is changed from the H level to the L level in S130, so that the precharge is completed. 101 shifts to the boost operation state.
  • the transistor NMOS7 is maintained off after the end of precharge.
  • the transistor PMOS12 is turned on, while the transistor PMOS11 is turned off.
  • the output voltage VOUT is supplied to the node Ns when the transistor PMOS12 is turned on, so that the switch drive circuit 21 operates similarly to the switch drive circuit 12 in FIG.
  • the voltage of the node Ns also rises as the output voltage VOUT rises, so that the transistor PMOS6 can be turned off during the L level period of the clock signal CLK2 even when the output voltage VOUT becomes higher than the input voltage VIN. it can.
  • the switch drive circuit 30 outputs the ground voltage GND to the node N5 by turning on the transistor NMOS14.
  • the transistor PMOS13 is turned on, so that the body (back gate) of the transistor PMOS6 is connected to the source (that is, the main electrode on the output terminal 10 side) of the transistor PMOS6, as in FIG.
  • the charge pump circuit 101 can operate similarly to the charge pump circuit 100 of FIG. 1 in the boosting operation state. Therefore, in S140, by inputting the clock signals CLK1 to CLK4 (FIG. 2) based on the reference clocks CLKa and CLKb, the charge pump circuit 101 outputs the output by repeating the state 1 and the state 2 shown in FIG. A voltage boosting operation is performed in which the voltage VOUT rises to twice the input voltage VIN. That is, the reference clocks CLKa (or clock signals CLK1) and CLKb (or clock signals CLK2 to CLK4) correspond to an example of “first and second clocks complementary to each other”.
  • the output terminal 10 can be precharged without passing a current through the parasitic diodes D9 and D10. As a result, it is possible to prevent latch-up from occurring in the parasitic diodes D9 and D10 during precharge and to stably start the boosting operation.
  • FIG. 8 is a circuit diagram illustrating the configuration of the charge pump circuit according to the first modification of the first embodiment.
  • the charge pump circuit 102 according to the first modification of the first embodiment is connected to the back gate of the transistor PMOS6 that is a switch element, as compared with the charge pump circuit 100 according to the comparative example. Further, it further includes a transistor PMOS17, a switch drive circuit 30 for controlling ON/OFF of the transistor PMOS17, and a transistor NMOS7 similar to that in FIG. Further, the charge pump circuit 102 includes a switch drive circuit 23 instead of the switch drive circuit 11 in the charge pump circuit 100 of the comparative example. The switch drive circuit 23 controls ON/OFF of the transistor PMOS5 which is a switch element to which the transistor PMOS17 is connected.
  • the transistor PMOS17 is connected between the back gate of the transistor PMOS5 and the main electrode (source in FIG. 8) on the output terminal 10 side of the two main electrodes of the transistor PMOS5.
  • the connection relationship between the transistors PMOS17 and PMOS5 is the same as the connection relationship between the transistors PMOS13 and PMOS6 in FIGS. Therefore, the parasitic diode D9 of the transistor PMOS5 and the parasitic diode D28 of the transistor PMOS17 are connected in series with opposite polarities on the path through the body (back gate) between the main electrodes of the transistor PMOS6.
  • the output node N5 of the switch drive circuit 30 is connected to the gate of the transistor PMOS17.
  • the switch drive circuit 23 further includes transistors PMOS15 and PMOS16 in addition to the inverter-connected transistors PMOS1 and NMOS1 similar to the switch drive circuit 12 of FIG.
  • the transistor PMOS15 is connected between the node Np0 (input voltage VIN) and the node Ns corresponding to the source of the transistor PMOS1 similarly to the transistor PMOS11 of FIG.
  • the transistor PMOS16 is connected between the node Np2 (output voltage VOUT) and the node Ns (transistor PMOS1).
  • the control signal EN is input to the gate of the transistor PMOS15.
  • the control signal ENB is input to the gate of the transistor PMOS16.
  • the transistors PMOS15 and NMOS16 have parasitic diodes D26 and D27 having the polarities shown in FIG. 8 by commonly connecting the back gate to the node Ns.
  • the switch drive circuit 23 operates as an inverter that uses the input voltage VIN as the power supply voltage when the transistor PMOS15 is on, while it outputs the output voltage VOUT when the transistor PMOS16 is on. It operates as an inverter that uses the power supply voltage.
  • the output node N3 of the inverter is connected to the gate of the transistor PMOS5. That is, in the configuration of FIG. 8, the function of the “first switch drive circuit” is realized by the switch drive circuit 23 among the plurality of switch drive circuits 23 and 12.
  • the transistors PMOS15 and PMOS16 form an example of a "voltage switching circuit”
  • the inverter formed by the transistors PMOS1 and NMOS1 forms an example of a "signal transmission circuit”.
  • the configuration of the other parts of the charge pump circuit 102 according to the first modification of the first embodiment is the same as that of the charge pump circuit 100 (FIG. 1) according to the comparative example, and therefore detailed description will not be repeated.
  • the transistors PMOS5 and PMOS6 forming the plurality of switch elements correspond to one embodiment of the "first P-type transistor", and the transistor PMOS17 constitutes the "back gate disconnection switch element”. This corresponds to an example of the “second P-type transistor”.
  • the switch drive circuits 23 and 30 and the transistor PMOS17 operate similarly to the switch drive circuits 21 and 30 and the transistor PMOS13 in FIG. 4 (charge pump circuit 101). Therefore, the behavior of the charge pump circuit 102 according to the first modification of the first embodiment in the operation stop state and the boost operation state is similar to that of the charge pump circuit 101 according to the first embodiment.
  • the transistor PMOS15 is turned on, while the transistor PMOS16 is turned off.
  • the input voltage VIN is supplied to the node Ns by the transistor PMOS15. Therefore, by fixing the clock signal CLK1 to the L level, the input voltage VIN can be output to the node N3, that is, the gate of the transistor PMOS5, via the transistor PMOS1. Accordingly, the transistor PMOS5 can be turned off by setting the gate to a high voltage with respect to the source connected to the node Np1 (output terminal 10).
  • the switch driving circuit 30 keeps the transistor PMOS17 off, the current path through the body (backgate) of the transistor PMOS5 is reverse voltage due to the parasitic diode D28 of the transistor PMOS17, which is a "backgate disconnection switch element". Blocked by blocking. Thereby, even if the transistor PMOS5 is turned on, the current path from the input terminal 5 to the output terminal 10 can be cut off.
  • the transistor PMOS17 is connected as the "back gate disconnection switch element" to the transistor PMOS5 of the plurality of switch elements, but like the first embodiment,
  • the current from the input terminal 5 to the output terminal 10 is cut off, the output terminal 10 is discharged, and the output voltage VOUT can be lowered to the ground voltage GND. ..
  • the clock signal CLK1 is changed from the L level to the H level in S100, and the clock signal CLK1 is changed from the H level to the L level in S120.
  • the output terminal 10 can be precharged by turning on the transistor PMOS5 without passing a current through the parasitic diodes D9 and D10.
  • the boosting operation similar to that of the charge pump circuits 100 and 101 can be executed according to the clock signals CLK1 to CLK4 (FIG. 2).
  • FIG. 9 is a circuit diagram illustrating the configuration of the charge pump circuit according to the second modification of the first embodiment.
  • the charge pump circuit 103 has the back gates of the transistors PMOS5 and PMOS6, which are switching elements, as compared with the charge pump circuit 100 according to the comparative example. Further provided are transistors PMOS13 and PMOS17 connected to each other, and a switch drive circuit 30 for controlling on/off of the transistors PMOS13 and PMOS17. Further, the charge pump circuit 103 includes the switch drive circuit 23 of FIG. 4 in place of the switch drive circuit 11 (FIG. 1) as compared with the charge pump circuit 100 of the comparative example, and the switch drive circuit 12 (FIG. 1). ), the switch drive circuit 21 of FIG. 8 is provided.
  • connection relationship between the transistors PMOS13 and PMOS6 is similar to that described in the first embodiment (FIGS. 4 and 5), and the connection relationship between the transistors PMOS17 and PMOS5 is the same as that in the first embodiment. This is similar to the modification (FIG. 8).
  • the configuration and operation of the switch drive circuit 30 are the same as those described with reference to FIGS. 4 and 8, and the transistors PMOS13 and PMOS17 are commonly turned on/off according to the voltage of the output node N5 of the switch drive circuit 30.
  • the switch drive circuit 21 controls the on/off of the transistor PMOS6 by the same configuration and operation as in FIG. Similarly, the switch drive circuit 23 controls ON/OFF of the transistor PMOS5 with the same configuration and operation as those in FIG.
  • each of the plurality of switch drive circuits 21 and 23 has a function of “first switch drive circuit”.
  • the precharge signal PR is the L level, that is, except during the precharge period
  • the transistor NMOS7 By discharging the output terminal 10 when turned on, the output voltage VOUT can be lowered to the ground voltage GND.
  • the switch drive circuits 21 and 23 turn off the transistors PMOS5 and PMOS6, and the reverse voltage blocking by the parasitic diodes D28 and D23 of the transistors PMOS17 and PMOS15, The current path from the input terminal 5 to the output terminal 10 can be cut off.
  • the clock signals CLK1 and CLK2 are changed from the L level to the H level in S100, and the clock signals CLK1 and CLK2 are changed from the H level to the L level in S120.
  • the boosting operation similar to that of the charge pump circuits 100 and 101 can be executed according to the clock signals CLK1 to CLK4 (FIG. 2).
  • Embodiment 2 In the first embodiment and the modifications thereof, the function of interrupting current from the input terminal 5 to the output terminal 10 in the operation stopped state in the charge pump circuit having the boost ratio (VOUT/VIN) of 2 has been described. The same overcurrent prevention function can be applied to different charge pump circuits. In the second embodiment, as an example, the addition of an overcurrent prevention function in a charge pump circuit having a boost ratio (VOUT/VIN) of 3 will be described.
  • FIG. 10 is a circuit diagram illustrating a configuration example of the charge pump circuit according to the second embodiment.
  • the charge pump circuit 105 according to the second embodiment is different from the charge pump circuit 101 (FIG. 4) according to the first embodiment in that the transistor PMOS18 as a switch element and the on/off state of the transistor PMOS18.
  • a switch drive circuit 25 for controlling the capacitor C2, a capacitor C2, an inverter 32, and inverter drive circuits 26 and 27 are further provided.
  • the transistor PMOS18 is connected between the node Np0 connected to the input terminal 5 and the transistor PMOS5. That is, in the configuration of FIG. 10, the transistors PMOS5, PMOS6, and PMPOS18, which are connected in series between the input terminal 5 and the output terminal 10, constitute the “first P-type transistor” that constitutes the “plurality of switch elements”. It corresponds to an embodiment of
  • a capacitor C2 is connected between the node N8 and a node Np3 corresponding to the connection point of the transistors PMOS5 and PMOS18.
  • the voltage of node N8 is controlled by inverter 32.
  • the switch driving circuit 25 has a P-type transistor PMOS 19 and an N-type transistor NMOS 12 which are connected in series between the node Np2 and the ground node Ng via a node N6.
  • the clock signal CLK5 is commonly input to the gates of the transistors PMOS19 and NMOS12.
  • the switch drive circuit 25 constitutes an inverter that receives the clock signal CLK5 as an input, using the output voltage VOUT and the ground voltage GND as power sources.
  • the transistors PMOS19 and NMOS12 have parasitic diodes D29 and D30 having the polarities shown in FIG. 10 by connecting their back gates to the node Np2 and the ground node Ng, respectively.
  • the inverter 32 has a P-type transistor PMOS22 and an N-type transistor NMOS14 which are connected in series via the node N8 between the node Np0 (input voltage VIN) and the ground node Ng (ground voltage GND).
  • the node N8 is connected to the node Np3 via the capacitor C2.
  • the gate of the transistor PMOS22 is connected to the output node of the inverter drive circuit 26 to which the clock signal CLK6 is input.
  • the gate of the transistor NMOS14 is connected to the output node of the inverter drive circuit 27 to which the clock signal CLK7 is input.
  • the transistors PMOS22 and NMOS14 have parasitic diodes D36 and D37 of the polarity shown in FIG. 12 by connecting their back gates to the node Np0 and the ground node Ng, respectively.
  • the inverter drive circuit 26 includes a P-type transistor PMOS20 and a P-type transistor PMOS20 connected in series between the node Np0 (input voltage VIN) and the ground node Ng (ground voltage GND) via an output node connected to the gate of the transistor PMOS22. It has an N-type transistor NMOS15.
  • the clock signal CLK6 is commonly input to the gates of the transistors PMOS20 and NMOS15.
  • the inverter drive circuit 27 is connected in series between the node Np0 (input voltage VIN) and the ground node Ng (ground voltage GND) via an output node connected to the gate of the transistor NMOS14, and is of a P type. It has a transistor PMOS 21 and an N-type transistor NMOS 13.
  • the clock signal CLK7 is commonly input to the gates of the transistors PMOS21 and NMOS13.
  • the inverter drive circuits 26 and 27 constitute an inverter that receives the clock signals CLK6 and CLK7 as inputs, using the input voltage VIN and the ground voltage GND as power supplies.
  • the transistors PMOS20 and NMOS15 have parasitic diodes D31 and D32 having the polarities shown in FIG. 12 by connecting their back gates to the node Np0 and the ground node Ng, respectively.
  • the transistors PMOS21 and NMOS13 have parasitic diodes D33 and D34 having the polarities shown in FIG. 12 by connecting their back gates to the node Np0 and the ground node Ng, respectively.
  • the configuration of the parts other than the above of charge pump circuit 105 according to the second embodiment is the same as that of charge pump circuit 101 according to the first embodiment, and therefore detailed description will not be repeated. That is, similar to FIG. 4, of the transistors PMOS5, PMOS6, and PMPOS18, which are a plurality of switch elements, the transistor PMOS6 becomes a “second P-type transistor” that constitutes a “back gate disconnection switch”. A corresponding transistor PMOS13 is arranged. Similar to the first embodiment, in the normal boosting operation, the transistor PMOS13 is turned off.
  • the charge pump circuit 105 in addition to the “voltage selection circuit” by the inverter drive circuits 13 and 14 and the inverter 20, an example of the “voltage selection circuit” is also provided by the inverter drive circuits 26 and 27 and the inverter 32. Composed. Further, the transistor NMOS7 constitutes an example of a "discharge element".
  • FIG. 11 is a waveform diagram of the clock signals CLK1 to CLK7 input to the charge pump circuit 105.
  • clock signals CLK1 to CLK4 are the same as those in FIG. 2, and clock signal CLK1 based on reference clock CLKa and clock signals CLK2 to CLK4 based on reference clock CLKb have opposite phases.
  • the clock signals CLK5 to CLK7 are added.
  • the clock signal CLK5 is in phase with the clock signals CLK2 to CLK4, and the clock signals CLK6 and CLK7 are in phase with the clock signal CLK1.
  • dead times are appropriately set for the clock signals CLK5 to CLK7.
  • FIG. 12 shows a chart for explaining the boosting operation of the charge pump circuit 105.
  • the charge pump circuit 105 alternately repeats the states X and Y shown in FIG. 12 according to the clock signals CLK1 to CLK7 based on the complementary reference clocks CLKa and CLKb.
  • reference clock CLKb (clock signals CLK2 to CLK5) is at H level
  • reference clock CLKa (clock signals CLK1, CLK6, CLK7) is at L level. Therefore, the switch drive circuits 21 and 25 output the L level voltage (ground voltage GND) to the nodes N4 and N6, while the switch drive circuit 11 outputs the H level voltage (output voltage VOUT) to the node N3. ..
  • the transistors PMOS18 and PMOS6 are turned on while the transistor PMOS5 is turned off.
  • the inverter 32 since the inverter drive circuits 26 and 27 output the H level voltage (input voltage VIN), the inverter 32 connects the node N8 to the ground node Ng (ground voltage GND) by turning on the transistor NMOS14. On the other hand, since the inverter drive circuits 13 and 14 output the L level voltage (input voltage VIN), the inverter 20 connects the node N2 to the node Np0 (input voltage VIN) by turning on the transistor PMOS7.
  • the node Np3 is connected to the input terminal 5 (input voltage VIN), but is disconnected from the output terminal 10 and the node Np1.
  • the switch drive circuits 21 and 25 output the H level (output voltage VOUT) to the nodes N4 and N6, while the switch drive circuit 11 outputs the L level voltage (ground voltage GND) to the node N3.
  • the transistors PMOS18 and PMOS6 are turned off while the transistor PMOS5 is turned on.
  • inverter drive circuits 26 and 27 output the L level voltage (ground voltage GND)
  • the inverter 32 connects the node N8 to the node Np0 (input voltage VIN) by turning on the transistor PMOS22.
  • inverter drive circuits 13 and 14 output the H level voltage (ground voltage GND)
  • inverter 20 connects node N2 to ground node Ng (ground voltage GND) by turning on transistor NMOS5.
  • the capacitor C1 is charged to the input voltage VIN, and the output voltage VOUT becomes the sum of the input voltage VIN and the voltage V(C2) of the capacitor C2 at that time.
  • the charge pump circuit 105 alternately repeats the above-described state X and state Y in accordance with the clock signals CLK1 to CLK7 based on the complementary reference clocks CLKa and CLKb, so that the input voltage VIN of 3 is obtained. It is possible to execute the boosting operation of outputting the doubled output voltage VOUT.
  • the precharge signal PR is at the L level, that is, other than the precharge period. Then, by turning on the transistor NMOS7, the output voltage VOUT can be lowered to the ground voltage GND.
  • the transistor PMOS12 is turned on, while the transistor PMOS11 is turned off.
  • the input voltage VIN is supplied to the node Ns by the transistor PMOS11. Therefore, by fixing the clock signal CLK2 to the L level, the input voltage VIN can be output to the node N4, that is, the gate of the transistor PMOS6, via the transistor PMOS2.
  • the transistor PMOS5 can be turned off as in the first embodiment.
  • the transistor PMOS13 is turned off by the switch driving circuit 30, the current path via the body (back gate) of the transistor PMOS5 is caused by the reverse voltage blocking by the parasitic diode D23 of the transistor PMOS13 which is the "back gate disconnection switch element". To be cut off. As a result, the current path from the input terminal 5 to the output terminal 10 can be cut off as in the first embodiment.
  • the output terminal 10 can be discharged to reduce the output voltage VOUT to the ground voltage GND.
  • a switch drive circuit configured to use the input voltage VIN as an inverter power supply when the output voltage VOUT drops (that is, a “first switch drive circuit”).
  • a transistor PMOS 13 in FIG. 12
  • switch drive circuit 30 switch drive circuit 30
  • the charge pump circuit having the boosting ratio of 3 has been described, but the first embodiment and its modification can be similarly applied to the charge pump circuit having the higher boosting ratio. is there.
  • the above-mentioned “first switch drive circuit” for at least one of the plurality of switch elements connected in series between the input terminal 5 and the output terminal 10, the above-mentioned “first switch drive circuit” and By disposing the "back gate disconnecting switch element”, the “back gate disconnecting switch driving circuit”, and the “discharge element”, it is possible to prevent the occurrence of overcurrent when the output voltage VOUT decreases due to a ground fault or the like. It is possible.
  • semiconductor device 200 includes power supply circuit 202, semiconductor circuit 210 including semiconductor element 215, and the charge pump circuit according to any of the first to fourth embodiments.
  • the semiconductor element 215 is typically composed of a transistor or a diode.
  • the power supply circuit 202 can generate a stable voltage VDD from the power supply voltage Vp supplied to the semiconductor device 200 from the outside.
  • the charge pump circuits 101 to 105 output the voltage VBB as the output voltage VOUT by performing the boosting operation using the voltage VDD from the power supply circuit 202 as the input voltage VIN.
  • the semiconductor element 215 can operate by receiving the boosted voltage VBB that is the output voltage of the charge pump circuits 101 to 105.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

Selon la présente invention, des premier et deuxième transistors (PMOS5, PMOS6) sont connectés en série entre une borne d'entrée (5) et une borne de sortie (10). Un troisième transistor (PMOS13) est connecté entre la grille arrière et la source du second transistor (PMOS6). La polarité d'une diode parasite (D23) du troisième transistor (PMOS13), qui est mis hors tension dans un état d'arrêt de fonctionnement du circuit de pompe de charge, est inversée par rapport à la polarité d'une diode parasite (D10) du deuxième transistor (PMOS6). Dans l'état d'arrêt de fonctionnement du tuyau de pompe de charge, un circuit d'attaque de commutateur (21) fournit une tension d'entrée (VIN) à la grille du troisième transistor (PMOS13), et un élément de décharge (7) est mis sous tension pour décharger la borne de sortie (10).
PCT/JP2018/048203 2018-12-27 2018-12-27 Circuit de pompe de charge et dispositif à semi-conducteurs WO2020136821A1 (fr)

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JP2020562061A JP7134255B2 (ja) 2018-12-27 2018-12-27 チャージポンプ回路及び半導体装置

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CN113541475A (zh) * 2021-07-19 2021-10-22 上海南芯半导体科技有限公司 一种Dickson开关电容电压转换器的驱动电路
CN113629995A (zh) * 2021-07-19 2021-11-09 上海南芯半导体科技有限公司 一种Dickson开关电容电压转换器的驱动电路

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JP2006067764A (ja) * 2004-08-30 2006-03-09 Sanyo Electric Co Ltd チャージポンプ回路
JP2007236079A (ja) * 2006-02-28 2007-09-13 Nec Corp チャージポンプ回路、移動通信端末、通信装置
JP2009117426A (ja) * 2007-11-01 2009-05-28 Sanyo Electric Co Ltd 電源回路及び携帯機器
JP2009183111A (ja) * 2008-01-31 2009-08-13 Panasonic Corp チャージポンプ回路およびそれを備える電子機器

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JP2003033006A (ja) * 2001-07-18 2003-01-31 Sanyo Electric Co Ltd チャージポンプ回路
JP2006067764A (ja) * 2004-08-30 2006-03-09 Sanyo Electric Co Ltd チャージポンプ回路
JP2007236079A (ja) * 2006-02-28 2007-09-13 Nec Corp チャージポンプ回路、移動通信端末、通信装置
JP2009117426A (ja) * 2007-11-01 2009-05-28 Sanyo Electric Co Ltd 電源回路及び携帯機器
JP2009183111A (ja) * 2008-01-31 2009-08-13 Panasonic Corp チャージポンプ回路およびそれを備える電子機器

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113541475A (zh) * 2021-07-19 2021-10-22 上海南芯半导体科技有限公司 一种Dickson开关电容电压转换器的驱动电路
CN113629995A (zh) * 2021-07-19 2021-11-09 上海南芯半导体科技有限公司 一种Dickson开关电容电压转换器的驱动电路
CN113541475B (zh) * 2021-07-19 2023-02-03 上海南芯半导体科技股份有限公司 一种Dickson开关电容电压转换器的驱动电路

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