WO2020133756A1 - Mems器件及其制造方法 - Google Patents

Mems器件及其制造方法 Download PDF

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Publication number
WO2020133756A1
WO2020133756A1 PCT/CN2019/079574 CN2019079574W WO2020133756A1 WO 2020133756 A1 WO2020133756 A1 WO 2020133756A1 CN 2019079574 W CN2019079574 W CN 2019079574W WO 2020133756 A1 WO2020133756 A1 WO 2020133756A1
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electrode
layer
forming
cmos circuit
transistor
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PCT/CN2019/079574
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English (en)
French (fr)
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孙伟
闻永祥
刘琛
葛俊山
马志坚
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杭州士兰集成电路有限公司
杭州士兰微电子股份有限公司
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Priority to US16/633,244 priority Critical patent/US11305985B2/en
Publication of WO2020133756A1 publication Critical patent/WO2020133756A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00047—Cavities
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0009—Structural features, others than packages, for protecting a device against environmental influences
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/0072—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks of microelectro-mechanical resonators or networks
    • H03H3/0073—Integration with other electronic structures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02007—Details of bulk acoustic wave devices
    • H03H9/02015—Characteristics of piezoelectric layers, e.g. cutting angles
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02007—Details of bulk acoustic wave devices
    • H03H9/02086—Means for compensation or elimination of undesirable effects
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
    • H03H9/0557—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement the other elements being buried in the substrate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/171—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator implemented with thin-film techniques, i.e. of the film bulk acoustic resonator [FBAR] type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/171—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator implemented with thin-film techniques, i.e. of the film bulk acoustic resonator [FBAR] type
    • H03H9/172—Means for mounting on a substrate, i.e. means constituting the material interface confining the waves to a volume
    • H03H9/173—Air-gaps
    • H—ELECTRICITY
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    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/074—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
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    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/704—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings
    • H10N30/706—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings characterised by the underlying bases, e.g. substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/802—Circuitry or processes for operating piezoelectric or electrostrictive devices not otherwise provided for, e.g. drive circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/87—Electrodes or interconnections, e.g. leads or terminals
    • H10N30/875—Further connection or lead arrangements, e.g. flexible wiring boards, terminal pins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/87—Electrodes or interconnections, e.g. leads or terminals
    • H10N30/877—Conductive materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/03—Static structures
    • B81B2203/0315—Cavities
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
    • B81C2203/0735—Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
    • B81C2203/0757—Topology for facilitating the monolithic integration
    • B81C2203/0771—Stacking the electronic processing unit and the micromechanical structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/021—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the air-gap type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/023—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the membrane type

Definitions

  • the present disclosure relates to the field of semiconductor technology, and more particularly, to a MEMS device and a method of manufacturing the same.
  • MEMS Micro-Electro-Mechanical System
  • IC Integrated Circuit
  • monolithic integration means that the MEMS structure and CMOS are fabricated on a single chip.
  • Hybrid integration is to manufacture MEMS and IC on different dies, and then encapsulate them in a package. Connect the MEMS bare chip with bumps to the IC chip by flip-chip welding or wire bonding to form a SIP .
  • Semi-hybrid is the use of three-dimensional integration technology to achieve three-dimensional integration of MEMS chips and CMOS.
  • Monolithic integration is an important development direction of MEMS and IC integration technology, especially for the RF RF thin film bulk acoustic wave filter has many advantages.
  • the processing circuit is close to the microstructure, which can achieve higher accuracy in signal detection and transmission;
  • the integrated system is reduced in size and power consumption is low; again, the number of devices is reduced, the number of package pins is reduced, and reliability is improved.
  • SIP system-in-package
  • the object of the present invention is to provide a MEMS device and a method for manufacturing the same, in which a cavity is formed by using a sacrificial layer and a through hole after forming a piezoelectric stack, ensuring that the shape of the cavity does not form a piezoelectric Deformed during stacking.
  • a method for manufacturing a MEMS device including: forming a CMOS circuit; and forming a MEMS module on the CMOS circuit, the CMOS circuit being connected to the MEMS module for driving The MEMS module, wherein the step of forming the MEMS module includes: forming a protective layer; forming a sacrificial layer in the protective layer; forming a first electrode on the protective layer and the sacrificial layer, and forming the An electrical connection between the first electrode and the CMOS circuit, the first electrode covering the sacrificial layer; forming a piezoelectric layer on the first electrode, the piezoelectric layer corresponding to the position of the sacrificial layer Forming a second electrode on the piezoelectric layer and forming an electrical connection between the second electrode and the CMOS circuit; forming a through hole on the first electrode or protective layer to the sacrificial layer ; And removing the sacrificial layer through the through hole to
  • the step of forming the sacrificial layer includes: forming an opening in the protective layer; filling the opening with a sacrificial material; and removing the sacrificial material outside the opening.
  • the sacrificial material includes phosphorosilicate glass.
  • the step of forming the sacrificial layer further includes forming a first contact hole and a second contact hole on the protective layer, the first electrode is electrically connected to the CMOS circuit through the first contact hole Connected, the second electrode is electrically connected to the CMOS circuit through the second contact hole.
  • the step of forming the first electrode includes: forming a first conductive layer on the protective layer and the sacrificial layer; and patterning the first conductive layer to form the first electrode, wherein A part of the first electrode is located in the first contact hole.
  • the step of forming the second electrode includes: forming a second conductive layer on the protective layer and the piezoelectric layer; and patterning the second conductive layer to form the second electrode, wherein, A part of the second electrode is located in the second contact hole.
  • the step of forming the cavity includes using a hydrofluoric acid vapor fumigation process to remove the sacrificial layer through the through hole.
  • the piezoelectric layer covers part of the first electrode and exposes the through hole.
  • the step of forming the CMOS circuit includes: forming a first transistor and a second transistor on the substrate; and sequentially forming a first dielectric layer and a first wiring layer on the first transistor and the second transistor , A second dielectric layer and a second wiring layer.
  • the step of the CMOS circuit further includes forming a plurality of first interconnect holes in the first dielectric layer; after forming the first wiring layer, the CMOS The step of the circuit further includes patterning the first wiring layer to form a plurality of first interconnect leads, the first interconnect leads contacting the first transistor or the second transistor through the first interconnect hole.
  • the step of the CMOS circuit further includes forming a plurality of second interconnect holes in the second dielectric layer; after forming the second wiring layer, the CMOS The step of the circuit further includes patterning the second wiring layer to form a plurality of second interconnect leads, one end of the second interconnect lead is connected to the first interconnect lead through the second interconnect hole, and the other end extends Into the first contact hole and the second contact hole.
  • the first transistor and the second transistor are connected through the first interconnect lead.
  • the protective layer has an etching ratio greater than that of silicon dioxide.
  • the material of the protective layer includes silicon nitride.
  • the thickness of the protective layer is greater than 2 ⁇ m.
  • the depth range of the cavity includes 1-1.5 ⁇ m.
  • the material of the first electrode and the second electrode includes molybdenum; the material of the piezoelectric layer includes aluminum nitride.
  • the thickness of the first electrode includes 0.5 to 0.8 ⁇ m; the thickness of the second electrode is less than or equal to 0.5 ⁇ m.
  • the MEMS device includes a thin film bulk acoustic wave filter.
  • a MEMS device including: a CMOS circuit; and a MEMS module located on the CMOS circuit, the CMOS circuit being connected to the MEMS module for driving the MEMS A module
  • the MEMS module includes: a protective layer on the CMOS circuit; a cavity in the protective layer; a first electrode on the protective layer and the cavity and the CMOS The circuit is electrically connected, the first electrode covers the cavity; the piezoelectric layer is located on the first electrode, the piezoelectric layer corresponds to the position of the cavity; the second electrode is located on the piezoelectric On the layer, electrically connected to the CMOS circuit; and a through hole, located on the protective layer or the first electrode, the through hole reaching the cavity, wherein the piezoelectric layer connects the through The hole is exposed.
  • the protective layer has a first contact hole and a second contact hole, a part of the first electrode is located in the first contact hole, the first electrode passes through the first contact hole and the The CMOS circuit is electrically connected, a part of the second electrode is located in the second contact hole, and the second electrode is electrically connected to the CMOS circuit through the second contact hole.
  • the CMOS circuit includes: a substrate; a first transistor and a second transistor on the substrate; a first dielectric layer on the first transistor and the second transistor; a plurality of first The interconnection leads are located on the first dielectric layer; the second dielectric layer is located on the plurality of first interconnection leads; and the plurality of second interconnection leads are located on the second dielectric layer.
  • the first dielectric layer has a plurality of first interconnect holes, and the first interconnect lead contacts the first transistor or the second transistor through the first interconnect hole; the second dielectric There are a plurality of second interconnect holes in the layer, one end of the second interconnect lead is connected to the first interconnect lead through the second interconnect hole, and the other end extends to the first contact hole and the second contact In the hole.
  • the first transistor and the second transistor are connected through the first interconnect lead.
  • the protective layer has an etching ratio greater than that of silicon dioxide.
  • the material of the protective layer includes silicon nitride.
  • the thickness of the protective layer is greater than 2 ⁇ m.
  • the depth range of the cavity includes 1-1.5 ⁇ m.
  • the material of the first electrode and the second electrode includes molybdenum; the material of the piezoelectric layer includes aluminum nitride.
  • the thickness of the first electrode includes 0.5 ⁇ m; the thickness of the second electrode is less than 0.5 ⁇ m.
  • the MEMS device is a thin film bulk acoustic wave filter.
  • MEMS modules are stacked on a CMOS circuit to form an integrated structure of a single-chip vertical CMOS circuit and a MEMS device, so there is no need to use eutectic bonding to connect different dies , Simplify the manufacturing process, thereby reducing manufacturing costs, reducing the total volume of the chip, which is more conducive to integration and lower power consumption, reducing packaging pins, thereby increasing the reliability of the device.
  • this manufacturing method by forming a sacrificial layer in the protective layer in advance, after forming the piezoelectric stack, the sacrificial layer is removed via the first electrode or the through hole on the protective layer to form a cavity, which ensures the shape of the cavity, Compared with the prior art, this manufacturing method does not affect the shape of the cavity when forming the piezoelectric stack.
  • the MEMS device is a thin film bulk acoustic wave filter. Since the distance between the COMS circuit and the filter is small, the accuracy of the filtered signal is further improved.
  • the MEMS device manufactured by this method has high sensitivity, and at the same time significantly reduces the manufacturing cost and improves the process compatibility.
  • FIG. 1 shows a schematic cross-sectional view of a MEMS device according to an embodiment of the invention.
  • FIG. 2 shows a schematic diagram of a method for manufacturing a MEMS device according to an embodiment of the invention.
  • FIG. 3 shows a schematic diagram of the manufacturing method of the CMOS circuit in FIG. 2.
  • FIG. 4 shows a schematic diagram of the manufacturing method of the MEMS module in FIG. 2.
  • 5A to 5J show schematic cross-sectional views of a part of stages in a method of manufacturing a MEMS device according to an embodiment of the present invention.
  • FIG. 1 shows a schematic cross-sectional view of a MEMS device according to an embodiment of the invention.
  • the MEMS device of the embodiment of the present invention includes: a CMOS circuit 10 and a MEMS module 20 located on the CMOS circuit 10, wherein the CMOS circuit 10 is connected to the MEMS module 20 and used to drive the MEMS module 20.
  • the present invention is implemented
  • the MEMS device of the example is preferably a thin film bulk acoustic wave filter.
  • the CMOS circuit 10 includes a substrate 100, a first well region 110, a first source/drain region 111, a first gate conductor 112, a first sidewall 113, a second well region 120, a second source/drain region 121, The second gate conductor 122, the second sidewall spacer 123, the field oxygen region 131, the gate oxide layer 132, the first dielectric layer 140, the plurality of first interconnecting leads 150, the second dielectric layer 160, and the plurality of second interconnecting leads 170 .
  • the MEMS module 20 includes a protective layer 210 having a first contact hole 211 and a second contact hole 212, a first electrode 230, a piezoelectric layer 240, a second electrode 250, and a cavity 260.
  • the first electrode 230 has a cavity 260
  • the through hole, the piezoelectric layer 240 covers part of the first electrode 230 and exposes the through hole.
  • the through hole may also be directly formed on the protective layer 210 and reach the cavity 260.
  • the first well region 110, the first source/drain region 111, the first gate conductor 112, and the first sidewall 113 constitute a first transistor
  • the second sidewall 123 constitutes a second transistor.
  • the first transistor and the second transistor are located on the substrate 100.
  • the embodiments of the present invention are not limited to this, and those skilled in the art may perform other operations on the number of transistors as needed. Settings.
  • the first dielectric layer 140 is located on the first transistor and the second transistor.
  • the first dielectric layer 140 has a plurality of first interconnect holes.
  • a plurality of first interconnect leads 150 are located on the first dielectric layer 140.
  • the first interconnect leads 150 pass through The first interconnect hole is in contact with the first transistor or the second transistor, and the first transistor and the second transistor are connected through the first interconnect lead 150.
  • the second dielectric layer 160 is located on the plurality of first interconnection leads 150.
  • the second dielectric layer 160 has a plurality of second interconnection holes.
  • the plurality of second interconnection leads 170 are located on the second dielectric layer 160. One end is connected to the first interconnect lead 150 through the second interconnect hole, and the other end extends into the first contact hole 211 and the second contact hole 212.
  • the protective layer 210 is located on the CMOS circuit 10, wherein the etching ratio of the protective layer 210 is greater than that of silicon dioxide.
  • the material of the protective layer 210 includes silicon nitride, and the thickness of the protective layer 210 is greater than 2 ⁇ m.
  • the cavity 260 is located in the protective layer 210, wherein the depth of the cavity 260 includes 1-1.5 ⁇ m.
  • the first electrode 230 is located on the protective layer 210 and the cavity 260 and covers the cavity 260.
  • the first electrode 230 is electrically connected to the CMOS circuit 10. Specifically, a part of the first electrode 230 is located in the first contact hole 211. 230 is connected to the second interconnection lead through the first contact hole to be electrically connected to the CMOS circuit 10.
  • the material of the first electrode 230 includes molybdenum, and the thickness includes 0.5 to 0.8 ⁇ m.
  • the piezoelectric layer 240 is located on the first electrode 230.
  • the piezoelectric layer 240 corresponds to the position of the cavity 260 and exposes the through hole.
  • the material of the piezoelectric layer 240 includes aluminum nitride.
  • the second electrode 250 is located on the piezoelectric layer 240 and is electrically connected to the CMOS circuit 10. Specifically, a part of the second electrode 250 is located in the second contact hole 212, and the second electrode 250 is connected to the second interconnection lead through the second contact hole Thus, it is electrically connected to the CMOS circuit 10, wherein the material of the second electrode 250 includes molybdenum, and the thickness of the second electrode 250 is less than 0.5 ⁇ m.
  • the first contact hole 211, the corresponding first interconnection lead 150, the corresponding second interconnection lead 170, and the first source/drain region 111 of the first transistor correspond in position in the vertical direction of the MEMS device.
  • the second contact hole 212, the corresponding first interconnection lead 150, the corresponding second interconnection lead 170, and the second source/drain region of the second transistor correspond in position in the vertical direction of the MEMS device.
  • the integrated structure of the CMOS circuit and the MEMS module in the vertical direction of a single chip is formed, so that it is not necessary to use eutectic bonding to connect different dies, which simplifies the manufacturing process and reduces the manufacturing cost.
  • FIG. 2 shows a schematic diagram of a method of manufacturing a MEMS device according to an embodiment of the present invention
  • FIG. 3 shows a schematic diagram of a method of manufacturing a CMOS circuit in FIG. 2
  • FIG. 4 shows a schematic diagram of a method of manufacturing a MEMS module in FIG. 2.
  • 5A to 5J show schematic cross-sectional views of a part of stages in the method for manufacturing a MEMS device according to an embodiment of the present invention.
  • CMOS circuit As shown in FIG. 2, in step S10, a CMOS circuit is formed, and as shown in FIG. 3, the CMOS circuit may be formed through the following steps S11 to S15.
  • a first transistor and a second transistor are formed on the substrate.
  • a first well region 110 and a second well region 120 are formed in the substrate 100, and are separated by silicon local oxidation (Local Oxidation of Silicon, LOCOS) technology forms a field oxygen region 131 between the first well region 110 and the second well region 120 on the substrate 100, a gate oxide layer 132 on the substrate 100, and a gate oxide layer on the substrate 100
  • Polysilicon is deposited on 132 to form a first gate conductor 112 and a second gate conductor 122 corresponding to the first well region 110 and the second well region 120 respectively.
  • the first well region 110 and the second well are lithographically and implanted.
  • a first source/drain region 111 and a second source/drain region 121 are respectively formed in the region 120, silicon dioxide is deposited on the first gate conductor 112 and the second gate conductor 122 and an anisotropic etching process is used
  • the side walls of the first gate conductor 112 and the second gate conductor 122 form a first sidewall 113 and a second sidewall 123, respectively, wherein the first well region 110, the first source/drain region 111, the first gate
  • the conductor 112 and the first sidewall 113 constitute a first transistor
  • the second well region 120, the second source/drain region 121, the second gate conductor 122, and the second sidewall 123 constitute a second transistor.
  • a first dielectric layer is formed on the first transistor and the second transistor, specifically, as shown in FIG. 5B, a first dielectric layer 140 is deposited on the first transistor and the second transistor, and the first A plurality of first interconnect holes 141 are formed on the dielectric layer 140, wherein the material of the first dielectric layer 140 includes borophosphosilicate glass.
  • step S13 a plurality of first interconnect wires are formed on the first dielectric layer, specifically, as shown in FIG. 5C, a first wiring layer is formed on the first dielectric layer 140, and the first wiring layer is patterned to form A plurality of first interconnecting leads 150, a part of the first interconnecting leads 150 is in contact with the first transistor through the first interconnecting hole, and another part of the first interconnecting leads 150 is in contact with the second transistor through the first interconnecting hole It is connected by the first interconnecting lead 150, wherein the material of the first interconnecting lead 150 includes aluminum.
  • a second dielectric layer is formed on the plurality of first interconnect leads, specifically, as shown in FIG. 5D, a second dielectric layer 160 is deposited on the plurality of first interconnect leads 150, and the second dielectric layer A plurality of second interconnect holes 161 are formed on the layer 160, wherein the material of the second dielectric layer 160 includes borophosphosilicate glass.
  • step S15 a plurality of second interconnecting leads are formed on the second dielectric layer.
  • a second wiring layer is formed on the second dielectric layer 160, and the second wiring layer is patterned to form A plurality of second interconnecting leads 170, a part of the second interconnecting leads 170 are in contact with the first interconnecting leads 150 through the second interconnecting holes to be connected to the first transistor, and another part of the second interconnecting leads 170 are connected to the first interconnecting leads through the second interconnecting holes
  • the 150 contact is connected to the second transistor, wherein the material of the second interconnection lead 170 includes aluminum.
  • step S20 a MEMS module is formed.
  • the MEMS module may be formed through the following steps S21 to S27.
  • a protective layer is formed. Specifically, as shown in FIG. 5F, a protective layer 210 is formed on the second dielectric layer 160 and the second interconnection lead 170, and a first contact hole 211 and a first contact hole are formed on the protective layer 210. Two contact holes 212, thereby exposing the second interconnection lead 170, that is, one end of the second interconnection lead 170 is connected to the first interconnection lead 150 through the second interconnection hole, and the other end extends into the first contact hole 211 and the second contact hole 212 Among them, the etching ratio of the protective layer 210 is greater than silicon dioxide, the material of the protective layer 210 includes silicon nitride, and the thickness of the protective layer 210 is greater than 2 ⁇ m.
  • a sacrificial layer is formed in the protective layer. Specifically, as shown in FIG. 5G, a dry etching process is used to form an opening in the protective layer 210.
  • the chemical vapor deposition method (Chemical Vapor Deposition, CVD) is used.
  • the sacrificial material is filled into the opening as the sacrificial layer 220, and the sacrificial material outside the opening is removed by a chemical mechanical polishing process, wherein the sacrificial material is preferably phosphorosilicate glass (PSG), and the thickness of the sacrificial layer 220 includes 1-1.5 ⁇ m.
  • PSG phosphorosilicate glass
  • a first electrode is formed in the protective layer and on the sacrificial layer.
  • a first conductive layer is formed on the protective layer 210 and the sacrificial layer 220 by sputtering, using light
  • the etching and etching processes pattern the first conductive layer to form the first electrode 230, wherein a part of the first electrode 230 is located in the first contact hole 211 to contact the second interconnecting lead 170 to be electrically connected to the first transistor, wherein
  • the first electrode 230 covers the sacrificial layer 220.
  • the material of the first electrode 230 is preferably molybdenum.
  • the thickness of the first electrode 230 is preferably 0.5 ⁇ m.
  • the sputtering temperature is less than 450°C.
  • a piezoelectric layer is formed on the first electrode. Specifically, as shown in FIG. 5I, a piezoelectric thin film material is sputtered on the first electrode 230, and the piezoelectric thin film is applied by photolithography and etching processes. The material is patterned to form a piezoelectric layer 240, and the position of the piezoelectric layer 240 corresponds to the sacrificial layer 220, wherein the material of the piezoelectric layer 240 is preferably aluminum nitride, and its thickness is determined by the frequency of the resonance unit.
  • a second electrode is formed on the piezoelectric layer.
  • a second conductive layer is formed on the protective layer 210 and the piezoelectric layer 240.
  • the second The two conductive layers are patterned to form a second electrode 250, wherein the second electrode 250 is separated from the first electrode 230 by the piezoelectric layer 240, and a part of the second electrode 250 is located in the second contact hole 212 to contact the second interconnection lead 170 Therefore, it is electrically connected to the second transistor, wherein the material of the second electrode 250 is preferably molybdenum, and the thickness of the second electrode 250 is less than 0.5 ⁇ m.
  • step S26 a through hole reaching the sacrificial layer is formed on the first electrode. Specifically, as shown in FIG. 5I, a through hole 231 reaching the sacrificial layer 220 is formed on the first electrode 230 using photolithography and etching processes .
  • step S27 the sacrificial layer is removed through the through hole to form a cavity.
  • a hydrofluoric acid vapor fumigation process is used to remove the sacrificial layer 220 through the through hole 231 to form the MEMS device shown in FIG.
  • the patterned first electrode 230 exposes a portion of the protective layer 210, avoiding the first electrode layer 230, the protective layer 210 is etched to form a through hole, and then the sacrificial layer 220 is removed through the through hole to form a cavity, Thus, the MEMS device shown in FIG. 1 is formed.
  • a MEMS module is stacked on a COMS circuit to form an integrated structure of a single-chip vertical CMOS circuit and a MEMS device, so there is no need to use eutectic bonding to connect different dies, simplifying the process
  • the manufacturing process reduces the manufacturing cost and the total chip volume, which is more conducive to integration and power consumption, and reduces the package pins, thereby increasing the reliability of the device.
  • this manufacturing method by forming a sacrificial layer in the protective layer in advance, after forming the piezoelectric stack, the sacrificial layer is removed via the first electrode or the through hole on the protective layer to form a cavity, which ensures the shape of the cavity, Compared with the prior art, this manufacturing method does not affect the shape of the cavity when forming the piezoelectric stack.
  • the MEMS device is a thin film bulk acoustic wave filter. Since the distance between the COMS circuit and the filter is small, the accuracy of the filtered signal is further improved.
  • the MEMS device manufactured by this method has high sensitivity, and at the same time significantly reduces the manufacturing cost and improves the process compatibility.

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Abstract

一种MEMS器件及一种MEMS器件制造方法，包括：形成CMOS电路（10）；以及在CMOS电路（10）上形成MEMS模块（20），CMOS电路（10）与MEMS模块（20）连接，用于驱动MEMS模块（20），其中，形成MEMS模块（20）的步骤包括：形成保护层（210）；在保护层（210）中形成牺牲层；在保护层（210）与牺牲层上形成第一电极（230），并形成第一电极（230）与CMOS电路（10）之间的电连接，第一电极（230）覆盖牺牲层；在第一电极（230）上形成压电层（240），压电层（240）与牺牲层的位置对应；在压电层（240）上形成第二电极（250），并形成第二电极（250）与CMOS电路（10）之间的电连接；在第一电极（230）上或保护层（210）形成到达牺牲层的通孔；以及经由通孔除去牺牲层形成空腔（260）。制造的MEMS器件灵敏度高同时又显著降低制造成本和改善工艺兼容性。

Description

MEMS器件及其制造方法
本申请要求了2018年12月29日提交的、申请号为201811641765.8、发明名称为“MEMS器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体技术领域，更具体地，涉及一种MEMS器件及其制造方法。
背景技术
微机械系统(Micro-Electro-Mechanical System,MEMS)与集成电路(integrated circuit,IC)目前是半导体产业最重要的两个发展领域。在全球科技迅速发展的推动下，MEMS与IC的集成成为一种必然趋势。其集成方法有三种：单片集成、半混合(键合)集成和混合集成。单片集成是指MEMS结构与CMOS制造在一个芯片上。混合集成是将MEMS和IC分别制造在不同的管芯上，然后封装在一个管壳中，将带凸点的MEMS裸片以倒装焊接形式或者引线键合方式与IC芯片相互连接，形成SIP。半混合是利用三维集成技术实现MEMS芯片和CMOS的立体集成。单片集成是MEMS与IC是集成技术的重要发展方向，尤其对于射频RF薄膜体声波滤波器而言有很多优点。首先，处理电路靠近微结构，对信号的检测、收发能够实现更高的精度；其次，集成系统体积减小，功耗低；再次，器件数量减少、封装管脚数降低，可靠性提高。
在现有的射频(Radio Frequency,RF)MEMS薄膜体声波滤波器制造技术中，大多采用系统级封装(system in a package,SIP)将滤波器、驱动电路以及处理电路合封在一起。SIP指在一个封装体内集成多个功能芯片，芯片之间通过衬底的引线键合进行连接。SIP的模块间互联很长、集成密度较低，对滤波器信号的传输不利，制造工艺繁琐且不利于集成。少数工艺采用二维平面结构将IC电路与薄膜体声波滤波器集成在同一平面的单芯片上，此种结构工艺繁琐且工艺灵活性差，特别是MEMS工艺受到CMOS器件的热开销限制。相对SIP合封，二维平面结构单芯片集成薄膜体声波滤波器与IC电路芯片面积减小，更加利于集成但工艺复杂。
发明内容
有鉴于此，本发明的目的是提供一种MEMS器件及其制造方法，其中，在形成压电叠层之后利用牺牲层与通孔形成空腔，保证了空腔的形状不会在形成压电叠层时变形。
根据本发明实施例的一方面，提供了一种MEMS器件的制造方法，包括：形成CMOS电路；以及在所述CMOS电路上形成MEMS模块，所述CMOS电路与所述MEMS模块连接，用于驱动所述MEMS模块，其中，形成所述MEMS模块的步骤包括：形成保护层；在所述保护层中形成牺牲层；在所述保护层与所述牺牲层上形成第一电极，并形成所述第一电极与所述CMOS电路之间的电连接，所述第一电极覆盖所述牺牲层；在所述第一电极上形成压电层，所述压电层与所述牺牲层的位置对应；在所述压电层上形成第二电极，并形成所述第二电极与所述CMOS电路之间的电连接；在所述第一电极或保护层上形成到达所述牺牲层的通孔；以及经由所述通孔除去所述牺牲层形成空腔。
优选地，形成所述牺牲层的步骤包括：在所述保护层中形成开口；将牺牲材料填充至所述开口；以及去除所述开口外部的所述牺牲材料。
优选地，所述牺牲材料包括磷硅玻璃。
优选地，在形成所述牺牲层的步骤之前，还包括在所述保护层上形成第一接触孔与第二接触孔，所述第一电极通过所述第一接触孔与所述CMOS电路电连接，所述第二电极通过所述第二接触孔与所述CMOS电路电连接。
优选地，形成所述第一电极的步骤包括：在所述保护层与所述牺牲层上形成第一导电层；以及将所述第一导电层图案化形成所述第一电极，其中，所述第一电极的一部分位于所述第一接触孔中。
优选地，形成所述第二电极的步骤包括：在所述保护层与所述压电层上形成第二导电层；以及将所述第二导电层图案化形成所述第二电极，其中，所述第二电极的一部分位于所述第二接触孔中。
优选地，形成所述空腔的步骤包括采用氢氟酸气相熏蒸工艺，经由所述通孔除去所述牺牲层。
优选地，所述压电层覆盖部分所述第一电极，并暴露所述通孔。
优选地，形成所述CMOS电路的步骤包括：在衬底上形成第一晶体管与第二晶体管；以及在所述第一晶体管与所述第二晶体管上依次形成第一介质层、第一布线层、第二介质层以及第二布线层。
优选地，在形成所述第一布线层之前，所述CMOS电路的步骤还包括在所述第一介质层中形成多个第一互联孔；在形成所述第一布线层之后，所述CMOS电路的步骤还包括将所述第一布线层图案化，形成多个第一互联引线，所述第一互联引线通过所述第一互联孔与所述第一晶体管或所述第二晶体管接触。
优选地，在形成所述第二布线层之前，所述CMOS电路的步骤还包括在所述第二介质层中形 成多个第二互联孔；在形成所述第二布线层之后，所述CMOS电路的步骤还包括将所述第二布线层图案化，形成多个第二互联引线，所述第二互联引线的一端通过所述第二互联孔与所述第一互联引线相连，另一端延伸至所述第一接触孔与所述第二接触孔中。
优选地，所述第一晶体管与所述第二晶体管通过所述第一互联引线相连。
优选地，所述保护层的刻蚀比大于二氧化硅。
优选地，所述保护层的材料包括氮化硅。
优选地，所述保护层的厚度大于2μm。
优选地，所述空腔的深度范围包括1-1.5μm。
优选地，所述第一电极与所述第二电极的材料包括钼；所述压电层的材料包括氮化铝。
优选地，所述第一电极的厚度包括0.5至0.8μm；所述第二电极的厚度小于或等于0.5μm。
优选地，所述MEMS器件包括薄膜体声波滤波器。
根据本发明实施例的另一方面，提供了一种MEMS器件，包括：CMOS电路；以及MEMS模块，位于所述CMOS电路上，所述CMOS电路与所述MEMS模块连接，用于驱动所述MEMS模块，其中，所述MEMS模块包括：保护层，位于所述CMOS电路上；空腔，位于所述保护层中；第一电极，位于所述保护层与所述空腔上，与所述CMOS电路电连接，所述第一电极覆盖所述空腔；压电层，位于所述第一电极上，所述压电层与所述空腔的位置对应；第二电极，位于所述压电层上，与所述CMOS电路电连接；以及通孔，位于所述保护层或所述第一电极上，所述通孔到达所述空腔中，其中，所述压电层将所述通孔暴露。
优选地，所述保护层上具有第一接触孔与第二接触孔，所述第一电极的一部分位于所述第一接触孔中，所述第一电极通过所述第一接触孔与所述CMOS电路电连接，所述第二电极的一部分位于所述第二接触孔中，所述第二电极通过所述第二接触孔与所述CMOS电路电连接。
优选地，所述CMOS电路包括：衬底；第一晶体管与第二晶体管，位于所述衬底上；第一介质层，位于所述第一晶体管与所述第二晶体管上；多条第一互联引线，位于所述第一介质层上；第二介质层，位于所述多条第一互联引线上；以及多条第二互联引线，位于所述第二介质层上。
优选地，所述第一介质层中具有多个第一互联孔，所述第一互联引线通过所述第一互联孔与所述第一晶体管或所述第二晶体管接触；所述第二介质层中具有多个第二互联孔，所述第二互联引线的一端通过所述第二互联孔与所述第一互联引线相连，另一端延伸至所述第一接触孔与所述第二接触孔中。
优选地，所述第一晶体管与所述第二晶体管通过所述第一互联引线相连。
优选地，所述保护层的刻蚀比大于二氧化硅。
优选地，所述保护层的材料包括氮化硅。
优选地，所述保护层的厚度大于2μm。
优选地，所述空腔的深度范围包括1-1.5μm。
优选地，所述第一电极与所述第二电极的材料包括钼；所述压电层的材料包括氮化铝。
优选地，所述第一电极的厚度包括0.5μm；所述第二电极的厚度小于0.5μm。
优选地，所述MEMS器件为薄膜体声波滤波器。
根据本发明实施例的MEMS器件及其制造方法，在COMS电路上堆叠MEMS模块，形成了单芯片垂直方向上的CMOS电路与MEMS器件的集成结构，因而无需采用共晶键合连接不同的管芯，简化了工艺制作流程，从而降低了制造成本，降低了芯片总体积，从而更利于集成且降低了功耗，减少了封装管脚，从而增加了器件的可靠性。在该制造方法中，通过在保护层中预先形成牺牲层，在形成压电叠层之后经由第一电极或保护层上的通孔去除牺牲层从而形成了空腔，保证了空腔的形状，与现有技术相比，该制造方法不会在形成压电叠层时影响空腔的形状。
在优选的实施例中，MEMS器件为薄膜体声波滤波器，由于COMS电路与滤波器之间的距离很小，进一步提高了滤波信号的精度。
该方法制造的MEMS器件灵敏度高，同时又显著降低制造成本和改善工艺兼容性。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1示出了本发明实施例的MEMS器件的截面示意图。
图2示出了本发明实施例的MEMS器件的制造方法示意图。
图3示出了图2中的CMOS电路的制造方法示意图。
图4示出了图2中的MEMS模块的制造方法示意图。
图5A至5J示出根据本发明实施例的MEMS器件的制造方法中一部分阶段的截面示意图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，可能未示出某些公知的部分。
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细 节来实现本发明。
本发明可以各种形式呈现，以下将描述其中一些示例。
图1示出了本发明实施例的MEMS器件的截面示意图。
如图1所示，本发明实施例的MEMS器件包括：CMOS电路10与位于CMOS电路10上的MEMS模块20，其中，CMOS电路10与MEMS模块20连接，并用于驱动MEMS模块20，本发明实施例的MEMS器件优选为薄膜体声波滤波器。CMOS电路10包括：衬底100、第一阱区110、第一源/漏区111、第一栅极导体112、第一侧墙113、第二阱区120、第二源/漏区121、第二栅极导体122、第二侧墙123、场氧区131、栅氧层132、第一介质层140、多个第一互联引线150、第二介质层160以及多个第二互联引线170。MEMS模块20包括：具有第一接触孔211与第二接触孔212的保护层210、第一电极230、压电层240、第二电极250以及空腔260，第一电极230具有到达空腔260的通孔，压电层240覆盖部分第一电极230，并暴露该通孔，在一些其他实施例中，通孔还可以直接形成在保护层210上，并到达空腔260。
第一阱区110、第一源/漏区111、第一栅极导体112、第一侧墙113构成第一晶体管，第二阱区120、第二源/漏区121、第二栅极导体122、第二侧墙123构成第二晶体管，第一晶体管与第二晶体管位于衬底100上，然而本发明的实施例并不限于此，本领域技术人员可根据需要对晶体管的个数进行其他设置。
第一介质层140位于第一晶体管与第二晶体管上，第一介质层140中具有多个第一互联孔，多条第一互联引线150位于第一介质层140上，第一互联引线150通过第一互联孔与第一晶体管或第二晶体管接触，第一晶体管与第二晶体管通过第一互联引线150相连。
第二介质层160位于多条第一互联引线150上，第二介质层160中具有多个第二互联孔，多条第二互联引线170位于第二介质层160上，第二互联引线170的一端通过第二互联孔与第一互联引线150相连，另一端延伸至第一接触孔211与第二接触孔212中。
保护层210位于CMOS电路10上，其中，保护层210的刻蚀比大于二氧化硅，在一些优选实施例中，保护层210的材料包括氮化硅，保护层210的厚度大于2μm。
空腔260位于保护层210中，其中，空腔260的深度范围包括1-1.5μm。
第一电极230位于保护层210与空腔260上并覆盖空腔260，第一电极230与CMOS电路10电连接，具体地，第一电极230的一部分位于第一接触孔211中，第一电极230通过第一接触孔与第二互联引线相连从而与CMOS电路10电连接。其中，第一电极230的材料包括钼，厚度包括0.5至0.8μm。
压电层240位于第一电极230上，压电层240与空腔260的位置对应并将通孔暴露，其中， 压电层240的材料包括氮化铝。
第二电极250位于压电层240上并与CMOS电路10电连接，具体地，第二电极250的一部分位于第二接触孔212中，第二电极250通过第二接触孔与第二互联引线相连从而与CMOS电路10电连接，其中，第二电极250的材料包括钼，第二电极250的厚度小于0.5μm。
在本实施例中，第一接触孔211、相应的第一互联引线150、相应的第二互联引线170以及第一晶体管的第一源/漏区111在MEMS器件的垂直方向上位置对应。第二接触孔212、相应的第一互联引线150、相应的第二互联引线170以及第二晶体管的第二源/漏区在MEMS器件的垂直方向上位置对应。形成了单芯片垂直方向上的CMOS电路与MEMS模块的集成结构，因而无需采用共晶键合连接不同的管芯，简化了工艺制作流程，从而降低了制造成本。
图2示出了本发明实施例的MEMS器件的制造方法示意图，图3示出了图2中的CMOS电路的制造方法示意图，图4示出了图2中的MEMS模块的制造方法示意图，图5A至5J示出根据本发明实施例的MEMS器件的制造方法中一部分阶段的截面示意图。在下文中，将会对本发明实施例的MEMS器件的制造方法进行详细说明。
如图2所示，在步骤S10中，形成CMOS电路，如图3所示，可以通过以下步骤S11至S15来形成CMOS电路。
在步骤S11中，在衬底上形成第一晶体管与第二晶体管，具体地，如图5A所示，在衬底100中形成第一阱区110与第二阱区120，利用硅局部氧化隔离(Local Oxidation of Silicon，LOCOS)技术在衬底100上形成位于第一阱区110与第二阱区120之间的场氧区131，在衬底100上形成栅氧层132，在栅氧层132上淀积多晶硅以对应第一阱区110与第二阱区120分别形成第一栅极导体112与第二栅极导体122，利用光刻与注入工艺在第一阱区110与第二阱区120中分别形成第一源/漏区111和第二源/漏区121，在第一栅极导体112与第二栅极导体122上淀积二氧化硅并利用各向异性刻蚀工艺在第一栅极导体112与第二栅极导体122的侧壁分别形成第一侧墙113与第二侧墙123，其中，第一阱区110、第一源/漏区111、第一栅极导体112、第一侧墙113构成第一晶体管，第二阱区120、第二源/漏区121、第二栅极导体122、第二侧墙123构成第二晶体管。
在步骤S12中，在第一晶体管与第二晶体管上形成第一介质层，具体地，如图5B所示，在第一晶体管与第二晶体管上淀积第一介质层140，并在第一介质层140上形成多个第一互联孔141，其中，第一介质层140的材料包括硼磷硅玻璃。
在步骤S13中，在第一介质层上形成多个第一互联引线，具体地，如图5C所示，在第一介质层140上形成第一布线层，将第一布线层图案化，形成多个第一互联引线150，一部分第一互联引线150通过第一互联孔与第一晶体管接触，另一部分第一互联引线150通过第一互联孔与第 二晶体管接触，第一晶体管与第二晶体管通过第一互联引线150相连，其中，第一互联引线150的材料包括铝。
在步骤S14中，在多个第一互联引线上形成第二介质层，具体地，如图5D所示，在多个第一互联引线150上淀积第二介质层160，并在第二介质层160上形成多个第二互联孔161，其中，第二介质层160的材料包括硼磷硅玻璃。
在步骤S15中，在第二介质层上形成多个第二互联引线，具体地，如图5E所示，在第二介质层160上形成第二布线层，将第二布线层图案化，形成多个第二互联引线170，一部分第二互联引线170通过第二互联孔与第一互联引线150接触从而与第一晶体管相连，另一部分第二互联引线170通过第二互联孔与第一互联引线150接触从而与第二晶体管相连，其中，第二互联引线170的材料包括铝。
如图2所示，在步骤S20中，形成MEMS模块，如图4所示，可以通过以下步骤S21至S27来形成MEMS模块。
在步骤S21中，形成保护层，具体地，如图5F所示，在第二介质层160与第二互联引线170上形成保护层210，并在保护层210上形成第一接触孔211与第二接触孔212，从而露出第二互联引线170，即第二互联引线170的一端通过第二互联孔与第一互联引线150相连，另一端延伸至第一接触孔211与第二接触孔212中，其中，保护层210的刻蚀比大于二氧化硅，保护层210的材料包括氮化硅，保护层210的厚度大于2μm。
在步骤S22中，在保护层中形成牺牲层，具体地，如图5G所示，采用干法刻蚀工艺，在保护层210中形成开口，利用化学气相沉积法(Chemical Vapor Deposition,CVD)将牺牲材料填充至开口中以作为牺牲层220，采用化学机械抛光工艺去除开口外部的牺牲材料，其中，牺牲材料优选为磷硅玻璃(PSG)，牺牲层220的厚度范围包括1-1.5μm。
在步骤S23中，在保护层中与牺牲层上形成第一电极，具体地，如图5H所示，通过溅射的方法，在保护层210与牺牲层220上形成第一导电层，采用光刻、刻蚀工艺，将第一导电层图案化形成第一电极230，其中，第一电极230的一部分位于第一接触孔211中与第二互联引线170接触从而与第一晶体管电连接，其中，第一电极230覆盖牺牲层220，第一电极230的材料优选为钼，第一电极230的厚度优选为0.5μm，为防止CMOS电路存在PN结扩散的问题，溅射温度小于450℃。
在步骤S24中，在第一电极上形成压电层，具体地，如图5I所示，在第一电极上230上溅射压电薄膜材料，采用光刻、刻蚀工艺，将压电薄膜材料图案化形成压电层240，压电层240的位置与牺牲层220对应，其中，压电层240的材料优选为氮化铝，其厚度由谐振单元的频率决定。
在步骤S25中，在压电层上形成第二电极，具体地，如图5I所示，在保护层210与压电层240上形成第二导电层，采用光刻、刻蚀工艺，将第二导电层图案化形成第二电极250，其中，第二电极250通过压电层240与第一电极230隔开，第二电极250的一部分位于第二接触孔212中与第二互联引线170接触从而与第二晶体管电连接，其中，第二电极250的材料优选为钼，第二电极250的厚度小于0.5μm。
在步骤S26中，在第一电极上形成到达牺牲层的通孔，具体地，如图5I所示，采用光刻、刻蚀工艺，在第一电极230上形成到达牺牲层220的通孔231。
在步骤S27中，经由通孔除去牺牲层形成空腔，具体地，如图5J所示，采用氢氟酸气相熏蒸工艺，经由通孔231除去牺牲层220形成如图1所示的MEMS器件。
在一些其他的实施例中，图案化的第一电极230暴露部分保护层210，避开第一电极层230，刻蚀保护层210形成通孔，再经由通孔除去牺牲层220形成空腔，从而形成如图1所示的MEMS器件。
根据本发明实施例的MEMS器件，在COMS电路上堆叠MEMS模块，形成了单芯片垂直方向上的CMOS电路与MEMS器件的集成结构，因而无需采用共晶键合连接不同的管芯，简化了工艺制作流程，从而降低了制造成本，降低了芯片总体积，从而更利于集成且降低了功耗，减少了封装管脚，从而增加了器件的可靠性。在该制造方法中，通过在保护层中预先形成牺牲层，在形成压电叠层之后经由第一电极或保护层上的通孔去除牺牲层从而形成了空腔，保证了空腔的形状，与现有技术相比，该制造方法不会在形成压电叠层时影响空腔的形状。
在优选的实施例中，MEMS器件为薄膜体声波滤波器，由于COMS电路与滤波器之间的距离很小，进一步提高了滤波信号的精度。
该方法制造的MEMS器件灵敏度高，同时又显著降低制造成本和改善工艺兼容性。
应当说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描 述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (31)

  1. 一种MEMS器件的制造方法，包括：
    形成CMOS电路；以及
    在所述CMOS电路上形成MEMS模块，所述CMOS电路与所述MEMS模块连接，用于驱动所述MEMS模块，
    其中，形成所述MEMS模块的步骤包括：
    形成保护层；
    在所述保护层中形成牺牲层；
    在所述保护层与所述牺牲层上形成第一电极，并形成所述第一电极与所述CMOS电路之间的电连接，所述第一电极覆盖所述牺牲层；
    在所述第一电极上形成压电层，所述压电层与所述牺牲层的位置对应；
    在所述压电层上形成第二电极，并形成所述第二电极与所述CMOS电路之间的电连接；
    在所述第一电极或保护层上形成到达所述牺牲层的通孔；以及
    经由所述通孔除去所述牺牲层形成空腔。
  2. 根据权利要求1所述的制造方法，其中，形成所述牺牲层的步骤包括：
    在所述保护层中形成开口；
    将牺牲材料填充至所述开口；以及
    去除所述开口外部的所述牺牲材料。
  3. 根据权利要求2所述的制造方法，其中，所述牺牲材料包括磷硅玻璃。
  4. 根据权利要求1所述的制造方法，在形成所述牺牲层的步骤之前，还包括在所述保护层上形成第一接触孔与第二接触孔，
    所述第一电极通过所述第一接触孔与所述CMOS电路电连接，所述第二电极通过所述第二接触孔与所述CMOS电路电连接。
  5. 根据权利要求4所述的制造方法，其中，形成所述第一电极的步骤包括：
    在所述保护层与所述牺牲层上形成第一导电层；以及
    将所述第一导电层图案化形成所述第一电极，
    其中，所述第一电极的一部分位于所述第一接触孔中。
  6. 根据权利要求5所述的制造方法，其中，形成所述第二电极的步骤包括：
    在所述保护层与所述压电层上形成第二导电层；以及
    将所述第二导电层图案化形成所述第二电极，
    其中，所述第二电极的一部分位于所述第二接触孔中。
  7. 根据权利要求1所述的制造方法，其中，形成所述空腔的步骤包括采用氢氟酸气相熏蒸工艺，经由所述通孔除去所述牺牲层。
  8. 根据权利要求7所述的制造方法，其中，所述压电层覆盖部分所述第一电极，并暴露所述通孔。
  9. 根据权利要求6所述的制造方法，其中，形成所述CMOS电路的步骤包括：
    在衬底上形成第一晶体管与第二晶体管；以及
    在所述第一晶体管与所述第二晶体管上依次形成第一介质层、第一布线层、第二介质层以及第二布线层。
  10. 根据权利要求9所述的制造方法，其中，在形成所述第一布线层之前，所述CMOS电路的步骤还包括在所述第一介质层中形成多个第一互联孔；
    在形成所述第一布线层之后，所述CMOS电路的步骤还包括将所述第一布线层图案化，形成多个第一互联引线，所述第一互联引线通过所述第一互联孔与所述第一晶体管或所述第二晶体管接触。
  11. 根据权利要求10所述的制造方法，其中，在形成所述第二布线层之前，所述CMOS电路的步骤还包括在所述第二介质层中形成多个第二互联孔；
    在形成所述第二布线层之后，所述CMOS电路的步骤还包括将所述第二布线层图案化，形成多个第二互联引线，所述第二互联引线的一端通过所述第二互联孔与所述第一互联引线相连，另一端延伸至所述第一接触孔与所述第二接触孔中。
  12. 根据权利要求10所述的制造方法，其中，所述第一晶体管与所述第二晶体管通过所述第一互联引线相连。
  13. 根据权利要求1至12任一所述的制造方法，其中，所述保护层的刻蚀比大于二氧化硅。
  14. 根据权利要求1至12任一所述的制造方法，其中，所述保护层的材料包括氮化硅。
  15. 根据权利要求1至12任一所述的制造方法，其中，所述保护层的厚度大于2μm。
  16. 根据权利要求1至12任一所述的制造方法，其中，所述空腔的深度范围包括1-1.5μm。
  17. 根据权利要求1至12任一所述的制造方法，其中，所述第一电极与所述第二电极的材料包括钼；
    所述压电层的材料包括氮化铝。
  18. 根据权利要求1至12任一所述的制造方法，其中，所述第一电极的厚度包括0.5至0.8μm；
    所述第二电极的厚度小于或等于0.5μm。
  19. 根据权利要求1至12任一所述的制造方法，其中，所述MEMS器件包括薄膜体声波滤波器。
  20. 一种MEMS器件，包括：
    CMOS电路；以及
    MEMS模块，位于所述CMOS电路上，所述CMOS电路与所述MEMS模块连接，用于驱动所述MEMS模块，
    其中，所述MEMS模块包括：
    保护层，位于所述CMOS电路上；
    空腔，位于所述保护层中；
    第一电极，位于所述保护层与所述空腔上，与所述CMOS电路电连接，所述第一电极覆盖所述空腔；
    压电层，位于所述第一电极上，所述压电层与所述空腔的位置对应；
    第二电极，位于所述压电层上，与所述CMOS电路电连接；以及
    通孔，位于所述保护层或所述第一电极上，所述通孔到达所述空腔中，
    其中，所述压电层将所述通孔暴露。
  21. 根据权利要求20所述的MEMS器件，其中，所述保护层上具有第一接触孔与第二接触孔，
    所述第一电极的一部分位于所述第一接触孔中，所述第一电极通过所述第一接触孔与所述CMOS电路电连接，
    所述第二电极的一部分位于所述第二接触孔中，所述第二电极通过所述第二接触孔与所述CMOS电路电连接。
  22. 根据权利要求21所述的MEMS器件，其中，所述CMOS电路包括：
    衬底；
    第一晶体管与第二晶体管，位于所述衬底上；
    第一介质层，位于所述第一晶体管与所述第二晶体管上；
    多条第一互联引线，位于所述第一介质层上；
    第二介质层，位于所述多条第一互联引线上；以及
    多条第二互联引线，位于所述第二介质层上。
  23. 根据权利要求22所述的MEMS器件，其中，所述第一介质层中具有多个第一互联孔， 所述第一互联引线通过所述第一互联孔与所述第一晶体管或所述第二晶体管接触；
    所述第二介质层中具有多个第二互联孔，所述第二互联引线的一端通过所述第二互联孔与所述第一互联引线相连，另一端延伸至所述第一接触孔与所述第二接触孔中。
  24. 根据权利要求23所述的MEMS器件，其中，所述第一晶体管与所述第二晶体管通过所述第一互联引线相连。
  25. 根据权利要求20至24任一所述的MEMS器件，其中，所述保护层的刻蚀比大于二氧化硅。
  26. 根据权利要求20至24任一所述的MEMS器件，其中，所述保护层的材料包括氮化硅。
  27. 根据权利要求20至24任一所述的MEMS器件，其中，所述保护层的厚度大于2μm。
  28. 根据权利要求20至24任一所述的MEMS器件，其中，所述空腔的深度范围包括1-1.5μm。
  29. 根据权利要求20至24任一所述的MEMS器件，其中，所述第一电极与所述第二电极的材料包括钼；
    所述压电层的材料包括氮化铝。
  30. 根据权利要求20至24任一所述的MEMS器件，其中，所述第一电极的厚度包括0.5μm；
    所述第二电极的厚度小于0.5μm。
  31. 根据权利要求20至24任一所述的MEMS器件，其中，所述MEMS器件为薄膜体声波滤波器。
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