WO2020134601A1 - 晶体谐振器与控制电路的集成结构及其集成方法 - Google Patents

晶体谐振器与控制电路的集成结构及其集成方法 Download PDF

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Publication number
WO2020134601A1
WO2020134601A1 PCT/CN2019/115651 CN2019115651W WO2020134601A1 WO 2020134601 A1 WO2020134601 A1 WO 2020134601A1 CN 2019115651 W CN2019115651 W CN 2019115651W WO 2020134601 A1 WO2020134601 A1 WO 2020134601A1
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device wafer
control circuit
crystal resonator
wafer
piezoelectric
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PCT/CN2019/115651
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English (en)
French (fr)
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秦晓珊
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中芯集成电路（宁波）有限公司上海分公司
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Priority to JP2021526613A priority Critical patent/JP7128559B2/ja
Priority to US17/419,660 priority patent/US20220077232A1/en
Publication of WO2020134601A1 publication Critical patent/WO2020134601A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N39/00—Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/205—Constructional features of resonators consisting of piezoelectric or electrostrictive material having multiple resonators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
    • H03H9/0557—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement the other elements being buried in the substrate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H03H9/1014—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H03H9/1042—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a housing formed by a cavity in a resin
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/19—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator consisting of quartz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/06—Forming electrodes or interconnections, e.g. leads or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/87—Electrodes or interconnections, e.g. leads or terminals
    • H10N30/875—Further connection or lead arrangements, e.g. flexible wiring boards, terminal pins
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/021—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the air-gap type

Definitions

  • the invention relates to the technical field of semiconductors, in particular to an integrated structure of a crystal resonator and a control circuit and an integrated method thereof.
  • the crystal resonator is a resonant device made by using the inverse piezoelectric effect of piezoelectric crystals. It is a key component of crystal oscillators and filters. It is widely used in high-frequency electronic signals to achieve accurate timing, frequency standards and filtering. An essential frequency control function in the signal processing system.
  • the size of various components also tends to be miniaturized.
  • the current crystal resonator is not only difficult to integrate with other semiconductor components, but also the size of the crystal resonator is large.
  • crystal resonators include surface mount crystal resonators, which specifically bond the base and the upper cover together by metal welding (or, adhesive glue) to form a closed cavity, crystal resonator
  • the piezoelectric resonant plate is located in the closed chamber, and the electrodes of the piezoelectric resonant plate are electrically connected to corresponding circuits through pads or leads.
  • the formed crystal resonator also needs to be electrically connected to the corresponding integrated circuit by soldering or bonding, thereby further limiting the crystal resonance The size of the device.
  • An object of the present invention is to provide an integrated method of a crystal resonator and a control circuit to solve the problem that the existing crystal resonator is large in size and not easy to integrate.
  • the present invention provides an integrated structure of a crystal resonator and a control circuit, including:
  • a piezoelectric resonance sheet including an upper electrode, a piezoelectric wafer and a lower electrode on the front surface of the device wafer, the piezoelectric resonance sheet being located above the lower cavity, and forming a first connection structure, the The upper electrode and the lower electrode of the piezoelectric resonator plate are electrically connected to the control circuit through the first connection structure;
  • a capping layer is formed on the front surface of the device wafer, the capping layer covers the piezoelectric resonator plate, and surrounds the crystal resonator with the piezoelectric resonator plate and the device wafer Upper cavity
  • a semiconductor chip is bonded on the back surface of the device wafer, and a second connection structure is formed, and the semiconductor chip is electrically connected to the control circuit through the second connection structure.
  • Another object of the present invention is to provide an integrated structure of a crystal resonator and a control circuit, including:
  • a piezoelectric resonance plate includes an upper electrode, a piezoelectric wafer and a lower electrode, the piezoelectric resonance plate is formed on the front surface of the device wafer and corresponds to the lower cavity;
  • a first connection structure for electrically connecting the upper electrode and the lower electrode of the piezoelectric resonator plate to the control circuit
  • a capping layer is formed on the front surface of the device wafer and covers the piezoelectric resonance sheet, and the capping layer also forms an upper cavity with the piezoelectric resonance sheet and the device wafer;
  • a semiconductor chip bonded on the back of the device wafer.
  • the second connection structure is for electrically connecting the semiconductor chip to the control circuit.
  • a lower cavity is formed in a device wafer on which a control circuit is formed by a semiconductor planar process, and a piezoelectric resonator plate is formed on the front surface of the device wafer, and further A capping layer is formed using a semiconductor planar process to cap the piezoelectric resonator plate in the upper cavity, so that the control circuit and the crystal resonator can be integrated on the same device wafer.
  • the semiconductor chip can be further integrated on the back of the device wafer, which greatly improves the integration of the crystal resonator and can realize the on-chip modulation of the parameters of the crystal resonator (for example, the temperature drift and frequency correction of the crystal resonator Equal to the original deviation), is conducive to improving the performance of the crystal resonator.
  • the crystal resonator provided by the present invention not only enables the crystal resonator to be integrated with other semiconductor devices, but also improves the integration of the device; and, compared with traditional crystal resonators (for example, surface mount crystal resonators) ), the size of the crystal resonator provided by the present invention is smaller, which is beneficial to realize the miniaturization of the crystal resonator, and can reduce the manufacturing cost and reduce the power consumption of the crystal resonator.
  • FIG. 1 is a schematic flowchart of an integrated method of a crystal resonator in an embodiment of the invention
  • FIGS. 2a to 2m are schematic structural views of an integrated method of a crystal resonator in an embodiment of the present invention during its preparation process.
  • the core idea of the present invention is to provide an integrated structure of a crystal resonator and a control circuit and a shape integration method thereof. Both the crystal resonator and the semiconductor chip are integrated on a device wafer formed with a control circuit through a semiconductor planar process. On the one hand, the device size of the formed crystal resonator can be further reduced, and on the other hand, the crystal resonator can be integrated with other semiconductor components to improve the integration of the device.
  • FIG. 1 is a schematic flowchart of an integrated method of a crystal resonator in an embodiment of the present invention
  • FIGS. 2a to 2k are schematic structural views of an integrated method of a crystal resonator in an embodiment of the present invention during its preparation process. The steps of forming a crystal resonator in this embodiment will be described in detail below with reference to the drawings.
  • step S100 referring specifically to FIG. 2a, a device wafer 100 is provided, in which a control circuit 110 is formed.
  • the device wafer 100 has a front surface 100U and a back surface 100D opposite to each other.
  • the control circuit 110 includes a plurality of interconnect structures, and at least part of the interconnect structures extend to the front surface of the device wafer.
  • the control circuit 110 can be used to apply an electrical signal to a piezoelectric resonator plate formed later, for example.
  • multiple crystal resonators can be prepared on the same device wafer 100 at the same time, so a plurality of device areas AA are correspondingly defined on the device wafer 100, and the control circuit 110 is formed in the device area AA.
  • control circuit 110 includes a first circuit 111 and a second circuit 112, and the first circuit 111 and the second circuit 112 are used to be electrically connected to the upper electrode and the lower electrode of the piezoelectric resonator plate formed later .
  • the first circuit 111 includes a first transistor, a first interconnect structure 111a and a third interconnect structure 111b, the first transistor is buried in the device wafer 100, the first An interconnect structure 111a and a third interconnect structure 111b are both connected to the first transistor and extend to the front surface of the device wafer 100.
  • the first interconnect structure 111a is connected to the drain of the first transistor, for example, and the second interconnect structure 111b is connected to the source of the first transistor, for example.
  • the second circuit 112 includes a second transistor, a second interconnect structure 112a and a fourth interconnect structure 112b, the second transistor is buried in the device wafer 100, the second interconnect structure Both 112a and the fourth interconnect structure 112b are connected to the second transistor and extend to the front surface of the device wafer 100.
  • the second interconnect structure 112a is connected to the drain of the second transistor, for example, and the four interconnect structure 112b is connected to the source of the second transistor, for example.
  • the device wafer 100 includes a base wafer 100A and a dielectric layer 100B formed on the base wafer 100A. And, both the first transistor and the second transistor are formed on the base wafer 100A, the dielectric layer 100B covers the first transistor and the second transistor, the third interconnect structure 111b, The first interconnect structure 111a, the second interconnect structure 112a, and the fourth interconnect structure 112b are all formed in the dielectric layer 100B and extend to the dielectric layer 100B away from the base wafer surface.
  • the base wafer 100A may be a silicon wafer or a silicon-on-insulator (SOI).
  • SOI silicon-on-insulator
  • the base wafer may specifically include an underlayer, a buried oxide layer, and a top silicon layer stacked in sequence from the back surface 100D to the front surface 100U.
  • step S200 specifically referring to FIG. 2b, the device wafer 100 is etched from the front surface of the device wafer 100 to form the lower cavity 120 of the crystal resonator. Specifically, the lower cavity 120 is exposed from the front surface 100U of the device wafer.
  • the lower cavity 120 is used, for example, to provide a vibration space for a piezoelectric resonator formed later.
  • the lower cavity 120 is formed in the dielectric layer 100B of the device wafer, and the lower cavity 120 is formed in each of the device regions AA. That is, the method of forming the lower cavity 120 includes: etching the dielectric layer 100B to the base wafer 100A to form the lower cavity 120 in the dielectric layer 100B.
  • the depth of the lower cavity 120 can be adjusted according to actual needs, which is not limited here.
  • the lower cavity 120 may be formed only in the dielectric layer 100B, or the lower cavity 120 may be further extended from the dielectric layer 100B to the base wafer 100A and the like.
  • the base wafer 100A may also be a silicon-on-insulator wafer.
  • the base wafer 100A when the lower cavity is formed, a top silicon layer may be further etched to extend the lower cavity from the dielectric layer to the buried layer Oxide layer.
  • a piezoelectric resonance sheet 200 including an upper electrode 230, a piezoelectric wafer 220, and a lower electrode 210 is formed on the front surface of the device wafer 100, wherein the piezoelectric
  • the upper electrode 230 and the lower electrode 210 are electrically connected to the control circuit through the first connection structure.
  • the lower electrode 210 is electrically connected to the first circuit 111 (specifically, the lower electrode 210 is electrically connected to the first interconnect structure 111a), and the upper electrode 230 is electrically connected to the second circuit 112 (specifically, (The upper electrode 230 is electrically connected to the second interconnect structure 112a).
  • an electrical signal can be transmitted to the piezoelectric resonator plate 200 through the control circuit 110 to generate an electric field in the piezoelectric resonator plate 200, so that the piezoelectric resonator plate 200 follows the magnitude of the electric field A corresponding degree of mechanical deformation occurs.
  • the deformation direction of the piezoelectric resonator plate 200 also changes accordingly. Therefore, when alternating current is applied to the piezoelectric resonator plate 200 by the control circuit 120, the deformation direction of the piezoelectric resonator plate 200 alternately changes in contraction or expansion with the plus or minus of the electric field, thereby generating mechanical vibration.
  • the method for forming the piezoelectric resonance plate 200 includes the following steps, for example.
  • a lower electrode 210 is formed on the set position of the front surface 100U of the device wafer 100.
  • the lower electrode 210 surrounds the periphery of the lower cavity 120 and is electrically connected to the first interconnect structure 111 a of the first circuit 111.
  • the lower electrode 210 can be electrically connected to the first transistor through the first interconnect structure 111a, so that the first transistor can be used to control the electrical signal to be applied to the lower electrode 210.
  • the lower electrode 210 covers the first interconnect structure 111a, and further makes the lower electrode 210 not cover the third interconnect structure 111b. And, the lower electrode 210 also does not cover the fourth interconnect structure 112b and the second interconnect structure 112a.
  • the material of the lower electrode 210 is silver, for example.
  • the lower electrode 210 may be formed sequentially using a thin film deposition process, a photolithography process, and an etching process; or, the lower electrode 210 may also be formed using an evaporation process.
  • Step two bonding the piezoelectric wafer 220 to the lower electrode 210, the piezoelectric wafer 220 being located above the lower cavity 120.
  • the edge of the piezoelectric wafer 220 overlaps the side wall of the lower cavity 120 and is located on the lower electrode 210, wherein the piezoelectric wafer 220 may be a quartz wafer, for example.
  • an upper electrode 230 is formed on the piezoelectric wafer 220. Similar to the lower electrode 210, the upper electrode 230 may also be formed by a vapor deposition process or a thin film deposition process, and its material is silver, for example.
  • the lower electrode 210, the piezoelectric wafer 220, and the upper electrode 230 are sequentially formed on the device wafer 100 by a semiconductor process.
  • the upper electrode and the lower electrode may be formed on both sides of the piezoelectric wafer, respectively, and the three are bonded to the device wafer as a whole.
  • the upper electrode 230 and the lower electrode 210 are electrically connected to the second interconnect structure 112a and the first interconnect structure 111a through the first connection structure, respectively.
  • the first connection structure includes a first connection member and a second connection member, wherein the first connection member connects the first interconnection structure 111a and the lower electrode 210 of the piezoelectric resonator plate, the The second connector connects the second interconnection structure 112a and the upper electrode 230 of the piezoelectric resonator plate.
  • the lower electrode 210 is located on the front surface of the device wafer 100 and below the piezoelectric wafer 220, and extends from the piezoelectric wafer 220 to make the lower electrode 210 Cover the first interconnect structure 111a. Therefore, it can be considered that a portion of the lower electrode 210 extending from the piezoelectric wafer constitutes the first connection member.
  • a first connector before forming the lower electrode, may be formed on the device wafer 100, and the first connector may be electrically connected to the first interconnect structure . And, after forming the lower electrode, the first connector is electrically connected to the lower electrode 210.
  • the first connection member includes, for example, a rewiring layer, the rewiring layer is connected to the first interconnect structure, and after the lower electrode is formed on the device wafer, the rewiring layer That is, it is electrically connected to the lower electrode 210.
  • the second connection member is formed after the upper electrode 230 is formed, so as to realize the electrical connection between the upper electrode 230 and the second interconnection structure 112a.
  • the second connection member may be composed of an interconnection line and a conductive plug (for example, a third conductive plug), the bottom of the third conductive plug is connected to the second interconnection structure 112a, the The top of the third conductive plug is connected to one end of the interconnection line, and the other end of the interconnection line at least partially covers the upper electrode 230 to be connected to the upper electrode 230.
  • the method for forming the second connector includes:
  • a plastic encapsulation layer 300 is formed on the front surface of the device wafer 100; wherein, the plastic encapsulation layer 300 covers the piezoelectric wafer 220 and exposes the upper electrode 230, the plastic encapsulation
  • the material of the layer 300 includes, for example, polyimide;
  • a through hole 300a is formed in the plastic encapsulation layer 300, and the through hole 300a penetrates the plastic encapsulation layer 300 to expose the second interconnect structure 112a;
  • the through hole 300a is filled with a conductive material to form a conductive plug (for example, a third conductive plug 310), the bottom of the third conductive plug 310 and the second
  • the interconnection structure 112a is electrically connected, and the top of the third conductive plug 310 is exposed to the plastic encapsulation layer 300;
  • an interconnection line 320 is formed on the plastic encapsulation layer 300, and the plastic encapsulation layer is removed.
  • one end of the interconnection line 320 is connected to the upper electrode 230, and the other end of the interconnection line 320 is electrically connected to the third conductive plug 310, so that the upper electrode 230 passes through the
  • the interconnection line 320 and the third conductive plug 310 are connected to the second interconnection structure 112 a of the second circuit 112.
  • the upper electrode is formed on the piezoelectric wafer and further extends from the piezoelectric wafer to form an upper electrode extension.
  • the third conductive plug can be located at the Below the upper electrode extension, and connect the bottom of the third conductive plug of the second connector to the second interconnect structure, and connect the top of the third conductive plug of the second connector to The upper electrode extension and supports the upper electrode extension.
  • the third conductive plug of the second connection member may be formed before the upper electrode is formed.
  • the method for forming the third conductive plug of the upper electrode and the second connector includes:
  • a plastic encapsulation layer is formed on the device wafer 100; in this embodiment, the plastic encapsulation layer covers the device wafer 100 and exposes the piezoelectric wafer 220;
  • a through hole is formed in the plastic encapsulation layer, and a conductive material is filled in the through hole to form a third conductive plug, and the third conductive plug is electrically connected to the second interconnection structure 112a;
  • an upper electrode is formed on the piezoelectric wafer 220, the upper electrode at least partially covers the piezoelectric wafer 220, and extends from the piezoelectric wafer 220 to the plastic encapsulation layer to cover the third A conductive plug, so that the upper electrode is electrically connected to the second interconnection structure 112a through the third conductive plug.
  • a capping layer 420 is formed on the front surface of the device wafer 100, and the capping layer 420 covers the piezoelectric resonant sheet 200 and The piezoelectric resonator 200 and the device wafer form an upper cavity 400 of the crystal resonator.
  • the piezoelectric resonator plate 200 is enclosed in the upper cavity 400 so that the piezoelectric resonator plate 200 can vibrate in the lower cavity 120 and the upper cavity 400.
  • the method of forming the capping layer 420 to enclose the upper cavity 400 includes, for example, the following steps.
  • a sacrificial layer 410 is formed on the surface of the device wafer 100, and the sacrificial layer 410 covers the piezoelectric resonator plate 200.
  • a capping material layer is formed on the surface of the device wafer 100, and the capping material layer covers the surface and sidewalls of the sacrificial layer 410 to cover the ⁇ 410.
  • the capping material layer also extends to cover the surface of the device wafer.
  • the space occupied by the sacrificial layer 410 corresponds to the upper cavity to be formed later. Therefore, by adjusting the height of the sacrificial layer, the height of the finally formed upper cavity can be adjusted accordingly. It should be recognized that the height of the upper cavity can be adjusted according to actual needs, and no limitation is made here.
  • At least one opening 420a is formed in the capping material layer to form the capping layer 420, wherein the opening 420a exposes the sacrificial layer 410.
  • the sacrificial layer 410 is removed through the opening 420a to form the upper cavity 400
  • the method further includes: blocking the opening in the capping layer 420 to close the upper cavity 400 and capping the piezoelectric resonator plate 200 in In the upper cavity 400.
  • a sealing plug 430 is formed in the opening to seal the upper cavity 400.
  • a first plastic encapsulation layer 610 may be formed on the front side 100U of the device wafer 100 to cover the entire device with the first plastic encapsulation layer 610 The structure on the front surface of the wafer (including covering the outer surface of the capping layer outside the upper cavity and the first wiring layer) to protect the structure under the first plastic encapsulation layer 610.
  • step S500 specifically referring to FIGS. 2i to 21, a semiconductor chip is bonded on the back surface of the device wafer, and the semiconductor chip is electrically connected to the control circuit through a second connection structure.
  • a driving circuit is formed in the semiconductor chip, and the driving circuit is used to provide an electrical signal, and the electrical signal passes through the control circuit and is further transmitted to the piezoelectric resonance plate 200 to control the The mechanical deformation of the piezoelectric resonator plate 200 will be described.
  • the second connection structure includes a conductive plug and a connection wire.
  • the connection line and the conductive plug can be used to draw the connection port of the control circuit from the front surface of the device wafer to the back surface of the device wafer.
  • the method for forming the second connection structure includes, for example:
  • connection line is formed on the front surface of the device wafer 100, and the connection line is electrically connected to the control circuit; in this embodiment, it is formed on the front surface of the device wafer 100
  • connection line 511 is electrically connected to the third interconnection structure 111b
  • second connection line 512 is electrically connected to the fourth interconnection structure 112b;
  • connection hole includes forming a first connection hole and a second connection hole, the first connection hole and the second connection hole respectively expose the first connection line 511 and the second connection hole Connection line 512;
  • the device wafer 100 may be thinned from the back of the device wafer 100, In order to reduce the thickness of the device wafer. In this way, when the first connection hole and the second connection hole are formed, the depth of the formed connection hole can be reduced, which is beneficial to ensure the morphology of the formed connection hole.
  • a conductive material is filled in the connection hole to form a conductive plug, one end of the conductive plug is connected to the connection line, and the other end of the conductive plug is used for electrical Connect the semiconductor chip.
  • the first conductive plug 521 and the second conductive plug 522 are formed correspondingly, and one end of the first conductive plug 521 is connected to the first connection line 511, and the first conductive plug 521 The other end of is used to electrically connect the semiconductor chip 500, one end of the second conductive plug 522 is connected to the second connection line 512, and the other end of the second conductive plug 522 is used to electrically connect the semiconductor chip 500.
  • the conductive plug is formed by etching the device wafer from the back of the device wafer 100 after the connection line is formed.
  • the conductive plug may be formed from the front surface of the device wafer before the connection line is formed.
  • the method for forming the second connection structure includes:
  • the device wafer 100 is etched from the front surface of the device wafer 100 to form a connection hole; in this embodiment, before forming the first plastic encapsulation layer, the device wafer is etched to form the Connection hole (same, may include forming a first connection hole and a second connection hole);
  • a conductive material is filled in the connection hole to form a conductive plug; in this embodiment, the first conductive plug 521 and the second conductive plug 522 can be formed separately;
  • connection line is formed on the front surface of the device wafer, and the connection line connects the conductive plug and the control circuit.
  • a first connection line 511 and a second connection line 512 are formed, the first connection line 511 connects the first conductive plug 521 and the third interconnection structure 111b, and the second rewiring 512 layers connect the second conductive plug 522 and the fourth interconnection structure 112b;
  • the device wafer is thinned from the back of the device wafer 100 until the conductive plug is exposed.
  • the first conductive plug 521 and the second conductive plug 522 are exposed for electrical connection with the semiconductor chip 500.
  • the step of thinning the device wafer from the back of the device wafer may be omitted.
  • the method for forming the second connection structure further includes:
  • a lead line is formed on the back surface of the device wafer 100, and the lead line covers the conductive plug.
  • the lead line includes forming a first lead line 531 and a second A lead wire 532, the first lead wire 531 covers the first conductive plug 521, and the second lead wire 532 covers the second conductive plug 522;
  • a plastic encapsulation layer 540 is formed on the back surface of the device wafer 100, and the plastic encapsulation layer 540 covers the first lead 531 and the second lead 532; and,
  • a contact hole is formed in the plastic encapsulation layer 540, and a conductive material is filled in the contact hole to form a contact plug, the bottom of the contact plug is electrically connected to the lead-out line, and the top of the contact plug is used for electrical Connecting the semiconductor chip; in this embodiment, including forming a first contact hole and a second contact hole, and filling the first contact hole and the second contact hole with a conductive material to form a first contact plug, respectively 551 and a second contact plug 552, the bottom of the first contact plug 551 is electrically connected to the first lead wire 531, the top of the first contact plug 551 is used to electrically connect the semiconductor chip, and the second contact The bottom of the plug 552 is electrically connected to the second lead wire 532, and the top of the second contact plug 552 is used to electrically connect the semiconductor chip.
  • connection port of the control circuit can be flexibly provided on the back surface of the device wafer 100 (for example, the connection port for connecting the semiconductor chip can be brought close to the position of the lower cavity, thereby So that the semiconductor chip can be correspondingly bonded in the middle region of the entire crystal resonator).
  • the lead wire covers the conductive plug and extends toward the lower cavity 120 (ie, extends toward the center of the device), so that When the semiconductor chip is closed, the semiconductor chip 500 can be installed correspondingly toward the center of the device.
  • the first lead 531 covers the first conductive plug 521 and extends toward the lower cavity 120
  • the second lead 532 covers the second conductive plug 522 and extends The direction close to the lower cavity 120 extends.
  • the first contact plug 551 connects the end of the first lead layer 531 close to the lower cavity 120
  • the second contact plug 552 connects the second lead layer 532 close to the lower cavity 120 Of the end.
  • the semiconductor chip constitutes a heterogeneous chip with respect to the device wafer 100. That is, the base material of the semiconductor chip is different from the base material of the device wafer 100.
  • the base material of the device wafer 100 is silicon
  • the base material of the heterogeneous chip may be a III-V semiconductor material or a II-VI semiconductor material (specifically including germanium, silicon germanium or GaAs, etc.).
  • a second stabilization layer 620 is formed on the device wafer 100, the second plastic encapsulation layer 620 covers the semiconductor chip, and the plastic encapsulation layer 540.
  • the second plastic encapsulation layer 620 is used to cover the entire device wafer structure on the thinned surface to cover the structure under the second plastic encapsulation layer 620 and protect the structure under the second plastic encapsulation layer 620.
  • the material of the second plastic encapsulation layer 620 includes photoresist, for example.
  • the piezoelectric resonance sheet and the capping layer are preferentially formed on the front surface of the device wafer in sequence, and then the semiconductor chip is bonded on the back surface of the device wafer.
  • the semiconductor chip may be preferentially bonded on the back surface of the device wafer, and then the piezoelectric resonance sheet and the capping layer are sequentially formed on the front surface of the device wafer.
  • the integration method of the crystal resonator and the control circuit includes:
  • a semiconductor chip is bonded on the back surface of the device wafer, and the semiconductor chip is electrically connected to the control circuit through a second connection structure;
  • a second plastic encapsulation layer is formed on the back surface of the device wafer to cover the semiconductor chip;
  • the piezoelectric resonance sheet and the capping layer are sequentially formed on the front surface of the device wafer, and the upper electrode and the lower electrode of the piezoelectric resonance sheet are electrically connected to the Described control circuit.
  • the crystal resonator includes:
  • at least part of the interconnect structure in the control circuit extends to the front surface of the device wafer 100;
  • the piezoelectric resonance plate 200 includes an upper electrode 230, a piezoelectric wafer 220, and a lower electrode 210.
  • the piezoelectric resonance 200 is formed on the front surface of the device wafer 100 and corresponds to the lower cavity; in this embodiment, The edge of the piezoelectric resonator plate 200 overlaps the side wall of the lower cavity 120;
  • a first connection structure for electrically connecting the upper electrode 230 and the lower electrode 210 of the piezoelectric resonator plate 200 to the control circuit;
  • a capping layer 420 is formed on the front surface of the device wafer 100 and covers the piezoelectric resonance sheet 200, and the capping layer 420 is also surrounded by the piezoelectric resonance sheet and the device wafer Upper cavity 400;
  • a semiconductor chip 500 is bonded on the back surface of the device wafer 100; wherein, for example, a drive circuit is formed in the semiconductor chip for generating an electrical signal and transmitting the electrical signal to the piezoelectric via the control circuit 100 Resonance piece 200;
  • the second connection structure is used to electrically connect the semiconductor chip 500 to the control circuit.
  • the semiconductor chip 500 may constitute a heterogeneous chip relative to the device wafer 100. That is, the base material of the semiconductor chip is different from the base material of the device wafer 100.
  • the base material of the device wafer 100 is silicon
  • the base material of the heterogeneous chip may be a III-V semiconductor material or a II-VI semiconductor material (specifically including germanium, silicon germanium or GaAs, etc.).
  • a capping layer 420 can be formed using semiconductor process technology to cover the piezoelectric resonator plate 200 in the upper cavity 400, thereby ensuring the piezoelectric resonance
  • the wafer 200 can oscillate in the upper cavity 400 and the lower cavity 120, so that the piezoelectric resonant wafer 200 and the control circuit can be integrated on the same device wafer.
  • the semiconductor chip can be further bonded to the device wafer 100, and then the semiconductor chip can be used to realize the original deviations such as temperature drift and frequency correction of the on-chip modulated crystal resonator through the control circuit 110, which is beneficial to improve the crystal The performance of the resonator.
  • the crystal resonator in this embodiment can not only improve the integration of the device, but also the crystal resonator formed based on the semiconductor process has a smaller size, thereby further reducing the power consumption of the device.
  • control circuit includes a first circuit 111 and a second circuit 112, the first circuit 111 and the second circuit 112 are respectively connected to the upper electrode and the lower electrode of the piezoelectric resonator plate 200 Electrical connection.
  • the first circuit 111 includes a first transistor, a first interconnect structure 111a and a third interconnect structure 111b, the first transistor is buried in the device wafer 100, the first interconnect structure Both 111 a and the third interconnect structure 111 b are electrically connected to the first transistor, and both extend to the front surface of the device wafer 100.
  • the first interconnect structure 111a is electrically connected to the lower electrode 210, and the third interconnect structure 111b is electrically connected to the semiconductor chip.
  • the second circuit 112 includes a second transistor, a second interconnect structure 112a and a fourth interconnect structure 112b, the second transistor is buried in the device wafer 100, the second interconnect structure Both 112a and the fourth interconnect structure 112b are electrically connected to the second transistor, and both extend to the front surface of the device wafer 100.
  • the second interconnect structure 112a is electrically connected to the upper electrode 230, and the fourth interconnect structure 112b is electrically connected to the semiconductor chip.
  • the first connection structure includes a first connection member and a second connection member, the first connection member connects the first interconnection structure 111a and the lower electrode 210 of the piezoelectric resonator plate, the first Two connecting pieces connect the second interconnection structure 112a and the upper electrode 230 of the piezoelectric resonator plate.
  • the lower electrode 210 is formed on the front surface of the device wafer 100 and surrounds the periphery of the lower cavity 120, and the lower electrode 210 also extends laterally out of the piezoelectric wafer 220 To form a lower electrode extension that covers the first interconnect structure 111a of the first circuit 111 so that the first interconnect structure of the lower electrode 210 and the first circuit 111 111a is electrically connected. Therefore, it can be considered that the lower electrode extension constitutes the first connector.
  • the upper electrode 230 is formed on the piezoelectric wafer 220, and the upper electrode 230 is electrically connected to the second interconnection structure 112a of the second circuit 112 through the second connector .
  • the second connector for connecting the upper electrode 230 and the second circuit 112 includes: a conductive plug (for example, a third conductive plug) and an interconnection line.
  • the third conductive plug is formed on the front surface of the device wafer 100, and the bottom of the third conductive plug is connected to the second interconnection structure 112a. And, one end of the interconnection line covers the upper electrode 230, and the other end of the interconnection line covers the top of the third conductive plug, so that the interconnection line and the third conductive plug connection.
  • the third conductive plug may also be used to support the interconnection line at this time.
  • the second connector may include only a conductive plug, and one end of the conductive plug is electrically connected to the upper electrode 230, and the other end of the conductive plug is electrically connected to the Second interconnect structure 112a.
  • the upper electrode is extended from the piezoelectric wafer to the end of the conductive plug.
  • the second connection structure includes: a conductive plug and a connection line.
  • the conductive plug penetrates the device wafer 100 so that one end of the conductive plug extends to the front surface of the device wafer, and the other end of the conductive plug extends to the device crystal
  • the back surface of the circle is electrically connected to the semiconductor chip 500; and the connection wire is formed on the front surface of the device wafer 100, and the connection wire connects the conductive plug and the control circuit.
  • the conductive plug of the second connection structure includes a first conductive plug 521 and a second conductive plug 522
  • the connection line includes a first connection line 511 and a second connection line 512.
  • the first connection line 511 connects the first conductive plug 521 and the third interconnection structure 111b
  • the second connection line 512 connects the second conductive plug 522 and the fourth interconnection ⁇ 112b.
  • the conductive plug and the connecting wire are used to realize that the connection port for electrically connecting the semiconductor chip in the control circuit can be drawn out from the front surface of the device wafer to the back surface of the device wafer, so that the semiconductor chip can be placed on the device
  • the back side of the wafer is electrically connected to the control circuit from the back side of the device wafer.
  • the second connection structure further includes a lead wire and a contact plug.
  • the lead-out line is formed on the back surface of the device wafer 100, one end of the lead-out line is connected to the conductive plug, the bottom of the contact plug is electrically connected to the other end of the lead-out line, The top is electrically connected to the semiconductor chip 500.
  • the lead wires in the second connection structure include a first lead wire 531 and a second lead wire 532
  • the contact pin includes a first contact pin 551 and a second contact pin 552.
  • One end of the first lead wire 531 is connected to the first conductive plug 521
  • the bottom of the first contact plug 551 is electrically connected to the other end of the first lead wire 531
  • the top of the first contact plug 551 Electrically connected to the semiconductor chip 500
  • one end of the second lead wire 532 is connected to the second conductive plug 522
  • the bottom of the second contact plug 552 is electrically connected to the other end of the second lead wire 532
  • the top of the second contact plug 552 is electrically connected to the semiconductor chip 500.
  • the lead wire extends toward the lower cavity 120 after covering the conductive plug.
  • the first lead wire 531 covers the first conductive plug 521 and extends toward the lower cavity 120, and the first contact plug 551 is close to the first lead wire 531 The ends of the lower cavity 120 are connected. In this way, the semiconductor chip 500 can be bonded at a position close to the lower cavity 120, so that the semiconductor chip 500 is closer to the center position of the device.
  • the device wafer 100 includes a base wafer 100A and a dielectric layer 100B.
  • the first transistor and the second transistor are both formed on the base wafer 100A
  • the dielectric layer 100B is formed on the base wafer 100A and covers the first transistor and the second transistor A transistor
  • the third interconnect structure 111b, the first interconnect structure 111a, the fourth interconnect structure 112b, and the second interconnect structure 112a are all formed in the dielectric layer 100B and extend to The surface of the dielectric layer 100B away from the base wafer 100A.
  • At least one opening is formed in the capping layer 400 of this embodiment, and a plug plug 430 is filled in the opening to close the upper cavity 400, so that the pressure The electric resonance plate 200 is enclosed in the upper cavity 400.
  • the crystal resonator further includes a first plastic encapsulation layer 610 formed on the front surface of the device wafer 100, and the first plastic encapsulation layer 610 covers the capping layer 420 is located The outer surface outside the upper cavity 400. That is, the structure on the entire front surface of the device wafer is covered with the first plastic encapsulation layer 610 to protect the structure under the first plastic encapsulation layer 610.
  • the crystal resonator further includes a second plastic encapsulation layer 620 formed on the back surface of the device wafer 100 and covering the semiconductor chip. It can be considered that the first plastic encapsulation layer 610 and the second plastic encapsulation layer 620 encapsulate the crystal resonator.
  • a lower cavity is formed in a device wafer forming a control circuit, and a piezoelectric resonator plate is further formed on the device wafer, and then passed A semiconductor planar process forms a capping layer to cap the piezoelectric resonator sheet in the upper cavity to form a crystal resonator, thereby realizing the integration of the control circuit and the crystal resonator on the same device wafer.
  • a semiconductor chip formed with a driving circuit can be further bonded to the device wafer, that is, the semiconductor chip, the control circuit, and the crystal resonator are integrated on the same device wafer, thereby facilitating on-chip modulation of the crystal Original deviations such as temperature drift and frequency correction of the resonator.
  • the crystal resonators formed based on the semiconductor planar process in the present invention have a smaller size, so that the crystal resonators can be reduced accordingly Power consumption.
  • the crystal resonator in the present invention is easier to integrate with other semiconductor components, which is beneficial to improve the integration of the device.
  • the piezoelectric resonator plate in the present invention can be formed on the back surface of the device wafer, which is beneficial to improve the process flexibility of the crystal resonator.

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Abstract

一种晶体谐振器与控制电路的集成结构及其集成方法。通过在形成有控制电路（110）的器件晶圆（100）中形成下空腔（120），并将压电谐振片（200）形成在器件晶圆（100）的正面（100U）上，以及利用半导体平面工艺形成封盖层（420）以将压电谐振片（200）封盖在上空腔（400）中构成谐振器。并且，还可将半导体芯片（500）进一步键合至同一器件晶圆（100）的背面（100D）上，有利于进一步提高晶体谐振器的集成度，并实现片上调制晶体谐振器的参数，具备更小的尺寸，有利于降低晶体谐振器的功耗，也更易于与其他半导体元器件集成，从而能够提高器件的集成度。

Description

晶体谐振器与控制电路的集成结构及其集成方法 技术领域
本发明涉及半导体技术领域，特别涉及一种晶体谐振器与控制电路的集成结构及其集成方法。
背景技术
晶体谐振器是利用压电晶体的逆压电效应制成的谐振器件，是晶体振荡器和滤波器的关键元件，被广泛应用于高频电子信号，实现精确计时、频率标准和滤波等测量和信号处理系统中必不可少的频率控制功能。
随着半导体技术的不断发展，以及集成电路的普及，各种元器件的尺寸也趋于小型化。然而，目前的晶体谐振器不仅难以与其他半导体元器件集成，并且晶体谐振器的尺寸也较大。
例如，目前常见的晶体谐振器包括表面贴装型晶体谐振器，其具体是将基座和上盖通过金属焊接(或者，粘接胶)粘合在一起，以形成密闭腔室，晶体谐振器的压电谐振片位于所述密闭腔室中，并且使压电谐振片的电极通过焊盘或者引线与相应的电路电性连接。基于如上所述的晶体谐振器，其器件尺寸很难进一步缩减，并且所形成的晶体谐振器还需要通过焊接或者粘合的方式与对应的集成电路电性连接，从而进一步限制了所述晶体谐振器的尺寸。
发明内容
本发明的目的在于提供一种晶体谐振器与控制电路的集成方法，以解决现有的晶体谐振器其尺寸较大且不易于集成的问题。
为解决上述技术问题，本发明提供一种晶体谐振器与控制电路的集成结构，包括：
提供一器件晶圆，所述器件晶圆中形成有控制电路；
从所述器件晶圆的正面刻蚀所述器件晶圆，以形成所述晶体谐振器的下空腔；
在所述器件晶圆的正面上形成包括上电极、压电晶片和下电极的压电谐振片，所述压电谐振片位于所述下空腔的上方，以及形成第一连接结构，所述压电谐振片的上电极和下电极通过所述第一连接结构电性连接至所述控制电路；
在所述器件晶圆的正面上形成封盖层，所述封盖层遮罩所述压电谐振片， 并与所述压电谐振片及所述器件晶圆围成所述晶体谐振器的上空腔；
在所述器件晶圆的背面上键合半导体芯片，以及形成第二连接结构，所述半导体芯片通过所述第二连接结构电性连接至所述控制电路。
本发明的又一目的在于提供一种晶体谐振器与控制电路的集成结构，包括：
器件晶圆，所述器件晶圆中形成有控制电路，以及在所述器件晶圆中还形成有下空腔，所述下空腔暴露于所述器件晶圆的正面；
压电谐振片，包括上电极、压电晶片和下电极，所述压电谐振片形成在所述器件晶圆的正面上并对应所述下空腔；
第一连接结构，用于使所述压电谐振片的上电极和下电极电连接至所述控制电路；
封盖层，形成在所述器件晶圆的正面上并遮罩所述压电谐振片，并且所述封盖层还与所述压电谐振片及所述器件晶圆围成上空腔；
半导体芯片，键合在所述器件晶圆的背面上；以及，
第二连接结构，用于使所述半导体芯片电连接至所述控制电路。
在本发明提供的晶体谐振器的集成方法中，通过半导体平面工艺在形成有控制电路的器件晶圆中形成下空腔，并将压电谐振片形成在该器件晶圆的正面上，以及进一步利用半导体平面工艺形成封盖层，以将压电谐振片封盖在上空腔中，从而实现控制电路和晶体谐振器能够集成在同一器件晶圆上。同时，还可将半导体芯片进一步集成在该器件晶圆的背面上，大大提高了晶体谐振器的集成度，并可实现片上调制晶体谐振器的参数(例如，晶体谐振器的温度漂移和频率矫正等原始偏差)，有利于提高晶体谐振器的性能。
可见，本发明提供的晶体谐振器，不仅使晶体谐振器能够实现与其他半导体元器集成，提高器件的集成度；并且，相比于传统的晶体谐振器(例如，表面贴装型晶体谐振器)，本发明提供的晶体谐振器的尺寸更小，有利于实现晶体谐振器的小型化，并能够减少制备成本和降低晶体谐振器的功耗。
附图说明
图1为本发明一实施例中的晶体谐振器的集成方法的流程示意图；
图2a～图2m为本发明一实施例中的晶体谐振器的集成方法在其制备过程中的结构示意图。
其中，附图标记如下：
100-器件晶圆；AA-器件区；100U-正面；100D-背面；100A-基底晶圆；100B- 介质层；110-控制电路；111-第一电路；111a-第一互连结构；111b-第三互连结构；112-第二电路；112a-第二互连结构；112b-第四互连结构；120-下空腔；200-压电谐振片；210-下电极；220-压电晶片；230-上电极；300-塑封层；300a-通孔；310-第三导电插塞；320-互连线；400-上空腔；410-牺牲层；420-封盖层；420a-开口；430-封堵插塞；500-半导体芯片；511-第一连接线；512-第二连接线；521-第一导电插塞；522-第二导电插塞；531-第一引出线；532-第二引出线；540-隔离介质层；551-第一接触栓；552-第二接触栓；610-第一塑封层；620-第二塑封层。
具体实施方式
本发明的核心思想在于提供了一种晶体谐振器与控制电路的集成结构及其形集成方法，通过半导体平面工艺将晶体谐振器和半导体芯片均集成在形成有控制电路的器件晶圆上。一方面，可以进一步缩减所形成的晶体谐振器的器件尺寸，另一方面，还可使所述晶体谐振器能够与其他半导体元器件集成，提高器件的集成度。
以下结合附图和具体实施例对本发明提出的晶体谐振器与控制电路的集成结构及其集成方法作进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
图1为本发明一实施例中的晶体谐振器的集成方法的流程示意图，图2a～图2k为本发明一实施例中的晶体谐振器的集成方法在其制备过程中的结构示意图。以下结合附图对本实施例中形成晶体谐振器的各个步骤进行详细说明。
在步骤S100中，具体参考图2a所示，提供一器件晶圆100，所述器件晶圆100中形成有控制电路110。
具体的，所述器件晶圆100具有相对的正面100U和背面100D，所述控制电110包括多个互连结构，并且至少部分互连结构延伸至所述器件晶圆的正面。其中，所述控制电路110例如可用于对后续形成的压电谐振片施加电信号。
其中，可以在同一器件晶圆100上同时制备多个晶体谐振器，因此在所述器件晶圆100上对应定义有多个器件区AA，所述控制电路110形成在所述器件区AA中。
进一步的，所述控制电路110包括第一电路111和第二电路112，所述第一电路111和第二电路112用于与后续所形成的压电谐振片的上电极和下电极电性 连接。
继续参考图2a所示，所述第一电路111包括第一晶体管、第一互连结构111a和第三互连结构111b，所述第一晶体管掩埋在所述器件晶圆100中，所述第一互连结构111a和第三互连结构111b均与所述第一晶体管连接并延伸至所述器件晶圆100的正面。其中，所述第一互连结构111a例如连接所述第一晶体管的漏极，所述二互连结构111b例如连接所述第一晶体管的源极。
类似的，所述第二电路112包括第二晶体管、第二互连结构112a和第四互连结构112b，所述第二晶体管掩埋在所述器件晶圆100中，所述第二互连结构112a和第四互连结构112b均与所述第二晶体管连接并延伸至所述器件晶圆100的正面。其中，所述第二互连结构112a例如连接所述第二晶体管的漏极，所述四互连结构112b例如连接所述第二晶体管的源极。
本实施例中，所述器件晶圆100包括基底晶圆100A和形成在所述基底晶圆100A上的介质层100B。以及，所述第一晶体管和所述第二晶体管均形成在所述基底晶圆100A上，所述介质层100B覆盖所述第一晶体管和第二晶体管，所述第三互连结构111b、所述第一互连结构111a、所述第二互连结构112a和所述第四互连结构112b均形成在所述介质层100B中并延伸至所述介质层100B的远离所述基底晶圆的表面。
此外，所述基底晶圆100A可以为硅晶圆，也可以为绝缘体上硅晶圆(silicon-on-insulator，SOI)。当所述基底晶圆100A为绝缘体上硅晶圆时，则所述基底晶圆可具体包括沿着由背面100D至正面100U依次层叠设置的底衬层、掩埋氧化层和顶硅层。
在步骤S200中，具体参考图2b所示，从所述器件晶圆100的正面刻蚀所述器件晶圆，以形成所述晶体谐振器的下空腔120。具体的，所述下空腔120从所述器件晶圆的正面100U暴露出，所述下空腔120例如用于为后续所形成的压电谐振片提供振动空间。
本实施例中，所述下空腔120形成在所述器件晶圆的所述介质层100B中，以及在每一所述器件区AA中均形成有所述下空腔120。即，形成所述下空腔120的方法包括：刻蚀所述介质层100B至所述基底晶圆100A，以在所述介质层100B中形成所述下空腔120。其中，所述下空腔120的深度可以根据实际需求调整，此处不做限定。例如，可使所述下空腔120仅形成在所述介质层100B中，或者可以使所述下空腔120从所述介质层100B进一步延伸至所述基底晶圆 100A中等。
需要说明的是，附图中仅为示意性的标示出了下空腔120、第一电路和第二电路之间的位置关系，应当认识到在具体方案中可根据实际电路的布局对应调整第一电路和第二电路的的排布方式，此处不予限定。
如上所述，所述基底晶圆100A还可以为绝缘体上硅晶圆。当所述基底晶圆100A为绝缘体上硅晶圆时，则在形成所述下空腔时，还可进一步刻蚀顶硅层，以使所述下空腔从介质层进一步延伸至所述掩埋氧化层。
在步骤S300中，具体参考图2c～2e所示，在所述器件晶圆100的正面上形成包括上电极230、压电晶片220和下电极210的压电谐振片200，其中所述压电谐振片200的边缘搭接在所述下空腔120的侧壁上，以使所述压电谐振片200对应所述下空腔120，以及形成第一连接结构，所述压电谐振片的上电极230和下电极210通过所述第一连接结构电性连接至所述控制电路。
本实施例中，下电极210与第一电路111电性连接(具体的，下电极210与第一互连结构111a电性连接)，上电极230与第二电路112电性连接(具体的，上电极230与第二互连结构112a电性连接)。如此，即可通过所述控制电路110将电信号传输至所述压电谐振片200，以在所述压电谐振片200内产生电场，从而使压电谐振片200随着所述电场的大小发生相应程度的机械形变。当压电谐振片200内的电场的方向相反时，则压电谐振片200的形变方向也随之改变。因此，在利用所述控制电路120对压电谐振片200施加交流电时，则压电谐振片200的形变方向会随着电场的正负作收缩或膨胀的交互变化，从而产生机械振动。
具体的，所述压电谐振片200的形成方法例如包括如下步骤。
步骤一，具体参考图2c所示，在所述器件晶圆100的正面100U的设定位置上形成下电极210。本实施例中，所述下电极210围绕在所述下空腔120的外围并电连接所述第一电路111的第一互连结构111a。如此，即可使所述下电极210通过所述第一互连结构111a与所述第一晶体管电性连接，从而可利用第一晶体管控制电信号施加于所述下电极210上。
需要说明的是，本实施例中，下电极210覆盖所述第一互连结构111a，并进一步使下电极210未覆盖所述第三互连结构111b。以及，下电极210也未覆盖所述第四互连结构112b和第二互连结构112a。
其中，所述下电极210的材质例如银。以及，可依次利用薄膜沉积工艺、 光刻工艺和刻蚀工艺形成所述下电极210；或者，也可以利用蒸镀工艺形成所述下电极210。
步骤二，继续参考图2c所示，键合压电晶片220至所述下电极210，所述压电晶片220位于所述下空腔120的上方。具体的，所述压电晶片220的边缘搭接在所述下空腔120的侧壁上并位于所述下电极210上，其中所述压电晶片220例如可以为石英晶片。
步骤三，继续参考图2c所示，在所述压电晶片220上形成上电极230。与下电极210类似的，所述上电极230也可以采用蒸镀工艺形成或薄膜沉积工艺形成，其材质例如为银。
需要说明的是，本实施例中，通过半导体工艺将所述下电极210、压电晶片220和上电极230依次形成在所述器件晶圆100上。然而，在其他实施例中，也可将上电极和下电极分别形成在压电晶片的两侧上，并将三者作为整体键合至所述器件晶圆上。
此外，如上所述，所形成的压电谐振片200中，其上电极230和下电极210通过第一连接结构分别电性连接至所述第二互连结构112a和第一互连结构111a。
具体的，所述第一连接结构包括第一连接件和第二连接件，其中所述第一连接件连接所述第一互连结构111a和所述压电谐振片的下电极210，所述第二连接件连接所述第二互连结构112a和所述压电谐振片的上电极230。
本实施例中，所述下电极210位于所述器件晶圆100的正面上并位于所述压电晶片220的下方，并从所述压电晶片220中延伸出，以使所述下电极210覆盖所述第一互连结构111a。因此可以认为，所述下电极210中从所述压电晶片延伸出的部分构成所述第一连接件。
当然，在其他实施例中，还可以在形成所述下电极之前，在所述器件晶圆100上形成第一连接件，并使所述第一连接件与所述第一互连结构电连接。以及，在形成所述下电极之后，使所述第一连接件电连接所述下电极210。此时，所述第一连接件例如包括重新布线层，所述重新布线层和所述第一互连结构连接，以及在所述器件晶圆上形成所述下电极之后，所述重新布线层即与所述下电极210电连接。
进一步的，在形成上电极230之后形成所述第二连接件，以实现上电极230和所述第二互连结构112a的电性连接。其中，所述第二连接件可以由一互连线 和导电插塞(例如为第三导电插塞)构成，所述第三导电插塞的底部连接所述第二互连结构112a，所述第三导电插塞的顶部连接所述互连线的一端，以及所述互连线的另一端至少部分覆盖上电极230以和所述上电极230连接。具体的，所述第二连接件的形成方法包括：
首先，具体参考图2d所示，在所述器件晶圆100的正面上形成塑封层300；其中，所述塑封层300覆盖所述压电晶片220并暴露出所述上电极230，所述塑封层300的材质例如包括聚酰亚胺；
接着，继续参考图2d所示，在所述塑封层300中形成通孔300a，所述通孔300a贯穿所述塑封层300以暴露出所述第二互连结构112a；
接着，具体参考图2e所示，在所述通孔300a中填充导电材料以形成导电插塞(例如为第三导电插塞310)，所述第三导电插塞310的底部与所述第二互连结构112a电性连接，所述第三导电插塞310的顶部暴露于所述塑封层300；
接着，继续参考图2e所示，在所述塑封层300上形成互连线320，并去除所述塑封层。其中，所述互连线320的一端与所述上电极230连接，所述互连线320的另一端与所述第三导电插塞310电性连接，从而使所述上电极230通过所述互连线320和所述第三导电插塞310连接至所述第二电路112的第二互连结构112a。
当然，作为替代的方案中，所述上电极形成在所述压电晶片上，并进一步从所述压电晶片上延伸出以构成上电极延伸部，此时可使第三导电插塞位于所述上电极延伸部的下方，并使第二连接件的第三导电插塞的底部连接至所述第二互连结构，以及使所述第二连接件的第三导电插塞的顶部连接至所述上电极延伸部，并支撑所述上电极延伸部。
在替代方案中，可以在形成所述上电极之前形成所述第二连接件的所述第三导电插塞。具体的，所述上电极和所述第二连接件的第三导电插塞的形成方法包括：
首先，在所述器件晶圆100上形成塑封层；本实施例中，所述塑封层覆盖所述器件晶圆100并暴露出所述压电晶片220；
接着，在所述塑封层中形成通孔，并在所述通孔中填充导电材料以形成第三导电插塞，所述第三导电插塞与所述第二互连结构112a电性连接；
接着，在所述压电晶片220上形成上电极，所述上电极至少部分覆盖所述压电晶片220，并从所述压电晶片220上延伸至所述塑封层，以覆盖所述第三导 电插塞，从而使所述上电极通过所述第三导电插塞与所述第二互连结构112a电性连接。
在步骤S400中，具体参考图2f～图2g所示，在所述器件晶圆100的正面上形成封盖层420，所述封盖层420遮罩所述压电谐振片200，并与所述压电谐振片200及所述器件晶圆围成所述晶体谐振器的上空腔400。
即，所述压电谐振片200即封闭在所述上空腔400中，以使所述压电谐振片200能够在所述下空腔120和所述上空腔400中振动。
具体的，形成所述封盖层420以围出所述上空腔400的方法例如包括以下步骤。
第一步骤，具体参考图2f所示，在所述器件晶圆100的表面上形成牺牲层410，所述牺牲层410覆盖所述压电谐振片200。
第二步骤，继续参考图2f所示，在所述器件晶圆100的表面上形成封盖材料层，所述封盖材料层覆盖所述牺牲层410的表面和侧壁，以包覆所述牺牲层410。本实施例中，所述封盖材料层还延伸覆盖所述器件晶圆的表面。
其中，所述牺牲层410所占据的空间，即对应后续需形成的上空腔。因此，可通过调整所述牺牲层的高度，以相应的调整最终所形成的上空腔的高度。应当认识到，所述上空腔的高度可根据实际需求相应的调整，此处不做限制。
第三步骤，具体参考图2g所示，在所述封盖材料层中形成至少一个开口420a，以构成所述封盖层420，其中所述开口420a暴露出所述牺牲层410。
第四步骤，继续参考图2g所示，通过所述开口420a去除所述牺牲层410，以形成所述上空腔400
可选的方案中，具体参考图2h所示，还包括：封堵所述封盖层420上的所述开口，以封闭所述上空腔400，并使所述压电谐振片200封盖在所述上空腔400中。具体的，通过在所述开口中形成封堵插塞430，以密封所述上空腔400。
继续参考图2h所示，在封堵所述封盖层420之后，还可在所述器件晶圆100的正面100U上形成第一塑封层610，以利用所述第一塑封层610覆盖整个器件晶圆的正面上的结构(包括，覆盖所述封盖层中位于所述上空腔外侧的外表面和第一布线层)，以对第一塑封层610下方的结构进行保护。
在步骤S500中，具体参考图2i～图2l所示，在所述器件晶圆的背面上键合半导体芯片，所述半导体芯片通过第二连接结构电性连接至所述控制电路。
其中，所述半导体芯片中例如形成有驱动电路，所述驱动电路用于提供一 电信号，所述电信号通过所述控制电路，并进一步传输至所述压电谐振片200上，以控制所述压电谐振片200的机械形变。
具体的，所述第二连接结构包括导电插塞和连接线。此时，例如可利用所述连接线和所述导电插塞，将所述控制电路的连接端口从器件晶圆的正面引出至器件晶圆的背面。
其中，所述第二连接结构的形成方法例如包括：
首先，具体参考图2c所示，在所述器件晶圆100的正面上形成连接线，所述连接线电连接所述控制电路；本实施例中，在所述器件晶圆100的正面上形成有第一连接线511和第二连接线512，所述第一连接线511电连接所述第三互连结构111b，所述第二连接线512电连接所述第四互连结构112b；
接着，具体参考图2j所示，从所述器件晶圆100的背面刻蚀所述器件晶圆以形成连接孔，所述连接孔均贯穿所述器件晶圆100，以暴露出所述连接线；本实施例中，形成连接孔时包括形成第一连接孔和第二连接孔，所述第一连接孔和所述第二连接孔分别暴露出所述第一连接线511和所述第二连接线512；
此外，具体参考图2i所示，还可以在刻蚀所述器件晶圆以形成第一连接孔和第二连接孔之前，从所述器件晶圆100的背面减薄所述器件晶圆100，以缩减所述器件晶圆的厚度。如此一来，在形成第一连接孔和第二连接孔时，即可降低所形成的连接孔的深度，有利于保障所形成的连接孔的形貌。
接着，具体参考图2j所示，在所述连接孔中填充导电材料，以形成导电插塞，所述导电插塞的一端与所述连接线连接，所述导电插塞的另一端用于电连接所述半导体芯片。
本实施例中，即相应的形成有第一导电插塞521和第二导电插塞522，所述第一导电插塞521的一端与第一连接线511连接，所述第一导电插塞521的另一端用于电连接所述半导体芯片500，所述第二导电插塞522的一端与第二连接线512连接，所述第二导电插塞522的另一端用于电连接所述半导体芯片500。
需要说明的是，本实施例的第二连接结构的形成方法中，所述导电插塞是在形成连接线之后，从器件晶圆100的背面刻蚀所述器件晶圆以形成。然而，在其他实施例中，所述导电插塞也可以在形成连接线之前，从所述器件晶圆的正面形成。
例如，在其他实施例中，所述第二连接结构的形成方法包括：
首先，从所述器件晶圆100的正面刻蚀所述器件晶圆，以形成连接孔；本 实施例中，在形成所述第一塑封层之前，刻蚀所述器件晶圆以形成所述连接孔(同样的，可以包括形成第一连接孔和第二连接孔)；
接着，在所述连接孔中填充导电材料，以形成导电插塞；本实施例中，即可分别形成第一导电插塞521和第二导电插塞522；
接着，在所述器件晶圆的正面上形成连接线，所述连接线连接所述导电插塞和所述控制电路。本实施例中包括形成第一连接线511和第二连接线512，所述第一连接线511连接所述第一导电插塞521和所述第三互连结构111b，所述第二重新布线512层连接所述第二导电插塞522和所述第四互连结构112b；
接着，从所述器件晶圆100的背面减薄所述器件晶圆，直至暴露出所述导电插塞。本实施例中即暴露出第一导电插塞521和所述第二导电插塞522，以用于与所述半导体芯片500电连接。或者，当所述第一导电插塞和第二导电插塞贯穿所述器件晶圆时，则从器件晶圆的背面减薄器件晶圆的步骤可以省略。
可选的方案中，所述第二连接结构的形成方法还包括：
首先，具体参考图2k所示，在所述器件晶圆100的背面上形成引出线，所述引出线覆盖所述导电插塞第；本实施例中，包括形成第一引出线531和第二引出线532，所述第一引出线531覆盖所述第一导电插塞521，所述第二引出线532覆盖所述第二导电插塞522；
接着，继续参考图2k所示，在所述器件晶圆100的背面上形成塑封层540，所述塑封层540覆盖所述第一引出线531和所述第二引出线532；以及，
接着，在所述塑封层540中形成接触孔，并在所述接触孔中填充导电材料以形成接触栓，所述接触栓的底部电连接所述引出线，所述接触栓的顶部用于电连接所述半导体芯片；本实施例中，包括形成第一接触孔和第二接触孔，并在所述第一接触孔和所述第二接触孔中填充导电材料，以分别形成第一接触栓551和第二接触栓552，所述第一接触栓551的底部电连接所述第一引出线531，所述第一接触栓551的顶部用于电连接所述半导体芯片，所述第二接触栓552的底部电连接所述第二引出线532，所述第二接触栓552的顶部用于电连接所述半导体芯片。
可以认为，通过设置所述引出线，可以使控制电路的连接端口在器件晶圆100的背面上灵活设置(例如，可使用于连接半导体芯片的连接端口靠近所述下空腔的位置上，从而使半导体芯片能够对应键合在整个晶体谐振器的中间区域)。
本实施例中，具体参考图2k和图2l所示，所述引出线覆盖所述导电插塞并往靠近所述下空腔120的方向延伸(即，往器件中心延伸)，从而在后续键合所述半导体芯片时，即可在使半导体芯片500相应的往器件中心设置。本实施例中，所述第一引出线531覆盖所述第一导电插塞521并往靠近所述下空腔120的方向延伸，第二引出线532覆盖所述第二导电插塞522并往靠近所述下空腔120的方向延伸。以及，所述第一接触栓551连接所述第一引线层531靠近所述下空腔120的端部，所述第二接触栓552连接所述第二引线层532靠近所述下空腔120的端部。
进一步的，所述半导体芯片相对于所述器件晶圆100构成异质芯片。即，所述半导体芯片的基底材质不同于所述器件晶圆100的基底材质。例如，本实施例中，器件晶圆100的基底材质为硅，则所述异质芯片的基底材质可以为III-V族半导体材料或Ⅱ-Ⅵ族半导体材料(具体例如包括锗、锗硅或砷化镓等)。
可选的方案中，具体参考图2m所示，在所述器件晶圆100上形成第二顿化层620，所述第二塑封层620覆盖所述半导体芯片，以及覆盖所述塑封层540。
可以理解的是，利用所述第二塑封层620覆盖减薄面上的整个器件晶圆结构，以封盖第二塑封层620下方的结构并对第二塑封层620下方的结构进行保护。其中，所述第二塑封层620的材质例如包括光刻胶。
此外需要说明的是，本实施例中，是优先在器件晶圆的正面上依次形成压电谐振片和封盖层，接着在器件晶圆的背面上键合半导体芯片。然而，在其他实施例中，还可以优先在器件晶圆的背面上键合半导体芯片，接着在器件晶圆的正面上依次形成压电谐振片和封盖层。
具体的，在另一个实施例中，晶体谐振器与控制电路的集成方法包括：
首先，在所述器件晶圆的背面上键合半导体芯片，并使所述半导体芯片通过第二连接结构电性连接至所述控制电路；
接着，在所述器件晶圆的背面上形成第二塑封层，以覆盖所述半导体芯片；
接着，从所述器件晶圆的正面刻蚀所述器件晶圆，以形成所述晶体谐振器的下空腔；
接着，在所述器件晶圆的正面上依次形成所述压电谐振片和所述封盖层，并使所述压电谐振片的上电极和下电极通过第一连接结构电性连接至所述控制电路。
基于如上所述的形成方法，本实施例中对所形成的晶体谐振器与控制电路 的集成结构进行说明，具体可结合图2a～图2m所示，所述晶体谐振器包括：
器件晶圆100，所述器件晶圆100中形成有控制电路，以及在所述器件晶圆100中还形成有下空腔120，所述下空腔120暴露于所述器件晶圆的正面；本实施例中，所述控制电路中的至少部分互连结构延伸至所述器件晶圆100的正面；
压电谐振片200，包括上电极230、压电晶片220和下电极210，所述压电谐振200形成在所述器件晶圆100的正面上并对应所述下空腔；本实施例中，所述压电谐振片200的边缘搭接在所述下空腔120的侧壁上；
第一连接结构，用于使所述压电谐振片200的上电极230和下电极210电连接至控制电路；以及，
封盖层420，形成在所述器件晶圆100的正面上并遮罩所述压电谐振片200，并且所述封盖层420还与所述压电谐振片及所述器件晶圆围成上空腔400；
半导体芯片500，键合在所述器件晶圆100的背面上；其中，所述半导体芯片中例如形成有驱动电路，用于产生电信号，并将电信号经由所述控制电路100传输至压电谐振片200；
第二连接结构，用于使所述半导体芯片500电连接至所述控制电路。
进一步的，所述半导体芯片500可相对于所述器件晶圆100构成异质芯片。即，所述半导体芯片的基底材质不同于所述器件晶圆100的基底材质。例如，本实施例中，器件晶圆100的基底材质为硅，则所述异质芯片的基底材质可以为III-V族半导体材料或Ⅱ-Ⅵ族半导体材料(具体例如包括锗、锗硅或砷化镓等)。
通过在器件晶圆100中形成下空腔120，并可利用半导体工艺技术形成封盖层420，以将所述压电谐振片200封盖在上空腔400中，从而可确保所述压电谐振片200能够在所述上空腔400和所述下空腔120中震荡，如此，即可使压电谐振片200能够和控制电路集成在同一器件晶圆上。同时，还可进一步将半导体芯片键合至器件晶圆100上，进而可利用半导体芯片并经由所述控制电路110，实现片上调制晶体谐振器的温度漂移和频率矫正等原始偏差，有利于提高晶体谐振器的性能。可见，本实施例中的晶体谐振器，不仅能够提高器件的集成度，并且基于半导体工艺所形成的晶体谐振器其的尺寸更小，从而还能够进一步降低器件功耗。
继续参考图2a所示，所述控制电路包括第一电路111和第二电路112，所述第一电路111和所述第二电路112分别与所述压电谐振片200的上电极和下电 极电性连接。
具体的，所述第一电路111包括第一晶体管、第一互连结构111a和第三互连结构111b，所述第一晶体管掩埋在所述器件晶圆100中，所述第一互连结构111a和第三互连结构111b均与所述第一晶体管电连接，并均延伸至所述器件晶圆100的正面。其中，所述第一互连结构111a与所述下电极210电性连接，所述第三互连结构111b与所述半导体芯片电连接。
类似的，所述第二电路112包括第二晶体管、第二互连结构112a和第四互连结构112b，所述第二晶体管掩埋在所述器件晶圆100中，所述第二互连结构112a和第四互连结构112b均与所述第二晶体管电连接，并均延伸至所述器件晶圆100的正面。其中，所述第二互连结构112a与所述上电极230电性连接，所述第四互连结构112b与所述半导体芯片电连接。
进一步的，所述第一连接结构包括第一连接件和第二连接件，所述第一连接件连接所述第一互连结构111a和所述压电谐振片的下电极210，所述第二连接件连接所述第二互连结构112a和所述压电谐振片的上电极230。
本实施例中，所述下电极210形成在所述器件晶圆100的正面上，并且围绕在所述下空腔120的外围，以及所述下电极210还横向延伸出所述压电晶片220以构成下电极延伸部，所述下电极延伸部覆盖所述第一电路111的所述第一互连结构111a，以使所述下电极210与所述第一电路111的第一互连结构111a电性连接。因此，可以认为，所述下电极延伸部即构成所述第一连接件。
以及，所述上电极230形成在所述压电晶片220上，并使所述上电极230通过所述第二连接件与所述第二电路112的所述第二互连结构112a电性连接。
具体的，用于连接所述上电极230和所述第二电路112的第二连接件包括：导电插塞(例如第三导电插塞)和互连线。所述第三导电插塞形成在所述器件晶圆100的正面上，并且所述第三导电插塞的底部与所述第二互连结构112a连接。以及，所述互连线的一端覆盖所述上电极230，所述互连线的另一端覆盖所述第三导电插塞的顶部，以使所述互连线和所述第三导电插塞连接。应当认识到，此时还可利用所述第三导电插塞支撑所述互连线。
此外，在其他实施例中，所述第二连接件可仅包括导电插塞，并使所述导电插塞的一端电连接所述上电极230，所述导电插塞的另一端电连接所述第二互连结构112a。例如，使所述上电极从压电晶片上延伸至所述导电插塞的端部上。
进一步的，所述第二连接结构包括：导电插塞和连接线。其中，所述导电 插塞贯穿所述器件晶圆100，以使所述导电插塞的一端延伸至所述器件晶圆的正面，以及使所述导电插塞的另一端延伸至所述器件晶圆的背面并和所述半导体芯片500电连接；以及，所述连接线形成在所述器件晶圆100的正面上，所述连接线连接所述导电插塞和所述控制电路。
本实施例中，第二连接结构的导电插塞包括第一导电插塞521和第二导电插塞522，以及连接线包括第一连接线511和第二连接线512。其中，所述第一连接线511连接所述第一导电插塞521和所述第三互连结构111b，所述第二连接线512连接所述第二导电插塞522和所述第四互连结构112b。
即，利用所述导电插塞和所述连接线，实现控制电路中用于电连接半导体芯片的连接端口能够从器件晶圆的正面引出至器件晶圆的背面，从而可以将半导体芯片设置在器件晶圆的背面上，并从器件晶圆的背面与控制电路电性连接。
可选的方案中，所述第二连接结构还包括引出线和接触栓。所述引出线形成在所述器件晶圆100的背面上，所述引出线的一端连接所述导电插塞，所述接触栓的底部电连接所述引出线的另一端，所述接触栓的顶部电连接所述半导体芯片500。
本实施例中，所述第二连接结构中的引出线包括第一引出线531和第二引出线532，以及所述接触栓包括第一接触栓551和第二接触栓552。所述第一引出线531的一端连接所述第一导电插塞521，所述第一接触栓551的底部电连接所述第一引出线531的另一端，所述第一接触栓551的顶部电连接所述半导体芯片500；以及，所述第二引出线532的一端连接所述第二导电插塞522，所述第二接触栓552的底部电连接所述第二引出线532的另一端，所述第二接触栓552的顶部电连接所述半导体芯片500。
进一步的，所述引出线在覆盖所述导电插塞的基础上还往靠近所述下空腔120的方向延伸。本实施例中，即所述第一引出线531覆盖所述第一导电插塞521并往靠近所述下空腔120的方向延伸，以及第一接触栓551与所述第一引出线531靠近下空腔120的端部连接。如此一来，即可将半导体芯片500键合在靠近下空腔120的位置上，使得半导体芯片500更靠近器件的中心位置。
继续参考图2a所示，本实施例中，所述器件晶圆100包括基底晶圆100A和介质层100B。其中，所述第一晶体管和所述第二晶体管均形成在所述基底晶圆100A上，所述介质层100B形成在所述基底晶圆100A上并覆盖所述第一晶体管和所述第二晶体管，以及所述第三互连结构111b、所述第一互连结构111a、 所述第四互连结构112b和所述第二互连结构112a均形成在所述介质层100B中并延伸至所述介质层100B的远离所述基底晶圆100A的表面。
继续参考图2m所示，本实施例的所述封盖层400中形成至少一个开口，并在所述开口中填充有封堵插塞430，以封闭所述上空腔400，从而使所述压电谐振片200封闭在所述上空腔400中。
以及，所述晶体谐振器还包括第一塑封层610，所述第一塑封层610形成在所述器件晶圆100的正面上，并且所述第一塑封层610覆盖所述封盖层420位于所述上空腔400外侧的外表面。即，利用所述第一塑封层610封盖整个器件晶圆正面上的结构，以对第一塑封层610下方的结构进行保护。以及，所述晶体谐振器还包括第二塑封层620，所述第二塑封层620形成在所述器件晶圆100的背面上并覆盖所述半导体芯片。可以认为，利用所述第一塑封层610和第二塑封层620封装所述晶体谐振器。
综上所述，本发明提供的晶体谐振器的集成方法中，通过在形成控制电路的器件晶圆中形成下空腔，并将压电谐振片进一步形成在该器件晶圆上，接着再通过半导体平面工艺形成封盖层，以将所述压电谐振片封盖在上空腔中构成晶体谐振器，从而实现了控制电路和晶体谐振器集成在同一器件晶圆上。基于此，还可将例如形成有驱动电路的半导体芯片进一步键合至该器件晶圆上，即半导体芯片、控制电路和晶体谐振器均集成在同一器件晶圆上，从而有利于实现片上调制晶体谐振器的温度漂移和频率矫正等原始偏差。并且，相比于传统的晶体谐振器(例如，表面贴装型晶体谐振器)，本发明中基于半导体平面工艺所形成的晶体谐振器，具备更小的尺寸，从而可相应的降低晶体谐振器的功耗。此外本发明中的晶体谐振器更也易于与其他半导体元器件集成，有利于提高器件的集成度。同时，本发明中的压电谐振片能够形成在器件晶圆的背面，有利于提高晶体谐振器的工艺灵活性。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (28)

  1. 一种晶体谐振器与控制电路的集成方法，其特征在于，包括：
    提供一器件晶圆，所述器件晶圆中形成有控制电路；
    从所述器件晶圆的正面刻蚀所述器件晶圆，以形成所述晶体谐振器的下空腔；
    在所述器件晶圆的正面上形成包括上电极、压电晶片和下电极的压电谐振片，所述压电谐振片位于所述下空腔的上方，以及形成第一连接结构，所述压电谐振片的上电极和下电极通过所述第一连接结构电性连接至所述控制电路；
    在所述器件晶圆的正面上形成封盖层，所述封盖层遮罩所述压电谐振片，并与所述压电谐振片及所述器件晶圆围成所述晶体谐振器的上空腔；
    在所述器件晶圆的背面上键合半导体芯片，以及形成第二连接结构，所述半导体芯片通过所述第二连接结构电性连接至所述控制电路。
  2. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于，所述器件晶圆包括基底晶圆和形成在所述基底晶圆上的介质层，所述下空腔形成在所述介质层中。
  3. 如权利要求2所述的晶体谐振器与控制电路的集成方法，其特征在于，所述基底晶圆为绝缘体上硅基底，包括沿着由所述背面至所述正面的方向依次层叠设置的底衬层、掩埋氧化层和顶硅层；以及，所述下空腔还从所述介质层延伸至所述掩埋氧化层。
  4. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于，所述压电谐振片的形成方法包括：
    在所述器件晶圆正面的设定位置上形成下电极；
    键合压电晶片至所述下电极；
    在所述压电晶片上形成所述上电极；或者，
    所述压电谐振片的上电极和下电极形成在压电晶片上，三者作为整体键合至所述器件晶圆的正面上。
  5. 如权利要求4所述的晶体谐振器与控制电路的集成方法，其特征在于，形成所述下电极的方法包括蒸镀工艺或薄膜沉积工艺；以及，形成所述上电极的方法包括蒸镀工艺或薄膜沉积工艺。
  6. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于， 所述控制电路包括第一互连结构和第二互连结构，所述第一连接结构包括第一连接件和第二连接件；
    其中，所述第一连接件连接所述第一互连结构和所述压电谐振片的下电极，所述第二连接件连接所述第二互连结构和所述压电谐振片的上电极。
  7. 如权利要求6所述的晶体谐振器与控制电路的集成方法，其特征在于，所述下电极位于所述器件晶圆的正面上，并且所述下电极还从所述压电晶片的下方延伸出以和所述第一互连结构电性连接，所述下电极中从所述压电晶片延伸出的部分构成所述第一连接件。
  8. 如权利要求6所述的晶体谐振器与控制电路的集成方法，其特征在于，在形成所述下电极之前，在所述器件晶圆上形成所述第一连接件，所述第一连接件与所述第一互连结构电连接，以及在所述器件晶圆上形成所述下电极之后，所述第一连接件电连接所述下电极。
  9. 如权利要求8所述的晶体谐振器与控制电路的集成方法，其特征在于，所述第一连接件包括重新布线层，所述重新布线层和所述第一互连结构连接；以及，在所述器件晶圆上形成所述下电极之后，所述互连线与所述下电极电连接。
  10. 如权利要求6所述的晶体谐振器与控制电路的集成方法，其特征在于，所述第二连接件的形成方法包括：
    在所述器件晶圆的正面上形成塑封层；
    在所述塑封层中形成通孔，并在所述通孔中填充导电材料以形成导电插塞，所述导电插塞的底部电性连接所述第二互连结构，所述导电插塞的顶部暴露于所述塑封层；
    在形成有所述上电极之后，所述上电极延伸出所述压电晶片至所述导电插塞的顶部，以使所述上电极和所述导电插塞电性连接；或者，在形成所述有上电极之后，在所述塑封层上形成互连线，所述互连线的一端覆盖所述上电极，所述互连线的另一端覆盖所述导电插塞；以及，
    去除所述塑封层。
  11. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于，形成所述封盖层以围出所述上空腔的方法包括：
    在所述器件晶圆的正面上形成牺牲层，所述牺牲层覆盖所述压电谐振片；
    在所述器件晶圆的正面上形成封盖材料层，所述封盖材料层覆盖所述牺牲层的表面和侧壁以包覆所述牺牲层；以及，
    在所述封盖材料层中形成至少一个开口，以构成所述封盖层，其中所述开口暴露出所述牺牲层，并通过所述开口去除所述牺牲层，以形成所述上空腔。
  12. 如权利要求11所述的晶体谐振器与控制电路的集成方法，其特征在于，在形成所述上空腔之后还包括：
    封堵所述封盖层上的所述开口，以封闭所述上空腔，并使所述压电谐振片封盖在所述上空腔中。
  13. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于，所述第二连接结构的形成方法包括：
    从所述器件晶圆的正面刻蚀所述器件晶圆，以形成连接孔；
    在所述连接孔中填充导电材料，以形成导电插塞；
    在所述器件晶圆的正面上形成连接线，所述连接线连接所述导电插塞和所述控制电路；以及，
    从所述器件晶圆的背面减薄所述器件晶圆，直至暴露出所述导电插塞，以用于与所述半导体芯片电连接。
  14. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于，所述第二连接结构形成方法包括：
    在所述器件晶圆的正面上形成连接线，所述连接线电连接所述控制电路；
    从所述器件晶圆的背面刻蚀所述器件晶圆以形成连接孔，所述连接孔均贯穿所述器件晶圆，以暴露出所述连接线；以及，
    在所述连接孔中填充导电材料以形成导电插塞，所述导电插塞的一端与所述连接线连接，所述导电插塞的另一端用于电连接所述半导体芯片。
  15. 如权利要求13或14所述的晶体谐振器与控制电路的集成方法，其特征在于，所述第二连接结构形成方法还包括：
    在所述器件晶圆的背面上形成引出线，所述引出线覆盖所述导电插塞；
    在所述器件晶圆的背面上形成塑封层，所述塑封层覆盖所述引出线；以及，
    在所述塑封层中形成接触孔，并在所述接触孔中填充导电材料以形成接触栓，所述接触栓的底部电连接所述引出线，所述接触栓的顶部用于电连接所述半导体芯片；
    在键合所述半导体芯片时，所述半导体芯片键合在所述塑封层上并与所述接触栓的顶部电连接。
  16. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于，在形成所述封盖层之后，以及在键合所述半导体芯片之前还包括：在所述器件晶圆的正面上形成第一塑封层，所述第一塑封层覆盖所述器件晶圆的正面和所述封盖层位于所述上空腔外侧的外表面；
    以及，在键合所述半导体芯片之后还包括：在所述器件晶圆的背面上形成第二塑封层，所述第二塑封层覆盖所述半导体芯片。
  17. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于，优先在所述器件晶圆的正面上依次形成所述压电谐振片和所述封盖层，接着在所述器件晶圆的背面上键合半导体芯片；
    或者，优先在所述器件晶圆的背面上键合半导体芯片，接着在所述器件晶圆的正面上依次形成所述压电谐振片和所述封盖层。
  18. 一种晶体谐振器与控制电路的集成结构，其特征在于，包括：
    器件晶圆，所述器件晶圆中形成有控制电路，以及在所述器件晶圆中还形成有下空腔，所述下空腔暴露于所述器件晶圆的正面；
    压电谐振片，包括上电极、压电晶片和下电极，所述压电谐振片形成在所述器件晶圆的正面上并对应所述下空腔；
    第一连接结构，用于使所述压电谐振片的上电极和下电极电连接至所述控制电路；
    封盖层，形成在所述器件晶圆的正面上并遮罩所述压电谐振片，并且所述封盖层还与所述压电谐振片及所述器件晶圆围成上空腔；
    半导体芯片，键合在所述器件晶圆的背面上；以及，
    第二连接结构，用于使所述半导体芯片电连接至所述控制电路。
  19. 如权利要求18所述的晶体谐振器与控制电路的集成结构，其特征在于，所述器件晶圆包括基底晶圆和形成在所述基底晶圆上的介质层，所述下空腔形成在所述介质层中。
  20. 如权利要求19所述的晶体谐振器与控制电路的集成方法，其特征在于，所述基底晶圆为绝缘体上硅基底，包括沿着由所述背面至所述正面的方向依次层叠设置的底衬层、掩埋氧化层和顶硅层；以及，所述下空腔还从所述介 质层延伸至所述掩埋氧化层。
  21. 如权利要求18所述的晶体谐振器与控制电路的集成结构，其特征在于，所述控制电路包括第一互连结构和第二互连结构，所述第一连接结构包括第一连接件和第二连接件；
    其中，所述第一连接件连接所述第一互连结构和所述压电谐振片的下电极，所述第二连接件连接所述第二互连结构和所述压电谐振片的上电极。
  22. 如权利要求21所述的晶体谐振器与控制电路的集成结构，其特征在于，所述下电极形成在所述器件晶圆的正面上并从所述压电晶片延伸出以和所述第一互连结构电性连接，所述下电极从所述压电晶片延伸出的部分构成所述第一连接件。
  23. 如权利要求21所述的晶体谐振器与控制电路的集成结构，其特征在于，所述第二连接件包括导电插塞，所述导电插塞的一端电连接所述上电极，所述导电插塞的另一端电连接所述第二互连结构
  24. 如权利要求21所述的晶体谐振器与控制电路的集成结构，其特征在于，所述第二连接件包括：
    导电插塞，形成在所述器件晶圆的正面上，并且所述导电插塞的底部与所述第二互连结构电连接；以及，
    互连线，所述互连线的一端覆盖所述上电极，所述互连线的另一端覆盖所述导电插塞的顶部，以使所述互连线和所述导电插塞连接。
  25. 如权利要求18所述的晶体谐振器与控制电路的集成结构，其特征在于，所述第二连接结构包括：
    导电插塞，贯穿所述器件晶圆，以使所述导电插塞的一端延伸至所述器件晶圆的正面，以及使所述导电插塞的另一端延伸至所述器件晶圆的背面并和所述半导体芯片电连接；以及，
    连接线，形成在所述器件晶圆的正面上，所述连接线连接所述导电插塞和所述控制电路。
  26. 如权利要求25所述的晶体谐振器与控制电路的集成结构，其特征在于，所述第二连接结构还包括：
    引出线，形成在所述器件晶圆的背面上，所述引出线的一端连接所述导电插塞；
    接触栓，所述接触栓的底部电连接所述引出线的另一端，所述接触栓的顶部电连接所述半导体芯片。
  27. 如权利要求18所述的晶体谐振器与控制电路的集成结构，其特征在于，所述封盖层中形成至少一个开口，并在所述开口中填充有封堵插塞，以封闭所述上空腔。
  28. 如权利要求18所述的晶体谐振器与控制电路的集成结构，其特征在于，还包括：
    第一塑封层，形成在所述器件晶圆的正面上，并覆盖所述封盖层位于所述上空腔外侧的外表面；以及，
    第二塑封层，形成在所述器件晶圆的背面上，并覆盖所述半导体芯片。
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