WO2020134602A1 - 晶体谐振器与控制电路的集成结构及其集成方法 - Google Patents
晶体谐振器与控制电路的集成结构及其集成方法 Download PDFInfo
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- WO2020134602A1 WO2020134602A1 PCT/CN2019/115652 CN2019115652W WO2020134602A1 WO 2020134602 A1 WO2020134602 A1 WO 2020134602A1 CN 2019115652 W CN2019115652 W CN 2019115652W WO 2020134602 A1 WO2020134602 A1 WO 2020134602A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N39/00—Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
- H03H9/205—Constructional features of resonators consisting of piezoelectric or electrostrictive material having multiple resonators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/10—Mounting in enclosures
- H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
- H03H9/1014—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
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- H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
- H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
- H03H9/0557—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement the other elements being buried in the substrate
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
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- H03H9/0561—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement consisting of a multilayered structure
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- H—ELECTRICITY
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- H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
- H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
- H03H9/19—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator consisting of quartz
Definitions
- the invention relates to the technical field of semiconductors, in particular to an integrated structure of a crystal resonator and a control circuit and an integrated method thereof.
- the crystal resonator is a resonant device made by using the inverse piezoelectric effect of piezoelectric crystals. It is a key component of crystal oscillators and filters. It is widely used in high-frequency electronic signals to achieve accurate timing, frequency standards and filtering. An essential frequency control function in the signal processing system.
- the size of various components also tends to be miniaturized.
- the current crystal resonator is not only difficult to integrate with other semiconductor components, but also the size of the crystal resonator is large.
- crystal resonators include surface mount crystal resonators, which specifically bond the base and the upper cover together by metal welding (or, adhesive glue) to form a closed cavity, crystal resonator
- the piezoelectric resonant plate is located in the closed chamber, and the electrodes of the piezoelectric resonant plate are electrically connected to corresponding circuits through pads or leads.
- the formed crystal resonator also needs to be electrically connected to the corresponding integrated circuit by soldering or bonding, thereby further limiting the crystal resonance The size of the device.
- An object of the present invention is to provide an integrated method of a crystal resonator and a control circuit to solve the problem that the existing crystal resonator is large in size and not easy to integrate.
- the present invention provides an integrated method of a crystal resonator and a control circuit, including:
- a piezoelectric resonance sheet including an upper electrode, a piezoelectric wafer and a lower electrode is formed on the back surface of the device wafer, the piezoelectric resonance sheet corresponds to the lower cavity, and a first connection structure is formed for The upper electrode and the lower electrode of the piezoelectric resonator plate are electrically connected to the control circuit through the first connection structure;
- a capping layer is formed on the back surface of the device wafer, and the capping layer covers the piezoelectric resonator plate, and surrounds the crystal resonator with the piezoelectric resonator plate and the device wafer Upper cavity; and,
- a semiconductor chip is bonded on the back surface of the device wafer, and a second connection structure is formed, and the semiconductor chip is electrically connected to the control circuit through the second connection structure.
- Another object of the present invention is to provide an integrated structure of a crystal resonator and a control circuit, including:
- a device wafer, a control circuit is formed in the device wafer, and a lower cavity is further formed in the device wafer, the lower cavity has an opening on the back of the device wafer;
- a piezoelectric resonance plate including an upper electrode, a piezoelectric wafer and a lower electrode, the piezoelectric resonance plate is formed on the back surface of the device wafer and corresponds to the lower cavity;
- a capping layer is formed on the back surface of the device wafer and covers the piezoelectric resonator plate, and the capping layer also forms an upper cavity with the piezoelectric resonator plate and the device wafer;
- a semiconductor chip bonded on the back of the device wafer.
- the second connection structure is for electrically connecting the semiconductor chip to the control circuit.
- a lower cavity is prepared through a semiconductor planar process, and the lower cavity can be exposed from the back of the device wafer, And the piezoelectric resonator plate can be formed on the back surface of the device wafer, and corresponds to the lower cavity to constitute a crystal resonator.
- the semiconductor chip is bonded to the back surface of the device wafer, and the integrated setting of the crystal resonator, the control circuit and the semiconductor chip is realized.
- the crystal resonator provided by the present invention not only realizes that the semiconductor chip, the control circuit and the crystal resonator can be integrated on the same semiconductor substrate, greatly improving the integration of the crystal resonator, but also realizes the on-chip modulation of the crystal resonator
- the parameters for example, the original deviations of the temperature drift and frequency correction of the crystal resonator
- the size of the crystal resonator formed by the forming method provided by the present invention is smaller, and the size of the crystal resonator can be realized. It is beneficial to reduce the manufacturing cost and the power consumption of the crystal resonator.
- FIG. 1 is a schematic flowchart of a method for integrating a crystal resonator and a control circuit in an embodiment of the invention
- FIGS. 2a to 2n are schematic structural diagrams of an integrated method of a crystal resonator and a control circuit in an embodiment of the present invention during its preparation process;
- FIG. 3 is a schematic diagram of an integrated structure of a crystal resonator and a control circuit in an embodiment of the invention.
- the core idea of the present invention is to provide an integrated structure of a crystal resonator and a control circuit and an integration method thereof.
- the piezoelectric resonance plate is integrated on a substrate formed with a control circuit through a semiconductor planar process.
- the device size of the formed crystal resonator can be further reduced, and on the other hand, the crystal resonator can be integrated with other semiconductor components to improve the integration of the device.
- FIG. 1 is a schematic flowchart of an integrated method of a crystal resonator and a control circuit in an embodiment of the present invention
- FIGS. 2a to 2n are an integrated method of a crystal resonator and a control circuit in an embodiment of the present invention during its preparation process Schematic diagram of the structure. The steps of forming a crystal resonator in this embodiment will be described in detail below with reference to the drawings.
- step S100 referring specifically to FIG. 2a, a device wafer 100 is provided, in which a control circuit 110 is formed.
- the device wafer 100 has a front side 100U and a back side 100D, and at least part of the interconnection structure of the control circuit 110 extends to and from the front side 100U of the device wafer The front of 100U is exposed.
- the control circuit 110 can be conveniently connected to the piezoelectric resonance plate and the semiconductor chip formed later.
- multiple crystal resonators can be prepared on the same device wafer 100 at the same time, so multiple device areas AA are correspondingly defined on the device wafer 100, and each crystal area AA corresponds to a crystal resonance Device.
- control circuit 110 includes a first circuit 111 and a second circuit 112.
- the first circuit 111 and the second circuit 112 are used to electrically connect the lower electrode and the upper electrode of the piezoelectric resonator plate formed later .
- the first circuit 111 includes a first transistor, a first interconnect structure 111a and a third interconnect structure 111b, the first transistor is buried in the device wafer, the first The interconnection structure 111a and the third interconnection structure 111b are both connected to the first transistor and extend to the front side of the device wafer.
- the first interconnect structure 111a is connected to the drain of the first transistor
- the third interconnect structure 111b is connected to the source of the first transistor.
- the second circuit 112 includes a second transistor, a second interconnect structure 112a and a fourth interconnect structure 112b, the second transistor is buried in the device wafer 100, the second interconnect structure Both 112a and the fourth interconnect structure 112b are connected to the second transistor and extend to the front side 100U of the device wafer 100.
- the second interconnect structure 112a is connected to the drain of the second transistor
- the fourth interconnect structure 112b is connected to the source of the second transistor.
- the device wafer 100 includes a base wafer 100A and a dielectric layer 100B formed on the base wafer 100A.
- the surface of the dielectric layer 100B away from the base wafer 100A constitutes a front surface 100U.
- both the first transistor and the second transistor are formed on the base wafer 100A, the dielectric layer 100B covers the first transistor and the second transistor, the third interconnect structure 111b, The first interconnect structure 111a, the fourth interconnect structure 112b, and the second interconnect structure 112a are all formed in the dielectric layer 100B and extend to the dielectric layer 100B away from the base wafer surface.
- the base wafer 100A may be a silicon wafer or a silicon-on-insulator (SOI).
- the base wafer 100A is a silicon-on-insulator wafer, which specifically includes an underlayer 101, a buried oxide layer 102 and a top layer stacked in this order from the back surface 100D to the front surface 100U Silicon layer 103.
- both the first transistor and the second transistor are formed in the top silicon layer 103 and are located above the buried oxide layer 102.
- the interconnection structure of the control circuit extends to the front surface 100U of the device wafer, and the piezoelectric resonator formed later will be provided on the back surface 100D of the device wafer, and subsequent The formed semiconductor chip is bonded to the back surface 100D of the device wafer.
- the first connection structure can be formed to lead the connection port of the control circuit 110 used to connect the piezoelectric resonant plate from the front surface of the device wafer to the back surface of the device wafer for further and subsequent
- the formed piezoelectric resonant sheet is electrically connected
- a second connection structure can be formed to lead the connection port for connecting the control circuit 110 to the semiconductor chip from the front surface of the device wafer to the back surface of the device wafer.
- the first connection structure includes a first connection member and a second connection member, wherein the first connection member connects the first interconnection structure 111a and is used to connect the piezoelectric resonator plate formed later
- the electrodes are electrically connected
- the second connecting member is connected to the second interconnection structure 112a, and is used to electrically connect to the upper electrode of the piezoelectric resonance plate formed later.
- the first connection member includes a first conductive plug 211a, and two ends of the first conductive plug 211a are respectively used to communicate with the first interconnection structure 111a and the subsequently formed lower electrode Electrical connection. That is, the first conductive plug 211a is used to draw the connection port of the first interconnection structure 111a in the control circuit from the front of the control circuit to the back of the control circuit, so that the subsequent formation on the back of the device wafer
- the lower electrode can be electrically connected to the control circuit on the back of the control circuit.
- the first connection member may further include a first connection line 221a, for example, the first connection line 221a is formed on the front surface of the device wafer, and the first connection One end of the line 221a connecting the first conductive plug 211a and the first interconnect structure, and the other end of the first conductive plug 211a are electrically connected to the lower electrode.
- a first connection line 221a for example, the first connection line 221a is formed on the front surface of the device wafer, and the first connection One end of the line 221a connecting the first conductive plug 211a and the first interconnect structure, and the other end of the first conductive plug 211a are electrically connected to the lower electrode.
- the first connection line of the first connection member is formed on the back surface of the device wafer, and the first connection line connects one end of the first conductive plug 211a
- the lower electrode and the other end of the first conductive plug 211a are electrically connected to the first interconnect structure of the control circuit.
- the second connector may include a second conductive plug 212a, and two ends of the second conductive plug 212a are respectively used to electrically connect with the second interconnection structure 112a and the subsequently formed upper electrode . That is, the second conductive plug 212a is used to draw the connection port of the second interconnection structure 112a in the control circuit from the front of the control circuit to the back of the control circuit, so that the subsequent formation on the back of the device wafer
- the upper electrode can be electrically connected to the control circuit on the back of the control circuit.
- the second connection member may further include a second connection line 222a, the second connection line 222a is formed on the front surface of the device wafer, for example, and the second connection line 212 is connected One end of the second conductive plug 212a and the second interconnection structure, and the other end of the second conductive plug 212a are electrically connected to the upper electrode.
- the second connection line in the second connection member is formed on the back surface of the device wafer, and the end of the second connection line connecting the second conductive plug 212a and the The upper electrode and the other end of the second conductive plug 212a are electrically connected to the second interconnection structure of the control circuit.
- first conductive plug 211a in the first connection piece and the second conductive plug 212a in the second connection piece China can be formed in the same process step, and the first connection line 221a in the first connection piece and The second connectors 222a of the second connectors may be formed simultaneously in the same process step.
- the second connection structure may also include a conductive plug and a connection line.
- the conductive plug in the second connection structure penetrates the device wafer, and the connection line in the second connection structure is formed on the front surface of the device wafer, for example, and connects the control circuit and the conductive plug . That is, the connection port for connecting to the semiconductor chip in the control circuit is drawn out from the front surface of the device wafer to the back surface of the device wafer through the conductive plug and the connection wire in the second connection structure.
- the conductive plug of the second connection structure includes a third conductive plug 211b and a fourth conductive plug 212b
- the connection line of the second connection structure includes a third connection line 221b and a fourth connection line 222b .
- first conductive plug 211a and the first connection line 221a of the first connector, the second conductive plug 212a and the second connection line 222a of the second connector, in the second connection structure may be formed in the same process step, and the forming method includes, for example, the following steps.
- the device wafer 100 is etched from the front surface 100U of the device wafer 100 to form a first connection hole, a second connection hole, a third connection hole, and a fourth connection hole .
- the bottoms of the first connection hole, the second connection hole, the third connection hole, and the fourth connection hole are closer to the back surface 100D of the device wafer relative to the bottom of the control circuit.
- first connection hole, the second connection hole, the third connection hole, and the fourth connection hole are filled with a conductive material to form first conductive plugs 211a and 211a, respectively.
- the second conductive plug 212a, the third conductive plug 211b, and the fourth conductive plug 212b are filled with a conductive material to form first conductive plugs 211a and 211a, respectively.
- the bottoms of the first conductive plug 211a, the second conductive plug 212a, the third conductive plug 211b, and the fourth conductive plug 212b are closer to the back surface of the device wafer relative to the control circuit 100D, so that the first conductive plug 211a, the second conductive plug 212a, the third conductive plug 211b, and the fourth conductive plug 212b extend from the front of the control circuit 110 to the back of the control circuit 110.
- the first transistor 111T and the second transistor 112T are formed in the top silicon layer 103 and above the buried oxide layer 102, while the first conductive plug 211a and the second conductive plug
- the plug 212a, the third conductive plug 211b, and the fourth conductive plug 212b penetrate the dielectric layer 100B and the top silicon layer 103 in sequence, and stop at the buried oxide layer 102. It can be considered that when the etching process is performed to form the first connection hole, the second connection hole, the third connection hole, and the fourth connection hole, the buried oxide layer 102 can be used as an etch stop layer to accurately Control the etching accuracy of the etching process.
- the first conductive plug 211a, the second conductive plug 212a, the third conductive plug 211b, and the fourth conductive plug 212b can be made It is exposed from the back surface of the thinned device wafer for electrical connection with the piezoelectric resonator plate and the semiconductor chip formed on the back surface.
- a first connection line 221a, a second connection line 222a, a third connection line 221b, and a fourth connection line 222b are formed on the front surface of the device wafer 100.
- the first connection line 221a connects the first conductive plug 211a and the first interconnection structure 111a
- the second connection line 222a connects the second conductive plug 212a and the second interconnection Connection structure 112a
- the third connection line 221b connects the third conductive plug 211b and the third interconnection structure 111b
- the fourth connection line 222b connects the fourth conductive plug 212b and the first Four interconnection structure 112b.
- connection line in the first connection member and the second connection line in the second connection member are both formed on the back surface of the device wafer, and the connection in the second connection structure
- the wire may also be formed on the back surface of the device wafer, in which case the first connector with the first conductive plug and the first connection wire, the second connector with the second conductive plug and the second connection wire, and the second
- the formation method of the connection structure includes, for example:
- the device wafer is etched from the front of the device wafer to form first and second connection holes, third and fourth connection holes;
- the first connection hole, the second connection hole, the third connection hole, and the fourth connection hole are filled with a conductive material to form a first conductive plug, a second conductive plug, a third conductive plug, and A fourth conductive plug, the first conductive plug is electrically connected to the first interconnect structure, the second conductive plug is electrically connected to the second interconnect structure, and the third conductive plug is electrically connected to the A third interconnect structure is electrically connected, and the fourth conductive plug is electrically connected to the fourth interconnect structure;
- the device wafer is thinned from the back of the device wafer, exposing the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug;
- a first connection line, a second connection line, a third connection line, and a fourth connection line are formed on the back surface of the device wafer.
- One end of the first connection line is connected to the first conductive plug.
- the other end of the first connection wire is used to electrically connect the lower electrode
- one end of the second connection wire is connected to the second conductive plug
- the other end of the second connection wire is used to electrically connect the upper electrode
- Electrodes, one end of the third connection line is connected to the third conductive plug, one end of the fourth connection line is connected to the fourth conductive plug, and the third connection line and the fourth connection line
- the other ends of are used to electrically connect the semiconductor chips.
- the first conductive plug 211a, the second conductive plug 212a, the third conductive plug 211b, and the fourth conductive plug 212b are forming the first connection line 221a and the second connection line 222a 3.
- the third connection line 221b and the fourth connection line 222b were previously prepared from the front surface of the device wafer.
- the conductive plug as described above can also be prepared from the backside of the device wafer after the device wafer is subsequently thinned. The method of preparing the first conductive plug and the second conductive plug from the back of the device wafer will be described in detail after the device wafer is subsequently thinned.
- the supporting wafer may be bonded on the front surface 100U of the device wafer 100. Therefore, in an optional solution, the first connection line 221a, the second connection line 222a, and the second The third connection line 221b and the fourth connection line 222b further include: forming a planarization layer 300 on the front surface 100U of the device wafer 100 to make the bonding surface of the device wafer 100 flatter.
- the planarization layer 300 is formed on the front surface 100U of the device wafer 100, and the surface of the planarization layer 300 facing away from the device wafer 100 is not lower than the redistribution layer (e.g. The surfaces of a connection line 221a, a second connection line 222a, a third connection line 221b, and a fourth connection line 222b).
- the redistribution layer e.g. The surfaces of a connection line 221a, a second connection line 222a, a third connection line 221b, and a fourth connection line 222b.
- the planarization layer 300 covers the device wafer 100 and the redistribution layer, and flattens the surface of the planarization layer 300 away from the device wafer 100, thereby making the bonding surface of the device wafer 100 relatively Flat; or, making the surface of the planarization layer 300 and the redistribution layer flush, so that the device wafer 100 can also have a flat bonding surface.
- the planarization layer 300 is formed by a grinding process.
- a rewiring layer is used as a grinding stop layer, so that the formed planarization layer 300, the first connection line 221a, and the second connection line 222a, The surfaces of the third connection line 221b and the fourth connection line 222b are flush to constitute the bonding surface of the device wafer 100.
- step S200 referring specifically to FIGS. 2c to 2f, a lower cavity 120 is formed in the device wafer 100, and the lower cavity 120 has an opening at the back of the device wafer.
- the method for forming the lower cavity 120 includes, for example, step S210 and step S220.
- step S210 specifically referring to FIG. 2c, the device wafer 100 is etched from the front surface of the device wafer 100 to form the lower cavity 120 of the crystal resonator.
- the lower cavity 120 extends from the front surface 100U of the device wafer 100 toward the inside of the device wafer 100, and the bottom of the lower cavity 120 is closer to the bottom of the control circuit 110 The backside 100D of the device wafer.
- the planarization layer 300, the dielectric layer 100B and the top silicon layer 103 are sequentially etched, and the etching stops at the buried oxide layer 102 to form the Bottom cavity 120.
- the buried oxide layer 102 can be used as an etch stop layer, so that the bottoms of the formed multiple conductive plugs can and The bottom of the lower cavity 120 is located at the same or similar depth.
- the first conductive plug 211a, the second conductive plug 212a, and the third conductive plug 211b can be ensured Both the fourth conductive plug 212b and the lower cavity 120 may be exposed.
- step S220 referring specifically to FIGS. 2e and 2f, the device wafer 100 is thinned from the back surface 100D of the device wafer 100 until the lower cavity 120 is exposed.
- the bottom of the lower cavity 120 extends to the buried oxide layer 102, so when the device wafer is thinned, the underlayer 101 and the buried oxide layer 102 are sequentially reduced and thinned To the top silicon layer 103 to expose the lower cavity 120.
- the bottoms of the first conductive plug 211a, the second conductive plug 212a, the third conductive plug 211b, and the fourth conductive plug 212b also extend to the buried oxide layer 102, so After thinning the device wafer, the first conductive plug 211a, the second conductive plug 212a, the third conductive plug 211b, and the fourth conductive plug 212b are also exposed, so that the exposed plurality of conductive plugs can be combined with The piezoelectric resonance plate and the semiconductor chip formed later are electrically connected.
- a support wafer 400 may be bonded on the front surface of the device wafer 100, so that the support wafer The device wafer 100 is thinned under the support of the circle 400.
- the support wafer 400 can also be used to close the opening of the lower cavity exposed to the front surface of the device wafer, so it can be considered that the support wafer 400 in this embodiment can be used to form a cover substrate to close the bottom
- the cavity is open on the front side of the device wafer.
- the formation method of the lower cavity 120 is: etching the device wafer 100 from the front and thinning the device wafer 100 from the back to make the opening of the lower cavity 120 It is exposed from the back of the device wafer 100.
- the method for forming the lower cavity 120 may also be: etching the device wafer from the back side of the device wafer to form the crystal resonator Bottom cavity 120. And, in other embodiments, before etching the device wafer from the back side of the device wafer, the device wafer may also be thinned.
- a method of etching the device wafer from the back of the device wafer to form a lower cavity includes, for example:
- the device wafer is thinned from the back of the device wafer; when the base wafer is a silicon-on-insulator wafer, the bottom of the base wafer can be sequentially removed when the device wafer is thinned Underlayer and mask oxide layer; of course, when thinning the device wafer, you can also choose to partially remove the underlayer, or completely remove the underlayer to expose the buried oxide layer, etc.;
- the buried oxide layer of the device wafer is etched from the back of the device wafer to form the lower cavity.
- the depth of etching the device wafer to form the lower cavity can be adjusted according to actual needs, and is not limited here.
- the top silicon layer 103 may be etched to form a lower cavity in the top silicon layer; alternatively, the top silicon may also be etched Layer and further etch the dielectric layer 100B, so that the formed lower cavity 120 extends from the top silicon layer 103 into the dielectric layer 100B.
- a support wafer may be optionally bonded to the front surface of the device wafer to assist the support
- the device wafer is described; of course, it is also possible to choose not to bond the support wafer, and a plastic encapsulation layer may be further formed on the front surface of the device wafer to cover the components exposed on the front surface of the device wafer.
- the first conductive plug 211a in the first connector, the second conductive plug 212a in the second connector, and the third conductive plug 211b in the second connection structure may be prepared from the back surface of the device wafer 100 after thinning the device wafer to form the device wafer.
- connection line as described above is formed on the front surface of the device wafer 100, and a conductive plug as described above is prepared from the back surface of the device wafer 100, and a method of connecting the conductive plug to the corresponding connection line include:
- a first connection line 221a, a second connection line 222a, a third connection line 221b, and a fourth connection line 222b are formed on the front surface of the device wafer 100;
- first connection line 221a is electrically connected to the first interconnect structure 111a
- second connection line 212a is electrically connected to the second interconnect structure 112a
- third connection line 221b is electrically connected to the first Three interconnect structures 111b
- fourth connection line 212b is electrically connected to the fourth interconnect structure 112b;
- the device wafer is etched from the back of the device wafer 100 to form a first connection hole, a second connection hole, and a third connection hole And a fourth connection hole, the first connection hole, the second connection hole, the third connection hole, and the fourth connection hole all penetrate the device wafer 100 to expose the first connection line 221a and the second connection line, respectively 222a, a third connection line 221b and a fourth connection line 222b;
- first connection hole, the second connection hole, the third connection hole, and the fourth connection hole are filled with a conductive material to form a first conductive plug 211a, a second conductive plug 212a, and a third conductive plug, respectively The plug 211b and the fourth conductive plug 212b.
- one end of the first conductive plug 211a is connected to the first connection line 221a
- the other end of the first conductive plug 211a is used to electrically connect with the lower electrode of the piezoelectric resonator plate
- the second conductive One end of the plug 212a is connected to the second connection line 222a
- the other end of the second conductive plug 212a is used for electrical connection with the electrode on the piezoelectric resonator plate
- one end of the third conductive plug 211b is connected to the third
- the connection line 221b is connected
- one end of the fourth conductive plug 212b is connected to the fourth connection line 222b
- the other ends of the third conductive plug 212b and the fourth conductive plug 212b are used to electrically connect the semiconductor chip connection.
- the connecting wires as described above are formed on the back surface of the device wafer 100, and the conductive plugs as described above are prepared from the back surface of the device wafer 100, and the conductive plugs are connected to the corresponding
- the method of connecting the cable includes:
- the device wafer 100 is thinned from the back of the device wafer 100, and the device wafer is etched from the back of the device wafer 100 to form a first connection hole, a second connection hole, a first Three connection holes and fourth connection holes;
- first connection hole, the second connection hole, the third connection hole, and the fourth connection hole are filled with a conductive material to form a first conductive plug, a second conductive plug, a third conductive plug, and A fourth conductive plug, one end of the first conductive plug is electrically connected to the first interconnect structure, one end of the second conductive plug is electrically connected to the second interconnect structure, and the third One end of the conductive plug is electrically connected to the third interconnection structure, and one end of the fourth conductive plug is electrically connected to the fourth interconnection structure;
- a first connection line, a second connection line, a third connection line, and a fourth connection line are formed on the back surface of the device wafer 100, and one end of the first connection line is connected to the first conductive plug.
- the other end of the first connection line is used to electrically connect the lower electrode
- one end of the second connection line is connected to the other end of the second conductive plug
- the other end of the second connection line One is used to electrically connect the upper electrode
- one end of the third connection line is connected to the third interconnection structure
- one end of the fourth connection line is connected to the fourth interconnection structure
- the third connection line and The other ends of the fourth connection wires are used to electrically connect the semiconductor chips.
- a top electrode 530 and a piezoelectric wafer are formed on the back surface of the device wafer 100 (that is, the surface of the device wafer 100 facing away from the support wafer 400) 520 and the piezoelectric resonance plate 500 of the lower electrode 510, the edge of the piezoelectric resonance plate 500 overlaps the side wall of the lower cavity 120, so that the piezoelectric resonance plate 500 corresponds to the lower cavity 120.
- the method for forming the piezoelectric resonance sheet 500 includes the following steps, for example.
- a lower electrode 510 is formed at a set position on the back surface of the device wafer 100 (ie, the surface facing away from the support wafer 400); in this embodiment, the lower electrode 510 Surrounding the periphery of the lower cavity 120 and covering the first conductive plug 211a, so that the lower electrode 510 is electrically connected to the first circuit 111 through the first conductive plug 211a, and correspondingly So that the lower electrode 510 is electrically connected to the first transistor through the first interconnect structure 111a.
- the material of the lower electrode 510 is silver, for example.
- the lower electrode 510 may be formed sequentially using a thin film deposition process, a photolithography process, and an etching process; or, the lower electrode 510 may also be formed using an evaporation process.
- Step two bonding the piezoelectric wafer 220 to the lower electrode 210, the edge of the piezoelectric wafer 520 overlaps the side wall of the lower cavity 120 and is located on the lower electrode 510, so that the piezoelectric wafer 520 corresponds to the lower cavity 120.
- the piezoelectric wafer 520 may be a quartz wafer, for example.
- an upper electrode 530 is formed on the piezoelectric wafer 520. Similar to the lower electrode 510, the upper electrode 530 can also be formed by a vapor deposition process or a thin film deposition process, and its material is silver, for example. In the subsequent process, the upper electrode 530 is electrically connected to the control circuit.
- the lower electrode 510, the piezoelectric wafer 520, and the upper electrode 530 are sequentially formed on the device wafer 100 by a semiconductor process.
- the upper electrode and the lower electrode may be formed on both sides of the piezoelectric wafer, respectively, and the three are bonded to the device wafer 100 as a whole.
- the lower electrode 510 is electrically connected to the first circuit through the first connector
- the upper electrode 530 is electrically connected to the second circuit through the second connector.
- the piezoelectric resonance sheet 500 is electrically connected to the control circuit 110 on the back surface of the control circuit 110, so that the lower electrode 510 and the upper electrode of the piezoelectric resonance sheet 500 can be used by the control circuit 110
- An electrical signal is applied at 530, so that an electric field can be generated between the lower electrode 510 and the upper electrode 530, so that the piezoelectric wafer 520 of the piezoelectric resonator plate 500 undergoes mechanical deformation under the action of the electric field.
- the deformation direction of the piezoelectric wafer 520 also changes accordingly. Therefore, when the control circuit 110 applies alternating current to the piezoelectric resonant plate 500, the deformation direction of the piezoelectric resonant plate 500 alternately contracts or expands with the sign of the electric field, thereby generating mechanical vibration.
- the first connection member includes a first conductive plug 211a and a first connection line 221a
- the lower electrode 510 is located under the piezoelectric wafer 520 and extends from the piezoelectric wafer 520, to The lower electrode 510 covers the first conductive plug 211a, so that the lower electrode 510 is electrically connected to the control circuit via the first connector.
- the second connector includes a second conductive plug 212a and a second connection line 222a, and further includes a fifth conductive plug 610, the bottom of the fifth conductive plug 610 is connected to the first
- the tops of the two conductive plugs 212a and the fifth conductive plug 610 are connected to the upper electrode 530 and support the upper electrode 530.
- a method for forming the fifth conductive plug 610 of the second connector and the upper electrode 530 includes:
- a plastic encapsulation layer 600 is formed on the back surface of the device wafer 100, the plastic encapsulation layer 600 covers the device wafer 100 and exposes the pressure Electronic chip 520; wherein the material of the plastic encapsulation layer 600 includes polyimide, for example;
- a through hole is formed in the plastic encapsulation layer 600; in this embodiment, the through hole penetrates the plastic encapsulation layer 600 to expose the second conductive plug 212a;
- a conductive material is filled in the through hole to form a fifth conductive plug 610, the bottom of the fifth conductive plug 610 is connected to the second conductive plug 212a, and the fifth conductive plug 610 The top is exposed to the plastic encapsulation layer 600;
- an upper electrode 530 is formed on the piezoelectric wafer 520, and the upper electrode 530 extends from the piezoelectric wafer 520 to the molding layer 600 to cover the fifth conductive plug Plug 610, so that the upper electrode 530 is electrically connected to the second conductive plug 212a through the fifth conductive plug 610.
- the plastic encapsulation layer 600 is removed.
- the top of the third conductive plug in the second connector may be The second connection line is connected.
- the second connector may include: a second connection line 222a, a second conductive plug 212a, a fifth conductive plug, and an interconnection line.
- the bottom of the fifth conductive plug is connected to the second conductive plug 212a
- the top of the fifth conductive plug is connected to one end of the interconnection line
- the other end of the interconnection line is at least partially
- the upper electrode 530 is covered to be connected to the upper electrode 530.
- the method for forming the fifth conductive plug and the interconnection line in the alternative solution includes, for example:
- a plastic encapsulation layer is formed on the surface of the device wafer 100 facing away from the support wafer 400; at this time, the plastic encapsulation layer may be formed after the upper electrode 530 is formed, and the plastic encapsulation layer is exposed to the Upper electrode 530;
- a through hole is formed in the plastic encapsulation layer, the through hole penetrates the plastic encapsulation layer to expose the second conductive plug 212a, and a conductive material is filled in the through hole to form a fifth conductive plug , The bottom of the fifth conductive plug is connected to the second conductive plug 212a;
- an interconnection line is formed on the plastic encapsulation layer, the interconnection line at least partially covers the upper electrode 530, and extends from the upper electrode 530 to cover the fifth conductive plug, and remove the ⁇ Plastic layer. That is, the upper electrode 530 is electrically connected to the second conductive plug 212a through the interconnection line and the fifth conductive plug.
- a capping layer 720 is formed on the back surface of the device wafer 100, and the capping layer 720 covers the piezoelectric resonance sheet 500 and The piezoelectric resonator plate 500 and the device wafer 100 form an upper cavity 700 of the crystal resonator.
- the method of forming the capping layer 420 to enclose the upper cavity 400 includes, for example, the following steps.
- a sacrificial layer 710 is formed on the surface of the device wafer 100, and the sacrificial layer 710 covers the piezoelectric resonator plate 500.
- a capping material layer is formed on the surface of the device wafer 100, and the capping material layer covers the surface and sidewalls of the sacrificial layer 710 to cover the ⁇ 710.
- the space occupied by the sacrificial layer 710 corresponds to the upper cavity to be formed later. Therefore, by adjusting the height of the sacrificial layer, the height of the finally formed upper cavity can be adjusted accordingly. It should be recognized that the height of the upper cavity can be adjusted according to actual needs, and no limitation is made here.
- the capping material layer further extends from the bottom of the sidewall of the sacrificial layer 710 to cover the back surface of the device wafer 100 to cover the third conductive plug 211b and the fourth conductive plug 212b.
- At least one opening 720a is formed in the capping material layer to form the capping layer 720, wherein the opening 720a exposes the sacrificial layer 710, And the sacrificial layer is removed through the opening 720a to form the upper cavity 700.
- the piezoelectric resonance plate 500 is enclosed in the upper cavity 700 so that the piezoelectric resonance plate 500 can vibrate in the lower cavity 120 and the upper cavity 700.
- the method further includes: blocking the opening on the capping layer 720 to close the upper cavity 700 and capping the piezoelectric resonance plate 500 in In the upper cavity 700.
- a sealing plug 730 is formed in the opening to seal the upper cavity 700.
- step S500 specifically referring to FIG. 2m, a semiconductor chip 900 is bonded on the back surface of the device wafer 100, and the semiconductor chip 900 is electrically connected to the control circuit through a second connection structure.
- a driving circuit is formed in the semiconductor chip, and the driving circuit is used to provide an electrical signal, and the electrical signal is transmitted to the piezoelectric resonator plate 500 through the control circuit to control the piezoelectric The mechanical deformation of the resonance sheet 500.
- the conductive plug and the connection wire are used to lead the connection port for the semiconductor chip circuit in the control circuit to the back surface of the device wafer.
- the method of forming the second connection structure further includes: forming a contact pad on the back surface of the device wafer, and the bottom of the contact pad is electrically connected to the second connection structure A conductive plug, the top of the contact pad is used to electrically connect the semiconductor chip.
- the capping layer 720 also extends to cover the back surface of the device wafer, so that the capping layer 720 also covers the third conductive plug and the fourth conductive plug. Therefore, in this embodiment, the contact pad is formed in the capping layer and penetrates the capping layer.
- the method for forming the contact pad in this embodiment includes, for example:
- a contact hole is formed in a portion where the capping layer 720 covers the back surface of the device wafer; in this embodiment, forming the contact hole includes forming a first contact hole and forming a second contact hole, the first contact hole And the second contact hole respectively expose the third interconnect structure 111b and the fourth interconnect structure 112b of the control circuit; and,
- a conductive material is filled in the contact hole to form a contact pad, the bottom of the contact pad is electrically connected to the control circuit, and the top of the contact pad is used to electrically connect the semiconductor chip.
- the first contact hole and the second contact hole are filled with a conductive material to form a first contact pad 910 and a second contact pad 920, respectively, wherein the bottom of the first contact pad 910 is electrically connected
- the top of the first contact pad 920 is used to electrically connect the semiconductor chip 900
- the bottom of the second contact pad 920 is electrically connected to the fourth interconnect structure 112b
- the top of the second contact pad 920 is used to electrically connect the semiconductor chip 900.
- the semiconductor chip constitutes a heterogeneous chip with respect to the device wafer 100. That is, the base material of the semiconductor chip is different from the base material of the device wafer 100.
- the base material of the device wafer 100 is silicon
- the base material of the heterogeneous chip may be a III-V semiconductor material or a II-VI semiconductor material (specifically including germanium, silicon germanium or GaAs, etc.).
- a plastic encapsulation layer 800 is further formed on the device wafer 100, the plastic encapsulation layer 800 covers the semiconductor chip, and the cover layer 720 is located above the The outer surface outside the cavity 700.
- the entire back surface of the device wafer 100 is covered with the plastic encapsulation layer 800 to cover the structure under the plastic encapsulation layer 800 and protect the structure under the plastic encapsulation layer 800.
- the material of the plastic encapsulation layer 800 includes photoresist, for example.
- the integrated structure of the formed crystal resonator and the control circuit will be described.
- the integrated structure of the crystal resonator and the control circuit include:
- at least part of the interconnect structure in the control circuit extends to the front side of the two device wafers 100;
- the piezoelectric resonance plate 500 includes an upper electrode 530, a piezoelectric wafer 520 and a lower electrode 510.
- the piezoelectric resonance 500 is formed on the back surface of the device wafer 100 and corresponds to the upper side of the lower cavity 120; In an embodiment, the edge of the piezoelectric resonator plate 200 overlaps the side wall of the lower cavity 120;
- a first connection structure formed on the device wafer 100, for electrically connecting the upper electrode 530 and the lower electrode 510 of the piezoelectric resonator plate 500 to the control circuit;
- a capping layer 720 is formed on the back surface of the device wafer 100 and covers the piezoelectric resonance sheet 500, and the capping layer 720 also surrounds the piezoelectric resonance sheet 500 and the device wafer Into a cavity;
- a semiconductor chip 900 bonded on the back surface of the device wafer 100;
- the second connection structure is used to electrically connect the semiconductor chip 900 to the control circuit.
- the base material of the semiconductor chip 900 is different from the base material of the device wafer 100.
- the base material of the device wafer 100 is silicon
- the base material of the heterogeneous chip may be a III-V semiconductor material or a II-VI semiconductor material (specifically including germanium, silicon germanium or GaAs, etc.).
- a capping layer 720 may be formed using semiconductor process technology to cover the piezoelectric resonance sheet 500 in the upper cavity 700, thereby ensuring the piezoelectric resonance
- the sheet 500 can oscillate in the upper cavity 700 and the lower cavity 120.
- the crystal resonator and the control circuit can be integrated on the same device wafer.
- the semiconductor chip can be further bonded to the device wafer 100, and then the semiconductor chip can be used to realize the original deviations such as temperature drift and frequency correction of the on-chip modulated crystal resonator through the control circuit 110, which is beneficial to improve the crystal The performance of the resonator. It can be seen that the crystal resonator in this embodiment can not only improve the integration of the device, but also the crystal resonator formed based on the semiconductor process has a smaller size, thereby further reducing the power consumption of the device.
- control circuit includes a first circuit 111 and a second circuit 112, the first circuit 111 and the second circuit 112 are respectively connected to the upper electrode and the lower electrode of the piezoelectric resonator plate 500 Electrical connection.
- the first circuit 111 includes a first transistor, a first interconnect structure 111a and a third interconnect structure 111b, the first transistor is buried in the device wafer 100, the first interconnect structure 111a The third interconnection structure 111b is electrically connected to the first transistor, and both extend to the front surface of the device wafer 100.
- the first interconnect structure 111a is electrically connected to the lower electrode 210
- the third interconnect structure 111b is electrically connected to the semiconductor chip.
- the second circuit 112 includes a second transistor, a second interconnect structure 112a and a fourth interconnect structure 112b, the second transistor is buried in the device wafer 100, the second interconnect structure 112a
- the fourth interconnection structure 112b is electrically connected to the second transistor, and both extend to the front surface of the device wafer 100.
- the second interconnect structure 112a is electrically connected to the upper electrode 230
- the fourth interconnect structure 112b is electrically connected to the semiconductor chip.
- the first connection structure includes a first connection member and a second connection member, the first connection member connects the first interconnection structure 111a and the lower electrode 510 of the piezoelectric resonator plate, the first Two connecting pieces connect the second interconnection structure 112a and the upper electrode 530 of the piezoelectric resonator plate.
- the first connector includes a first conductive plug 211a, the first conductive plug 211a penetrates the device wafer 100, so that one end of the first conductive plug 211a extends to the device crystal
- the front side of the circle 100 is electrically connected to the first interconnection structure, and the other end of the first conductive plug 211a extends to the back side of the device wafer 100 and to the piezoelectric resonator 500
- the lower electrode 510 is electrically connected.
- the first connecting member further includes a first connecting line 211.
- the first connection line 221a is formed on the front surface of the device wafer 100, and the first connection line 221a connects the first conductive plug 211a and the first interconnect structure 111a.
- the first connection line 221a is formed on the back surface of the device wafer 100, and the first connection line connects the first conductive plug and the lower electrode.
- the lower electrode 510 is formed on the back surface of the device wafer 100 and is located at the periphery of the lower cavity 120, and the lower electrode 510 also extends laterally out of the piezoelectric wafer 520 to A lower electrode extension is formed, and the lower electrode extension covers the first conductive plug 211a to electrically connect the lower electrode 210 and the first interconnection structure 111a of the first circuit 111.
- the second connector includes a second conductive plug 212a, the second conductive plug 212a penetrates the device wafer 100, so that one end of the second conductive plug 212a extends to the device crystal
- the front surface of the circle 100 is electrically connected to the second interconnection structure, and the other end of the second conductive plug 212a extends to the back surface of the device wafer 100 and to the piezoelectric resonance plate 500
- the upper electrode 530 is electrically connected.
- the second connection member further includes a second connection line 212.
- the second connection line 222a is formed on the front surface of the device wafer 100, and the second connection line 222a connects the second conductive plug 212a and the second interconnection structure 112a.
- the second connection line 222a is formed on the back surface of the device wafer 100, and the second connection line connects the second conductive plug and the upper electrode.
- the second connector further includes: a fifth conductive plug 610 and an interconnection line.
- the fifth conductive plug is formed on the back surface of the device wafer 100, and the bottom of the fifth conductive plug is connected to the second conductive plug 212a.
- one end of the interconnection line covers the upper electrode 530, and the other end of the interconnection line at least partially covers the top of the fifth conductive plug to make the interconnection line and the fifth conductive Plug connection.
- the fifth conductive plug may also be used to support the interconnection line at this time.
- the second connector may include only the fifth conductive plug, and one end of the fifth conductive plug is electrically connected to the upper electrode 530, and the other end of the fifth conductive plug is electrically connected to the Second conductive plug 212a.
- the upper electrode is extended from the piezoelectric wafer to the end of the fifth conductive plug.
- the second connection structure includes a conductive plug and a connection line.
- the conductive plug in the second connection structure penetrates the device wafer 100, so that one end of the conductive plug extends to the front surface of the device wafer 100, and the other end of the conductive plug extends To the back surface of the device wafer 100 and electrically connected to the semiconductor chip 900, the connection line is formed on the front surface of the device wafer 100, and the connection line connects the conductive plug and the device Described control circuit.
- the conductive plug of the second connection structure includes a third conductive plug 211b and a fourth conductive plug 212b
- the connection line of the second connection structure includes a first connection line 221b and a second connection line 222b
- the third connection line 221b connects the third conductive plug 211b and the third interconnection structure 111b
- the fourth connection line 222b connects the fourth conductive plug 212b and the fourth interconnection ⁇ 112b.
- the second connection structure may further include a contact pad, the contact pad is formed on the back surface of the device wafer, and the bottom of the contact pad is electrically connected to the conductive plug in the second connection structure, and the The top of the contact pad is electrically connected to the semiconductor chip.
- the capping layer 720 also extends from the bottom of the sidewall of the upper cavity 120 to cover the surface of the device wafer 100, and the semiconductor chip is bonded to the cap On the cap layer 720, that is, the semiconductor chip 900 is bonded on the cap layer 720.
- the contact pad in this embodiment can be penetrated through the capping layer 720, so that the bottom of the contact pad is electrically connected to the conductive plug, and the top of the contact pad is electrically connected to the semiconductor chip 900 .
- the contact pads of the second connection structure include a first contact pad 910 and a second contact pad 920.
- the bottom of the first contact pad 910 is electrically connected to the third conductive plug 211b
- the top of the first contact pad 910 is electrically connected to the semiconductor chip 900
- the bottom of the second contact pad 920 is electrically connected to the In the fourth conductive plug 212b
- the top of the second contact pad 920 is electrically connected to the semiconductor chip 900.
- the device wafer 100 includes a base wafer and a dielectric layer 100B. Wherein both the first transistor and the second transistor are formed on the base wafer, and the dielectric layer 100B is formed on the base wafer and covers the first transistor and the second transistor, And the third interconnect structure, the first interconnect structure, the fourth interconnect structure and the second interconnect structure are all formed in the dielectric layer 100B and extend to the dielectric layer away from the Describe the surface of the base wafer.
- the crystal resonator further includes: a plastic encapsulation layer 800 formed on the back surface of the device wafer 100, and the plastic encapsulation layer 800 covers the semiconductor chip 900 and the capping layer 720 is located above the The outer surface outside the cavity 120. That is, the structure on the entire back surface of the device wafer is covered with the plastic encapsulation layer 800 to protect the structure under the plastic encapsulation layer 800.
- the lower cavity 120 penetrates the device wafer 100 so that the lower cavity 120 further has an opening on the front of the device wafer.
- a cover substrate is also bonded on the front surface of the device wafer to close the opening of the lower cavity exposed to the front surface of the device with the cover substrate.
- the cover substrate can be formed of, for example, a silicon base.
- the crystal resonator, the control circuit and the semiconductor chip can be integrated on the same substrate, which is beneficial to realize the on-chip modulation of the parameters of the crystal resonator ( For example, original deviations such as temperature drift and frequency correction, etc.), which can improve the performance of the crystal resonator.
- the crystal resonators formed based on the semiconductor planar process in the present invention have a smaller size, so that the crystal resonators can be reduced accordingly Power consumption.
- the crystal resonator in the present invention is easier to integrate with other semiconductor components, which is beneficial to improve the integration of the device.
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Abstract
一种晶体谐振器与控制电路的集成结构及其集成方法。将压电谐振片(500)和半导体芯片(900)均形成在器件晶圆(100)的背面上,从而使半导体芯片(900)、控制电路(110)和晶体谐振器均设置在同一器件晶圆(100)上。如此,不仅有利于提高晶体谐振器的集成度,并且还可实现片上调制晶体谐振器的参数,同时相比于传统的晶体谐振器,该晶体谐振器具备更小的尺寸,有利于降低晶体谐振器的功耗。
Description
本发明涉及半导体技术领域,特别涉及一种晶体谐振器与控制电路的集成结构及其集成方法。
晶体谐振器是利用压电晶体的逆压电效应制成的谐振器件,是晶体振荡器和滤波器的关键元件,被广泛应用于高频电子信号,实现精确计时、频率标准和滤波等测量和信号处理系统中必不可少的频率控制功能。
随着半导体技术的不断发展,以及集成电路的普及,各种元器件的尺寸也趋于小型化。然而,目前的晶体谐振器不仅难以与其他半导体元器件集成,并且晶体谐振器的尺寸也较大。
例如,目前常见的晶体谐振器包括表面贴装型晶体谐振器,其具体是将基座和上盖通过金属焊接(或者,粘接胶)粘合在一起,以形成密闭腔室,晶体谐振器的压电谐振片位于所述密闭腔室中,并且使压电谐振片的电极通过焊盘或者引线与相应的电路电性连接。基于如上所述的晶体谐振器,其器件尺寸很难进一步缩减,并且所形成的晶体谐振器还需要通过焊接或者粘合的方式与对应的集成电路电性连接,从而进一步限制了所述晶体谐振器的尺寸。
发明内容
本发明的目的在于提供一种晶体谐振器与控制电路的集成方法,以解决现有的晶体谐振器其尺寸较大且不易于集成的问题。
为解决上述技术问题,本发明提供一种晶体谐振器与控制电路的集成方法,包括:
提供器件晶圆,所述器件晶圆中形成有控制电路;
在所述器件晶圆中形成下空腔,所述下空腔具有位于所述器件晶圆背面的开口;
在所述器件晶圆的背面上形成包括上电极、压电晶片和下电极的压电谐振片,所述压电谐振片对应所述下空腔,以及形成第一连接结构,用于使所述压电谐振片的上电极和下电极通过所述第一连接结构电性连接至所述控制电路;
在所述器件晶圆的背面上形成封盖层,所述封盖层遮罩所述压电谐振片,并与所述压电谐振片及所述器件晶圆围成所述晶体谐振器的上空腔;以及,
在所述器件晶圆的背面上键合半导体芯片,以及形成第二连接结构,所述半导体芯片通过所述第二连接结构电性连接至所述控制电路。
本发明的又一目的在于提供一种晶体谐振器与控制电路的集成结构,包括:
器件晶圆,所述器件晶圆中形成有控制电路,以及在所述器件晶圆中还形成有下空腔,所述下空腔具有位于所述器件晶圆背面的开口;
压电谐振片,包括上电极、压电晶片和下电极,所述压电谐振片形成在所述器件晶圆的背面上并对应所述下空腔;
第一连接结构,形成在所述器件晶圆上,用于使所述压电谐振片的上电极和下电极均与所述控制电路电性连接;以及,
封盖层,形成在所述器件晶圆的背面上并遮罩所述压电谐振片,并且所述封盖层还与所述压电谐振片及所述器件晶圆围成上空腔;
半导体芯片,键合在所述器件晶圆的背面上;以及,
第二连接结构,用于使所述半导体芯片电连接至所述控制电路。
在本发明提供的晶体谐振器与控制电路的集成方法中,基于形成有控制电路的器件晶圆,通过半导体平面工艺制备下空腔,并使下空腔能够从器件晶圆的背面暴露出,并且使压电谐振片能够形成在器件晶圆的背面上,并对应所述下空腔以构成晶体谐振器。同时,还将半导体芯片键合至器件晶圆的背面上,实现了晶体谐振器、控制电路和半导体芯片的集成设置。
可见,本发明提供的晶体谐振器,不仅实现了半导体芯片、控制电路和晶体谐振器能够集成在同一半导体衬底上,大大提高晶体谐振器的集成度,同时还可实现片上调制晶体谐振器的参数(例如,晶体谐振器的温度漂移和频率矫正等原始偏差),有利于提高晶体谐振器的性能。并且,相比于传统的晶体谐振器(例如,表面贴装型晶体谐振器),通过本发明提供的形成方法所形成的晶体谐振器的尺寸更小,能够实现晶体谐振器的小型化,有利于减少制备成本和降低晶体谐振器的功耗。
图1为本发明一实施例中的晶体谐振器与控制电路的集成方法的流程示意 图;
图2a~图2n为本发明一实施例中的晶体谐振器与控制电路的集成方法在其制备过程中的结构示意图;
图3为本发明一实施例中的晶体谐振器与控制电路的集成结构的示意图。
其中,附图标记如下:
100-器件晶圆;AA-器件区;100U-正面;100D-背面;100A-基底晶圆;100B-介质层;101-底衬层;102-掩埋氧化层;103-顶硅层;110-控制电路;111-第一电路;111a-第一互连结构;111b-第三互连结构;112-第二电路;112a-第二互连结构;112b-第四互连结构;120-下空腔;211b-第三导电插塞;212b-第四导电插塞;211a-第一导电插塞;212a-第二导电插塞;221b-第三连接线;222b-第四连接线;221a-第一连接线;222a-第二连接线;300-平坦化层;400-支撑晶圆;500-压电谐振片;510-下电极;520-压电晶片;530-上电极;600-塑封层;610-第五导电插塞;700-上空腔;710-牺牲层;720-封盖层;720a-开口;730-封堵插塞;800-塑封层;900-半导体芯片;910-第一接触垫;920-第二接触垫。
本发明的核心思想在于提供了一种晶体谐振器与控制电路的集成结构及其集成方法,通过半导体平面工艺将压电谐振片集成在形成有控制电路的衬底上。一方面,可以进一步缩减所形成的晶体谐振器的器件尺寸,另一方面,还可使所述晶体谐振器能够与其他半导体元器件集成,提高器件的集成度。
以下结合附图和具体实施例对本发明提出的晶体谐振器与控制电路的集成结构及其集成方法作进一步详细说明。根据下面说明,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
图1为本发明一实施例中的晶体谐振器与控制电路的集成方法的流程示意图,图2a~图2n为本发明一实施例中的晶体谐振器与控制电路的集成方法在其制备过程中的结构示意图。以下结合附图对本实施例中形成晶体谐振器的各个步骤进行详细说明。
在步骤S100中,具体参考图2a所示,提供器件晶圆100,在所述器件晶圆100中形成有控制电路110。
本实施例中,所述器件晶圆100具有相对的正面100U和背面100D,以及所述控制电路110的至少部分互连结构延伸至所述器件晶圆的正面100U,并从所述器件晶圆100的正面100U暴露出。如此,即可使所述控制电路110便于与后续所形成的压电谐振片和半导体芯片电性连接。
进一步的,可以在同一器件晶圆100上同时制备多个晶体谐振器,因此在所述器件晶圆100上对应定义有多个器件区AA,每一所述器件区AA中对应形成一个晶体谐振器。
具体的,所述控制电路110包括第一电路111和第二电路112,所述第一电路111和第二电路112用于与后续所形成的压电谐振片的下电极和上电极电性连接。
继续参考图2a所示,所述第一电路111包括第一晶体管、第一互连结构111a和第三互连结构111b,所述第一晶体管掩埋在所述器件晶圆中,所述第一互连结构111a和第三互连结构111b均与所述第一晶体管连接,并延伸至所述器件晶圆的正面。例如,所述第一互连结构111a与所述第一晶体管的漏极连接,所述第三互连结构111b与所述第一晶体管的源极连接。
类似的,所述第二电路112包括第二晶体管、第二互连结构112a和第四互连结构112b,所述第二晶体管掩埋在所述器件晶圆100中,所述第二互连结构112a和第四互连结构112b均与所述第二晶体管连接,并延伸至所述器件晶圆100的正面100U。例如,所述第二互连结构112a与所述第二晶体管的漏极连接,所述第四互连结构112b与所述第二晶体管的源极连接。
本实施例中,所述器件晶圆100包括基底晶圆100A和形成在所述基底晶圆100A上的介质层100B,则所述介质层100B远离基底晶圆100A的表面构成正面100U。以及,所述第一晶体管和所述第二晶体管均形成在所述基底晶圆100A上,所述介质层100B覆盖所述第一晶体管和第二晶体管,所述第三互连结构111b、所述第一互连结构111a、所述第四互连结构112b和所述第二互连结构112a均形成在所述介质层100B中并延伸至所述介质层100B的远离所述基底晶圆的表面。
其中,所述基底晶圆100A可以为硅晶圆,也可以为绝缘体上硅晶圆(silicon-on-insulator,SOI)。本实施例中,所述基底晶圆100A为绝缘体上硅晶圆,其具体包括沿着由所述背面100D至所述正面100U的方向依次层叠设置的底衬层101、掩埋氧化层102和顶硅层103。本实施例中,所述第一晶体管和所述第二晶体管均形成顶硅层103中,并位于所述掩埋氧化层102的上方。
需要说明的是,本实施例中,所述控制电路的互连结构延伸至器件晶圆的正面100U,而后续所形成的压电谐振片将设置在所述器件晶圆的背面100D,以及后续所形成的半导体芯片键合在所述器件晶圆的背面100D。基于此,在后续工艺中,可通过形成第一连接结构,以实现将控制电路110用于连接压电谐振片的连接端口从器件晶圆的正面引出至器件晶圆的背面,以进一步和后续所形成的压电谐振片电性连接;以及,可通过形成第二连接结构,以实现将控制电路110用于连接半导体芯片的连接端口从器件晶圆的正面引出至器件晶圆的背面。
具体的,所述第一连接结构包括第一连接件和第二连接件,其中所述第一连接件连接所述第一互连结构111a,并用于与后续所形成的压电谐振片的下电极电连接,所述第二连接件连接所述第二互连结构112a,并用于和后续所形成的压电谐振片的上电极电连接。
第一连接结构中,所述第一连接件包括第一导电插塞211a,所述第一导电插塞211a的两端分别用于与所述第一互连结构111a和后续所形成的下电极电连接。即,利用所述第一导电插塞211a将所述控制电路中第一互连结构111a的连接端口从控制电路的正面引出至控制电路的背面,从而使后续形成在器件晶圆的背面上的下电极能够在控制电路的背面与所述控制电路电性连接。
可选的,在本实施例中,所述第一连接件还可包括第一连接线221a,所述第一连接线221a例如形成在所述器件晶圆的正面上,并且所述第一连接线221a的连接所述第一导电插塞211a的一端和所述第一互连结构,以及所述第一导电插塞211a的另一端电连接所述下电极。
或者,在其他实施例中,所述第一连接件中的第一连接线形成在器件晶圆的背面上,并且所述第一连接线的连接所述第一导电插塞211a的一端和所述下电极,以及所述第一导电插塞211a的另一端电连接所述控制电路的所述第一互连结构。
类似的,所述第二连接件可包括第二导电插塞212a,所述第二导电插塞212a的两端分别用于与所述第二互连结构112a和后续所形成的上电极电连接。即,利用所述第二导电插塞212a将所述控制电路中第二互连结构112a的连接端口从控制电路的正面引出至控制电路的背面,从而使后续形成在器件晶圆的背面上的上电极能够在控制电路的背面与所述控制电路电性连接。
以及本实施例中,所述第二连接件还可包括第二连接线222a,所述第二连 接线222a例如形成在所述器件晶圆的正面上,并且所述第二连接线212的连接所述第二导电插塞212a的一端和所述第二互连结构,以及所述第二导电插塞212a的另一端电连接所述上电极。
或者,在其他实施例中,所述第二连接件中的第二连接线形成在器件晶圆的背面上,并且所述第二连接线的连接所述第二导电插塞212a的一端和所述上电极,以及所述第二导电插塞212a的另一端电连接所述控制电路的所述第二互连结构。
其中,所述第一连接件中的第一导电插塞211a和第二连接件中国的第二导电插塞212a可以在同一工艺步骤中形成,以及第一连接件中的第一连接线221a和第二连接件中的第二连接件222a可以在同一工艺步骤中同时形成。
此外,第二连接结构中也可包括导电插塞和连接线。类似的,所述第二连接结构中的导电插塞贯穿器件晶圆,以及第二连接结构中的连接线例如形成在器件晶圆的正面上,并连接所述控制电路和所述导电插塞。即,通过第二连接结构中的导电插塞和连接线将所述控制电路中用于与半导体芯片连接的连接端口从所述器件晶圆的正面引出至器件晶圆的背面。本实施例中,所述第二连接结构的导电插塞包括第三导电插塞211b和第四导电插塞212b,以及第二连接结构的连接线包括第三连接线221b和第四连接线222b。
进一步的,所述第一连接件的第一导电插塞211a和第一连接线221a,所述第二连接件的第二导电插塞212a和第二连接线222a,所述第二连接结构中的第三导电插塞211b、第三连接线221b、第四导电插塞212b和第四连接线222b,可以在同一工艺步骤中形成,其形成方法例如包括如下步骤。
第一步骤,具体参考图2b所示,从所述器件晶圆100的正面100U刻蚀所述器件晶圆100以形成第一连接孔、第二连接孔、第三连接孔和第四连接孔。具体的,所述第一连接孔、第二连接孔、第三连接孔和第四连接孔的底部相对于所述控制电路的底部更靠近所述器件晶圆的背面100D。
第二步骤,继续参考图2b所示,在所述第一连接孔、所述第二连接孔、第三连接孔和第四连接孔中填充导电材料,以分别形成第一导电插塞211a和第二导电插塞212a、第三导电插塞211b和第四导电插塞212b。
即,所述第一导电插塞211a、所述第二导电插塞212a、第三导电插塞211b和第四导电插塞212b的底部相对于所述控制电路更靠近所述器件晶圆的背面 100D,从而使第一导电插塞211a、第二导电插塞212a、第三导电插塞211b和第四导电插塞212b从控制电路110的正面延伸至控制电路110的背面。
具体而言,所述第一晶体管111T和所述第二晶体管112T形成在所述顶硅层103中,并位于所述掩埋氧化层102的上方,而第一导电插塞211a、第二导电插塞212a、第三导电插塞211b和第四导电插塞212b依次贯穿介质层100B和顶硅层103,并停止于所述掩埋氧化层102。可以认为,执行刻蚀工艺以形成所述第一连接孔、所述第二连接孔、第三连接孔和第四连接孔时,可利用所述掩埋氧化层102作为刻蚀停止层,以精确控制刻蚀工艺的刻蚀精度。
后续工艺中,在减薄所述器件晶圆的背面之后,即可使所述第一导电插塞211a、所述第二导电插塞212a、第三导电插塞211b和第四导电插塞212b从减薄后的器件晶圆的背面暴露出,以用于与形成在背面上的压电谐振片和半导体芯片电连接。
第三步骤,继续参考图2c所示,在所述器件晶圆100的正面上形成第一连接线221a、第二连接线222a、第三连接线221b和第四连接线222b。其中,所述第一连接线221a连接所述第一导电插塞211a和所述第一互连结构111a,所述第二连接线222a连接所述第二导电插塞212a和所述第二互连结构112a,所述第三连接线221b连接所述第三导电插塞211b和所述第三互连结构111b,所述第四连接线222b连接所述第四导电插塞212b和所述第四互连结构112b。
此外,在其他实施例中,所述第一连接件中的第一连接线和第二连接件中的第二连接线均形成器件晶圆的背面上,以及所述第二连接结构中的连接线也可以形成在器件晶圆的背面上,此时具有第一导电插塞和第一连接线的第一连接件、具有第二导电插塞和第二连接线的第二连接件以及第二连接结构的形成方法例如包括:
首先,从所述器件晶圆的正面刻蚀所述器件晶圆以形成第一连接孔和第二连接孔、第三连接孔和第四连接孔;
接着,在所述第一连接孔、第二连接孔、第三连接孔和第四连接孔中填充导电材料,以分别形成第一导电插塞、第二导电插塞、第三导电插塞和第四导电插塞,所述第一导电插塞与所述第一互连结构电连接,所述第二导电插塞与第二互连结构电连接,所述第三导电插塞与所述第三互连结构电连接,所述第四导电插塞与第四互连结构电连接;
接着,从所述器件晶圆的背面减薄所述器件晶圆,暴露出所述第一导电插塞、第二导电插塞、第三导电插塞和第四导电插塞;
接着,在所述器件晶圆的背面上形成第一连接线、第二连接线、第三连接线和第四连接线,所述第一连接线的一端连接所述第一导电插塞,所述第一连接线的另一端用于电连接所述下电极,所述第二连接线的一端连接所述第二导电插塞,所述第二连接线的另一端用于电连接所述上电极,所述第三连接线的一端连接所述第三导电插塞,所述第四连接线的一端连接所述第四导电插塞,以及所述第三连接线和所述第四连接线的另一端均用于电连接所述半导体芯片。
需要说明的是,如上所述的第一导电插塞211a、第二导电插塞212a、第三导电插塞211b和第四导电插塞212b是在形成第一连接线221a、第二连接线222a、第三连接线221b和第四连接线222b之前从所述器件晶圆的正面制备。然而应当认识到,如上所述的导电插塞也可以在后续减薄所述器件晶圆之后,从所述器件晶圆的背面制备。从器件晶圆的背面制备第一导电插塞和第二导电插塞的方法将在后续减薄所述器件晶圆之后,进行详细说明。
此外,在后续工艺中会,可在所述器件晶圆100的正面100U上键合支撑晶圆,因此可选的方案中,在形成所述第一连接线221a、第二连接线222a、第三连接线221b和第四连接线222b之后还包括:在所述器件晶圆100的正面100U上形成平坦化层300,以使所述器件晶圆100的键合表面更为平坦。
具体参考图2c所示,所述平坦化层300形成在器件晶圆100的正面100U上,并且所述平坦化层300背离所述器件晶圆100的表面不低于重新布线层(例如包括第一连接线221a、第二连接线222a、第三连接线221b和第四连接线222b)的表面。例如,所述平坦化层300覆盖所述器件晶圆100和所述重新布线层,并使所述平坦化层300背离器件晶圆100的表面平坦,从而使器件晶圆100的键合表面较为平坦;或者,使所述平坦化层300和所述重新布线层表面齐平,如此也可使器件晶圆100具备平坦的键合表面。
本实施例中,采用研磨工艺形成所述平坦化层300,此时例如以重新布线层为研磨停止层,从而使所形成的平坦化层300、第一连接线221a、第二连接线222a、第三连接线221b和第四连接线222b的表面齐平,以构成器件晶圆100的键合表面。
在步骤S200中,具体参考图2c~图2f所示,在所述器件晶圆100中形成下 空腔120,所述下空腔120具有位于所述器件晶圆背面的开口。
本实施例中,所述下空腔120的形成方法例如包括步骤S210和步骤S220。
在步骤S210中,具体参考图2c所示,从所述器件晶圆100的正面刻蚀所述器件晶圆100,以形成所述晶体谐振器的下空腔120。
具体的,所述下空腔120从所述器件晶圆100的正面100U往所述器件晶圆100的内部延伸,并且所述下空腔120的底部相对于所述控制电路110的底部更靠近所述器件晶圆的背面100D。
本实施例中,在形成所述下空腔120时,依次刻蚀所述平坦化层300、介质层100B和顶硅层103,并刻蚀停止于所述掩埋氧化层102,以形成所述下空腔120。
即,在执行刻蚀工艺以形成第一连接孔、第二连接孔、第三连接孔和第四连接孔,以进一步制备第一导电插塞211a、第二导电插塞212a、第三导电插塞211b和第四导电插塞212b,以及在执行刻蚀工艺形成下空腔120时,都可以利用掩埋氧化层102作为刻蚀停止层,以使所形成的多个导电插塞的底部能够和所述下空腔120的底部位于相同或相近的深度位置。如此一来,在后续工艺中,从器件晶圆100的背面100D对器件晶圆进行减薄工艺时,即能够确保第一导电插塞211a、第二导电插塞212a、第三导电插塞211b和第四导电插塞212b和下空腔120均可以被暴露出。
需要说明的是,附图中仅为示意性的标示出了下空腔120、第一电路和第二电路之间的位置关系,应当认识到在具体方案中可根据实际电路的布局对应调整第一电路和第二电路的排布方式,此处不予限定。
在步骤S220中,具体参考图2e和图2f所示,从所述器件晶圆100的背面100D减薄所述器件晶圆100,直至暴露出所述下空腔120。
如上所述,所述下空腔120的底部延伸至掩埋氧化层102,因此在减薄所述器件晶圆时,则依次削减所述底衬层101和所述掩埋氧化层102,并减薄至所述顶硅层103,以暴露出所述下空腔120。并且,本实施例中,所述第一导电插塞211a、第二导电插塞212a、第三导电插塞211b和第四导电插塞212b的底部也均延伸至掩埋氧化层102,因此在减薄所述器件晶圆之后,还暴露出第一导电插塞211a、第二导电插塞212a、第三导电插塞211b和第四导电插塞212b,以使暴露的多个导电插塞能够和后续所形成的压电谐振片以及半导体芯片电性连接。
可选的方案中,具体参考图2d所示,在减薄所述器件晶圆100之前,可以 在所述器件晶圆100的正面上键合一支撑晶圆400,从而可以在所述支撑晶圆400的支撑作用下减薄所述器件晶圆100。此时,还可利用所述支撑晶圆400封闭所述下空腔暴露于器件晶圆正面的开口,因此可以认为本实施例中的支撑晶圆400能够用于构成封盖基板,以封闭下空腔在器件晶圆正面的开口。
需要说明的是,本实施例中,所述下空腔120的形成方法是:从正面刻蚀器件晶圆100,并从背面减薄所述器件晶圆100,以使下空腔120的开口从器件晶圆100的背面暴露出。
或者参考图3所示,在其他实施例中,所述下空腔120的形成方法还可以是:从所述器件晶圆的背面刻蚀所述器件晶圆,以形成所述晶体谐振器的下空腔120。以及,其他实施例中,从器件晶圆的背面刻蚀所述器件晶圆之前,还可以先减薄所述器件晶圆。
重点参考图3所示,在一个具体的实施例中,从器件晶圆背面刻蚀所述器件晶圆以形成下空腔的方法例如包括:
首先,从器件晶圆的背面减薄所述器件晶圆;当所述基底晶圆为绝缘体上硅晶圆时,则在减薄所述器件晶圆时可依次去除所述基底晶圆的底衬层和掩膜氧化层;当然,在减薄所述器件晶圆时,也可以选择部分去除所述底衬层,或者全部去除所述底衬层至暴露出所述掩埋氧化层等;
接着,从器件晶圆的背面刻蚀所述器件晶圆的掩埋氧化层,以形成所述下空腔。需要说明的是,刻蚀所述器件晶圆以形成下空腔的深度可根据实际需求调整,此处不做限制。例如,在减薄所述器件晶圆以暴露出顶硅层103时,则可刻蚀所述顶硅层103以在顶硅层中形成下空腔;或者,也可以刻蚀所述顶硅层并进一步刻蚀所述介质层100B,以使所形成的下空腔120从所述顶硅层103延伸至所述介质层100B中。
还需要说明的是,如图3所示的下空腔的形成方法中,在形成所述下空腔之前,可以选择在器件晶圆的正面上也键合一支撑晶圆,以辅助支撑所述器件晶圆;当然,也可以选择不键合支撑晶圆,并可进一步在器件晶圆的正面上形成塑封层,以覆盖暴露于器件晶圆正面的组件。
此外,如上所述,在其他实施例中,第一连接件中的第一导电插塞211a、第二连接件中的第二导插塞212a、第二连接结构中的第三导电插塞211b和第四导插塞212b可以在减薄所述器件晶圆以形成器件晶圆之后,从器件晶圆100的 背面上制备。
具体的,在器件晶圆100的正面上形成如上所述的连接线,并从器件晶圆100的背面上制备如上所述的导电插塞,以及使导电插塞与相应的连接线连接的方法包括:
首先,在键合所述支撑晶圆400之前,在所述器件晶圆100的正面上形成第一连接线221a、第二连接线222a、第三连接线221b和第四连接线222b;
其中,所述第一连接线221a电连接所述第一互连结构111a,所述第二连接线212a电连接所述第二互连结构112a,所述第三连接线221b电连接所述第三互连结构111b,所述第四连接线212b电连接所述第四互连结构112b;
接着,在减薄所述器件晶圆以形成所述器件晶圆100之后,从所述器件晶圆100的背面刻蚀器件晶圆以形成第一连接孔、第二连接孔、第三连接孔和第四连接孔,所述第一连接孔、第二连接孔、第三连接孔和第四连接孔均贯穿所述器件晶圆100,以分别暴露出第一连接线221a、第二连接线222a、第三连接线221b和第四连接线222b;
接着,在所述第一连接孔、第二连接孔、第三连接孔和第四连接孔中填充导电材料,以分别形成第一导电插塞211a、第二导电插塞212a、第三导电插塞211b和第四导电插塞212b。
其中,所述第一导电插塞211a的一端与第一连接线221a连接,所述第一导电插塞211a的另一端用于与所述压电谐振片下电极电连接,所述第二导电插塞212a的一端与第二连接线222a连接,所述第二导电插塞212a的另一端用于与所述压电谐振片上电极电连接,所述第三导电插塞211b的一端与第三连接线221b连接,所述第四导电插塞212b的一端与第四连接线222b连接,所述第三导电插塞212b和第四导电插塞212b的另一端均用于与所述半导体芯片电连接。
此外,另一实施例中,在器件晶圆100的背面上形成如上所述的连接线,并从器件晶圆100的背面上制备如上所述的导电插塞,以及使导电插塞与相应的连接线连接的方法包括:
首先,从所述器件晶圆100的背面减薄所述器件晶圆100,并从所述器件晶圆100的背面刻蚀所述器件晶圆以形成第一连接孔、第二连接孔、第三连接孔和第四连接孔;
接着,在所述第一连接孔、第二连接孔、第三连接孔和第四连接孔中填充 导电材料,以分别形成第一导电插塞、第二导电插塞、第三导电插塞和第四导电插塞,所述第一导电插塞的一端与所述第一互连结构电连接,所述第二导电插塞的一端与所述第二互连结构电连接,所述第三导电插塞的一端与所述第三互连结构电连接,所述第四导电插塞的一端与所述第四互连结构电连接;
接着,在所述器件晶圆100的背面上形成第一连接线、第二连接线、第三连接线和第四连接线,所述第一连接线的一端连接所述第一导电插塞的另一端,所述第一连接线的另一端用于电连接所述下电极,以及所述第二连接线的一端连接所述第二导电插塞的另一端,所述第二连接线的另一单用于电连接所述上电极,所述第三连接线的一端连接第三互连结构,所述第四连接线的一端连接所述第四互连结构,所述第三连接线和所述第四连接线的另一端均用于电连接所述半导体芯片。
在步骤S300中,具体参考图2g~2i所示,在所述器件晶圆100的背面(即,器件晶圆100背离所述支撑晶圆400的表面)上形成包括上电极530、压电晶片520和下电极510的压电谐振片500,所述压电谐振片500的边缘搭接在所述下空腔120的侧壁上,以使所述压电谐振片500对应所述下空腔120。
具体的,所述压电谐振片500的形成方法例如包括如下步骤。
步骤一,具体参考图2g所示,在所述器件晶圆100的背面(即,背离支撑晶圆400的表面)的设定位置上形成下电极510;本实施例中,所述下电极510围绕在所述下空腔120的外围并覆盖所述第一导电插塞211a,从而使所述下电极510通过所述第一导电插塞211a电性连接至所述第一电路111,并相应的使所述下电极510通过所述第一互连结构111a与所述第一晶体管电性连接。
其中,所述下电极510的材质例如银。以及,可依次利用薄膜沉积工艺、光刻工艺和刻蚀工艺形成所述下电极510;或者,也可以利用蒸镀工艺形成所述下电极510。
步骤二,继续参考图2g所示,键合压电晶片220至所述下电极210,所述压电晶片520的边缘搭接在所述下空腔120的侧壁上并位于所述下电极510上,以使所述压电晶片520对应所述下空腔120。其中,所述压电晶片520例如可以为石英晶片。
步骤三,继续参考图2h所示,在所述压电晶片520上形成上电极530。与下电极510类似的,所述上电极530也可以采用蒸镀工艺或薄膜沉积工艺形成, 其材质例如为银。在后续工艺中,使所述上电极530电性连接至所述控制电路。
需要说明的是,本实施例中,通过半导体工艺将所述下电极510、压电晶片520和上电极530依次形成在所述器件晶圆100上。然而,在其他实施例中,也可将上电极和下电极分别形成在压电晶片的两侧上,并将三者作为整体键合至所述器件晶圆100上。
此外,如上所述,所形成的压电谐振片500中,其下电极510通过第一连接件与第一电路电性连接,上电极530通过第二连接件与第二电路电性连接。
即,所述压电谐振片500在所述控制电路110的背面与所述控制电路110电性连接,从而可利用所述控制电路110对所述压电谐振片500的下电极510和上电极530施加电信号,从而可在下电极510和所述上电极530之间产生电场,进而使所述压电谐振片500的压电晶片520在所述电场的作用下发生机械形变。当压电谐振片500内的电场的方向相反时,则压电晶片520的形变方向也随之改变。因此,在利用所述控制电路110对压电谐振片500施加交流电时,则压电谐振片500的形变方向会随着电场的正负作收缩或膨胀的交互变化,从而产生机械振动。
其中,所述第一连接件包括第一导电插塞211a和第一连接线221a,以及所述下电极510位于所述压电晶片520的下方并从所述压电晶片520中延伸出,以使所述下电极510覆盖所述第一导电插塞211a,如此即可实现下电极510经由第一连接件电性连接至控制电路。
继续参考图2h所示,第二连接件包括第二导电插塞212a和第二连接线222a,并且还包括第五导电插塞610,所述第五导电插塞610的底部连接至所述第二导电插塞212a,以及所述第五导电插塞610的顶部连接至所述上电极530,并支撑所述上电极530。
具体的,所述第二连接件的第五导电插塞610和所述上电极530的形成方法包括:
首先,具体参考图2h所示,在形成所述上电极之前,在所述器件晶圆100的背面上形成塑封层600,所述塑封层600覆盖所述器件晶圆100并暴露出所述压电晶片520;其中所述塑封层600的材质例如包括聚酰亚胺;
接着,继续参考图2h所示,在所述塑封层600中形成通孔;本实施例中,所述通孔贯穿所述塑封层600以暴露出所述第二导电插塞212a;
接着,在所述通孔中填充导电材料以形成第五导电插塞610,所述第五导电插塞610的底部与所述第二导电插塞212a连接,所述第五导电插塞610的顶部暴露于所述塑封层600;
接着,具体参考图2h所示,在所述压电晶片520上形成上电极530,所述上电极530从所述压电晶片520延伸至所述塑封层600,以覆盖所述第五导电插塞610,从而使所述上电极530通过所述第五导电插塞610与所述第二导电插塞212a电性连接。
接着,具体参考图2i所示,去除所述塑封层600。
需要说明的是,其他实施例中,当第二连接件中的第二连接线形成在器件晶圆的背面上时,则所述第二连接件中的第三导电插塞的顶部即可与第二连接线连接。
当然,作为替代的方案中,所述第二连接件可以包括:第二连接线222a、第二导电插塞212a、第五导电插塞和互连线。其中,所述第五导电插塞的底部连接所述第二导电插塞212a,所述第五导电插塞的顶部连接所述互连线的一端,以及所述互连线的另一端至少部分覆盖上电极530以和所述上电极530连接。
具体的,形成替代方案中的第五导电插塞和互连线的方法例如包括:
首先,在所述器件晶圆100背离所述支撑晶圆400的表面上形成塑封层;此时可以在形成所述上电极530之后形成所述塑封层,并使所述塑封层暴露出所述上电极530;
接着,在所述塑封层中形成通孔,所述通孔贯穿所述塑封层以暴露出所述第二导电插塞212a,并在所述通孔中填充导电材料以形成第五导电插塞,所述第五导电插塞的底部与所述第二导电插塞212a连接;
接着,在所述塑封层上形成互连线,所述互连线至少部分覆盖所述上电极530,并从所述上电极530上延伸出以覆盖所述第五导电插塞,并去除所述塑封层。即,通过所述互连线和所述第五导电插塞实现上电极530电性连接至所述第二导电插塞212a。
在步骤S400中,具体参考图2j~图2k所示,在所述器件晶圆100的背面上形成封盖层720,所述封盖层720遮罩所述压电谐振片500,并与所述压电谐振片500及所述器件晶圆100围成所述晶体谐振器的上空腔700。
具体的,形成所述封盖层420以围出所述上空腔400的方法例如包括以下 步骤。
第一步骤,具体参考图2j所示,在所述器件晶圆100的表面上形成牺牲层710,所述牺牲层710覆盖所述压电谐振片500。
第二步骤,继续参考图2j所示,在所述器件晶圆100的表面上形成封盖材料层,所述封盖材料层覆盖所述牺牲层710的表面和侧壁,以包覆所述牺牲层710。
其中,所述牺牲层710所占据的空间,即对应后续需形成的上空腔。因此,可通过调整所述牺牲层的高度,以相应的调整最终所形成的上空腔的高度。应当认识到,所述上空腔的高度可根据实际需求相应的调整,此处不做限制。
进一步的,所述封盖材料层还从所述牺牲层710的侧壁底部进一步延伸覆盖所述器件晶圆100的背面,以覆盖所述第三导电插塞211b和第四导电插塞212b。
第三步骤,具体参考图2j和图2k所示,在所述封盖材料层中形成至少一个开口720a,以构成所述封盖层720,其中所述开口720a暴露出所述牺牲层710,并通过所述开口720a去除所述牺牲层,以形成所述上空腔700。
此时,所述压电谐振片500即封闭在所述上空腔700中,以使所述压电谐振片500能够在所述下空腔120和所述上空腔700中振动。
可选的方案中,具体参考图2l所示,还包括:封堵所述封盖层720上的所述开口,以封闭所述上空腔700,并使所述压电谐振片500封盖在所述上空腔700中。具体的,通过在所述开口中形成封堵插塞730,以密封所述上空腔700。
在步骤S500中,具体参考图2m所示,在所述器件晶圆100的背面上键合半导体芯片900,所述半导体芯片900通过第二连接结构电性连接至所述控制电路。
其中,所述半导体芯片中例如形成有驱动电路,所述驱动电路用于提供一电信号,所述电信号通过所述控制电路传输至所述压电谐振片500上,以控制所述压电谐振片500的机械形变。
如上所述,所述第二连接结构中,利用导电插塞和连接线将控制电路中用于与半导体芯片线路的连接端口引出至器件晶圆的背面。以及,在键合所述半导体芯片之前,所述第二连接结构的形成方法还包括:在所述器件晶圆的背面上形成接触垫,所述接触垫的底部电连接第二连接结构中的导电插塞,所述接触垫的顶部用于电连接所述半导体芯片。
本实施例中,所述封盖层720还延伸覆盖所述器件晶圆的背面,从而使封 盖层720还覆盖所述第三导电插塞和第四导电插塞。因此可以认为,本实施例中接触垫即形成在所述封盖层中,并贯穿所述封盖层。具体的,本实施例中的接触垫的形成方法例如包括:
首先,在所述封盖层720覆盖所述器件晶圆背面的部分中形成接触孔;本实施例中,形成接触孔包括形成第一接触孔和形成第二接触孔,所述第一接触孔和第二接触孔分别暴露出所述控制电路的第三互连结构111b和第四互连结构112b;以及,
接着,在所述接触孔中填充导电材料以形成接触垫,所述接触垫的底部电连接所述控制电路,所述接触垫的顶部用于电连接所述半导体芯片。本实施例中,即在所述第一接触孔和第二接触孔中填充导电材料,以分别形成第一接触垫910和第二接触垫920,其中所述第一接触垫910的底部电连接所述第三互连结构111b,所述第一接触垫920的顶部用于电连接所述半导体芯片900,所述第二接触垫920的底部电连接所述第四互连结构112b,所述第二接触垫920的顶部用于电连接所述半导体芯片900。
进一步的,所述半导体芯片相对于所述器件晶圆100构成异质芯片。即,所述半导体芯片的基底材质不同于所述器件晶圆100的基底材质。例如,本实施例中,器件晶圆100的基底材质为硅,则所述异质芯片的基底材质可以为III-V族半导体材料或Ⅱ-Ⅵ族半导体材料(具体例如包括锗、锗硅或砷化镓等)。
可选的方案中,具体参考图2n所示,在所述器件晶圆100上还形成塑封层800,所述塑封层800覆盖所述半导体芯片,以及覆盖所述封盖层720位于所述上空腔700外侧的外表面。
可以理解的是,利用所述塑封层800覆盖整个器件晶圆100的背面,以封盖塑封层800下方的结构并对塑封层800下方的结构进行保护。其中,所述塑封层800的材质例如包括光刻胶。
基于如上所述的形成方法,本实施例中对所形成的晶体谐振器与控制电路的集成结构进行说明,具体可参考图2a~图2n所示,所述晶体谐振器与控制电路的集成结构包括:
器件晶圆100,所述器件晶圆100中形成有控制电路,以及在所述器件晶圆100中还形成有下空腔120,所述下空腔120具有位于所述器件晶圆背面的开口;本实施例中,所述控制电路中的至少部分互连结构延伸至所述二器件晶圆100 的正面;
压电谐振片500,包括上电极530、压电晶片520和下电极510,所述压电谐振500形成在所述器件晶圆100的背面上并对应在所述下空腔120的上方;本实施例中,所述压电谐振片200的边缘搭接在所述下空腔120的侧壁上;
第一连接结构,形成在所述器件晶圆100上,用于使所述压电谐振片500的上电极530和下电极510均与所述控制电路电性连接;以及,
封盖层720,形成在所述器件晶圆100的背面上并遮罩所述压电谐振片500,并且所述封盖层720还与所述压电谐振片500及所述器件晶圆围成上空腔;
半导体芯片900,键合在所述器件晶圆100的背面上;以及,
第二连接结构,用于使所述半导体芯片900电连接至所述控制电路。
进一步的,所述半导体芯片900的基底材质不同于所述器件晶圆100的基底材质。例如,本实施例中,器件晶圆100的基底材质为硅,则所述异质芯片的基底材质可以为III-V族半导体材料或Ⅱ-Ⅵ族半导体材料(具体例如包括锗、锗硅或砷化镓等)。
通过在器件晶圆100中形成下空腔120,并可利用半导体工艺技术形成封盖层720,以将所述压电谐振片500封盖在上空腔700中,从而可确保所述压电谐振片500能够在所述上空腔700和所述下空腔120中震荡。由此,即可使晶体谐振器能够和控制电路集成在同一器件晶圆上。同时,还可进一步将半导体芯片键合至器件晶圆100上,进而可利用半导体芯片并经由所述控制电路110,实现片上调制晶体谐振器的温度漂移和频率矫正等原始偏差,有利于提高晶体谐振器的性能。可见,本实施例中的晶体谐振器,不仅能够提高器件的集成度,并且基于半导体工艺所形成的晶体谐振器其的尺寸更小,从而还能够进一步降低器件功耗。
继续参考图2a所示,所述控制电路包括第一电路111和第二电路112,所述第一电路111和所述第二电路112分别与所述压电谐振片500的上电极和下电极电性连接。
其中,所述第一电路111包括第一晶体管、第一互连结构111a和第三互连结构111b,所述第一晶体管掩埋在所述器件晶圆100中,所述第一互连结构111a和第三互连结构111b与所述第一晶体管电连接,并均延伸至所述器件晶圆100的正面。其中,所述第一互连结构111a与所述下电极210电性连接,所述第三 互连结构111b与所述半导体芯片电连接。
以及,所述第二电路112包括第二晶体管、第二互连结构112a和第四互连结构112b,所述第二晶体管掩埋在所述器件晶圆100中,所述第二互连结构112a和第四互连结构112b均与所述第二晶体管电连接,并均延伸至所述器件晶圆100的正面。其中,所述第二互连结构112a与所述上电极230电性连接,所述第四互连结构112b与所述半导体芯片电连接。
进一步的,所述第一连接结构包括第一连接件和第二连接件,所述第一连接件连接所述第一互连结构111a和所述压电谐振片的下电极510,所述第二连接件连接所述第二互连结构112a和所述压电谐振片的上电极530。
其中,所述第一连接件包括第一导电插塞211a,所述第一导电插塞211a贯穿所述器件晶圆100,以使所述第一导电插塞211a的一端延伸至所述器件晶圆100的正面并和所述第一互连结构电性连接,以及使所述第一导电插塞211a的另一端延伸至所述器件晶圆100的背面并和所述压电谐振片500的下电极510电性连接。
进一步的,所述第一连接件还包括第一连接线211。本实施例中,所述第一连接线221a形成在所述器件晶圆100的正面上,所述第一连接线221a连接所述第一导电插塞211a和所述第一互连结构111a。或者,在其他实施例中,所述第一连接线221a形成在器件晶圆100的背面上,并使所述第一连接线连接所述第一导电插塞和所述下电极。
本实施例中,所述下电极510形成在所述器件晶圆100的背面上,并位于所述下空腔120的外围,以及所述下电极510还横向延伸出所述压电晶片520以构成下电极延伸部,所述下电极延伸部覆盖所述第一导电插塞211a,以使所述下电极210与所述第一电路111的第一互连结构111a电性连接。
以及,所述第二连接件包括第二导电插塞212a,所述第二导电插塞212a贯穿所述器件晶圆100,以使所述第二导电插塞212a的一端延伸至所述器件晶圆100的正面并和所述第二互连结构电性连接,以及使所述第二导电插塞212a的另一端延伸至所述器件晶圆100的背面并和所述压电谐振片500的上电极530电性连接。
进一步的,所述第二连接件还包括第二连接线212。本实施例中,所述第二连接线222a形成在所述器件晶圆100的正面上,并使所述第二连接线222a连接 所述第二导电插塞212a和所述第二互连结构112a。或者,在其他实施例中,所述第二连接线222a形成在器件晶圆100的背面上,并使所述第二连接线连接所述第二导电插塞和所述上电极。
进一步的,所述第二连接件还包括:第五导电插塞610和互连线。所述第五导电插塞形成在所述器件晶圆100的背面上,并且所述第五导电插塞的底部与所述第二导电插塞212a连接。以及,所述互连线的一端覆盖所述上电极530,所述互连线的另一端至少部分覆盖所述第五导电插塞的顶部,以使所述互连线和所述第五导电插塞连接。应当认识到,此时还可利用所述第五导电插塞支撑所述互连线。
或者,所述第二连接件可仅包括第五导电插塞,并使所述第五导电插塞的一端电连接所述上电极530,所述第五导电插塞的另一端电连接所述第二导电插塞212a。例如,使所述上电极从压电晶片上延伸至所述第五导电插塞的端部上。
进一步的,所述第二连接结构包括导电插塞和连接线。其中,第二连接结构中的导电插塞贯穿所述器件晶圆100,以使所述导电插塞的一端延伸至所述器件晶圆100的正面,以及使所述导电插塞的另一端延伸至所述器件晶圆100的背面并和所述半导体芯片900电性连接,所述连接线形成在所述器件晶圆100的正面上,并使所述连接线连接所述导电插塞和所述控制电路。
本实施例中,所述第二连接结构的导电插塞包括第三导电插塞211b和第四导电插塞212b,以及第二连接结构的连接线包括第一连接线221b和第二连接线222b。其中,所述第三连接线221b连接所述第三导电插塞211b和所述第三互连结构111b,所述第四连接线222b连接所述第四导电插塞212b和所述第四互连结构112b。
可选的,所述第二连接结构还可包括接触垫,所述接触垫形成在器件晶圆的背面上,并且所述接触垫的底部电连接第二连接结构中的导电插塞,以及所述接触垫的顶部电连接所述半导体芯片。
继续参考图2n所示,本实施例中,所述封盖层720还从所述上空腔120的侧壁底部延伸覆盖所述器件晶圆100的表面,所述半导体芯片键合在所述封盖层720上,即半导体芯片900键合在封盖层720上。
基于此,则可使本实施例中的接触垫贯穿所述封盖层720,以使所述接触垫的底部电连接所述导电插塞,所述接触垫的顶部电连接所述半导体芯片900。
本实施例中,所述第二连接结构的接触垫包括第一接触垫910和第二接触垫920。其中,所述第一接触垫910的底部电连接所述第三导电插塞211b,所述第一接触垫910的顶部电连接所述半导体芯片900,以及第二接触垫920的底部电连接所述第四导电插塞212b,所述第二接触垫920的顶部电连接所述半导体芯片900。
继续参考图2n所示,本实施例中,所述器件晶圆100包括基底晶圆和介质层100B。其中,所述第一晶体管和所述第二晶体管均形成在所述基底晶圆上,所述介质层100B形成在所述基底晶圆上并覆盖所述第一晶体管和所述第二晶体管,以及所述第三互连结构、所述第一互连结构、所述第四互连结构和所述第二互连结构均形成在所述介质层100B中并延伸至所述介质层远离所述基底晶圆的表面。
进一步的,所述晶体谐振器还包括:塑封层800,形成在所述器件晶圆100的背面上,并且所述塑封层800覆盖所述半导体芯片900和所述封盖层720位于所述上空腔120外侧的外表面。即,利用所述塑封层800封盖整个器件晶圆背面上的结构,以对塑封层800下方的结构进行保护。
本实施例中,所述下空腔120贯穿所述器件晶圆100,从而使所述下空腔120还具有位于所述器件晶圆正面的开口。基于此,可选的方案中,在所述器件晶圆的正面上还键合有一封盖基板,以利用所述封盖基板封闭所述下空腔暴露于器件正面的开口,其中所述封盖基板例如可采用硅基底等构成。
综上所述,本发明提供的晶体谐振器与控制电路的集成方法中,可将晶体谐振器、控制电路和半导体芯片均集成在同一衬底上,有利于实现片上调制晶体谐振器的参数(例如,温度漂移和频率矫正等原始偏差等),从而可提高晶体谐振器的性能。
并且,相比于传统的晶体谐振器(例如,表面贴装型晶体谐振器),本发明中基于半导体平面工艺所形成的晶体谐振器,具备更小的尺寸,从而可相应的降低晶体谐振器的功耗。以及,本发明中的晶体谐振器更也易于与其他半导体元器件集成,有利于提高器件的集成度。
上述描述仅是对本发明较佳实施例的描述,并非对本发明范围的任何限定,本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰,均属于权利要求书的保护范围。
Claims (35)
- 一种晶体谐振器与控制电路的集成方法,其特征在于,包括:提供器件晶圆,所述器件晶圆中形成有控制电路;在所述器件晶圆中形成下空腔,所述下空腔具有位于所述器件晶圆背面的开口;在所述器件晶圆的背面上形成包括上电极、压电晶片和下电极的压电谐振片,所述压电谐振片对应所述下空腔,以及形成第一连接结构,用于使所述压电谐振片的上电极和下电极通过所述第一连接结构电性连接至所述控制电路;在所述器件晶圆的背面上形成封盖层,所述封盖层遮罩所述压电谐振片,并与所述压电谐振片及所述器件晶圆围成所述晶体谐振器的上空腔;以及,在所述器件晶圆的背面上键合半导体芯片,以及形成第二连接结构,所述半导体芯片通过所述第二连接结构电性连接至所述控制电路。
- 如权利要求1所述的晶体谐振器与控制电路的集成方法,其特征在于,所述器件晶圆包括基底晶圆和形成在所述基底晶圆上的介质层。
- 如权利要求2所述的晶体谐振器与控制电路的集成方法,其特征在于,所述基底晶圆为绝缘体上硅基底晶圆,包括沿着由所述背面至所述正面的方向依次层叠设置的底衬层、掩埋氧化层和顶硅层。
- 如权利要求1所述的晶体谐振器与控制电路的集成方法,其特征在于,所述下空腔的形成方法包括:从所述器件晶圆的正面刻蚀所述器件晶圆,以形成所述晶体谐振器的下空腔,并从所述器件晶圆的背面减薄所述器件晶圆,以暴露出所述下空腔,并在所述器件晶圆的正面键合封盖基板,以封闭所述下空腔在器件晶圆正面的开口;或者,所述下空腔的形成方法包括:从所述器件晶圆的背面刻蚀所述器件晶圆,以形成所述晶体谐振器的下空腔。
- 如权利要求4所述的晶体谐振器与控制电路的集成方法,其特征在于,所述器件晶圆包括绝缘体上硅衬底,包括沿着由背面至正面的方向依次层叠设置的底衬层、掩埋氧化层和顶硅层;其中,通过背面刻蚀所述器件晶圆以形成下空腔之前还包括去除所述底衬层和掩埋氧化层,以及从所述器件晶圆的背面刻蚀所述器件晶圆包括刻蚀所述顶硅层,以形成所述下空腔。
- 如权利要求1所述的晶体谐振器与控制电路的集成方法,其特征在于,所述压电谐振片的形成方法包括:在所述器件晶圆背面的设定位置上形成下电极;键合压电晶片至所述下电极;在所述压电晶片上形成所述上电极;或者,所述压电谐振片的上电极和下电极形成在压电晶片上,三者作为整体键合至所述器件晶圆的背面上。
- 如权利要求6所述的晶体谐振器与控制电路的集成方法,其特征在于,形成所述下电极的方法包括蒸镀工艺或薄膜沉积工艺;以及,形成所述上电极的方法包括蒸镀工艺或薄膜沉积工艺。
- 如权利要求1所述的晶体谐振器与控制电路的集成方法,其特征在于,所述控制电路包括第一互连结构和第二互连结构,所述连接结构包括第一连接件和第二连接件;其中,所述第一连接件连接所述第一互连结构和所述压电谐振片的下电极,所述第二连接件连接所述第二互连结构和所述压点谐振片的上电极。
- 如权利要求8所述的晶体谐振器与控制电路的集成方法,其特征在于,在形成所述下电极之前,形成所述第一连接件;其中,所述第一连接件包括位于所述器件晶圆中的第一导电插塞,所述第一导电插塞的两端分别用于与所述第一互连结构和所述下电极电连接;或者,所述第一连接件包括位于所述器件晶圆中的第一导电插塞以及位于所述器件晶圆背面且与所述第一导电插塞的一端电连接的第一连接线,所述第一导电插塞的另一端与所述第一互连结构电连接,所述第一连接线与所述下电极电连接;或者,所述第一连接件包括位于所述器件晶圆中的第一导电插塞以及位于所述器件晶圆正面且与所述第一导电插塞的一端电连接的第一连接线,所述第一导电插塞的另一端与下电极电连接,所述第一连接线与所述第一互连结构电连接。
- 如权利要求9所述的晶体谐振器与控制电路的集成方法,其特征在于,形成具有所述第一导电插塞和位于器件晶圆正面的第一连接线的第一连接件的方法包括:从所述器件晶圆的正面刻蚀所述器件晶圆以形成第一连接孔;在所述第一连接孔中填充导电材料,以形成第一导电插塞;在所述器件晶圆的正面上形成第一连接线,所述第一连接线连接所述第一导电插塞和所述第一互连结构;从所述器件晶圆的背面减薄所述器件晶圆,暴露出所述第一导电插塞,以用于与所述压电谐振片的下电极电连接;或者,形成具有所述第一导电插塞和位于器件晶圆正面的第一连接线的第一连接件的方法包括:在所述器件晶圆的正面上形成第一连接线,所述第一连接线电连接所述第一互连结构;从所述器件晶圆的背面减薄所述器件晶圆,并从所述器件晶圆的背面刻蚀所述器件晶圆以形成第一连接孔,所述第一连接孔贯穿所述器件晶圆,以暴露出所述第一连接线;以及,在所述第一连接孔中填充导电材料,以形成第一导电插塞,所述第一导电插塞的一端与第一连接线连接,所述第一导电插塞的另一端用于与所述压电谐振片的下电极电连接。
- 如权利要求9所述的晶体谐振器与控制电路的集成方法,其特征在于,形成具有所述第一导电插塞和位于器件晶圆背面的第一连接线的第一连接件的方法包括:从所述器件晶圆的正面刻蚀所述器件晶圆以形成第一连接孔;在所述第一连接孔中填充导电材料,以形成第一导电插塞,所述第一导电插塞与所述第一互连结构电连接;从所述器件晶圆的背面减薄所述器件晶圆,暴露出所述第一导电插塞;在所述器件晶圆的背面上形成第一连接线,所述第一连接线的一端连接所述第一导电插塞,所述第一连接线的另一端用于电连接所述下电极;或者,形成具有所述第一导电插塞和位于器件晶圆背面的第一连接线的第一连接件的方法包括:从所述器件晶圆的背面减薄所述器件晶圆,并从所述器件晶圆的背面刻蚀所述器件晶圆以形成第一连接孔;在所述第一连接孔中填充导电材料,以形成第一导电插塞,所述第一导电 插塞的一端与所述第一互连结构电连接;在所述器件晶圆的背面上形成第一连接线,所述第一连接线的一端连接所述第一导电插塞的另一端,所述第一连接线的另一端用于电连接所述下电极。
- 如权利要求9所述的晶体谐振器与控制电路的集成方法,其特征在于,所述下电极位于所述器件晶圆的背面上,并且所述下电极还从所述压电晶片延伸出以和所述第一连接件电性连接。
- 如权利要求8所述的晶体谐振器与控制电路的集成方法,其特征在于,在形成所述上电极之前,形成所述第二连接件;其中,所述第二连接件包括位于所述器件晶圆中的第二导电插塞,所述第二导电插塞的两端分别用于与所述第二互连结构和所述上电极电连接;或者,所述第二连接件包括位于所述器件晶圆中的第二导电插塞以及位于所述器件晶圆背面且与所述第二导电插塞的一端电连接的第二连接线,所述第二导电插塞的另一端与所述第二互连结构电连接,所述第二连接线与所述上电极电连接;或者,所述第二连接件包括位于所述器件晶圆中的第二导电插塞以及位于所述器件晶圆正面且与所述第二导电插塞的一端电连接的第二连接线,所述第二导电插塞的另一端与上电极电连接,所述第二连接线与所述第二互连结构电连接。
- 如权利要求13所述的晶体谐振器与控制电路的集成方法,其特征在于,形成具有所述第二导电插塞和位于器件晶圆正面的第二连接线的第二连接件的方法包括:从所述器件晶圆的正面刻蚀所述器件晶圆以形成第二连接孔;在所述第二连接孔中填充导电材料,以形成第二导电插塞;在所述器件晶圆的正面上形成第二连接线,所述第二连接线连接所述第二导电插塞和所述第二互连结构;从所述器件晶圆的背面减薄所述器件晶圆,暴露出所述第二导电插塞,以用于与所述压电谐振片的上电极电连接;或者,形成具有所述第二导电插塞和位于器件晶圆正面的第二连接线的第一连接件的方法包括:在所述器件晶圆的正面上形成第二连接线,所述第二连接线电连接所述第 二互连结构;从所述器件晶圆的背面减薄所述器件晶圆,并从所述器件晶圆的背面刻蚀所述器件晶圆以形成第二连接孔,所述第二连接孔贯穿所述器件晶圆,以暴露出所述第二连接线;以及,在所述第二连接孔中填充导电材料,以形成第二导电插塞,所述第二导电插塞的一端与第二连接线连接,所述第二导电插塞的另一端用于与所述压电谐振片的上电极电连接。
- 如权利要求13所述的晶体谐振器与控制电路的集成方法,其特征在于,形成具有所述第二导电插塞和位于器件晶圆背面的第二连接线的第二连接件的方法包括:从所述器件晶圆的正面刻蚀所述器件晶圆以形成第二连接孔;在所述第二连接孔中填充导电材料,以形成第二导电插塞,所述第二导电插塞与所述第二互连结构电连接;从所述器件晶圆的背面减薄所述器件晶圆,暴露出所述第二导电插塞;在所述器件晶圆的背面上形成第二连接线,所述第二连接线的一端连接所述第二导电插塞,所述第二连接线的另一端用于电连接所述上电极;或者,形成具有所述第二导电插塞和位于器件晶圆背面的第二连接线的第二连接件的方法包括:从所述器件晶圆的背面减薄所述器件晶圆,并从所述器件晶圆的背面刻蚀所述器件晶圆以形成第二连接孔;在所述第二连接孔中填充导电材料,以形成第二导电插塞,所述第二导电插塞的一端与所述第二互连结构电连接;在所述器件晶圆的背面上形成第二连接线,所述第二连接线的一端连接所述第二导电插塞的另一端,所述第二连接线的另一端用于电连接所述上电极。
- 如权利要求13所述的晶体谐振器与控制电路的集成方法,其特征在于,所述第二连接件的形成方法还包括:在所述器件晶圆的背面上形成塑封层;在所述塑封层中开设通孔,并在所述通孔中填充导电材料以形成第五导电插塞,所述第五导电插塞的底部电连接所述第二导电插塞,所述第五导电插塞的顶部暴露于所述塑封层;以及,在形成有所述上电极之后,所述上电极延伸出所述压电晶片至所述第五导电插塞的顶部,以使所述上电极和所述第五导电插塞电性连接;或者,在形成有所述上电极之后,在所述塑封层上形成互连线,所述互连线的一端覆盖所述上电极,所述互连线的另一端覆盖所述第五导电插塞,并去除所述塑封层。
- 如权利要求1所述的晶体谐振器与控制电路的集成方法,其特征在于,形成所述封盖层以围出所述上空腔的方法包括:在所述器件晶圆的背面上形成牺牲层,所述牺牲层覆盖所述压电谐振片;在所述器件晶圆的背面上形成封盖材料层,所述封盖材料层覆盖所述牺牲层的表面和侧壁,以包覆所述牺牲层;以及,在所述封盖材料层中形成至少一个开口,以构成所述封盖层,其中所述开口暴露出所述牺牲层,并通过所述开口去除所述牺牲层,以形成所述上空腔。
- 如权利要求17所述的晶体谐振器与控制电路的集成方法,其特征在于,在形成所述上空腔之后,还包括:封堵所述封盖层上的所述开口,以封闭所述上空腔,并使所述压电谐振片封盖在所述上空腔中。
- 如权利要求1所述的晶体谐振器与控制电路的集成方法,其特征在于,所述第二连接结构的形成方法包括:从所述器件晶圆的正面刻蚀所述器件晶圆以形成连接孔;在所述连接孔中填充导电材料,以形成导电插塞;在所述器件晶圆的正面上形成连接线,所述连接线连接所述导电插塞和所述控制电路;以及,从所述器件晶圆的背面减薄所述器件晶圆,暴露出所述导电插塞,以用于与所述半导体芯片电连接。
- 如权利要求1所述的晶体谐振器与控制电路的集成方法,其特征在于,所述第二连接结构的形成方法包括:在所述器件晶圆的正面上形成连接线,所述连接线电连接所述控制电路;并从所述器件晶圆的背面刻蚀所述器件晶圆以形成连接孔,所述连接孔均贯穿所述器件晶圆,以暴露出所述连接线;以及,在所述连接孔中填充导电材料以形成导电插塞,所述导电插塞的一端与连接线连接,所述导电插塞的另一端用于与所述半导体芯片电连接。
- 如权利要求19或20所述的晶体谐振器与控制电路的集成方法,其特征在于,所述第二连接结构的形成方法还包括:在所述器件晶圆的背面上形成接触垫,所述接触垫的底部电连接所述导电插塞,所述接触垫的顶部用于电连接所述半导体芯片。
- 如权利要求1所述的晶体谐振器与控制电路的集成方法,其特征在于,在键合所述半导体芯片之后,还包括:在所述器件晶圆的背面上形成塑封层,所述塑封层覆盖所述半导体芯片,以及覆盖所述封盖层位于所述上空腔外侧的外表面。
- 一种晶体谐振器与控制电路的集成结构,其特征在于,包括:器件晶圆,所述器件晶圆中形成有控制电路,以及在所述器件晶圆中还形成有下空腔,所述下空腔具有位于所述器件晶圆背面的开口;压电谐振片,包括上电极、压电晶片和下电极,所述压电谐振片形成在所述器件晶圆的背面上并对应所述下空腔;第一连接结构,形成在所述器件晶圆上,用于使所述压电谐振片的上电极和下电极均与所述控制电路电性连接;以及,封盖层,形成在所述器件晶圆的背面上并遮罩所述压电谐振片,并且所述封盖层还与所述压电谐振片及所述器件晶圆围成上空腔;半导体芯片,键合在所述器件晶圆的背面上;以及,第二连接结构,用于使所述半导体芯片电连接至所述控制电路。
- 如权利要求23所述的晶体谐振器与控制电路的集成结构,其特征在于,所述控制电路包括第一互连结构和第二互连结构,所述连接结构包括第一连接件和第二连接件;其中,所述第一连接件连接所述第一互连结构和所述压电谐振片的下电极,所述第二连接件连接所述第二互连结构和所述压点谐振片的上电极。
- 如权利要求24所述的晶体谐振器与控制电路的集成结构,其特征在于,所述第一连接件包括:第一导电插塞,贯穿所述器件晶圆,以使所述第一导电插塞的一端延伸至所述器件晶圆的正面并和所述第一互连结构电性连接,以及使所述第一导电插塞的另一端延伸至所述器件晶圆的背面并和所述压电谐振片的下电极电性连接。
- 如权利要求25所述的晶体谐振器与控制电路的集成结构,其特征在于,所述第一连接件还包括第一连接线;所述第一连接线形成在所述器件晶圆的正面上,并且所述第一连接线连接所述第一导电插塞和所述第一互连结构;或者,所述第一连接线形成在所述器件晶圆的背面上,并且所述第一连接线连接所述第一导电插塞和所述下电极。
- 如权利要求25所述的晶体谐振器与控制电路的集成结构,其特征在于,所述下电极位于所述器件晶圆的背面上,并且所述下电极还从所述压电晶片延伸出以和所述第一导电插塞电性连接。
- 如权利要求27所述的晶体谐振器与控制电路的集成结构,其特征在于,所述第二连接件包括:第二导电插塞,贯穿所述器件晶圆,以使所述第二导电插塞的一端延伸至所述器件晶圆的正面并和所述第二互连结构电性连接,以及使所述第二导电插塞的另一端延伸至所述器件晶圆的背面并和所述压电谐振片的上电极电性连接。
- 如权利要求28所述的晶体谐振器与控制电路的集成结构,其特征在于,所述第二连接件还包括第二连接线;第二连接线,形成在所述器件晶圆的正面上,所述第二连接线连接所述第二导电插塞和所述第二互连结构;或者,所述第二连接线形成在所述器件晶圆的背面上,并且所述第二连接线连接所述第二导电插塞和所述上电极。
- 如权利要求28所述的晶体谐振器与控制电路的集成结构,其特征在于,所述第二连接件还包括:第五导电插塞,形成在所述器件晶圆的背面上,并且所述第五导电插塞的一端电连接所述上电极,所述第五导电插塞的另一端电连接所述第二导电插塞。
- 如权利要求28所述的晶体谐振器与控制电路的集成结构,其特征在于,所述第二连接件还包括:第五导电插塞,形成在所述器件晶圆的背面上,并且所述第五导电插塞的底部电连接所述第二导电插塞;互连线,所述互连线的一端覆盖所述上电极,所述互连线的另一端覆盖所 述第五导电插塞的顶部。
- 如权利要求23所述的晶体谐振器与控制电路的集成结构,其特征在于,所述第二连接结构包括:导电插塞,贯穿所述器件晶圆,以使所述导电插塞的一端延伸至所述器件晶圆的正面,以及使所述导电插塞的另一端延伸至所述器件晶圆的背面并和所述半导体芯片电性连接;以及,连接线,形成在所述器件晶圆的正面上,所述连接线连接所述导电插塞和所述控制电路。
- 如权利要求32所述的晶体谐振器与控制电路的集成结构,其特征在于,所述第二连接结构还包括接触垫,所述接触垫的底部电连接所述导电插塞,所述接触垫的顶部电连接所述半导体芯片。
- 如权利要求23所述的晶体谐振器与控制电路的集成结构,其特征在于,所述封盖层中形成至少一个开口,并在所述开口中填充有封堵插塞,以封闭所述上空腔。
- 如权利要求23所述的晶体谐振器与控制电路的集成结构,其特征在于,还包括:塑封层,形成在所述器件晶圆的背面上,并且所述塑封层覆盖所述半导体芯片和所述封盖层位于所述上空腔外侧的外表面。
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