WO2020134600A1 - 晶体谐振器与控制电路的集成结构及其集成方法 - Google Patents

晶体谐振器与控制电路的集成结构及其集成方法 Download PDF

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Publication number
WO2020134600A1
WO2020134600A1 PCT/CN2019/115650 CN2019115650W WO2020134600A1 WO 2020134600 A1 WO2020134600 A1 WO 2020134600A1 CN 2019115650 W CN2019115650 W CN 2019115650W WO 2020134600 A1 WO2020134600 A1 WO 2020134600A1
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device wafer
wafer
piezoelectric
control circuit
substrate
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PCT/CN2019/115650
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English (en)
French (fr)
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秦晓珊
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中芯集成电路（宁波）有限公司上海分公司
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Priority to JP2021526567A priority Critical patent/JP2022510125A/ja
Priority to US17/419,529 priority patent/US20220085785A1/en
Publication of WO2020134600A1 publication Critical patent/WO2020134600A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/205—Constructional features of resonators consisting of piezoelectric or electrostrictive material having multiple resonators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
    • H03H9/0557—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement the other elements being buried in the substrate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H03H9/105—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a cover cap mounted on an element forming part of the BAW device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/125—Driving means, e.g. electrodes, coils
    • H03H9/13—Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/021—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the air-gap type

Definitions

  • the invention relates to the technical field of semiconductors, in particular to an integrated structure of a crystal resonator and a control circuit and an integrated method thereof.
  • the crystal resonator is a resonant device made by using the inverse piezoelectric effect of piezoelectric crystals. It is a key component of crystal oscillators and filters. It is widely used in high-frequency electronic signals to achieve accurate timing, frequency standards and filtering. An essential frequency control function in the signal processing system.
  • the size of various components also tends to be miniaturized.
  • the current crystal resonator is not only difficult to integrate with other semiconductor components, but also the size of the crystal resonator is large.
  • crystal resonators include surface mount crystal resonators, which specifically bond the base and the upper cover together by metal welding (or, adhesive glue) to form a closed cavity, crystal resonator
  • the piezoelectric resonant plate is located in the closed chamber, and the electrodes of the piezoelectric resonant plate are electrically connected to corresponding circuits through pads or leads.
  • the formed crystal resonator also needs to be electrically connected to the corresponding integrated circuit by soldering or bonding, thereby further limiting the crystal resonance The size of the device.
  • An object of the present invention is to provide an integrated method of a crystal resonator and a control circuit to solve the problem that the existing crystal resonator is large in size and not easy to integrate.
  • the present invention provides an integrated structure of a crystal resonator and a control circuit, including:
  • a piezoelectric resonance sheet including an upper electrode, a piezoelectric wafer, and a lower electrode formed on one of the front surface of the device wafer and the substrate ;
  • both the upper electrode and the lower electrode of the piezoelectric resonator plate are electrically connected to the control circuit;
  • a semiconductor chip is bonded on the back surface of the device wafer, and a second connection structure is formed, and the semiconductor chip is electrically connected to the control circuit through the second connection structure.
  • Another object of the present invention is to provide an integrated structure of a crystal resonator and a control circuit, including:
  • a substrate the substrate is bonded to the device wafer from the front of the device wafer, and an upper cavity is formed in the substrate, the opening of the upper cavity and the opening of the lower cavity are oppositely arranged;
  • a piezoelectric resonance plate includes an upper electrode, a piezoelectric wafer, and a lower electrode.
  • the piezoelectric resonance plate is located between the device wafer and the substrate, and two sides of the piezoelectric resonance plate correspond to the lower Cavity and the upper cavity;
  • a first connection structure for electrically connecting the upper electrode and the lower electrode of the piezoelectric resonator plate to the control circuit
  • a semiconductor chip bonded on the back of the device wafer.
  • the second connection structure is for electrically connecting the semiconductor chip to the control circuit.
  • a lower cavity and an upper cavity are respectively formed in the device wafer and the substrate through a semiconductor planar process, and the substrate and the device wafer are bonded using a bonding process to convert the piezoelectric
  • the resonator plate is sandwiched between the device wafer and the substrate, so that the control circuit and the crystal resonator can be integrated on the same device wafer.
  • the semiconductor chip can be further integrated on the back of the device wafer, which greatly improves the integration of the crystal resonator and can realize the on-chip modulation of the parameters of the crystal resonator (for example, the temperature drift and frequency correction of the crystal resonator Equal to the original deviation), is conducive to improving the performance of the crystal resonator.
  • the crystal resonator provided by the present invention not only enables the crystal resonator to be integrated with other semiconductor devices, but also improves the integration of the device; and, compared with traditional crystal resonators (for example, surface mount crystal resonators) ), the size of the crystal resonator provided by the present invention is smaller, which is beneficial to realize the miniaturization of the crystal resonator, and can reduce the manufacturing cost and reduce the power consumption of the crystal resonator.
  • FIG. 1 is a schematic flowchart of an integration method of a crystal resonator and a control circuit in Embodiment 1 of the present invention
  • FIGS. 2a to 2i are schematic structural views of the method for integrating the crystal resonator and the control circuit in the first embodiment of the present invention during its preparation process;
  • 3a to 3d are schematic structural views of the method for integrating the crystal resonator and the control circuit in the third embodiment of the present invention during its preparation process.
  • the core idea of the present invention is to provide an integrated structure of a crystal resonator and a control circuit and a shape integration method thereof. Both the crystal resonator and the semiconductor chip are integrated on a device wafer formed with a control circuit through a semiconductor planar process. On the one hand, the device size of the formed crystal resonator can be further reduced, and on the other hand, the crystal resonator can be integrated with other semiconductor components to improve the integration of the device.
  • FIG. 1 is a schematic flowchart of an integrated method of a crystal resonator and a control circuit in an embodiment of the present invention
  • FIGS. 2a to 2i are an integrated method of a crystal resonator and a control circuit in an embodiment of the present invention during its preparation process Schematic diagram of the structure. The steps of forming a crystal resonator in this embodiment will be described in detail below with reference to the drawings.
  • step S100 referring specifically to FIG. 2a, a device wafer 100 is provided, in which a control circuit 110 is formed.
  • the device wafer 100 has a front surface 100U and a back surface 100D opposite to each other.
  • the control circuit 110 includes a plurality of interconnect structures, and at least part of the interconnect structures extend to the front surface of the device wafer.
  • the control circuit 110 can be used to apply an electrical signal to a piezoelectric resonator plate formed later, for example.
  • multiple crystal resonators can be prepared on the same device wafer 100 at the same time, so a plurality of device areas AA are correspondingly defined on the device wafer 100, and the control circuit 110 is formed in the device area AA.
  • control circuit 110 includes a first circuit 111 and a second circuit 112, and the first circuit 111 and the second circuit 112 are used to be electrically connected to the upper electrode and the lower electrode of the piezoelectric resonator plate formed later .
  • the first circuit 111 includes a first transistor, a first interconnect structure 111a and a third interconnect structure 111b, the first transistor is buried in the device wafer 100, the first An interconnect structure 111a and a third interconnect structure 111b are both connected to the first transistor and extend to the front surface of the device wafer 100.
  • the first interconnect structure 111a is connected to the drain of the first transistor, for example, and the second interconnect structure 111b is connected to the source of the first transistor, for example.
  • the second circuit 112 includes a second transistor, a second interconnect structure 112a and a fourth interconnect structure 112b, the second transistor is buried in the device wafer 100, the second interconnect structure Both 112a and the fourth interconnect structure 112b are connected to the second transistor and extend to the front surface of the device wafer 100.
  • the second interconnect structure 112a is connected to the drain of the second transistor, and the fourth interconnect structure 112b is connected to the source of the second transistor, for example.
  • the device wafer 100 includes a base wafer 100A and a dielectric layer 100B formed on the base wafer 100A. And, both the first transistor and the second transistor are formed on the base wafer 100A, the dielectric layer 100B covers the first transistor and the second transistor, the third interconnect structure 111b, The first interconnect structure 111a, the second interconnect structure 112a, and the fourth interconnect structure 112b are all formed in the dielectric layer 100B and extend to the dielectric layer 100B away from the base wafer surface.
  • the base wafer 100A may be a silicon wafer or a silicon-on-insulator (SOI).
  • SOI silicon-on-insulator
  • the base wafer may specifically include an underlayer 101, a buried oxide layer 102, and a top silicon layer 103 that are sequentially stacked from the back surface 100D to the front surface 100U .
  • the interconnection structure of the control circuit 110 extends to the front surface 100U of the device wafer, and the semiconductor chip formed later will be disposed on the back surface 100D of the device wafer.
  • the second connection structure may be formed to lead the signal port of the control circuit 110 from the front surface of the device wafer to the back surface of the device wafer, so as to further electrically connect with the semiconductor chip formed later .
  • the second connection structure includes a conductive plug and a connection line
  • the conductive plug penetrates the device wafer 100
  • the connection line is formed on the front surface of the device wafer 100 and connects the conductive plug and The control circuit.
  • the conductive plug and the connecting wire in the second connection structure can be used to draw the connection port for connecting with the semiconductor chip in the control circuit from the front surface of the device wafer to the back surface of the device wafer.
  • the conductive plug of the second connection structure includes a first conductive plug 211b and a second conductive plug 212b
  • the connection line of the second connection structure includes a first connection line 221b and a second connection line 222b
  • the method for forming the conductive plug of the second connection structure and the connection line includes, for example, the following steps.
  • the device wafer 100 is etched from the front surface 100U of the device wafer to form a connection hole.
  • the first connection hole and the second connection hole are formed. Specifically, the bottoms of the first connection hole and the second connection hole are closer to the back surface 100D of the device wafer relative to the bottom of the control circuit.
  • the second step is to fill the connection hole with a conductive material to form a conductive plug.
  • the first connection hole and the second connection hole are filled with a conductive material to form a first conductive plug 211b and a second conductive plug 212b, respectively.
  • the bottoms of the first conductive plug 211b and the second conductive plug 212b are closer to the back surface 100D of the device wafer relative to the control circuit.
  • the first transistor 111T and the second transistor 112T are formed in the top silicon layer 103 and above the buried oxide layer 102, while the first conductive plug 211b and the second The conductive plug 212b penetrates through the dielectric layer 100B and the top silicon layer 103 in sequence, and stops at the buried oxide layer 102. It can be considered that when the etching process is performed to form the connection hole, the buried oxide layer 102 can be used as an etching stop layer to precisely control the etching accuracy of the etching process.
  • a connection line is formed on the front surface of the device wafer 100.
  • a first connection line 221b and a second connection line 222b are formed, the first connection line 221b connects the first conductive plug 211b and the third interconnection structure 111b, the second connection The line 222b connects the second conductive plug 212b and the fourth interconnection structure 112b.
  • the first conductive plug 211b and the second conductive plug 212b may be exposed from the back surface of the thinned device wafer 100 for use To be electrically connected to the semiconductor chip.
  • first conductive plug 211b and the second conductive plug 212b as described above are prepared from the front surface of the device wafer before forming the first connection line 221b and the second connection line 222b.
  • first conductive plug 211b and the second conductive plug 212b may also be prepared from the back side of the device wafer after the device wafer is subsequently thinned. The method of preparing the conductive plug from the back of the device wafer will be described in detail after the device wafer is thinned later.
  • step S200 referring specifically to FIG. 2c, the device wafer 100 is etched from the front surface of the device wafer 100 to form the lower cavity 120 of the crystal resonator. Specifically, the lower cavity 120 is exposed from the front surface 100U of the device wafer.
  • the lower cavity 120 is used, for example, to provide a vibration space for a piezoelectric resonator formed later.
  • the lower cavity 120 is formed in the dielectric layer 100B of the device wafer, and the lower cavity 120 is formed in each of the device regions AA. That is, the method of forming the lower cavity 120 includes: etching the dielectric layer 100B to the base wafer 100A to form the lower cavity 120 in the dielectric layer 100B.
  • the depth of the lower cavity 120 can be adjusted according to actual needs, which is not limited here.
  • the lower cavity 120 may be formed only in the dielectric layer 100B, or the lower cavity 120 may be further extended from the dielectric layer 100B to the base wafer 100A and the like.
  • the base wafer 100A may also be a silicon-on-insulator wafer. Then, when the lower cavity is formed, the top silicon layer may be further etched to extend the lower cavity from the dielectric layer to the buried oxide layer.
  • step S300 referring specifically to FIG. 2d, a substrate 300 is provided, and the substrate 300 is etched to form an upper cavity 310 of the crystal resonator, and the upper cavity 310 and the lower cavity 120 are correspondingly provided.
  • the depth of the upper cavity 310 can be adjusted according to actual needs, which is not limited herein.
  • the bonding substrate 300 device wafer 100 is subsequently formed, the upper cavity 310 and the lower cavity 120 respectively correspond to the two sides of the piezoelectric resonator plate.
  • a plurality of device areas AA are also defined on the substrate 300, a plurality of device areas of the device wafer 100 and a plurality of device areas of the substrate correspond to each other, and the lower cavity 120 That is, it is formed in the device area AA.
  • step S400 a piezoelectric resonance sheet including an upper electrode, a piezoelectric wafer, and a lower electrode is formed, and the upper electrode, the piezoelectric wafer, and the lower electrode are formed on the front surface of the device wafer 100 and the On one of the substrates 300.
  • the piezoelectric resonance sheet including the upper electrode, the piezoelectric wafer, and the lower electrode may be formed on the front surface of the device wafer 100, or may be formed on the substrate 300; or, the piezoelectric resonance The lower electrode of the sheet is formed on the front surface of the device wafer 100, and the upper electrode of the piezoelectric resonance sheet and the piezoelectric wafer are sequentially formed on the substrate 300; or, the lower electrode of the piezoelectric resonance sheet A piezoelectric wafer and a piezoelectric wafer are sequentially formed on the front surface of the device wafer 100, and an upper electrode of the piezoelectric resonator plate is formed on the substrate 300.
  • the upper electrode, the piezoelectric wafer, and the lower electrode of the piezoelectric resonator plate are all formed on the substrate 300.
  • the method of forming the piezoelectric resonator plate on the substrate 300 includes the following steps.
  • an upper electrode 530 is formed at a set position on the surface of the substrate 300.
  • the upper electrode 530 is located at the periphery of the upper cavity 310.
  • the upper electrode 530 is electrically connected to the control circuit 110, specifically the upper electrode 530 and the second The second interconnect structure of the circuit 112 is electrically connected.
  • Step two bonding the piezoelectric wafer 520 to the upper electrode 530.
  • the piezoelectric wafer 520 is located above the upper cavity 310, and the edge of the piezoelectric wafer 520 overlaps the upper electrode 530.
  • the piezoelectric wafer 520 may be a quartz wafer, for example.
  • the size of the upper cavity 310 is smaller than the size of the piezoelectric wafer 520, so that the edge of the piezoelectric wafer 520 is mounted on the surface of the substrate and covers the upper cavity 310 Opening.
  • the upper cavity has, for example, a first cavity and a second cavity, the first cavity is located in a deeper position of the substrate relative to the second cavity, and the second cavity is close to The surface of the substrate, and the size of the first cavity is smaller than the size of the piezoelectric wafer 520, and the size of the second cavity is larger than the size of the piezoelectric wafer.
  • the edge of the piezoelectric wafer 520 can be mounted on the first cavity, and the piezoelectric wafer 520 can be accommodated at least partially in the second cavity. At this time, it can be considered that the size of the opening of the upper cavity is larger than the width of the piezoelectric wafer.
  • the upper electrode 530 extends laterally from below the piezoelectric wafer 520 to form an upper electrode extension.
  • the upper electrode 530 can be connected to the second interconnect structure of the second circuit 112 through the upper electrode extension.
  • Step three specifically referring to FIG. 2e, a lower electrode 510 is formed on the piezoelectric wafer 520. Wherein, the lower electrode 510 may also expose the middle area of the piezoelectric wafer 520.
  • the lower electrode 510 is electrically connected to the control circuit 110, and specifically, the lower electrode 510 is electrically connected to the first interconnect structure of the first circuit 111.
  • the first circuit 111 is electrically connected to the lower electrode 510
  • the second circuit 112 is electrically connected to the upper electrode 530 to apply electrical signals to the lower electrode 510 and the upper electrode 530, respectively , So that an electric field can be generated between the lower electrode 510 and the upper electrode 530, so that the piezoelectric wafer 520 located between the upper electrode 530 and the lower electrode 510 can be mechanically generated under the action of the electric field deformation.
  • the piezoelectric wafer 520 may undergo a corresponding degree of mechanical deformation with the magnitude of the electric field, and when the electric field direction between the upper electrode 530 and the lower electrode 510 is opposite, the deformation direction of the piezoelectric wafer 520 also follows Change. Therefore, when alternating current is applied to the upper electrode 530 and the lower electrode 510 by the control circuit 110, the deformation direction of the piezoelectric wafer 520 will alternately contract or expand with the sign of the electric field, thereby generating mechanical vibration.
  • the method for forming the lower electrode 510 on the substrate 300 includes the following steps, for example.
  • a first plastic encapsulation layer 410 is formed on the substrate 300.
  • the first plastic encapsulation layer 410 covers the substrate 300 and exposes the piezoelectric wafer 520.
  • the upper electrode 530 is formed under the piezoelectric wafer 520 and extends laterally from the piezoelectric wafer 520 to form an upper electrode extension, so the first plastic encapsulation layer 410 also covers the upper electrode extension of the upper electrode 530.
  • the surface of the first plastic encapsulation layer 410 is not higher than the surface of the piezoelectric wafer 520.
  • the first plastic encapsulation layer 410 is formed by a planarization process so that the surface of the first plastic encapsulation layer 410 is flush with the surface of the piezoelectric wafer 520.
  • a lower electrode 510 is formed on the surface of the piezoelectric wafer 520, and the lower electrode 510 also extends laterally from the piezoelectric wafer 520 to the first molding layer 410 to constitute the lower electrode extension.
  • the lower electrode 510 can be connected to the control circuit (specifically connected to the first interconnect structure of the first circuit 111) through the lower electrode extension.
  • the material of the lower electrode 510 and the upper electrode 530 may include silver.
  • the upper electrode 530 and the lower electrode 510 may be formed in sequence using a thin film deposition process or an evaporation process.
  • the upper electrode 530, the piezoelectric wafer 520, and the lower electrode 510 are sequentially formed on the substrate 300 through a semiconductor process.
  • the upper electrode and the lower electrode may be formed on both sides of the piezoelectric wafer, respectively, and the three are bonded to the substrate as a whole.
  • the method further includes: forming a second plastic encapsulation layer on the first plastic encapsulation layer 410, so that the surface of the substrate 300 is flatter, thereby facilitating subsequent Bonding process.
  • a second plastic encapsulation layer 420 is formed on the first plastic encapsulation layer 410, the surface of the second plastic encapsulation layer 420 is not higher than the surface of the lower electrode 510 to expose the lower electrode 510 .
  • the second plastic encapsulation layer 420 may be formed through a planarization process so that the surface of the second plastic encapsulation layer 420 is flush with the surface of the lower electrode 510.
  • the second molding layer 420 can also expose the middle region of the piezoelectric wafer 520, so that when the substrate 300 is bonded to the device wafer 100 in a subsequent process, the The middle region of the piezoelectric wafer 520 corresponds to the lower cavity 120 of the device wafer 100.
  • a first connection structure is formed on the device wafer 100 or the substrate 300.
  • the first connection structure can be used to electrically connect the lower electrode 510 on the substrate 300 to the control circuit of the device wafer 100 (specifically connected to the first interconnect structure of the first circuit), And the upper electrode 530 on the substrate 300 is electrically connected to the control circuit of the device wafer 100 (specifically connected to the second interconnect structure of the second circuit).
  • the first connection structure includes a first connection member and a second connection member, wherein the first connection member connects the first interconnection structure 111a and the lower electrode 510 of the piezoelectric resonator plate, the The second connection member connects the second interconnection structure 112a and the upper electrode 530 of the piezoelectric resonator plate.
  • the lower electrode 510 is exposed on the surface of the second plastic encapsulation layer 420 and has a lower electrode extension, and the top of the first interconnect structure 111a is also exposed
  • the lower electrode 510 can be positioned on the front surface of the device wafer 100, and the lower electrode extension can be connected to the first One interconnect structure 111a.
  • the lower electrode extension of the lower electrode 510 directly constitutes the first connector.
  • the upper electrode 530 is buried in the first plastic encapsulation layer 410, so that the upper electrode extension of the upper electrode 530 can be further electrically connected to the second interconnection structure 112a through the second connector .
  • the upper electrode 530 and the piezoelectric wafer 520 are sequentially formed on the substrate 300, and then a second connector may be formed on the substrate 300.
  • the method for forming the second connector includes:
  • a plastic seal layer is formed on the surface of the substrate 300; in this embodiment, the first plastic seal layer 410 and the second plastic seal layer 420 constitute the plastic seal layer;
  • a through hole is opened in the plastic encapsulation layer, the through hole exposes the upper electrode 530, and a conductive material is filled in the through hole to form a conductive plug (for example, the first Three conductive plugs 230), one end of the third conductive plug 230 is electrically connected to the upper electrode 530. Specifically, the third conductive plug 230 is connected to the upper electrode extension of the upper electrode 530.
  • the second plastic encapsulation layer 420 and the first plastic encapsulation layer 410 are sequentially etched to form the through hole, and the through hole is filled with a conductive material to form a third conductive plug 230 ,
  • One end of the third conductive plug 230 is electrically connected to the upper electrode 530, and the other end of the third conductive plug 230 is exposed to the surface of the second plastic encapsulation layer 420, thereby bonding the device crystal
  • the circle 100 and the substrate 300 can electrically connect the other end of the third conductive plug 230 to the second interconnect structure.
  • step S600 specifically referring to FIG. 2h, the substrate 300 is bonded from the front surface of the device wafer 100 so that the piezoelectric resonance sheet 500 is located between the device wafer 100 and the substrate 300, And the upper cavity 310 and the lower cavity 120 are respectively located on both sides of the piezoelectric resonator plate 500 to form a crystal resonator. And, the upper electrode 530 and the lower electrode 510 of the piezoelectric resonator plate 500 are electrically connected to the control circuit through the first connection structure.
  • the first circuit 111 passes through the first connector (ie, the lower electrode extension)
  • the lower electrode 510 is electrically connected
  • the second circuit 112 is electrically connected to the upper electrode 530 through a second connector (including a third conductive plug 230).
  • the control circuit can apply electrical signals to both sides of the piezoelectric wafer 520 to deform the piezoelectric wafer 520 and vibrate in the upper cavity 310 and the lower cavity 120.
  • the bonding method of the device wafer 100 and the substrate 300 includes, for example, forming an adhesive layer on the device wafer 100 and/or the substrate 300, and using the adhesive layer to make the The device wafer 100 and the substrate 300 are bonded to each other.
  • the adhesive layer may be formed on the substrate on which the piezoelectric wafer is formed, and the surface of the piezoelectric wafer may be exposed to the surface of the adhesive layer, and then the adhesive layer and the The substrates on which the piezoelectric wafers are formed are bonded to each other.
  • the piezoelectric resonant sheet 500 is formed on the substrate 300, and the bonding method of the device wafer 100 and the substrate 300 includes, for example, forming an adhesive layer on the base 300, In addition, the surface of the piezoelectric resonant sheet 500 is exposed to the surface of the adhesive layer, and then the substrate 300 and the device wafer 100 can be bonded to each other using the adhesive layer.
  • the upper electrode 530, the piezoelectric wafer 520, and the lower electrode 510 of the piezoelectric resonant sheet 500 are all formed on the substrate 300, and the piezoelectric resonant sheet 500 covers the upper cavity 310 Opening, and after the bonding process is performed, the lower cavity 120 corresponds to the side of the piezoelectric resonator 500 facing away from the upper cavity 310 to form a crystal resonator, and the crystal resonator and the device wafer
  • the control circuit in 100 is electrically connected, thereby realizing the integrated setting of the crystal resonator and the control circuit.
  • step S700 specifically referring to FIG. 2i, a semiconductor chip 700 is bonded on the back surface of the device wafer, and the semiconductor chip 700 is electrically connected to the control circuit through the second connection structure.
  • a driving circuit is formed in the semiconductor chip 700, and the driving circuit is used to provide an electrical signal, and the electrical signal is applied to the piezoelectric resonator plate 500 through a control circuit to control the piezoelectric The mechanical deformation of the resonance sheet 500.
  • the semiconductor chip 700 forms a heterogeneous chip with respect to the device wafer 100. That is, the base material of the semiconductor chip 700 is different from the base material of the device wafer 100.
  • the base material of the device wafer 100 is silicon
  • the base material of the heterogeneous chip may be a III-V semiconductor material or a II-VI semiconductor material (specifically including germanium, silicon germanium or GaAs, etc.).
  • the second connection structure includes a conductive plug and a connection line, so that the connection line and the conductive plug are used to lead the connection port of the control circuit from the front surface of the device wafer to the device wafer the back of.
  • the device wafer before bonding the substrate 300, the device wafer may be etched from the front of the device wafer to form a conductive plug of the second connection structure, and a connection line of the second connection structure may be further formed.
  • the method before bonding the semiconductor chip, the method further includes: thinning the device wafer from the back surface of the device wafer 100 to expose the conductive plug. In this way, the subsequently bonded semiconductor chip 700 can be electrically connected to the conductive plug in the second connection structure.
  • the underlayer and the buried oxide layer are sequentially removed until the top silicon layer is exposed to expose the first The conductive plug and the second conductive plug.
  • the conductive plug may also be formed by etching the device wafer from the back of the device wafer 100.
  • the method for forming the second connection structure includes:
  • connection line is formed on the front surface of the device wafer 100, and the connection line is electrically connected to the control circuit; in this embodiment, A first connection line 221b and a second connection line 222b are formed on the front surface, the first connection line 221b is electrically connected to the third interconnection structure 111b, and the second connection line 222b is electrically connected to the fourth interconnection structure 112b;
  • connection hole penetrates the device wafer 100 to expose the connection line; in this embodiment, a connection is formed
  • the hole includes forming a first connection hole and a second connection hole, the first connection hole and the second connection hole respectively expose the first connection line 221b and the second connection line 222b;
  • the device wafer 100 may also be thinned from the back of the device wafer 100, In order to reduce the thickness of the device wafer. In this way, when the first connection hole and the second connection hole are formed, the depth of the formed connection hole can be reduced, which is beneficial to ensure the morphology of the formed connection hole.
  • connection hole a conductive material is filled in the connection hole to form a conductive plug, one end of the conductive plug is connected to the connection line, and the other end of the conductive plug is used to electrically connect the semiconductor chip.
  • the first conductive plug 211b and the second conductive plug 212b are formed correspondingly, one end of the first conductive plug 211b is connected to the first connection line 221b, and the first conductive plug 211b The other end of is used to electrically connect the semiconductor chip 700, one end of the second conductive plug 212b is connected to the second connection line 222b, and the other end of the second conductive plug 212b is used to electrically connect the semiconductor chip 700.
  • a plastic encapsulation layer may also be formed on the back surface of the device wafer to cover the semiconductor chip.
  • the substrate is preferentially bonded to the front surface of the device wafer, and then the semiconductor chip is bonded to the rear surface of the device wafer.
  • the semiconductor chip may be preferentially bonded on the back surface of the device wafer, and then the substrate may be bonded on the front surface of the device wafer.
  • the integration method of the crystal resonator and the control circuit includes:
  • a semiconductor chip is bonded on the back surface of the device wafer, and a second connection structure is formed, so that the semiconductor chip is electrically connected to the control circuit through the second connection structure;
  • a substrate is provided, and the substrate is bonded to the front surface of the device wafer, and a first connection structure is formed, so that the upper electrode and the lower electrode of the piezoelectric resonator plate are electrically connected through the first connection structure To the control circuit.
  • the upper electrode 530, the piezoelectric wafer 520 and the lower electrode 510 of the piezoelectric resonator plate 500 are all formed on the front surface of the device wafer 100, and the The piezoelectric resonator 500 covers the opening of the lower cavity 120, and the formed crystal resonator is electrically connected to the control circuit in the device wafer 100, and then performs a bonding process to make the upper cavity 310 correspond to the
  • the side of the piezoelectric resonator plate 500 facing away from the lower cavity 120 constitutes a crystal resonator, thereby achieving an integrated arrangement of the crystal resonator and the control circuit.
  • a device wafer with a control circuit and a method for forming a lower cavity in the device wafer can be referred to the first embodiment, and details are not described here.
  • the method of forming the piezoelectric resonance plate 500 on the device wafer 100 includes:
  • a lower electrode 510 is formed at a set position on the front surface of the device wafer 100; in this embodiment, the lower electrode 510 is located on the periphery of the lower cavity 120;
  • the piezoelectric wafer 520 is located above the lower cavity 120, and covers the opening of the lower cavity 120, and all The edge of the piezoelectric wafer 520 is mounted on the lower electrode 510;
  • the upper electrode 530 is formed on the piezoelectric wafer 520.
  • the upper electrode and the lower electrode may be formed on both sides of the piezoelectric wafer, respectively, and the three are bonded to the front surface of the device wafer 100 as a whole.
  • the lower electrode 510 and the piezoelectric wafer 520 are sequentially formed on the device wafer 100, and at this time, the first connection structure may also be formed on the device wafer 100.
  • the first connection structure includes a first connector for electrically connecting the lower electrode and a second connector for electrically connecting the upper electrode.
  • the lower electrode 510 extends relative to the piezoelectric wafer 520 to form a lower electrode extension, and the lower electrode extension can be electrically connected to the first interconnect structure, in which case the lower electrode extension can be considered That is, a first connection member is formed for connecting the lower electrode 510 to the control circuit.
  • the second connection member may be formed after forming the piezoelectric wafer 520 and before forming the upper electrode 530.
  • the method of forming the second connector before forming the upper electrode, and electrically connecting the second connector and the upper electrode includes the following steps.
  • Step 1 forming a plastic encapsulation layer on the front surface of the device wafer 100; in this embodiment, the plastic encapsulation layer covers the front surface of the device wafer 100 and exposes the piezoelectric wafer 520;
  • Step 2 Open a through hole in the plastic encapsulation layer, and fill the through hole with a conductive material to form a conductive plug (for example, a third conductive plug 230), the bottom of the third conductive plug 230 is electrically Connected to the second interconnect structure, the top of the third conductive plug is exposed to the plastic encapsulation layer;
  • a conductive plug for example, a third conductive plug 230
  • Step 3 After the upper electrode 530 is formed on the device wafer 100, the upper electrode 530 at least partially covers the piezoelectric wafer 520, and further extends from the piezoelectric wafer to the third conductive plug The top of the plug to electrically connect the upper electrode 530 and the conductive plug. That is, the upper electrode extension of the upper electrode 530 extending from the piezoelectric wafer is directly electrically connected to the third conductive plug 230.
  • an interconnection line may also be formed on the upper electrode 530, and the interconnection line extends from the upper electrode to the The top of the third conductive plug, so that the upper electrode is electrically connected to the third conductive plug through the interconnection line. That is, the upper electrode 530 is electrically connected to the third conductive plug through an interconnection line.
  • the piezoelectric resonator plate 500 is formed on the device wafer 100 and the upper cavity 310 is formed on the substrate 300, the device wafer 100 and the substrate 300 can be bonded.
  • the method of bonding the device wafer 100 and the substrate 300 includes: first, forming an adhesive layer on the device wafer 100 and exposing the surface of the piezoelectric wafer to the adhesive Then, using the adhesive layer, the device wafer 100 and the substrate 300 are bonded.
  • the upper cavity in the substrate 300 can correspond to the side of the piezoelectric wafer 520 facing away from the lower cavity.
  • the size of the upper cavity may be larger than that of the piezoelectric wafer, so that the piezoelectric wafer is located in the upper cavity.
  • the semiconductor chip is bonded to the substrate, and the semiconductor chip and the control circuit are electrically connected by the second connection structure.
  • the method of forming the second connection structure and bonding the semiconductor chip refer to Embodiment 1, which will not be repeated here.
  • the piezoelectric resonant plate including the upper electrode, the piezoelectric wafer, and the lower electrode are formed on the substrate or the device wafer.
  • the difference from the above embodiment is that in this embodiment, the upper electrode and the piezoelectric wafer are formed on the substrate, and the lower electrode is formed on the device wafer.
  • FIGS. 3a to 3d are schematic structural views of a method for integrating a crystal resonator and a control circuit in the third embodiment of the present invention during its preparation process. The steps of forming a crystal resonator in this embodiment will be described in detail below with reference to the drawings.
  • a device wafer 100 is provided, in which a control circuit is formed, and a lower electrode 510 is formed on the front surface of the device wafer 100, the lower electrode 510 and the first mutual The structure is electrically connected.
  • a wiring layer 610 may also be re-routed on the device wafer 100 at the same time, the re-wiring layer 610 covers the second interconnect structure.
  • the lower electrode 510 after being formed on the lower electrode 510, it further includes: forming a second plastic encapsulation layer 420 on the device wafer 100, the surface of the second plastic encapsulation layer 420 is not higher than the lower electrode 510, to The lower electrode 510 is exposed. In this embodiment, the surface of the second plastic encapsulation layer 420 is not higher than the surface of the redistribution layer 610 to expose the redistribution layer 610.
  • the lower electrode 510 can be disposed on one side of the piezoelectric wafer, and the rewiring layer 610 can be used to electrically connect the upper electrode on the other side of the piezoelectric wafer.
  • the second plastic encapsulation layer 420 can be formed by a planarization process so that the surface of the second plastic encapsulation layer 420 is flush with the surface of the lower electrode 510, so that the surface of the device wafer 100 can be effectively improved Degree, is conducive to the realization of subsequent bonding process.
  • the second plastic encapsulation layer 420 and the dielectric layer 100B are sequentially etched to form a hollow Cavity 120 and surround the lower electrode 510 around the lower cavity 120.
  • the device wafer is also etched from the front surface of the device wafer to form a conductive plug of the second connection structure (including the first conductive plug)
  • the plug 211b and the second conductive plug 212b), and the connection lines (including the first connection line 221b and the second connection line 222b) of the second connection structure are also formed on the front surface of the device wafer.
  • a substrate 300 is provided, and an upper electrode 530 and a piezoelectric wafer 520 are sequentially formed above the substrate 300 corresponding to the upper cavity.
  • the upper electrode may be formed by an evaporation process or a thin film deposition process, and the piezoelectric wafer is bonded to the upper electrode.
  • the upper electrode 530 surrounds the periphery of the upper cavity 310.
  • the upper electrode 530 is electrically connected to the redistribution layer 610 on the device wafer 100, so that the upper electrode 530 and the The second interconnection structure 112a of the second circuit 112 is electrically connected.
  • the middle region of the piezoelectric wafer 520 corresponds to the upper cavity 310 in the substrate 300, the edge of the piezoelectric wafer 520 overlaps the upper electrode 530, and the upper electrode 530 is separated from the piezoelectric wafer
  • the lower portion of 520 extends laterally to form an upper electrode extension.
  • the method further includes: forming a first plastic encapsulation layer 410 on the substrate 300, the first plastic encapsulation layer 410 covering the substrate 300 and The upper electrode extension of the upper electrode 530, and the surface of the first plastic encapsulation layer 410 is not higher than the surface of the piezoelectric wafer 520 to expose the piezoelectric wafer 520.
  • the first plastic encapsulation layer 410 can also be formed by a planarization process so that the surface of the first plastic encapsulation layer 410 is flush with the surface of the piezoelectric wafer 520, so that The surface of the substrate 300 is flatter, which facilitates the subsequent bonding process.
  • a conductive plug of a first connection structure is formed on the device wafer 100 or the substrate 300, so that after the subsequent device wafer 100 and the substrate 300 are bonded, the first A connection structure electrically connects the upper electrode 530 and the second interconnection structure.
  • the method for forming the conductive plug of the first connection structure includes:
  • a plastic encapsulation layer is formed on the surface of the substrate 100.
  • the plastic encapsulation layer includes the first plastic encapsulation layer 410;
  • the plastic encapsulation layer is etched to form a through hole; in this embodiment, the first plastic encapsulation layer 410 is etched, the through hole exposes the upper electrode extension of the upper electrode 530, and The through hole is filled with a conductive material to form a conductive plug (for example, a third conductive plug 230), and the top of the third conductive plug 230 is exposed to the surface of the first plastic encapsulation layer 410.
  • the third conductive plug 230 is connected to the upper electrode extension of the upper electrode 530.
  • the upper electrode 530 can be electrically connected to the second interconnection structure through the third conductive plug 230 and the redistribution layer 610.
  • the substrate 300 is bonded from the front surface of the device wafer so that the side of the piezoelectric wafer 520 facing away from the upper cavity 310 corresponds to the lower cavity 120, which is located at the
  • the lower electrode 510 on the device wafer 100 is correspondingly located on the side of the piezoelectric wafer 520 away from the upper electrode 530.
  • the method of bonding the device wafer 100 and the substrate 300 includes: first, forming an adhesive layer on the substrate 300 and exposing the surface of the piezoelectric wafer 520 to the adhesive Bonding layer; then, using the adhesive layer, bonding the device wafer and the substrate.
  • the rewiring layer 610 connected to the second interconnect structure on the device wafer 100 can be connected to the substrate 300 and the upper electrode 530
  • the third conductive plug 230 electrically contacts, so that the upper electrode 530 is electrically connected to the control circuit.
  • the crystal resonator includes:
  • at least part of the interconnect structure in the control circuit extends to the front surface of the device wafer 100;
  • the piezoelectric resonance plate 500 includes a lower electrode 510, a piezoelectric wafer 520, and an upper electrode 530.
  • the piezoelectric resonance plate 500 is located between the device wafer 100 and the substrate 300, and the piezoelectric resonance plate 500 The two sides of the respectively correspond to the lower cavity 120 and the upper cavity 310;
  • the first connection structure is used to electrically connect the upper electrode 530 and the lower electrode 510 of the piezoelectric resonator plate 500 to the control circuit;
  • a semiconductor chip 700 is bonded on the back surface of the device wafer 100; wherein, for example, a driving circuit is formed in the semiconductor chip 700 for generating an electrical signal, and transmitting the electrical signal to the pressure via the control circuit 100 Electric resonance piece 500;
  • the second connection structure is used to electrically connect the semiconductor chip 700 to the control circuit.
  • the semiconductor chip 700 may constitute a heterogeneous chip relative to the device wafer 100. That is, the base material of the semiconductor chip is different from the base material of the device wafer 100.
  • the base material of the device wafer 100 is silicon
  • the base material of the heterogeneous chip may be a III-V semiconductor material or a II-VI semiconductor material (specifically including germanium, silicon germanium or GaAs, etc.).
  • a lower cavity 120 and an upper cavity 310 are respectively formed on the device wafer 100 and the substrate 300, and the upper cavity 120 and the lower cavity 310 are corresponded through a bonding process, and are respectively provided on the piezoelectric
  • the control circuit is integrated on the same device wafer.
  • the semiconductor chip can be further bonded to the device wafer 100, and then the semiconductor chip can be used to realize the original deviations such as temperature drift and frequency correction of the on-chip modulated crystal resonator through the control circuit 110, which is beneficial to improve the crystal The performance of the resonator.
  • the crystal resonator in this embodiment can not only improve the integration of the device, but also the crystal resonator formed based on the semiconductor process has a smaller size, thereby further reducing the power consumption of the device.
  • control circuit includes a first circuit 111 and a second circuit 112, the first circuit 111 and the second circuit 112 are respectively connected to the upper electrode and the lower electrode of the piezoelectric resonator plate 500 Electrical connection.
  • the first circuit 111 includes a first transistor, a first interconnect structure 111a and a third interconnect structure 111b, the first transistor is buried in the device wafer 100, the first interconnect structure Both 111 a and the third interconnect structure 111 b are electrically connected to the first transistor, and both extend to the front surface of the device wafer 100.
  • the first interconnect structure 111a is electrically connected to the lower electrode 510, and the third interconnect structure 111b is electrically connected to the semiconductor chip.
  • the second circuit 112 includes a second transistor, a second interconnect structure 112a and a fourth interconnect structure 112b, the second transistor is buried in the device wafer 100, the second interconnect structure Both 112a and the fourth interconnect structure 112b are electrically connected to the second transistor, and both extend to the front surface of the device wafer 100.
  • the second interconnect structure 112a is electrically connected to the upper electrode 530, and the fourth interconnect structure 112b is electrically connected to the semiconductor chip.
  • the first connection structure includes a first connection member and a second connection member, the first connection member connects the first interconnection structure 111a and the lower electrode 510 of the piezoelectric resonator plate, the first Two connecting pieces connect the second interconnection structure 112a and the upper electrode 530 of the piezoelectric resonator plate.
  • the lower electrode 510 is formed on the front surface of the device wafer 100 and surrounds the periphery of the lower cavity 120, and the lower electrode 510 also extends laterally out of the piezoelectric wafer 520 To form a lower electrode extension which covers the first interconnect structure 111a of the first circuit 111 so that the first interconnect structure of the lower electrode 510 and the first circuit 111 111a is electrically connected. Therefore, it can be considered that the lower electrode extension constitutes the first connector.
  • the upper electrode 530 is formed on the piezoelectric wafer 520, and the upper electrode 530 is electrically connected to the second interconnection structure 112a of the second circuit 112 through the second connector .
  • the second connector includes a conductive plug (for example, a third conductive plug 230), one end of the third conductive plug 230 is electrically connected to the upper electrode 530, and the third conductive plug 230 The other end of is electrically connected to the second interconnection structure 112a.
  • the upper electrode 530 is extended from the piezoelectric wafer to the end of the third conductive plug.
  • a plastic encapsulation layer is further provided between the device wafer 100 and the substrate 300, the plastic encapsulation layer covers the sidewall of the piezoelectric wafer 520 and covers the upper electrode extension and the lower electrode extension .
  • the third conductive plug 230 in the second connector penetrates the plastic encapsulation layer, so that one end of the third conductive plug 230 is connected to the upper electrode extension, and the other end of the third conductive plug 230
  • the second interconnect structure is electrically connected.
  • the second connector may further include an interconnection line.
  • One end of the interconnection line covers the upper electrode 530, and the other end of the interconnection line at least partially covers the top of the third conductive plug, so that the upper electrode 530 passes through the interconnection line and the The third conductive plug is electrically connected to the control circuit.
  • the second connection structure for connecting the semiconductor chip 700 and the control circuit includes a conductive plug and a connection line, wherein the conductive plug in the second connection structure penetrates the device wafer 100 so that One end of the conductive plug extends to the front surface of the device wafer 100, and the other end of the conductive plug extends to the back surface of the device wafer 100 and is electrically connected to the semiconductor chip 700.
  • the connection line is formed on the front surface of the device wafer 100, and the connection line connects the conductive plug and the control circuit.
  • the conductive plug and the connecting wire are used to realize that the connection port for electrically connecting the semiconductor chip in the control circuit can be drawn out from the front surface of the device wafer to the back surface of the device wafer, so that the semiconductor chip can be placed on the device
  • the back side of the wafer is electrically connected to the control circuit from the back side of the device wafer.
  • the conductive plug of the second connection structure includes a first conductive plug 211b and a second conductive plug 212b
  • the connection line of the second connection structure includes a first connection line 221b and a second connection line 222b .
  • the first connection line 221b connects the first conductive plug 211b and the third interconnection structure 111b
  • the second connection line 222b connects the second conductive plug 212b and the fourth interconnection ⁇ 112b.
  • the device wafer 100 includes a base wafer 100A and a dielectric layer 100B.
  • the first transistor and the second transistor are both formed on the base wafer 100A
  • the dielectric layer 100B is formed on the base wafer 100A and covers the first transistor and the second transistor A transistor
  • the third interconnect structure 111b, the first interconnect structure 111a, the fourth interconnect structure 112b, and the second interconnect structure 112a are all formed in the dielectric layer 100B and extend to The surface of the dielectric layer 100B away from the base wafer 100A.
  • the integrated structure of the crystal resonator and the control circuit further includes a plastic encapsulation layer formed on the back surface of the device wafer and covering the semiconductor chip 700.
  • a lower cavity is formed in the device wafer, an upper cavity is formed in the substrate, and the device wafer and the substrate are bonded using a bonding process , To clamp the piezoelectric resonator between the device wafer and the substrate, and make the lower cavity and the upper cavity correspond to the two sides of the piezoelectric resonator, respectively, so that the control circuit and the crystal resonator are integrated in the same device On wafer.
  • a semiconductor chip formed with a driving circuit can be further bonded to the back surface of the device wafer, that is, the semiconductor chip, the control circuit, and the crystal resonator are all integrated on the same semiconductor substrate, thereby facilitating on-chip modulation Original deviations such as temperature drift and frequency correction of crystal resonators.
  • the crystal resonators formed based on the semiconductor planar process in the present invention have a smaller size, so that the crystal resonators can be reduced accordingly Power consumption.
  • the crystal resonator in the present invention is easier to integrate with other semiconductor components, which is beneficial to improve the integration of the device.

Abstract

一种晶体谐振器与控制电路的集成结构及其集成方法。通过在形成有控制电路的器件晶圆（100）中形成下空腔（120）以及在基板（300）中形成上空腔（310），并利用键合工艺使器件晶圆（100）和基板（300）键合，以将压电谐振片夹持在器件晶圆（100）和基板（300）之间，从而实现晶体谐振器和控制电路的集成设置。还可将半导体芯片（700）进一步键合至同一器件晶圆（100）的背面上。

Description

晶体谐振器与控制电路的集成结构及其集成方法 技术领域
本发明涉及半导体技术领域，特别涉及一种晶体谐振器与控制电路的集成结构及其集成方法。
背景技术
晶体谐振器是利用压电晶体的逆压电效应制成的谐振器件，是晶体振荡器和滤波器的关键元件，被广泛应用于高频电子信号，实现精确计时、频率标准和滤波等测量和信号处理系统中必不可少的频率控制功能。
随着半导体技术的不断发展，以及集成电路的普及，各种元器件的尺寸也趋于小型化。然而，目前的晶体谐振器不仅难以与其他半导体元器件集成，并且晶体谐振器的尺寸也较大。
例如，目前常见的晶体谐振器包括表面贴装型晶体谐振器，其具体是将基座和上盖通过金属焊接(或者，粘接胶)粘合在一起，以形成密闭腔室，晶体谐振器的压电谐振片位于所述密闭腔室中，并且使压电谐振片的电极通过焊盘或者引线与相应的电路电性连接。基于如上所述的晶体谐振器，其器件尺寸很难进一步缩减，并且所形成的晶体谐振器还需要通过焊接或者粘合的方式与对应的集成电路电性连接，从而进一步限制了所述晶体谐振器的尺寸。
发明内容
本发明的目的在于提供一种晶体谐振器与控制电路的集成方法，以解决现有的晶体谐振器其尺寸较大且不易于集成的问题。
为解决上述技术问题，本发明提供一种晶体谐振器与控制电路的集成结构，包括：
提供器件晶圆，所述器件晶圆中形成有控制电路；
从所述器件晶圆的正面刻蚀所述器件晶圆，以形成所述晶体谐振器的下空腔；
提供基板，并刻蚀所述基板以形成所述晶体谐振器的上空腔，所述上空腔和所述下空腔对应设置；
形成包括上电极、压电晶片和下电极的压电谐振片，所述上电极、所述压 电晶片和所述下电极形成在所述器件晶圆的正面和所述基板的其中之一上；
在所述器件晶圆或所述基板上形成第一连接结构；
在所述器件晶圆的正面上键合所述基板，以使所述压电谐振片位于所述器件晶圆和所述基板之间，以及使所述上空腔和所述下空腔分别位于所述压电谐振片的两侧，并通过所述第一连接结构使所述压电谐振片的上电极和下电极均与所述控制电路电性连接；以及，
在所述器件晶圆的背面上键合半导体芯片，以及形成第二连接结构，所述半导体芯片通过所述第二连接结构电性连接至所述控制电路。
本发明的又一目的在于提供一种晶体谐振器与控制电路的集成结构，包括：
器件晶圆，所述器件晶圆中形成有控制电路，以及在所述器件晶圆中还形成有下空腔，所述下空腔暴露于所述器件晶圆的正面；
基板，所述基板从所述器件晶圆的正面键合于所述器件晶圆上，并且所述基板中形成有上空腔，所述上空腔的开口和所述下空腔的开口相对设置；
压电谐振片，包括上电极、压电晶片和下电极，所述压电谐振片位于所述器件晶圆和所述基板之间，并且所述压电谐振片的两侧分别对应所述下空腔和所述上空腔；
第一连接结构，用于使所述压电谐振片的上电极和下电极电连接至所述控制电路；
半导体芯片，键合在所述器件晶圆的背面上；以及，
第二连接结构，用于使所述半导体芯片电连接至所述控制电路。
在本发明提供的晶体谐振器的集成方法中，通过半导体平面工艺分别在器件晶圆和基板中形成下空腔和上空腔，并利用键合工艺键合基板和器件晶圆，以将压电谐振片夹持在器件晶圆和基板之间，从而实现控制电路和晶体谐振器能够集成在同一器件晶圆上。同时，还可将半导体芯片进一步集成在该器件晶圆的背面上，大大提高了晶体谐振器的集成度，并可实现片上调制晶体谐振器的参数(例如，晶体谐振器的温度漂移和频率矫正等原始偏差)，有利于提高晶体谐振器的性能。
可见，本发明提供的晶体谐振器，不仅使晶体谐振器能够实现与其他半导体元器集成，提高器件的集成度；并且，相比于传统的晶体谐振器(例如，表面贴装型晶体谐振器)，本发明提供的晶体谐振器的尺寸更小，有利于实现晶体 谐振器的小型化，并能够减少制备成本和降低晶体谐振器的功耗。
附图说明
图1为本发明实施例一中的晶体谐振器与控制电路的集成方法的流程示意图；
图2a～图2i为本发明实施例一中的晶体谐振器与控制电路的集成方法在其制备过程中的结构示意图；
图3a～图3d为本发明实施例三中的晶体谐振器与控制电路的集成方法在其制备过程中的结构示意图。
其中，附图标记如下：
100-器件晶圆；AA-器件区；100U-正面；100D-背面；100A-基底晶圆；100B-介质层；110-控制电路；111-第一电路；111a-第一互连结构；111b-第三互连结构；112-第二电路；112a-第二互连结构；112b-第四互连结构；120-下空腔；211b-第一导电插塞；212b-第二导电插塞；221b-第一连接线；222b-第二连接线；230-第三导电插塞；410-第一塑封层；420-第二塑封层；500-压电谐振片；510-下电极；520-压电晶片；530-上电极；610-重新布线层；700-半导体芯片。
具体实施方式
本发明的核心思想在于提供了一种晶体谐振器与控制电路的集成结构及其形集成方法，通过半导体平面工艺将晶体谐振器和半导体芯片均集成在形成有控制电路的器件晶圆上。一方面，可以进一步缩减所形成的晶体谐振器的器件尺寸，另一方面，还可使所述晶体谐振器能够与其他半导体元器件集成，提高器件的集成度。
以下结合附图和具体实施例对本发明提出的晶体谐振器与控制电路的集成结构及其集成方法作进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
图1为本发明一实施例中的晶体谐振器与控制电路的集成方法的流程示意图，图2a～图2i为本发明一实施例中的晶体谐振器与控制电路的集成方法在其制备过程中的结构示意图。以下结合附图对本实施例中形成晶体谐振器的各个步骤进行详细说明。
在步骤S100中，具体参考图2a所示，提供一器件晶圆100，所述器件晶圆100中形成有控制电路110。
具体的，所述器件晶圆100具有相对的正面100U和背面100D，所述控制电110包括多个互连结构，并且至少部分互连结构延伸至所述器件晶圆的正面。其中，所述控制电路110例如可用于对后续形成的压电谐振片施加电信号。
其中，可以在同一器件晶圆100上同时制备多个晶体谐振器，因此在所述器件晶圆100上对应定义有多个器件区AA，所述控制电路110形成在所述器件区AA中。
进一步的，所述控制电路110包括第一电路111和第二电路112，所述第一电路111和第二电路112用于与后续所形成的压电谐振片的上电极和下电极电性连接。
继续参考图2a所示，所述第一电路111包括第一晶体管、第一互连结构111a和第三互连结构111b，所述第一晶体管掩埋在所述器件晶圆100中，所述第一互连结构111a和第三互连结构111b均与所述第一晶体管连接并延伸至所述器件晶圆100的正面。其中，所述第一互连结构111a例如连接所述第一晶体管的漏极，所述二互连结构111b例如连接所述第一晶体管的源极。
类似的，所述第二电路112包括第二晶体管、第二互连结构112a和第四互连结构112b，所述第二晶体管掩埋在所述器件晶圆100中，所述第二互连结构112a和第四互连结构112b均与所述第二晶体管连接并延伸至所述器件晶圆100的正面。其中，所述第二互连结构112a例如连接所述第二晶体管的漏极，所述第四互连结构112b例如连接所述第二晶体管的源极。
本实施例中，所述器件晶圆100包括基底晶圆100A和形成在所述基底晶圆100A上的介质层100B。以及，所述第一晶体管和所述第二晶体管均形成在所述基底晶圆100A上，所述介质层100B覆盖所述第一晶体管和第二晶体管，所述第三互连结构111b、所述第一互连结构111a、所述第二互连结构112a和所述第四互连结构112b均形成在所述介质层100B中并延伸至所述介质层100B的远离所述基底晶圆的表面。
此外，所述基底晶圆100A可以为硅晶圆，也可以为绝缘体上硅晶圆(silicon-on-insulator，SOI)。当所述基底晶圆100A为绝缘体上硅晶圆时，则所述基底晶圆可具体包括沿着由背面100D至正面100U依次层叠设置的底衬层 101、掩埋氧化层102和顶硅层103。
需要说明的是，本实施例中，所述控制电路110的互连结构延伸至器件晶圆的正面100U，而后续所形成的半导体芯片将设置在所述器件晶圆的背面100D。基于此，在后续工艺中，可通过形成第二连接结构，以实现将控制电路110的信号端口从器件晶圆的正面引出至器件晶圆的背面，以进一步和后续所形成半导体芯片电性连接。
具体的，第二连接结构包括导电插塞和连接线，所述导电插塞贯穿所述器件晶圆100，所述连接线形成在所述器件晶圆100的正面并连接所述导电插塞和所述控制电路。如此，即可利用所述第二连接结构中的导电插塞和连接线将所述控制电路中用于与半导体芯片连接的连接端口从所述器件晶圆的正面引出至器件晶圆的背面。
本实施例中，所述第二连接结构的导电插塞包括第一导电插塞211b和第二导电插塞212b，以及第二连接结构的连接线包括第一连接线221b和第二连接线222b。其中，所述第二连接结构的导电插塞和连接线的形成方法例如包括如下步骤。
第一步骤，从所述器件晶圆的正面100U刻蚀所述器件晶圆100以形成连接孔。本实施例中，即形成第一连接孔和第二连接孔。具体的，第一连接孔和第二连接孔的底部相对于所述控制电路的底部更靠近所述器件晶圆的背面100D。
第二步骤，具体参考图2b所示，在所述连接孔中填充导电材料，以形成导电插塞。本实施例中，即在所述第一连接孔和第二连接孔中填充导电材料，以分别形成第一导电插塞211b和第二导电插塞212b。
本实施例中，第一导电插塞211b和第二导电插塞212b的底部相对于所述控制电路更靠近所述器件晶圆的背面100D。具体而言，所述第一晶体管111T和所述第二晶体管112T形成在所述顶硅层103中，并位于所述掩埋氧化层102的上方，而所述第一导电插塞211b和第二导电插塞212b依次贯穿介质层100B和顶硅层103，并停止于所述掩埋氧化层102。可以认为，执行刻蚀工艺以形成连接孔时，可利用所述掩埋氧化层102作为刻蚀停止层，以精确控制刻蚀工艺的刻蚀精度。
第三步骤，继续参考图2b所示，在所述器件晶圆100的正面上形成连接线。本实施例中，即形成第一连接线221b和第二连接线222b，所述第一连接线221b 连接所述第一导电插塞211b和所述第三互连结构111b，所述第二连接线222b连接所述第二导电插塞212b和所述第四互连结构112b。
后续工艺中，在减薄所述器件晶圆的背面之后，即可使所述第一导电插塞211b和第二导电插塞212b从减薄后的器件晶圆100的背面暴露出，以用于与半导体芯片电连接。
需要说明的是，如上所述的第一导电插塞211b和第二导电插塞212b是在形成第一连接线221b和第二连接线222b之前从所述器件晶圆的正面制备。然而应当认识到，所述第一导电插塞211b和第二导电插塞212b也可以在后续减薄所述器件晶圆之后，从所述器件晶圆的背面制备。从器件晶圆的背面制备上述导电插塞的方法将在后续减薄所述器件晶圆之后，进行详细说明。
在步骤S200中，具体参考图2c所示，从所述器件晶圆100的正面刻蚀所述器件晶圆，以形成所述晶体谐振器的下空腔120。具体的，所述下空腔120从所述器件晶圆的正面100U暴露出，所述下空腔120例如用于为后续所形成的压电谐振片提供振动空间。
本实施例中，所述下空腔120形成在所述器件晶圆的所述介质层100B中，以及在每一所述器件区AA中均形成有所述下空腔120。即，形成所述下空腔120的方法包括：刻蚀所述介质层100B至所述基底晶圆100A，以在所述介质层100B中形成所述下空腔120。其中，所述下空腔120的深度可以根据实际需求调整，此处不做限定。例如，可使所述下空腔120仅形成在所述介质层100B中，或者可以使所述下空腔120从所述介质层100B进一步延伸至所述基底晶圆100A中等。
需要说明的是，附图中仅为示意性的标示出了下空腔120、第一电路和第二电路之间的位置关系，应当认识到在具体方案中可根据实际电路的布局对应调整第一电路和第二电路的的排布方式，此处不予限定。
此外，如上所述，所述基底晶圆100A还可以为绝缘体上硅晶圆。那么，在形成所述下空腔时，还可以进一步刻蚀顶硅层，以使所述下空腔从介质层进一步延伸至所述掩埋氧化层。
在步骤S300中，具体参考图2d所示，提供基板300，并刻蚀所述基板300以形成所述晶体谐振器的上空腔310，所述上空腔310和所述下空腔120对应设置。同样的，所述上空腔310的深度可以根据实际需求调整，此处不做限定。 在后续形成键合基板300器件晶圆100时，所述上空腔310和所述下空腔120分别对应在所述压电谐振片的两侧。
与所述器件晶圆100相对应的，所述基板300上也定义有多个器件区AA，器件晶圆100的多个器件区和基板的多个器件区相互对应，所述下空腔120即形成在所述器件区AA中。
在步骤S400中，形成包括上电极、压电晶片和下电极的压电谐振片，所述上电极、所述压电晶片和所述下电极形成在所述器件晶圆100的正面和所述基板300的其中之一上。
即，可使包括上电极、压电晶片和下电极的压电谐振片均形成在所述器件晶圆100的正面上，或均形成在所述基板300上；或者，使所述压电谐振片的下电极形成在所述器件晶圆100的正面上，所述压电谐振片的上电极和压电晶片依次形成在所述基板300上；或者，使所述压电谐振片的下电极和压电晶片依次形成在所述器件晶圆100的正面上，所述压电谐振片的上电极形成在所述基板300上。
本实施例中，所述压电谐振片的上电极、压电晶片和下电极均形成在所述基板300上。具体的，在所述基板300上形成所述压电谐振片的方法包括如下步骤。
步骤一，具体参考图2d所示，在所述基板300表面的设定位置上形成上电极530。本实施例中，所述上电极530位于所述上空腔310的外围，在后续工艺中，使所述上电极530与控制电路110电性连接，具体使所述上电极530与所述第二电路112的所述第二互连结构电性连接。
步骤二，继续参考图2d所示，键合压电晶片520至所述上电极530。本实施例中，所述压电晶片520位于所述上空腔310的上方，并且所述压电晶片520的边缘搭接在所述上电极530上。其中，所述压电晶片520例如可以为石英晶片。
本实施例中，所述上空腔310的尺寸小于所述压电晶片520的尺寸，以利于将所述压电晶片520的边缘搭载于所述基板的表面上并封盖所述上空腔310的开口。
然而，在其他实施例中，所述上空腔例如具有第一空腔和第二空腔，所述第一空腔相对于第二空腔位于所述基底的更深位置中，第二空腔靠近所述基底 的表面，并且第一空腔的尺寸小于所述压电晶片520的尺寸，以及第二空腔的尺寸大于压电晶片的尺寸。基于此，即可使所述压电晶片520的边缘搭载在所述第一空腔上，并使所述压电晶片520至少部分被容纳在所述第二空腔中。此时可以认为，所述上空腔的开口尺寸大于所述压电晶片的宽度尺寸。
进一步的，所述上电极530从所述压电晶片520的下方横向延伸出，以构成上电极延伸部。在后续工艺中，即可通过所述上电极延伸部使所述上电极530连接至所述第二电路112的第二互连结构。
步骤三，具体参考图2e所示，在所述压电晶片520上形成下电极510。其中，所述下电极510还可以暴露出所述压电晶片520的中间区域。在后续工艺中，使所述下电极510与控制电路110电性连接，具体的使下电极510与所述第一电路111的所述第一互连结构电性连接。
即，所述控制电路110中，第一电路111与下电极510电性连接，第二电路112与上电极530电性连接，以分别对所述下电极510和所述上电极530施加电信号，从而可在下电极510和所述上电极530之间产生电场，进而使位于所述上电极530和所述下电极510之间的所述压电晶片520能够在所述电场的作用下发生机械形变。其中，所述压电晶片520可随着所述电场的大小发生相应程度的机械形变，以及当上电极530和下电极510之间的电场方向相反时，则压电晶片520的形变方向也随之改变。因此，在利用所述控制电路110对上电极530和下电极510施加交流电时，则压电晶片520的形变方向会随着电场的正负作收缩或膨胀的交互变化，从而产生机械振动。
本实施例中，在所述基板300上形成所述下电极510的方法例如包括如下步骤。
第一步骤，具体参考图2e所示，在所述基板300上形成第一塑封层410，所述第一塑封层410覆盖所述基板300并暴露出所述压电晶片520。需要说明的是，本实施例中，所述上电极530形成在所述压电晶片520下方并从所述压电晶片520横向延伸出，以构成上电极延伸部，因此所述第一塑封层410还覆盖所述上电极530的上电极延伸部。
进一步的，所述第一塑封层410的表面不高于压电晶片520的表面。本实施例中，通过平坦化工艺形成所述第一塑封层410，以使所述第一塑封层410的表面与所述压电晶片520的表面齐平。
第二步骤，继续参考图2e所示，在所述压电晶片520的表面上形成下电极510，并且所述下电极510还从所述压电晶片520上横向延伸至所述第一塑封层410上，以构成下电极延伸部。在后续工艺中，即可通过所述下电极延伸部使所述下电极510连接至控制电路(具体连接至所述第一电路111的第一互连结构)。
其中，所述下电极510和所述上电极530的材质可均包括银。以及，可依次利用薄膜沉积工艺或蒸镀工艺形成所述上电极530和所述下电极510。
需要说明的是，本实施例中，通过半导体工艺将所述上电极530、压电晶片520和下电极510依次形成在所述基板300上。然而，在其他实施例中，也可将上电极和下电极分别形成在压电晶片的两侧上，并将三者作为整体键合至所述基板上。
可选的方案中，在形成所述下电极510之后，还包括：在所述第一塑封层410上形成第二塑封层，以使所述基板300的表面更为平坦，从而有利于后续的键合工艺。
具体参考图2f所示，在所述第一塑封层410上形成第二塑封层420，所述第二塑封层420的表面不高于所述下电极510的表面以暴露出所述下电极510。本实施例中，可通过平坦化工艺形成所述第二塑封层420，以使所述第二塑封层420的表面与所述下电极510的表面齐平。以及，所述第二塑封层420还可暴露出所述压电晶片520的中间区域，从而在后续工艺中将所述基板300键合至所述器件晶圆100上时，即可使所述压电晶片520的中间区域对应在器件晶圆100的下空腔120中。
在步骤S500中，在所述器件晶圆100或所述基板300上形成第一连接结构。在后续工艺，即可通过所述第一连接结构，实现基板300上的下电极510电性连接至器件晶圆100的控制电路上(具体连接至第一电路的第一互连结构上)，以及实现基板300上的上电极530电性连接至器件晶圆100的控制电路上(具体连接至第二电路的第二互连结构上)。
具体的，所述第一连接结构包括第一连接件和第二连接件，其中所述第一连接件连接所述第一互连结构111a和所述压电谐振片的下电极510，所述第二连接件连接所述第二互连结构112a和所述压电谐振片的上电极530。
具体的，参考图2g所示，本实施例中，所述下电极510暴露于所述第二塑封层420的表面并具有下电极延伸部，以及所述第一互连结构111a的顶部也暴 露于所述器件晶圆100的表面，因此在键合器件晶圆100和基板300时，即可以使下电极510位于所述器件晶圆100的正面上，并使下电极延伸部连接所述第一互连结构111a。此时可以认为，所述下电极510的下电极延伸部直接构成所述第一连接件。
接着参考图2g所示，所述上电极530掩埋在所述第一塑封层410中，因此可进一步通过第二连接件使上电极530的上电极延伸部电连接所述第二互连结构112a。
本实施例中，所述上电极530和所述压电晶片520依次形成在所述基板300上，进而可以在所述基板300上形成第二连接件。具体的，所述第二连接件的形成方法包括：
首先，在所述基板300的表面上形成塑封层；本实施例中，所述第一塑封层410和所述第二塑封层420即构成所述塑封层；
接着，具体参考图2g所示，在所述塑封层中开设通孔，所述通孔暴露出所述上电极530，并在所述通孔中填充导电材料以形成导电插塞(例如为第三导电插塞230)，所述第三导电插塞230的一端电连接所述上电极530。具体而言，所述第三导电插塞230与所述上电极530的上电极延伸部连接。
本实施例中，即依次刻蚀所述第二塑封层420和所述第一塑封层410，以形成所述通孔，并在所述通孔中填充导电材料以形成第三导电插塞230，所述第三导电插塞230的一端电连接所述上电极530，所述第三导电插塞230的另一端暴露于所述第二塑封层420的表面，从而在键合所述器件晶圆100和所述基板300时，可使所述第三导电插塞230的另一端电连接至所述第二互连结构。
在步骤S600中，具体参考图2h所示，从所述器件晶圆100的正面键合所述基板300，以使压电谐振片500位于所述器件晶圆100和所述基板300之间，以及使所述上空腔310和所述下空腔120分别位于所述压电谐振片500的两侧，以构成晶体谐振器。以及，通过所述第一连接结构使所述压电谐振片500的上电极530和下电极510均与所述控制电路电性连接。
如上所述，本实施例中，在键合所述器件晶圆100和所述基板300之后，所述控制电路中，第一电路111通过第一连接件(即，下电极延伸部)与所述下电极510电性连接，所述第二电路112通过第二连接件(包括第三导电插塞230)与所述上电极530电性连接。如此，即可通过所述控制电路，在所述压电 晶片520的两侧施加电信号，以使所述压电晶片520发生形变并在所述上空腔310和所述下空腔120振动。
其中，所述器件晶圆100和所述基板300的键合方法例如包括：在所述器件晶圆100和/或所述基板300上形成粘合层，并利用所述粘合层使所述器件晶圆100和所述基板300相互键合。具体的，可以在形成有压电晶片的基底上形成所述粘合层，并使所述压电晶片的表面暴露于所述粘合层的表面，接着，再利用所述粘合层和未形成有所述压电晶片的基底相互键合。
本实施例中，所述压电谐振片500形成在所述基板300上，则所述器件晶圆100和所述基板300的键合方法例如包括：在所述基底300上形成粘合层，并且所述压电谐振片500的表面暴露于所述粘合层的表面，接着即可利用所述粘合层使所述基板300和所述器件晶圆100相互键合。
即，本实施例中，所述压电谐振片500的上电极530、压电晶片520和下电极510均形成在所述基板300上，并使所述压电谐振片500封盖上空腔310的开口，以及在执行键合工艺之后使下空腔120对应在所述压电谐振片500背离所述上空腔310的一侧以构成晶体谐振器，并使所述晶体谐振器与器件晶圆100中的控制电路电性连接，由此实现了晶体谐振器和控制电路的集成设置。
在步骤S700中，具体参考图2i所示，在所述器件晶圆的背面上键合半导体芯片700，所述半导体芯片700通过所述第二连接结构电性连接至所述控制电路。
其中，所述半导体芯片700中例如形成有驱动电路，所述驱动电路用于提供一电信号，所述电信号通过控制电路被施加在所述压电谐振片500上，以控制所述压电谐振片500的机械形变。
进一步的，所述半导体芯片700相对于所述器件晶圆100构成异质芯片。即，所述半导体芯片700的基底材质不同于所述器件晶圆100的基底材质。例如，本实施例中，器件晶圆100的基底材质为硅，则所述异质芯片的基底材质可以为III-V族半导体材料或Ⅱ-Ⅵ族半导体材料(具体例如包括锗、锗硅或砷化镓等)。
如上所述，所述第二连接结构包括导电插塞和连接线，以利用所述连接线和所述导电插塞，将所述控制电路的连接端口从器件晶圆的正面引出至器件晶圆的背面。
其中，可以在键合所述基板300之前，从器件晶圆的正面刻蚀器件晶圆以 形成所述第二连接结构的导电插塞，并进一步形成第二连接结构的连接线。此时，在键合所述半导体芯片之前，还包括：从器件晶圆100的背面减薄所述器件晶圆，以暴露出所述导电插塞。如此，即可使后续键合的半导体芯片700能够与第二连接结构中的导电插塞电连接。
本实施例中，从器件晶圆100的背面减薄所述器件晶圆时，即依次去除所述底衬层和所述掩埋氧化层，直至所述顶硅层，以暴露出所述第一导电插塞和所述第二导电插塞。
或者，在其他实施例中，第二连接结构的形成方法中，所述导电插塞也可以从器件晶圆100的背面刻蚀所述器件晶圆以形成。例如，在其他实施例中，所述第二连接结构的形成方法包括：
首先，在键合所述基板300之前，在所述器件晶圆100的正面上形成连接线，所述连接线电连接所述控制电路；本实施例中，即在所述器件晶圆100的正面上形成有第一连接线221b和第二连接线222b，所述第一连接线221b电连接所述第三互连结构111b，所述第二连接线222b电连接所述第四互连结构112b；
接着，从所述器件晶圆100的背面刻蚀所述器件晶圆以形成连接孔，所述连接孔贯穿所述器件晶圆100，以暴露出所述连接线；本实施例中，形成连接孔时包括形成第一连接孔和第二连接孔，所述第一连接孔和所述第二连接孔分别暴露出所述第一连接线221b和所述第二连接线222b；
此外，具体参考图2i所示，在刻蚀所述器件晶圆以形成第一连接孔和第二连接孔之前，还可以从所述器件晶圆100的背面减薄所述器件晶圆100，以缩减所述器件晶圆的厚度。如此一来，在形成第一连接孔和第二连接孔时，即可降低所形成的连接孔的深度，有利于保障所形成的连接孔的形貌。
接着，在所述连接孔中填充导电材料，以形成导电插塞，所述导电插塞的一端与所述连接线连接，所述导电插塞的另一端用于电连接所述半导体芯片。
本实施例中，即相应的形成有第一导电插塞211b和第二导电插塞212b，所述第一导电插塞211b的一端与第一连接线221b连接，所述第一导电插塞211b的另一端用于电连接所述半导体芯片700，所述第二导电插塞212b的一端与第二连接线222b连接，所述第二导电插塞212b的另一端用于电连接所述半导体芯片700。
在后续工艺中，还可在所述器件晶圆的背面上形成塑封层，以封盖所述半 导体芯片。
此外需要说明的是，本实施例中，是优先在器件晶圆的正面上键合基板，接着在器件晶圆的背面上键合半导体芯片。然而，在其他实施例中，还可以优先在器件晶圆的背面上键合半导体芯片，接着在器件晶圆的正面上键合基板。
具体的，在另一个实施例中，晶体谐振器与控制电路的集成方法包括：
首先，在所述器件晶圆的背面上键合半导体芯片，以及形成第二连接结构，以使所述半导体芯片通过所述第二连接结构电性连接至所述控制电路；
接着，从所述器件晶圆的正面刻蚀所述器件晶圆，以形成所述晶体谐振器的下空腔；
接着，提供基板，并将基板键合在所述器件晶圆的正面，并形成第一连接结构，以使所述压电谐振片的上电极和下电极通过所述第一连接结构电性连接至所述控制电路。
实施例二
与实施例一的区别在于，本实施例中，所述压电谐振片500的上电极530、压电晶片520和下电极510均形成在所述器件晶圆100的正面上，并使所述压电谐振片500封盖下空腔120的开口，以及所形成的晶体谐振器与器件晶圆100中的控制电路电性连接，接着再执行键合工艺，以使上空腔310对应在所述压电谐振片500背离所述下空腔120的一侧以构成晶体谐振器，由此实现了晶体谐振器和控制电路的集成设置。
本实施例中，提供具有控制电路的器件晶圆，以及在所述器件晶圆中形成下空腔的方法可参考实施例一所，此处不做赘述。
以及，本实施例中将所述压电谐振片500形成在所述器件晶圆100上的方法包括：
首先，在所述器件晶圆100正面的设定位置上形成下电极510；本实施例中，所述下电极510位于所述下空腔120的外围；
接着，键合压电晶片520至所述下电极510；本实施例中，所述压电晶片520位于所述下空腔120的上方，并封盖所述下空腔120的开口，以及所述压电晶片520的边缘搭载在所述下电极510上；
接着，在所述压电晶片520上形成所述上电极530。
当然，在其他实施例中，也可将上电极和下电极分别形成在压电晶片的两 侧上，并将三者作为整体键合至所述器件晶圆100的正面上。
进一步的，本实施例中，所述下电极510和所述压电晶片520依次形成在所述器件晶圆100上，此时可将第一连接结构也形成在所述器件晶圆100上。具体的，所述第一连接结构包括用于电连接下电极的第一连接件和用于电连接上电极的第二连接件。
其中，所述下电极510相对于所述压电晶片520延伸出以构成下电极延伸部，所述下电极延伸部能够与第一互连结构电连接，此时可以认为所述下电极延伸部即构成了第一连接件，用于实现下电极510与控制电路连接。
进一步的，所述第二连接件可以在形成所述压电晶片520之后，以及形成所述上电极530之前形成。具体的，在形成所述上电极之前形成所述第二连接件，并使所述第二连接件和上电极电性连接的方法包括如下步骤。
步骤一，在所述器件晶圆100的正面上形成塑封层；本实施例中，所述塑封层覆盖所述器件晶圆100的正面并暴露出所述压电晶片520；
步骤二，在所述塑封层中开设通孔，并在所述通孔中填充导电材料以形成导电插塞(例如为第三导电插塞230)，所述第三导电插塞230的底部电性连接至所述第二互连结构，所述第三导电插塞的顶部暴露于所述塑封层；
步骤三，在所述器件晶圆100上形成所述上电极530之后，所述上电极530至少部分覆盖所述压电晶片520，并进一步延伸出所述压电晶片至所述第三导电插塞的顶部，以使所述上电极530和所述导电插塞电性连接。即，所述上电极530中从压电晶片延伸出的上电极延伸部直接与所述第三导电插塞230电性连接。
或者，步骤三中，在形成所述上电极530于所述压电晶片520上之后，还可在所述上电极530上形成互连线，所述互连线从所述上电极延伸至所述第三导电插塞的顶部，以使所述上电极通过所述互连线和所述第三导电插塞电性连接。即，在所述上电极530通过一互连线与所述第三导电插塞电性连接。
进一步的，在器件晶圆100上形成有所述压电谐振片500，以及在基板300上形成所述上空腔310之后，即可键合所述器件晶圆100和所述基板300。
具体的，键合所述器件晶圆100和所述基板300的方法包括：首先，在所述器件晶圆100上形成粘合层，并使所述压电晶片的表面暴露于所述粘合层；接着，利用所述粘合层，键合所述器件晶圆100和所述基板300。
执行键合工艺之后，即可使基板300中的上空腔对应在所述压电晶片520背离所述下空腔的一侧。其中，所述上空腔的尺寸可以大于所述压电晶片的尺寸，从而使所述压电晶片位于所述上空腔内。
本实施例中，在器件晶圆和基板相互键合之后，在所述基板上键合半导体芯片，并通过第二连接结构，使半导体芯片和控制电路电连接。其中，形成所述第二连接结构并键合所述半导体芯片的方法可参考实施例一，此处不做赘述。
实施例三
实施例一和实施例二中，包括上电极、压电晶片和下电极的压电谐振片均形成在基板或所述器件晶圆上。而与上述实施例的区别在于，本实施例中上电极和压电晶片形成在基板上，下电极形成在器件晶圆上。
图3a～图3d为本发明实施例三中的晶体谐振器与控制电路的集成方法在其制备过程中的结构示意图，以下结合附图对本实施例中形成晶体谐振器的各个步骤进行详细说明。
首先参考图3a所示，提供器件晶圆100，所述器件晶圆100中形成有控制电路，并在所述器件晶圆100的正面上形成下电极510，所述下电极510与第一互连结构电连接。
此外，在形成所述下电极510时，还可同时在所述器件晶圆100上重新布线层610，所述重新布线层610覆盖所述第二互连结构。
进一步的，在形成在所述下电极510之后，还包括：在所述器件晶圆100上形成第二塑封层420，所述第二塑封层420的表面不高于所述下电极510，以暴露出所述下电极510。本实施例中，所述第二塑封层420的表面也不高于重新布线层610的表面，以暴露出所述重新布线层610。在后续执行键合工艺之后，即可使所述下电极510设置在压电晶片的一侧，以及使重新布线层610用于与位于压电晶片另一侧的上电极电性连接。
其中，可通过平坦化工艺形成所述第二塑封层420，以使所述第二塑封层420的表面与所述下电极510的表面齐平，如此即可有效提高器件晶圆100的表面平坦度，有利于实现后续的键合工艺。
继续参考图3a所述，本实施例中，在依次形成所述下电极510和所述第二塑封层420之后，依次刻蚀所述第二塑封层420和所述介质层100B以形成下空腔120，并使所述下电极510围绕在所述下空腔120的外围。
此外，和实施例一类似的，本实施例中在形成第二连接结构时，也是从器件晶圆的正面刻蚀器件晶圆，以形成第二连接结构的导电插塞(包括第一导电插塞211b和第二导电插塞212b)，以及在器件晶圆的正面上还形成有第二连接结构的连接线(包括第一连接线221b和第二连接线222b)。
接着参考图3b所示，提供基板300，并在基板300对应上空腔的上方依次形成上电极530和压电晶片520。其中，所述上电极可以利用蒸镀工艺或者薄膜沉积工艺形成，以及所述压电晶片键合至所述上电极上。
具体的，所述上电极530围绕在上空腔310的外围，在后续工艺中，使所述上电极530电性连接器件晶圆100上的重新布线层610，以使所述上电极530与所述第二电路112的所述第二互连结构112a电性连接。以及，所述压电晶片520的中间区域对应基板300中的上空腔310，所述压电晶片520的边缘搭接在所述上电极530上，并且所述上电极530从所述压电晶片520的下方横向延伸出，以构成上电极延伸部。
继续参考图3b所示，本实施例中，在形成所述压电晶片520之后还包括：在所述基板300上形成第一塑封层410，所述第一塑封层410覆盖所述基板300和所述上电极530的上电极延伸部，并且所述第一塑封层410的表面不高于压电晶片520的表面，以暴露出所述压电晶片520。
类似的，本实施例中，也可通过平坦化工艺形成所述第一塑封层410，以使所述第一塑封层410的表面与所述压电晶片520的表面齐平，如此即可所述基板300的表面更为平坦，从而有利于后续的键合工艺。
接着参考图3c所示，在所述器件晶圆100或所述基板300上形成第一连接结构的导电插塞，从而在后续器件晶圆100和基板300键合之后，即可利用所述第一连接结构使所述上电极530和所述第二互连结构电连接。其中，第一连接结构的导电插塞的形成方法包括：
首先，在所述基板100的表面上形成塑封层，本实施例中所述塑封层即包括所述第一塑封层410；
接着，刻蚀所述塑封层，以形成一通孔；本实施例中，即刻蚀所述第一塑封层410，所述通孔暴露出所述上电极530的所述上电极延伸部，并在所述通孔中填充导电材料以形成导电插塞(例如为第三导电插塞230)，所述第三导电插塞230的顶部暴露于所述第一塑封层410的表面。具体而言，所述第三导电插 塞230与所述上电极530的上电极延伸部连接。如此，即可使所述上电极530能够通过所述第三导电插塞230和所述重新布线层610电连接至第二互连结构。
接着参考图3d所示，从器件晶圆的正面键合所述基板300，以使所述压电晶片520背离所述上空腔310的一侧对应所述下空腔120，此时位于所述器件晶圆100上的下电极510相应的位于所述压电晶片520远离所述上电极530的一侧。
本实施例中，键合所述器件晶圆100和所述基板300的方法包括：首先，在所述基板300上形成粘合层，并使所述压电晶片520的表面暴露于所述粘合层；接着，利用所述粘合层，键合所述器件晶圆和所述基板。
具体的，在键合所述器件晶圆100和所述基板300后，即可使器件晶圆100上与第二互连结构连接的重新布线层610，能够和基板300上与上电极530连接的第三导电插塞230电接触，从而使上电极530电性连接所述控制电路。
后续工艺中，形成第二连接结构并键合半导体芯片的方法可参考实施例一，此处不做赘述。
基于如上所述的形成方法，本实施例中对所形成的晶体谐振器与控制电路的集成结构进行说明，具体可结合图2a～图2i以及图3d所示，所述晶体谐振器包括：
器件晶圆100，所述器件晶圆100中形成有控制电路，以及在所述器件晶圆100中还形成有下空腔120，所述下空腔120暴露于所述器件晶圆的正面；本实施例中，所述控制电路中的至少部分互连结构延伸至所述器件晶圆100的正面；
基板300，所述基板300从器件晶圆的正面键合在所述器件晶圆100上，并且所述基板300中形成有上空腔310，所述上空腔310的开口朝向所述器件晶圆100，即所述上空腔310的开口和所述下空腔120的开口相对设置；
压电谐振片500，包括下电极510、压电晶片520和上电极530，所述压电谐振片500位于所述器件晶圆100和所述基板300之间，并且所述压电谐振片500的两侧分别对应所述下空腔120和所述上空腔310；
第一连接结构，用于使所述压电谐振片500的上电极530和下电极510与所述控制电路电性连接；
半导体芯片700，键合在所述器件晶圆100的背面上；其中，所述半导体芯片700中例如形成有驱动电路，用于产生电信号，并将电信号经由所述控制电 路100传输至压电谐振片500；
第二连接结构，用于使所述半导体芯片700电性连接至所述控制电路。
进一步的，所述半导体芯片700可相对于所述器件晶圆100构成异质芯片。即，所述半导体芯片的基底材质不同于所述器件晶圆100的基底材质。例如，本实施例中，器件晶圆100的基底材质为硅，则所述异质芯片的基底材质可以为III-V族半导体材料或Ⅱ-Ⅵ族半导体材料(具体例如包括锗、锗硅或砷化镓等)。
即，利用半导体平面工艺，分别在器件晶圆100和基板300上分别形成下空腔120和上空腔310，并通过键合工艺使上空腔120和下空腔310对应，并分别设置在压电谐振片500相对的两侧，从而可基于控制电路使所述压电谐振片500能够在所述上空腔310和所述下空腔120中震荡，如此，即可使压电谐振片500能够和控制电路集成在同一器件晶圆上。同时，还可进一步将半导体芯片键合至器件晶圆100上，进而可利用半导体芯片并经由所述控制电路110，实现片上调制晶体谐振器的温度漂移和频率矫正等原始偏差，有利于提高晶体谐振器的性能。可见，本实施例中的晶体谐振器，不仅能够提高器件的集成度，并且基于半导体工艺所形成的晶体谐振器其的尺寸更小，从而还能够进一步降低器件功耗。
继续参考图2a所示，所述控制电路包括第一电路111和第二电路112，所述第一电路111和所述第二电路112分别与所述压电谐振片500的上电极和下电极电性连接。
具体的，所述第一电路111包括第一晶体管、第一互连结构111a和第三互连结构111b，所述第一晶体管掩埋在所述器件晶圆100中，所述第一互连结构111a和第三互连结构111b均与所述第一晶体管电连接，并均延伸至所述器件晶圆100的正面。其中，所述第一互连结构111a与所述下电极510电性连接，所述第三互连结构111b与所述半导体芯片电连接。
类似的，所述第二电路112包括第二晶体管、第二互连结构112a和第四互连结构112b，所述第二晶体管掩埋在所述器件晶圆100中，所述第二互连结构112a和第四互连结构112b均与所述第二晶体管电连接，并均延伸至所述器件晶圆100的正面。其中，所述第二互连结构112a与所述上电极530电性连接，所述第四互连结构112b与所述半导体芯片电连接。
进一步的，所述第一连接结构包括第一连接件和第二连接件，所述第一连接件连接所述第一互连结构111a和所述压电谐振片的下电极510，所述第二连接件连接所述第二互连结构112a和所述压电谐振片的上电极530。
本实施例中，所述下电极510形成在所述器件晶圆100的正面上，并且围绕在所述下空腔120的外围，以及所述下电极510还横向延伸出所述压电晶片520以构成下电极延伸部，所述下电极延伸部覆盖所述第一电路111的所述第一互连结构111a，以使所述下电极510与所述第一电路111的第一互连结构111a电性连接。因此，可以认为，所述下电极延伸部即构成所述第一连接件。
以及，所述上电极530形成在所述压电晶片520上，并使所述上电极530通过所述第二连接件与所述第二电路112的所述第二互连结构112a电性连接。
具体的，所述第二连接件包括导电插塞(例如为第三导电插塞230)，所述第三导电插塞230的一端电连接所述上电极530，所述第三导电插塞230的另一端电连接所述第二互连结构112a。例如，使所述上电极530从压电晶片上延伸至所述第三导电插塞的端部上。
进一步的，在所述器件晶圆100和所述基板300之间还设置有塑封层，所述塑封层包覆所述压电晶片520的侧壁，并覆盖上电极延伸部和下电极延伸部。第二连接件中的所述第三导电插塞230贯穿所述塑封层，以使第三导电插塞230的一端连接至所述上电极延伸部，所述第三导电插塞230的另一端电连接所述第二互连结构。
当然，在其他实施例中，所述第二连接件还可包括一互连线。所述互连线的一端覆盖所述上电极530，所述互连线的另一端至少部分覆盖所述第三导电插塞的顶部，以使所述上电极530通过所述互连线和所述第三导电插塞电性连接至所述控制电路。
进一步的，用于连接半导体芯片700和所述控制电路的所述第二连接结构包括导电插塞和连接线，其中，第二连接结构中的导电插塞贯穿所述器件晶圆100，以使所述导电插塞的一端延伸至所述器件晶圆100的正面，以及使所述导电插塞的另一端延伸至所述器件晶圆100的背面并和所述半导体芯片700电性连接，所述连接线形成在所述器件晶圆100的正面上，并使所述连接线连接所述导电插塞和所述控制电路。
即，利用所述导电插塞和所述连接线，实现控制电路中用于电连接半导体 芯片的连接端口能够从器件晶圆的正面引出至器件晶圆的背面，从而可以将半导体芯片设置在器件晶圆的背面上，并从器件晶圆的背面与控制电路电性连接。
本实施例中，所述第二连接结构的导电插塞包括第一导电插塞211b和第二导电插塞212b，以及第二连接结构的连接线包括第一连接线221b和第二连接线222b。其中，所述第一连接线221b连接所述第一导电插塞211b和所述第三互连结构111b，所述第二连接线222b连接所述第二导电插塞212b和所述第四互连结构112b。
继续参考图2a所示，本实施例中，所述器件晶圆100包括基底晶圆100A和介质层100B。其中，所述第一晶体管和所述第二晶体管均形成在所述基底晶圆100A上，所述介质层100B形成在所述基底晶圆100A上并覆盖所述第一晶体管和所述第二晶体管，以及所述第三互连结构111b、所述第一互连结构111a、所述第四互连结构112b和所述第二互连结构112a均形成在所述介质层100B中并延伸至所述介质层100B的远离所述基底晶圆100A的表面。
以及，所述晶体谐振器和控制电路的集成结构还包括塑封层，所述塑封层形成在所述器件晶圆的背面上，并覆盖所述半导体芯片700。
综上所述，本发明提供的晶体谐振器与控制电路的集成方法中，在器件晶圆中形成下空腔，在基板中形成上空腔，并利用键合工艺使器件晶圆和基板键合，以将压电谐振片夹持在器件晶圆和基板之间，并使下空腔和上空腔分别对应在压电谐振片的两侧，从而实现了控制电路和晶体谐振器集成在同一器件晶圆上。基于此，还可将例如形成有驱动电路的半导体芯片进一步键合至器件晶圆的背面上，即半导体芯片、控制电路和晶体谐振器均集成在同一半导体衬底上，从而有利于实现片上调制晶体谐振器的温度漂移和频率矫正等原始偏差。并且，相比于传统的晶体谐振器(例如，表面贴装型晶体谐振器)，本发明中基于半导体平面工艺所形成的晶体谐振器，具备更小的尺寸，从而可相应的降低晶体谐振器的功耗。此外本发明中的晶体谐振器更也易于与其他半导体元器件集成，有利于提高器件的集成度。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (30)

  1. 一种晶体谐振器与控制电路的集成方法，其特征在于，包括：
    提供器件晶圆，所述器件晶圆中形成有控制电路；
    从所述器件晶圆的正面刻蚀所述器件晶圆，以形成所述晶体谐振器的下空腔；
    提供基板，并刻蚀所述基板以形成所述晶体谐振器的上空腔，所述上空腔和所述下空腔对应设置；
    形成包括上电极、压电晶片和下电极的压电谐振片，所述上电极、所述压电晶片和所述下电极形成在所述器件晶圆的正面和所述基板的其中之一上；
    在所述器件晶圆或所述基板上形成第一连接结构；
    在所述器件晶圆的正面上键合所述基板，以使所述压电谐振片位于所述器件晶圆和所述基板之间，以及使所述上空腔和所述下空腔分别位于所述压电谐振片的两侧，并通过所述第一连接结构使所述压电谐振片的上电极和下电极均与所述控制电路电性连接；以及，
    在所述器件晶圆的背面上键合半导体芯片，以及形成第二连接结构，所述半导体芯片通过所述第二连接结构电性连接至所述控制电路。
  2. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于，所述器件晶圆包括基底晶圆和形成在所述基底晶圆上的介质层，所述下空腔形成在所述介质层中。
  3. 如权利要求2所述的晶体谐振器与控制电路的集成方法，其特征在于，所述基底晶圆为绝缘体上硅基底，包括沿着由所述背面至所述正面的方向依次层叠设置的底衬层、掩埋氧化层和顶硅层；以及，所述下空腔还从所述介质层延伸至所述掩埋氧化层。
  4. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于，所述压电谐振片形成在所述器件晶圆的正面或所述基板上；或者，所述压电谐振片的下电极形成在所述器件晶圆的正面上，所述压电谐振片的上电极和压电晶片依次形成在所述基板上；或者，所述压电谐振片的下电极和压电晶片依次形成在所述器件晶圆的正面上，所述压电谐振片的上电极形成在所述基板上。
  5. 如权利要求4所述的晶体谐振器与控制电路的集成方法，其特征在于，所述压电谐振片形成在所述器件晶圆的正面上的方法包括：
    在所述器件晶圆正面的设定位置上形成下电极；
    键合压电晶片至所述下电极；
    在所述压电晶片上形成所述上电极；或者，
    所述压电谐振片的上电极和下电极形成在压电晶片上，三者作为整体键合至所述器件晶圆的正面上。
  6. 如权利要求4所述的晶体谐振器与控制电路的集成方法，其特征在于，所述压电谐振片形成在所述基板上的方法包括：
    在所述基板表面的设定位置上形成上电极；
    键合压电晶片至所述上电极；
    在所述压电晶片上形成所述下电极；或者，
    所述压电谐振片的上电极和下电极形成在压电晶片上，三者作为整体键合至所述基板上。
  7. 如权利要求5或6所述的晶体谐振器与控制电路的集成方法，其特征在于，形成所述下电极的方法包括蒸镀工艺或薄膜沉积工艺；以及，形成所述上电极的方法包括蒸镀工艺或薄膜沉积工艺。
  8. 如权利要求4所述的晶体谐振器与控制电路的集成方法，其特征在于，所述上电极形成在所述基板上，所述下电极形成在所述器件晶圆的正面上；其中，所述上电极和所述下电极利用蒸镀工艺或者薄膜沉积工艺形成，以及所述压电晶片键合至所述上电极或者所述下电极。
  9. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于，所述控制电路包括第一互连结构和第二互连结构，所述第一连接结构包括第一连接件和第二连接件；
    其中，所述第一连接件连接所述第一互连结构和所述压电谐振片的下电极，所述第二连接件连接所述第二互连结构和所述压电谐振片的上电极。
  10. 如权利要求9所述的晶体谐振器与控制电路的集成方法，其特征在于，所述器件晶圆具有所述下电极之后，所述下电极位于所述器件晶圆的正面上，并且所述下电极还从所述压电晶片的下方延伸出以和所述第一互连结构电性连接，所述下电极中从所述压电晶片延伸出的部分构成所述第一连接件。
  11. 如权利要求9所述的晶体谐振器与控制电路的集成方法，其特征在于，在所述器件晶圆上具有所述下电极之前，在所述器件晶圆上形成所述第一连接 件，所述第一连接件与所述第一互连结构电连接，以及在所述器件晶圆上具有所述下电极之后，所述第一连接件电连接所述下电极。
  12. 如权利要求11所述的晶体谐振器与控制电路的集成方法，其特征在于，所述第一连接件包括重新布线层，所述重新布线层和所述第一互连结构连接；以及，在所述器件晶圆上具有所述下电极之后，所述重新布线层与所述下电极电连接。
  13. 如权利要求9所述的晶体谐振器与控制电路的集成方法，其特征在于，所述压电晶片形成在器件晶圆的正面上，并在所述器件晶圆具有所述上电极之前，在所述器件晶圆上形成第二连接件，所述第二连接件与所述第二互连结构电连接；以及，在所述器件晶圆上具有所述上电极之后，所述上电极与所述第二连接件电连接。
  14. 如权利要求13所述的晶体谐振器与控制电路的集成方法，其特征在于，所述第二连接件的形成方法包括：
    在所述器件晶圆的正面上形成塑封层；
    在所述塑封层中形成通孔，并在所述通孔中填充导电材料以形成导电插塞，所述导电插塞的底部电性连接所述第二互连结构，所述导电插塞的顶部暴露于所述塑封层；以及，
    在所述器件晶圆上具有所述上电极之后，所述上电极延伸出所述压电晶片至所述导电插塞的顶部，以使所述上电极和所述导电插塞电性连接；或者，在所述器件晶圆上具有所述上电极之后，在所述塑封层上形成互连线，所述互连线的一端覆盖所述上电极，所述互连线的另一端覆盖所述导电插塞。
  15. 如权利要求9所述的晶体谐振器与控制电路的集成方法，其特征在于，所述上电极和所述压电晶片依次形成在所述基板上，并在所述器件晶圆和所述基板键合之前，在所述基板上形成所述第二连接件，所述第二连接件与所述上电极电连接；以及，在所述器件晶圆和所述基板键合之后，所述第二连接件与所述第二互连结构电连接。
  16. 如权利要求15所述的晶体谐振器与控制电路的集成方法，其特征在于，所述第二连接件的形成方法还包括：
    在所述基板的表面上形成塑封层；
    在所述塑封层中开设通孔，所述通孔暴露出所述上电极，并在所述通孔中 填充导电材料以形成导电插塞，所述导电插塞的一端电连接所述上电极；
    以及，在键合所述器件晶圆和所述基板时，所述导电插塞的另一端电连接至所述第二互连结构。
  17. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于，所述第二连接结构的形成方法包括：
    从所述器件晶圆的正面刻蚀所述器件晶圆，以形成连接孔；
    在所述连接孔中填充导电材料，以形成导电插塞；
    在所述器件晶圆的正面上形成连接线，所述连接线连接所述导电插塞和所述控制电路；以及，
    从所述器件晶圆的背面减薄所述器件晶圆，直至暴露出所述导电插塞，以用于与所述半导体芯片电连接。
  18. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于，所述第二连接结构的形成方法包括：
    在所述器件晶圆的正面上形成连接线，所述连接线电连接所述控制电路；
    从所述器件晶圆的背面刻蚀所述器件晶圆以形成连接孔，所述连接孔贯穿所述器件晶圆，以暴露出所述连接线；以及，
    在所述连接孔中填充导电材料以形成导电插塞，所述导电插塞的一端与连接线连接，所述导电插塞的另一端用于电连接所述半导体芯片。
  19. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于，所述器件晶圆和所述基板的键合方法包括：
    在所述器件晶圆和/或所述基板上形成粘合层，并利用所述粘合层使所述器件晶圆和所述基板相互键合。
  20. 如权利要求19所述的晶体谐振器与控制电路的集成方法，其特征在于，所述压电谐振片的上电极和压电晶片依次形成在所述基板上；
    其中，所述键合方法包括：
    在所述基板上形成粘合层，并使所述压电晶片的表面暴露于所述粘合层；
    利用所述粘合层，键合所述器件晶圆和所述基板。
  21. 如权利要求19所述的晶体谐振器与控制电路的集成方法，其特征在于，所述压电谐振片的下电极和压电晶片依次形成在所述器件晶圆上；
    其中，所述键合方法包括：
    在所述器件晶圆上形成粘合层，并使所述压电晶片的表面暴露于所述粘合层；
    利用所述粘合层，键合所述器件晶圆和所述基板。
  22. 如权利要求1所述的晶体谐振器与控制电路的集成方法，其特征在于，优先在所述器件晶圆的正面上键合所述基板，接着在所述器件晶圆的背面上键合半导体芯片；
    或者，优先在所述器件晶圆的背面上键合半导体芯片，接着在所述器件晶圆的正面上键合所述基板。
  23. 一种晶体谐振器与控制电路的集成结构，其特征在于，包括：
    器件晶圆，所述器件晶圆中形成有控制电路，以及在所述器件晶圆中还形成有下空腔，所述下空腔暴露于所述器件晶圆的正面；
    基板，所述基板从所述器件晶圆的正面键合于所述器件晶圆上，并且所述基板中形成有上空腔，所述上空腔的开口和所述下空腔的开口相对设置；
    压电谐振片，包括上电极、压电晶片和下电极，所述压电谐振片位于所述器件晶圆和所述基板之间，并且所述压电谐振片的两侧分别对应所述下空腔和所述上空腔；
    第一连接结构，用于使所述压电谐振片的上电极和下电极电连接至所述控制电路；
    半导体芯片，键合在所述器件晶圆的背面上；以及，
    第二连接结构，用于使所述半导体芯片电连接至所述控制电路。
  24. 如权利要求23所述的晶体谐振器与控制电路的集成结构，其特征在于，所述器件晶圆包括基底晶圆和形成在所述基底晶圆上的介质层，所述下空腔形成在所述介质层中。
  25. 如权利要求23所述的晶体谐振器与控制电路的集成方法，其特征在于，所述基底晶圆为绝缘体上硅基底，包括沿着由所述背面至所述正面的方向依次层叠设置的底衬层、掩埋氧化层和顶硅层；以及，所述下空腔还从所述介质层延伸至所述掩埋氧化层。
  26. 如权利要求23所述的晶体谐振器与控制电路的集成结构，其特征在于，所述控制电路包括第一互连结构和第二互连结构，所述第一连接结构包括第一连接件和第二连接件；
    其中，所述第一连接件连接所述第一互连结构和所述压电谐振片的下电极，所述第二连接件连接所述第二互连结构和所述压电谐振片的上电极。
  27. 如权利要求26所述的晶体谐振器与控制电路的集成结构，其特征在于，所述下电极位于所述器件晶圆的正面上并从所述压电晶片延伸出以和所述第一互连结构电性连接，所述下电极从所述压电晶片延伸出的部分构成所述第一连接件。
  28. 如权利要求26所述的晶体谐振器与控制电路的集成结构，其特征在于，所述第二连接件包括导电插塞，所述导电插塞的一端电连接所述上电极，所述导电插塞的另一端电连接所述第二互连结构。
  29. 如权利要求26所述的晶体谐振器与控制电路的集成结构，其特征在于，所述第二连接件包括：
    导电插塞，形成在所述器件晶圆的正面上，并且所述导电插塞的底部与所述第二互连结构电连接；以及，
    互连线，所述互连线的一端覆盖所述上电极，所述互连线的另一端覆盖所述导电插塞的顶部。
  30. 如权利要求23所述的晶体谐振器与控制电路的集成结构，其特征在于，所述第二连接结构包括：
    导电插塞，贯穿所述器件晶圆，以使所述导电插塞的一端延伸至所述器件晶圆的正面，以及使所述导电插塞的另一端延伸至所述器件晶圆的背面并和所述半导体芯片电连接；以及，
    连接线，形成在所述器件晶圆的正面上，所述连接线连接所述导电插塞和所述控制电路。
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