WO2020133753A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

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Publication number
WO2020133753A1
WO2020133753A1 PCT/CN2019/079503 CN2019079503W WO2020133753A1 WO 2020133753 A1 WO2020133753 A1 WO 2020133753A1 CN 2019079503 W CN2019079503 W CN 2019079503W WO 2020133753 A1 WO2020133753 A1 WO 2020133753A1
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WIPO (PCT)
Prior art keywords
area
array substrate
frame
layer
blocking groove
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Ceased
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PCT/CN2019/079503
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English (en)
French (fr)
Inventor
赵朝军
艾飞
龙时宇
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Publication of WO2020133753A1 publication Critical patent/WO2020133753A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells

Definitions

  • the invention relates to the field of display devices, in particular to an array substrate and a liquid crystal display panel.
  • Liquid crystal display (LCD, Liquid Crystal Display) has many advantages such as thin body, power saving, no radiation, etc., and has been widely used.
  • the liquid crystal display device is composed of a liquid crystal display panel and a backlight module disposed on the back of the liquid crystal display panel.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates, control whether the liquid crystal molecules change direction by energizing the glass substrate or not, and refract the light of the backlight module to generate a picture.
  • the liquid crystal display panel is composed of a color filter substrate (CF, ColorFilter), a thin film transistor substrate (TFT, ThinFilmTransistor), a liquid crystal (LC) and a sealant frame (Sealant) sandwiched between the color filter substrate and the thin film transistor substrate .
  • the thin film transistor substrate and the color filter substrate each have an alignment film layer. After the alignment film layer is in contact with the liquid crystal, the liquid crystal molecules can be pre-tilted in a certain direction, thereby providing a bearing angle for the liquid crystal molecules.
  • the alignment film layer The material is usually polyimide (Polyimide, PI) material, which is formed by coating PI on the substrate.
  • narrow bezel technology is more and more widely applied to mobile phone panels.
  • narrow frame products for example, 0.7 narrow frame products, how to improve their moisture resistance and adhesion is a big problem.
  • the overlapping area of the alignment film layer and the sealant frame is the key factor affecting the moisture resistance and adhesion.
  • FIG. 1 is a schematic structural view of a frame of an existing liquid crystal display panel.
  • the frame width of the liquid crystal display panel is 0.7 mm.
  • the liquid crystal display panel includes a color filter substrate 10 and a thin film transistor substrate 11 disposed opposite to the color filter substrate 10.
  • liquid crystal (not shown in the drawings) is interposed between the color filter substrate 10 and the thin film transistor substrate 11, and in the frame area B, the color filter substrate 10 and the thin film transistor substrate 11 Connected by a sealant frame 13.
  • An alignment film layer 15 is provided on the color film substrate 10 and the thin film transistor substrate 11 respectively, the alignment film layer 15 extends from the display area A to the frame area B, and the alignment film layer 15 and the The sealant frame 13 partially overlaps.
  • the moisture resistance and adhesion of the liquid crystal display panel depend on the overlapping area of the alignment film layer 15 and the sealant frame 13.
  • the alignment film layer 15 is formed by coating a PI liquid, and the PI liquid has fluidity.
  • a trench 111 is usually formed on the flat layer (PLN) 110 of the thin film transistor substrate 11 to prevent the PI liquid from crossing the trench and improve the PI printing accuracy.
  • the defect is that the thickness of the flat layer 110 is thick, so that the depth of the trench 111 is deep, the slope angle (Taper) formed at the trench 111 is large, which easily causes the upper film layer to be in the trench 111 remains, resulting in poor performance of the LCD panel.
  • the technical problem to be solved by the present invention is to provide an array substrate and a liquid crystal display panel, which can block the material spread of the alignment film layer without affecting the subsequent deposition of the film layer, thereby improving the performance of the array substrate.
  • a sealant frame is provided above the flat layer, the sealant frame partially overlaps the alignment film layer, and the first spoiler Located outside the orthographic projection area of the sealant frame, the second spoiler is located in the orthographic projection area of the sealant frame, the array substrate further includes a circuit layer, the circuit layer is disposed on the flat Below the layer, the first blocking groove is located above the circuit layer.
  • the depth of the first choke groove is not equal to the depth of the second choke groove.
  • the present invention also provides an array substrate.
  • the array substrate includes a display area and a bezel area provided on at least one side of the display area.
  • the surface of the array substrate has a flat layer.
  • the flat layer extends from the display area to the bezel area, and in the bezel area, in a direction away from the display area, the flat layer has at least a first blocking groove and a second blocking groove, The depths of the first blocking groove and the second blocking groove are smaller than the thickness of the flat layer, and an alignment film layer is provided on the flat layer, and the alignment film layer extends from the display area to The frame area, but does not exceed the second spoiler.
  • the depth of the first choke groove is not equal to the depth of the second choke groove.
  • a sealant frame is provided above the flat layer, and the sealant frame partially overlaps the alignment film layer.
  • the second blocking groove is located in the orthographic projection area of the sealant frame.
  • the first blocking groove is located outside the orthographic projection area of the sealant frame.
  • the array substrate further includes a circuit layer, the circuit layer is disposed under the flat layer, and the first blocking groove is located above the circuit layer.
  • the invention also provides a liquid crystal display panel, comprising an array substrate as described above and a color film substrate opposite to the array substrate, in the display area, between the color film substrate and the array substrate A liquid crystal is interposed, and in the frame area, the color film substrate and the array substrate are connected by a sealant frame.
  • the depth of the first choke groove is not equal to the depth of the second choke groove.
  • the sealant frame in the frame area, partially overlaps the alignment film layer.
  • the first blocking groove is located outside the orthographic projection area of the sealant frame.
  • an alignment film layer is provided on a surface of the color film substrate facing the array substrate, and the alignment film layer extends from the display area to the bezel area.
  • the array substrate further includes a circuit layer, the circuit layer is disposed below the flat layer, and the first blocking groove is located above the circuit layer.
  • the advantage of the present invention is that the first blocking groove and the second blocking groove form a double line of defense, which plays a role of blocking the material spread of the alignment film, and the first blocking groove and the second blocking groove are Shallow grooves, so that the slope angle of the flat layer at the first flow blocking groove and the second flow blocking groove is small, and the subsequently deposited film layer will not be in the first flow blocking groove and the second flow blocking The residue at the flow channel will not affect the subsequent deposition of the film layer, thereby improving the performance of the array substrate.
  • FIG. 1 is a schematic structural view of a frame of an existing liquid crystal display panel
  • FIG. 3 is a schematic diagram of the structure of the liquid crystal display panel of the present invention.
  • the array substrate 20 of the present invention is divided into a display area A and a frame area B disposed on at least one side of the display area A.
  • the bezel area B surrounds the display area A.
  • the bezel area B may also be provided on only one side, two sides, or three sides of the display area A .
  • FIG. 2 only a part of the display area A and a part of the frame area B are schematically shown.
  • the surface of the array substrate 20 has a flat layer 21 extending from the display area A to the frame area B.
  • the flat layer 21 has at least a first flow blocking groove 211 and a second flow blocking groove 212.
  • the first choke groove 211 is disposed near the display area A
  • the second choke groove 212 is disposed away from the display area A.
  • the method for forming the first choke groove 211 and the second choke groove 212 includes, but is not limited to, after the flat layer 21 is coated, the flat layer 21 is processed through a half tone mask Patterning to form the first blocking groove 211 and the second blocking groove 212 in the frame area B.
  • the depths of the first blocking groove 211 and the second blocking groove 212 are smaller than the thickness of the flat layer 21. That is to say, the first blocking groove 211 and the second blocking groove 212 do not penetrate the flat layer 21, then the first blocking groove 211 and the second blocking groove 212 do not Will contact or destroy the film layer under the flat layer 21. In this embodiment, the depth of the first blocking groove 211 and the depth of the second blocking groove 212 are not equal.
  • the array substrate 1 further includes a circuit layer 24, and the circuit layer 24 includes, but is not limited to, a GOA circuit layer.
  • the circuit layer 24 is disposed under the flat layer 21.
  • the first blocking groove 211 is located above the circuit layer 24, and the second blocking groove 212 may be located above the circuit layer 24 or on one side of the circuit layer 24.
  • the first blocking groove 211 is located above the circuit layer 24, and the second blocking groove 212 is located on one side of the circuit layer 24.
  • the first blocking groove 211 and the second blocking groove 212 are not in contact with the circuit layer 24 under the flat layer 21, and can be anywhere in the border area B Digging trenches improves the design freedom.
  • An alignment film layer 22 is disposed on the flat layer 21 and extends from the display area A to the frame area B.
  • the boundary of the alignment film layer 22 is located in a region between the display area A and the side of the second blocking groove 212 away from the display area A. That is, when the alignment film 22 extends from the display area A to the frame area B, it does not exceed the second blocking groove 212.
  • the alignment film layer 22 does not cover all the frame region B, and the boundary only extends to the second flow blocking groove 212 at the farthest, or fills the second flow blocking groove 212 at the farthest. .
  • the material of the alignment film layer 22 will spread along the X direction on the surface of the flat layer 21 , And the first choke groove 211 and the second choke groove 212 form a double line of defense, which acts to block the material of the alignment film 22 from spreading; at the same time, the first choke groove 211 and the The depth of the second blocking groove 212 is smaller than the thickness of the flat layer 21, that is to say, the first blocking groove 211 and the second blocking groove 212 are both shallow grooves, so that The slope angle of the flat layer 21 at the spoiler 211 and the second spoiler 212 is small, and subsequently the deposited film layer will not be in the first spoiler 211 and the second spoiler 212 The residue will not affect the subsequent deposition of the film layer, and will not cause poor performance of the array substrate.
  • a sealant frame 23 is provided above the flat layer 21.
  • the sealing frame 23 is made of conventional sealing material. Wherein, the sealant frame 23 is provided on the side of the bezel area B away from the display area A, and the sealant frame 23 is not provided on the side of the bezel area B close to the display area A, That is to say, in the X direction, the sealant frame 23 does not fill all the frame area B.
  • the sealant frame 23 partially overlaps the alignment film layer 22. Since the first blocking groove 211 and the second blocking groove 212 form a double line of defense, which can block the material spread of the alignment film layer 22, the seal frame 23 of the present invention and the prior art seal frame 13 (please refer to FIG. 1) under the same width, the overlapping area of the sealant frame 23 and the alignment film layer 22 of the present invention can be reduced, thereby improving the sealing performance of the sealant frame 23, and Improve the moisture resistance and adhesion of electronic devices using the array substrate.
  • the first spoiler 211 is located outside the orthographic projection area of the sealant frame 23, and the second spoiler 212 is located in the orthographic projection area of the sealant frame 23, That is to say, the first choke groove 211 is provided in the area where the sealing frame 23 is not provided in the frame area B, and the second choke groove 212 is provided in the frame area B where the seal is provided
  • the area of the glue frame 23 can further reduce the overlapping area of the seal glue frame 23 and the alignment film layer 22.
  • the invention also provides a liquid crystal display panel.
  • 3 is a schematic diagram of the side structure of the liquid crystal display panel of the present invention.
  • the liquid crystal display panel of the present invention includes an array substrate 2 as described above and a color filter substrate 3 opposite to the array substrate 2.
  • the liquid crystal display panel is also divided into a display area A and a frame area B.
  • liquid crystal (not shown in the drawings) is interposed between the color filter substrate 3 and the array substrate 2.
  • the color filter substrate 3 and the array substrate 2 are connected by the sealant frame 23.
  • an alignment film layer 31 is also provided on the surface of the color film substrate 3 facing the array substrate 2, and the alignment film layer 31 extends from the display area A to the frame area B.
  • the alignment film layer 31 and the alignment film layer 22 are conventional structures in the art, and will not be described in detail.
  • the first flow blocking groove 211 and the second flow blocking groove 212 form a double line of defense, which can block the material of the alignment film layer 22 from spreading, the seal frame of the present invention 23 and the prior art sealant frame 13 (see FIG.
  • the first spoiler and the second spoiler form a double line of defense, which plays a role in preventing the material of the alignment film from spreading ,
  • the first blocking groove 211 and the second blocking groove 212 are shallow grooves, so that the slope angle of the flat layer at the first blocking groove 211 and the second blocking groove 212 is small, Furthermore, the subsequently deposited film layer will not remain at the first blocking groove 211 and the second blocking groove 212, will not affect the subsequent deposition of the film layer, and will not cause poor performance of the liquid crystal display panel.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板（20）及液晶显示面板，第一阻流槽（211）及第二阻流槽（212）形成双重防线，起到阻挡配向膜层（22）的材料蔓延的作用，且第一阻流槽（211）及第二阻流槽（212）为浅槽，后续沉积的膜层不会在第一阻流槽（211）及第二阻流槽（212）处残留，不会影响后续膜层的沉积，不会造成阵列基板（20）性能不良。

Description

阵列基板及液晶显示面板 技术领域
本发明涉及显示装置领域，尤其涉及一种阵列基板及液晶显示面板。
 背景技术
液晶显示装置(LCD，LiquidCrystalDisplay)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。其中，液晶显示装置由液晶显示面板及设置在液晶显示面板背面的背光模组组成。所述液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，通过玻璃基板通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜基板(CF，ColorFilter)、薄膜晶体管基板(TFT， ThinFilmTransistor)、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成。通常，薄膜晶体管基板及彩膜基板上分别具有一层配向膜层，该配向膜层与液晶接触后，能够使得液晶产生一定方向的预倾角，从而给液晶分子提供一个承载的角度，配向膜层的材料通常选用聚酰亚胺(Polyimide,PI)材料，由PI液涂布于基板上所形成。
随着时代进步，LCD技术发展也越来越快，高PPI、窄边框产品越来越受到追捧，因此窄边框技术被越来越广泛应用到手机面板。对于窄边框产品而言，例如，0.7窄边框产品，如何提高其抗湿性及黏附性是很大的难题。其中配向膜层与密封胶框的重合面积是影响抗湿性及黏附性的关键因素。
图1是现有的一种液晶显示面板边框处的结构示意图。请参阅图1，该液晶显示面板的边框宽度为0.7mm，所述液晶显示面板包括彩膜基板10及与所述彩膜基板10相对设置的薄膜晶体管基板11。在显示区A，在所述彩膜基板10与薄膜晶体管基板11之间夹设有液晶（附图中未绘示），在边框区B，所述彩膜基板10与所述薄膜晶体管基板11通过一密封胶框13连接。在所述彩膜基板10及所述薄膜晶体管基板11上分别设置有一配向膜层15，所述配向膜层15自所述显示区A延伸至边框区B，且所述配向膜层15与所述密封胶框13部分重叠。所述液晶显示面板的抗湿性及黏附性就取决于所述配向膜层15与所述密封胶框13重叠的面积。
 技术问题
通常，配向膜层15由PI液涂布形成，而PI液具有流动性。在所述薄膜晶体管基板11上，通常通过在所述薄膜晶体管基板11的平坦层（PLN）110上形成一道沟槽111，以阻挡PI液越过沟槽，提高了PI印刷精度，但此技术的缺陷在于所述平坦层110厚度较厚，使得所述沟槽111的深度较深，则在所述沟槽111处形成的坡度角（Taper）较大，易导致上层膜层在所述沟槽111处残留，造成液晶显示面板性能不良。
 技术解决方案
本发明所要解决的技术问题是，提供一种阵列基板及液晶显示面板，其能够阻挡配向膜层的材料蔓延，且不会影响后续膜层的沉积，从而改善阵列基板性能。
为了解决上述问题，本发明提供了一种阵列基板，其包括显示区及设置在所述显示区至少一侧的一边框区，所述阵列基板的表面具有一平坦层，所述平坦层自所述显示区延伸至所述边框区，在所述边框区，沿远离所述显示区的方向，所述平坦层至少具有一第一阻流槽及一第二阻流槽，所述第一阻流槽及所述第二阻流槽的深度均小于所述平坦层的厚度，在所述平坦层上设置有一配向膜层，所述配向膜层自所述显示区延伸至所述边框区，但未超过所述第二阻流槽，在所述边框区，在所述平坦层上方设置有一密封胶框，所述密封胶框与所述配向膜层部分重叠，所述第一阻流槽位于所述密封胶框的正投影区域外，所述第二阻流槽位于所述密封胶框的正投影区域内，所述阵列基板还包括一电路层，所述电路层设置在所述平坦层之下，所述第一阻流槽位于所述电路层上方。
在一实施例中，所述第一阻流槽的深度与所述第二阻流槽的深度不相等。
为了解决上述问题，本发明还提供了一种阵列基板，所述阵列基板包括一显示区及设置在所述显示区至少一侧的一边框区，所述阵列基板的表面具有一平坦层，所述平坦层自所述显示区延伸至所述边框区，在所述边框区，沿远离所述显示区的方向，所述平坦层至少具有一第一阻流槽及一第二阻流槽，所述第一阻流槽及所述第二阻流槽的深度均小于所述平坦层的厚度，在所述平坦层上设置有一配向膜层，所述配向膜层自所述显示区延伸至所述边框区，但未超过所述第二阻流槽。
在一实施例中，所述第一阻流槽的深度与所述第二阻流槽的深度不相等。
在一实施例中，在所述边框区，在所述平坦层上方设置有一密封胶框，所述密封胶框与所述配向膜层部分重叠。
在一实施例中，所述第二阻流槽位于所述密封胶框的正投影区域内。
在一实施例中，所述第一阻流槽位于所述密封胶框的正投影区域外。
在一实施例中，所述阵列基板还包括一电路层，所述电路层设置在所述平坦层之下，所述第一阻流槽位于所述电路层上方。
本发明还提供一种液晶显示面板，包括一如上述的阵列基板及一与所述阵列基板对置的彩膜基板，在所述显示区，在所述彩膜基板与所述阵列基板之间夹设有液晶，在所述边框区，所述彩膜基板与所述阵列基板通过一密封胶框连接。
在一实施例中，所述第一阻流槽的深度与所述第二阻流槽的深度不相等。
在一实施例中，在所述边框区，所述密封胶框与所述配向膜层部分重叠。
在一实施例中，所述第二阻流槽位于所述密封胶框的正投影区域内。
在一实施例中，所述第一阻流槽位于所述密封胶框的正投影区域外。
在一实施例中，在所述彩膜基板朝向所述阵列基板的表面设置有一配向膜层，所述配向膜层自所述显示区延伸至所述边框区。
在一实施例中，所述阵列基板还包括一电路层，所述电路层设置在所述平坦层之下，且所述第一阻流槽位于所述电路层上方。
 有益效果
本发明的优点在于，第一阻流槽及所述第二阻流槽形成双重防线，起到阻挡配向膜层的材料蔓延的作用，且第一阻流槽及所述第二阻流槽为浅槽，使得在所述第一阻流槽及所述第二阻流槽处平坦层的坡度角小，进而后续沉积的膜层不会在所述第一阻流槽及所述第二阻流槽处残留，不会影响后续膜层的沉积，从而改善阵列基板性能。
 附图说明
图1是现有的一种液晶显示面板边框处的结构示意图；
图2是本发明阵列基板的结构示意图；
图3是本发明液晶显示面板的结构示意图。
 本发明的实施方式
下面结合附图对本发明提供的阵列基板及液晶显示面板的具体实施方式做详细说明。
图2是本发明阵列基板的侧面结构示意图，请参阅2，本发明阵列基板20 划分为一显示区A及设置在所述显示区A至少一侧的一边框区B。在本实施例中，所述边框区B包围所述显示区A，在本发明其他实施例中，所述边框区B也可以仅设置在所述显示区A的一侧、两侧或者三侧。其中，图2仅示意性地绘示部分所述显示区A及部分所述边框区B。
所述阵列基板20的表面具有一平坦层21，所述平坦层21自所述显示区A延伸至所述边框区B。在所述边框区B，沿远离所述显示区A的方向，例如，沿如图2所示的X方向，所述平坦层21至少具有一第一阻流槽211及一第二阻流槽212。具体地说，所述第一阻流槽211靠近所述显示区A设置，所述第二阻流槽212远离所述显示区A设置。形成所述第一阻流槽211及所述第二阻流槽212的方法包括但不限于，在平坦层21涂布后，通过一半色调（half tone）掩膜版对所述平坦层21进行图案化，以在所述边框区B形成所述第一阻流槽211及所述第二阻流槽212。
其中，所述第一阻流槽211及所述第二阻流槽212的深度均小于所述平坦层21的厚度。也就是说，所述第一阻流槽211及所述第二阻流槽212并未贯穿所述平坦层21，则所述第一阻流槽211及所述第二阻流槽212并不会接触或破坏所述平坦层21下方的膜层。在本实施例中，所述第一阻流槽211的深度与所述第二阻流槽212的深度不相等。
由于所述第一阻流槽211及所述第二阻流槽212并未贯穿所述平坦层21，则并不会存在所述第一阻流槽211及所述第二阻流槽212与位于平坦层21下方的膜层接触的情况，因此，可在所述边框区B的任意位置挖槽，提高了设计的自由度。具体地说，所述阵列基板1还包括一电路层24，所述电路层24包括但不限于GOA电路层。所述电路层24设置在所述平坦层21之下。所述第一阻流槽211位于所述电路层24上方，所述第二阻流槽212可以位于所述电路层24的上方，也可以位于所述电路层24的一侧。在本实施例中，所述第一阻流槽211位于所述电路层24上方，所述第二阻流槽212位于所述电路层24的一侧。在本实施例中不会存在所述第一阻流槽211及所述第二阻流槽212与位于平坦层21下方的电路层24接触的情况，则可在所述边框区B的任意位置挖槽，提高了设计的自由度。
一配向膜层22设置在所述平坦层21上，且自所述显示区A延伸至所述边框区B。其中，所述配向膜层22的边界位于所述显示区A与所述第二阻流槽212远离所述显示区A一侧之间的区域内。亦即，所述配向膜层22自所述显示区A延伸至所述边框区B时，其并未超过所述第二阻流槽212。具体地说，所述配向膜层22并未覆盖全部的边框区B，其边界最远仅延伸至所述第二阻流槽212，或者说最远仅填满所述第二阻流槽212。
在所述阵列基板2的制作工艺中，在所述平坦层21上制作所述配向膜层22时，所述配向膜层22的材料会在所述平坦层21的表面沿所述X方向蔓延，而所述第一阻流槽211及所述第二阻流槽212形成双重防线，起到阻挡所述配向膜层22的材料蔓延的作用；同时，所述第一阻流槽211及所述第二阻流槽212的深度小于所述平坦层21的厚度，也就是说，所述第一阻流槽211及所述第二阻流槽212均为浅槽，使得在所述第一阻流槽211及所述第二阻流槽212处所述平坦层21的坡度角小，进而后续沉积的膜层不会在所述第一阻流槽211及所述第二阻流槽212处残留，不会影响后续膜层的沉积，不会造成阵列基板性能不良。
在所述边框区B，在所述平坦层21上方设置有一密封胶框23。所述密封胶框23由常规的密封材料制成。其中，所述密封胶框23设置在所述边框区B远离所述显示区A的一侧，在所述边框区B靠近所述显示区A的一侧并未设置所述密封胶框23，也就是说，在沿X方向，所述密封胶框23并未填充全部的边框区B。
所述密封胶框23与所述配向膜层22部分重叠。由于所述第一阻流槽211及所述第二阻流槽212形成双重防线，能够阻挡所述配向膜层22的材料蔓延，则在本发明密封胶框23与现有技术的密封胶框13（请参阅图1）具有同等宽度的情况下，可以使得本发明所述密封胶框23与所述配向膜层22的重叠面积减小，从而提高所述密封胶框23的密封性能，进而改善采用该阵列基板的电子器件的抗湿性及黏附性。
进一步，在本实施例中，所述第一阻流槽211位于所述密封胶框23的正投影区域外，所述第二阻流槽212位于所述密封胶框23的正投影区域内，也就是说，所述第一阻流槽211设置在所述边框区B没有设置所述密封胶框23的区域，所述第二阻流槽212设置在所述边框区B设置有所述密封胶框23的区域，从而能够进一步减小所述密封胶框23与所述配向膜层22的重叠面积。
本发明还提供一种液晶显示面板。图3是本发明液晶显示面板的侧面结构示意图。请参阅图3，本发明液晶显示面板包括一如上述的阵列基板2及一与所述阵列基板2对置的彩膜基板3。其中，根据所述阵列基板2的划分方法，将所述液晶显示面板也划分为显示区A及边框区B。在所述显示区A，在所述彩膜基板3与所述阵列基板2之间夹设有液晶（附图中未绘示）。在所述边框区B，所述彩膜基板3与所述阵列基板2通过所述密封胶框23连接。
其中，在所述彩膜基板3朝向所述阵列基板2的表面也设置有一配向膜层31，所述配向膜层31自所述显示区A延伸至所述边框区B。其中所述配向膜层31及所述配向膜层22均为本领域常规结构，不再赘述。
在本发明的液晶显示面板中，由于所述第一阻流槽211及所述第二阻流槽212形成双重防线，能够阻挡所述配向膜层22的材料蔓延，则在本发明密封胶框23与现有技术的密封胶框13（请参阅图1）具有同等宽度的情况下，可以使得本发明所述密封胶框23与所述配向膜层22的重叠面积减小，从而提高所述密封胶框23的密封性能，进而改善液晶显示面板的抗湿性及黏附性；同时，第一阻流槽及所述第二阻流槽形成双重防线，起到阻挡配向膜层的材料蔓延的作用，且所述第一阻流槽211及所述第二阻流槽212为浅槽，使得在所述第一阻流槽211及所述第二阻流槽212处平坦层的坡度角小，进而后续沉积的膜层不会在所述第一阻流槽211及所述第二阻流槽212处残留，不会影响后续膜层的沉积，不会造成液晶显示面板性能不良。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (15)

  1. 一种阵列基板，其包括显示区及设置在所述显示区至少一侧的一边框区，所述阵列基板的表面具有一平坦层，所述平坦层自所述显示区延伸至所述边框区，在所述边框区，沿远离所述显示区的方向，所述平坦层至少具有一第一阻流槽及一第二阻流槽，所述第一阻流槽及所述第二阻流槽的深度均小于所述平坦层的厚度，在所述平坦层上设置有一配向膜层，所述配向膜层自所述显示区延伸至所述边框区，但未超过所述第二阻流槽，在所述边框区，在所述平坦层上方设置有一密封胶框，所述密封胶框与所述配向膜层部分重叠，所述第一阻流槽位于所述密封胶框的正投影区域外，所述第二阻流槽位于所述密封胶框的正投影区域内，所述阵列基板还包括一电路层，所述电路层设置在所述平坦层之下，所述第一阻流槽位于所述电路层上方。
  2. 根据权利要求1所述的阵列基板，其中所述第一阻流槽的深度与所述第二阻流槽的深度不相等。
  3. 一种阵列基板，其包括显示区及设置在所述显示区至少一侧的一边框区，所述阵列基板的表面具有一平坦层，所述平坦层自所述显示区延伸至所述边框区，在所述边框区，沿远离所述显示区的方向，所述平坦层至少具有一第一阻流槽及一第二阻流槽，所述第一阻流槽及所述第二阻流槽的深度均小于所述平坦层的厚度，在所述平坦层上设置有一配向膜层，所述配向膜层自所述显示区延伸至所述边框区，但未超过所述第二阻流槽。
  4. 根据权利要求3所述的阵列基板，其中所述第一阻流槽的深度与所述第二阻流槽的深度不相等。
  5. 根据权利要求3所述的阵列基板，其中在所述边框区，在所述平坦层上方设置有一密封胶框，所述密封胶框与所述配向膜层部分重叠。
  6. 根据权利要求5所述的阵列基板，其中所述第二阻流槽位于所述密封胶框的正投影区域内。
  7. 根据权利要求5所述的阵列基板，其中所述第一阻流槽位于所述密封胶框的正投影区域外。
  8. 根据权利要求3所述的阵列基板，其中所述阵列基板还包括一电路层，所述电路层设置在所述平坦层之下，所述第一阻流槽位于所述电路层上方。
  9. 一种液晶显示面板，其中包括一如权利要求3所述的阵列基板及一与所述阵列基板对置的彩膜基板；在所述阵列基板的显示区，并在所述彩膜基板与所述阵列基板之间夹设有液晶；在所述阵列基板的边框区，所述彩膜基板与所述阵列基板通过一密封胶框连接。
  10. 根据权利要求9所述的液晶显示面板，其中所述第一阻流槽的深度与所述第二阻流槽的深度不相等。
  11. 根据权利要求9所述的液晶显示面板，其中在所述边框区，所述密封胶框与所述配向膜层部分重叠。
  12. 根据权利要求11所述的液晶显示面板，其中所述第二阻流槽位于所述密封胶框的正投影区域内。
  13. 根据权利要求11所述的液晶显示面板，其中所述第一阻流槽位于所述密封胶框的正投影区域外。
  14. 根据权利要求9所述的液晶显示面板，其中在所述彩膜基板朝向所述阵列基板的表面设置有一配向膜层，所述配向膜层自所述显示区延伸至所述边框区。
  15. 根据权利要求9所述的液晶显示面板，其中所述阵列基板还包括一电路层，所述电路层设置在所述平坦层之下，且所述第一阻流槽位于所述电路层上方。
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