WO2020125603A1 - 一种模拟开关开启电路及方法 - Google Patents

一种模拟开关开启电路及方法 Download PDF

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Publication number
WO2020125603A1
WO2020125603A1 PCT/CN2019/125837 CN2019125837W WO2020125603A1 WO 2020125603 A1 WO2020125603 A1 WO 2020125603A1 CN 2019125837 W CN2019125837 W CN 2019125837W WO 2020125603 A1 WO2020125603 A1 WO 2020125603A1
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Prior art keywords
field effect
circuit
clock signal
channel field
current
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PCT/CN2019/125837
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English (en)
French (fr)
Inventor
何永强
程剑涛
杜黎明
罗旭程
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上海艾为电子技术股份有限公司
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Publication of WO2020125603A1 publication Critical patent/WO2020125603A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention relates to the technical field of semiconductor integrated circuits, in particular to an analog switch starting circuit and method.
  • Analog switches made of semiconductors are also widely used in various fields and become an indispensable part of our lives.
  • Analog switches in semiconductor integrated circuits are widely used in signal propagation channels.
  • Analog switches are mainly used to complete the signal switching function in the signal link, and their functions are similar to switches. Among them, when the analog switch of the audio-type device is turned on, it will cause a POP sound from the relevant audio-type device because it is turned on too quickly.
  • analog switches often use capacitors and resistors, switched capacitors, or currents applied to the capacitors to generate switching voltage filtering to cause a certain delay in circuit startup.
  • the slow opening circuit of the analog switch mainly uses the method of applying current to the capacitor to generate a delay.
  • the analog switch is closed, and the Zener diode is clamped under the action of the current
  • the voltage provides the voltage required by the analog switch for the field effect transistor to complete the startup.
  • the analog switch can reach the microsecond level, it is still too fast. In the process of the switch being turned on, it will cause the device to generate POP sound.
  • embodiments of the present invention provide an analog switch opening circuit and method to solve the problem in the prior art that the POP sound generated by audio equipment caused by the switch opening too fast cannot be avoided.
  • analog switch opening circuit and method provided by the embodiments of the present invention have an analog switch opening time adjustable function.
  • the first aspect of the present invention discloses an analog switch start circuit
  • the analog switch start circuit includes: a control circuit, a current generating circuit and a main switch circuit;
  • the control circuit is configured to decode the input time setting signal into a second clock signal, and divide the second clock signal based on the input first clock signal to generate a third clock signal and a Four clock signals;
  • the input terminal of the current generation circuit is connected to the output terminal of the control circuit for receiving the third clock signal and the fourth clock signal, and the current generation circuit is based on the third clock signal and the fourth clock signal Control generates current and outputs the current to the main switch circuit;
  • the input end of the main switch circuit is connected to the output end of the current generation circuit, and is used to receive the current output by the current generation circuit and complete the start-up under the action of the current.
  • control circuit includes: a decoding module and a counter;
  • the decoding module is used to decode the input time setting signal into a second clock signal and transmit it to the counter;
  • the input terminal of the counter is connected to the output terminal of the decoding module, and is used to divide the second clock signal based on the input first clock signal to generate a third clock signal and a fourth clock signal with opposite phases.
  • the current generating circuit includes: a first switch, a second switch, a first capacitor, a second capacitor, a first N-channel field effect transistor, a second N-channel field effect transistor, and a first P-channel field effect transistor And the second P-channel field effect transistor;
  • the control terminal of the first switch is used for inputting the third clock signal, the first terminal of the first switch is a reference voltage input terminal, the second terminal of the first switch and one terminal of the first capacitor Connected, the second end of the first switch is connected to the first end of the second switch, and the other end of the first capacitor is grounded;
  • the control end of the second switch is used to input the fourth clock signal, the second end of the second switch is connected to one end of the second capacitor, and the second end of the second switch is connected to the first The drain of an N-channel field effect transistor is connected, and the other end of the second capacitor is connected to the source of the first N-channel field effect transistor and is grounded;
  • the drain and gate of the first N-channel field effect transistor are connected, the gate of the first N-channel field effect transistor is connected to the gate of the second N-channel field effect transistor, and the first N-channel
  • the source of the MOSFET is connected to the source of the second N-channel MOSFET;
  • the drain of the second N-channel FET is connected to the drain of the first P-channel FET, the drain of the first P-channel FET is connected to the gate, and the first P-channel
  • the gate of the MOSFET is connected to the gate of the second P-channel MOSFET;
  • the source of the first P-channel field effect transistor is connected to the source of the second P-channel field effect transistor, and is used to generate the operating voltage of the current generating circuit;
  • the drain of the second P-channel field effect transistor is connected to the main switch circuit, and is used to output the current of the current generating circuit to a stable state to the main switch circuit;
  • the first switch When the third clock signal is at a high level and the fourth clock signal is at a low level, the first switch is closed, the second switch is opened, and the first capacitor is charged until the first The voltage of a capacitor reaches the reference voltage, the first capacitor is discharged, and a current is output to increase the operating voltage of the current generating circuit;
  • the first N-channel field effect transistor, the second N-channel field effect transistor, the first P-channel field effect transistor and the first The two P-channel field effect transistors are turned on, so that the current generation circuit reaches a stable state, and the current when the current generation circuit reaches the stability is output to the main switching circuit through the drain of the second P-channel field effect transistor.
  • the first N-channel FET and the second N-channel FET are the same, and the first P-channel FET and the second P-channel FET are the same.
  • the main switch circuit includes: a third N-channel field effect transistor, a third capacitor, a fourth capacitor and a Zener diode;
  • the gate of the third N-channel field effect transistor is connected to the output end of the current generating circuit
  • the gate of the third N-channel field effect tube is connected to one end of the third capacitor, and the other end of the third capacitor is connected to the drain of the third N channel field effect tube;
  • the gate of the third N-channel field effect tube is connected to one end of the fourth capacitor, and the other end of the fourth capacitor is connected to the source of the third N channel field effect tube;
  • the fourth capacitor is connected in parallel with the Zener diode
  • the gate of the third N-channel field effect transistor receives the current output from the drain of the second P-channel field effect, the third capacitor and the fourth capacitor are charged, and the third N-channel field effect The voltage across the gate and the source of the tube is clamped by the Zener diode, so that the main switching circuit starts up under the action of the current.
  • the third N-channel field effect transistor is a main switching transistor of an analog switch opening circuit.
  • the gate-source voltage of the main switch tube rises slowly with time.
  • a second aspect of the present invention discloses an analog switch opening method, which is suitable for the analog switch circuit disclosed in the first aspect.
  • the analog switch slow opening circuit includes a control circuit, a current generating circuit, and a main switch circuit.
  • the method includes:
  • the control circuit decodes the input time setting signal into a second clock signal
  • the control circuit divides the second clock signal based on the input first clock signal to generate a third clock signal and a fourth clock signal with opposite phases;
  • the current generating circuit receives the third clock signal and the fourth clock signal with opposite phases;
  • the current generating circuit generates a current based on the control of the third clock signal and the fourth clock signal, and outputs the current to the main switching circuit;
  • the main switch circuit receives the current output by the current generation circuit, and completes startup under the action of the current.
  • the current generating circuit includes: a first switch, a second switch, a first capacitor, a second capacitor, a first N-channel field effect transistor, a second N-channel field effect transistor, a first P-channel field effect transistor and In a second P-channel field effect transistor, the current generation circuit generates a current based on the control of the third clock signal and the fourth clock signal, and outputs the current to the main switching circuit, including:
  • the first switch When the third clock signal is at a high level and the fourth clock signal is at a low level, the first switch is closed, the second switch is opened, and the first capacitor is charged until the first When the voltage of a capacitor reaches the reference voltage, the first capacitor discharges, increasing the operating voltage of the current generating circuit;
  • the first N-channel field effect transistor, the second N-channel field effect transistor, the first P-channel field effect transistor and the first The two P-channel field effect transistors are turned on, so that the current generation circuit reaches a stable state, and the current when the current generation circuit reaches stability is output to the main switching circuit through the drain of the second P-channel field effect transistor .
  • the main switch circuit includes: a third N-channel field effect transistor, a third capacitor, a fourth capacitor, and a Zener diode, and the main switch circuit receives the current output by the current generation circuit, and The completion of starting under the action of the current includes:
  • the gate of the third N-channel field effect transistor receives the current output from the drain of the second P-channel field effect transistor, charges the third capacitor and the fourth capacitor, and causes the third N-channel
  • the voltage across the gate and source of the MOSFET is clamped by the Zener diode, so that the main switching circuit is started under the action of the current.
  • the analog switch opening circuit includes: a control circuit, a current generating circuit, and a main switch circuit.
  • the control circuit decodes the input time setting signal into a second clock signal, and divides the second clock signal based on the input first clock signal to generate a third clock signal and a fourth clock signal with opposite phases .
  • the current generating circuit receives the third clock signal and the fourth clock signal, generates a current based on the control of the third clock signal and the fourth clock signal, and outputs the current to the main switching circuit .
  • the main switch circuit receives the current output by the current generation circuit, and completes startup under the action of the current. Therefore, the analog switch opening circuit and method disclosed in the embodiments of the present invention can solve the problem of POP sound generated by audio equipment caused by the switch opening too fast, and have an analog switch opening time adjustable function.
  • FIG. 1 is a schematic structural diagram of an analog switch opening circuit disclosed in an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another analog switch opening circuit disclosed in an embodiment of the present invention.
  • FIG. 3 is a waveform diagram of a third clock signal and a fourth clock signal disclosed in an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a voltage simulation curve at the connection between the voltage across the gate and source of the main switch tube and the gate of the first N-channel field effect tube and the drain of the first N-channel field effect tube disclosed in an embodiment of the present invention ;
  • FIG. 5 is a schematic flowchart of a method for opening a simulated switch disclosed in an embodiment of the present invention.
  • the slow opening circuit of the analog switch mainly uses a method of applying current to the capacitor to generate a delay.
  • the analog switch is closed to make the circuit conductive and the circuit
  • the Zener diode in the current generates a clamping voltage under the action of the current to provide the voltage required by the analog switch for the field effect transistor to complete the startup.
  • the analog switch can reach the microsecond level, it is still too fast. During the process of the analog switch being turned on, it will cause the device to generate POP sound. Therefore, an analog switch opening circuit and method disclosed in the embodiments of the present invention can solve the problem of POP sound generated by audio-type devices caused by the switch opening too fast, and have an analog switch opening time adjustable function.
  • FIG. 1 it is a schematic structural diagram of an analog switch turn-on circuit provided by an embodiment of the present invention.
  • the analog switch opening circuit includes: a control circuit 101, a current generating circuit 102, and a main switch circuit 103.
  • control circuit 101 is connected to the current generating circuit 102.
  • the control circuit 101 is used to generate a third clock signal and a fourth clock signal. After the third clock signal and the fourth clock signal are processed by the current generating circuit 102, the current generating circuit 102 outputs the main switch Current required by circuit 103. After the current is processed by the main switch circuit 103, the analog switch can be slowly started.
  • control circuit 101 is configured to decode the time setting signal input to the control circuit 101 into a second clock signal, and divide the frequency of the second clock signal based on the first clock signal input to the control circuit 101, The third clock signal and the fourth clock signal having opposite phases are generated.
  • time setting signal is used to indicate the time taken to turn on the analog switch circuit.
  • time setting signal is preset, and the time for turning on the analog switch circuit can be arbitrarily adjusted, which can be set according to the actual situation, which is not limited by the embodiment of the present invention.
  • the first time signal is used to indicate the time corresponding to the current clock.
  • the input terminal of the current generation circuit 102 is connected to the output terminal of the control circuit 101.
  • the current generating circuit 102 is configured to receive the third clock signal and the fourth clock signal with opposite phases.
  • the current generating circuit 102 generates a current based on the control of the third clock signal and the fourth clock signal and outputs The current goes to the main switch circuit 103.
  • the input terminal of the main switch circuit 103 is connected to the output terminal of the current generation circuit 102.
  • the main switch circuit 103 is configured to receive the current output by the current generation circuit 102 and complete the slow start of the analog switch under the action of the current.
  • the main switch circuit 103 is configured to receive the current output by the current generation circuit 102, and suppress the rise rate of the voltage of the main switch circuit 103 based on the current so that the main switch circuit The voltage of 103 rises slowly with time.
  • the analog switch opening circuit disclosed in the embodiment of the present invention includes a control circuit, a current generating circuit and a main switch circuit.
  • the control circuit decodes the input time setting signal into a second clock signal, and divides the second clock signal based on the input first clock signal to generate a third clock signal and a fourth clock signal having opposite phases.
  • the current generating circuit receives the third clock signal and the fourth clock signal, generates a current based on the control of the third clock signal and the fourth clock signal, and outputs the current to the main switching circuit.
  • the main switch circuit receives the current, receives the current output by the current generating circuit, and completes startup under the action of the current.
  • an analog switch opening circuit disclosed in an embodiment of the present invention, by inputting a time setting signal to the control circuit, the control circuit generates a third clock signal and a third clock signal based on the input time setting signal and the first clock signal
  • the fourth clock signal causes the current generation circuit to generate current based on the control of the received third clock signal and the fourth clock signal, so that the main switch circuit suppresses the speed of voltage rise based on the received current, thereby completing the slow start of the analog switch.
  • this embodiment since the time setting signal can be set in advance as required, this embodiment has an analog switch opening time adjustable function.
  • FIG. 2 it is a schematic structural diagram of another analog switch opening circuit provided by an embodiment of the present invention.
  • the analog switch opening circuit includes: a control circuit 201, a current generation circuit 202, and a main switch circuit 203.
  • the control circuit 201 includes a decoding module and a counter.
  • the decoding module is used to decode the input time setting signal into a second clock signal and transmit it to the counter.
  • the input terminal of the counter is connected to the output terminal of the decoding module, and is used to divide the second clock signal based on the input first clock signal to generate a third clock signal and a fourth clock signal with opposite phases.
  • the decoding module is a state machine implemented by digital codes.
  • FIG. 3 it is a waveform diagram of a third clock signal and a fourth clock signal provided by an embodiment of the present invention.
  • the current generating circuit 202 includes: a first switch S1, a second switch S2, a first capacitor C1, a second capacitor C2, a first N-channel field effect transistor N1, a second N-channel field effect transistor N2 1.
  • the control terminal of the first switch S1 is used to input the third clock signal, the first terminal of the first switch S1 is an input terminal of the reference voltage VB, and the second terminal of the first switch S1 is One end of the first capacitor C1 is connected, the second end of the first switch S1 is connected to the first end of the second switch S2, and the other end of the first capacitor C1 is grounded.
  • the control end of the second switch S2 is used to input the fourth clock signal, the second end of the second switch S2 is connected to one end of the second capacitor C2, and the second end of the second switch S2 It is connected to the drain of the first N-channel field effect transistor N1, and the other end of the second capacitor C2 is connected to the source of the first N-channel field effect transistor N1 and is grounded.
  • the drain of the first N-channel field effect transistor N1 is connected to the gate.
  • the gate of the first N-channel field effect transistor N1 is connected to the gate of the second N-channel field effect transistor N2.
  • the source of an N-channel field effect transistor N1 is connected to the source of the second N-channel field effect transistor N2.
  • the drain of the second N-channel field effect transistor N2 is connected to the drain of the first P-channel field effect transistor P1, the drain of the first P channel field effect transistor P1 is connected to the gate, and the first The gate of a P-channel field effect transistor P1 is connected to the gate of the second P-channel field effect transistor P2.
  • the source of the first P-channel field effect transistor P1 is connected to the source of the second P-channel field effect transistor P2, and is used to generate the operating voltage VDD of the current generating circuit.
  • the drain of the second P-channel field effect transistor P2 is connected to the main switching circuit 203, and is used to output the current of the current generating circuit 202 to a stable state to the main switching circuit 203.
  • the first switch S1 When the third clock signal is at a high level and the fourth clock signal is at a low level, the first switch S1 is closed, the second switch S2 is opened, and the first capacitor C1 is charged until The voltage of the first capacitor C1 reaches the reference voltage VB, the first capacitor C1 discharges, and outputs a current, so that the operating voltage VDD of the current generating circuit 202 rises.
  • the first N-channel field effect transistor N1, the second N-channel field effect transistor N2, the first P-channel field effect transistor P1 and The second P-channel field effect transistor P2 is turned on, so that the current generating circuit 202 reaches a stable state, and at this time, the current when the current generating circuit 202 reaches a stable state passes through the drain of the second P-channel field effect transistor P2
  • the electrode is output to the main switch circuit 203, specifically, to the gate of the third N-channel field effect transistor N3 in the main switch circuit 203.
  • the first switch S1 when the first switch S1 is closed and the second switch S2 is open, the first N-channel field effect transistor N1, the second N-channel field effect transistor N2, the The first P-channel field effect transistor P1 and the second P-channel field effect transistor P2 are turned on.
  • the first N-channel field effect transistor N1 and the second N-channel field effect transistor N2 are the same, that is, the gate width and gate length of the field effect transistor are equal, and the first P-channel field effect transistor P1 The same as the second P-channel field effect transistor P2.
  • the first output terminal of the counter is connected to the first switch S1
  • the second output terminal of the counter is connected to the second switch S2.
  • the first switch S1 is opened, the second switch S2 is closed, and the first capacitor C1 and the The second capacitor C2 is connected in parallel to increase the capacitance.
  • the first N-channel field effect transistor N1, the second N-channel field effect transistor N2, the first P-channel field effect transistor P1 and the second P-channel field effect transistor P2 are turned off, and no current is generated.
  • the magnitude of the current is:
  • I is the output current
  • f is the frequency of a third clock output signal
  • u n is the electron mobility
  • Cox is the gate oxide capacitance per unit area
  • W is the gate of the first N-channel FET N1 is wide
  • L is the gate length of the first N-channel field effect transistor N1
  • Vt is the turn-on threshold voltage of the field effect transistor
  • VB is the reference voltage
  • VA is the gate of the first N-channel field effect transistor N1 and the first N-channel field effect
  • the voltage of the common terminal connected to the drain of the tube N1, fC1 (VB-VA) is the charge that the first capacitor C1 carries from the reference voltage VB to the first N-channel field effect transistor per unit time.
  • the magnitude of the current I corresponds to the magnitude of the frequency of the third clock signal. The greater the frequency of the third clock signal, the greater the current I.
  • the main switch circuit 203 includes: a third N-channel field effect transistor N3, a third capacitor C3, a fourth capacitor C4, and a Zener diode D0.
  • the gate of the third N-channel field effect transistor N3 is connected to the drain of the second P-channel field effect transistor P2.
  • the gate of the third N-channel field effect transistor N3 is connected to one end of the third capacitor C3, and the other end of the third capacitor C3 is connected to the drain of the third N channel field effect transistor N3.
  • the gate of the third N-channel field effect transistor N3 is connected to one end of the fourth capacitor C4, and the other end of the fourth capacitor C4 is connected to the source of the third N channel field effect transistor N3.
  • the fourth capacitor C4 is connected in parallel with the Zener diode D0.
  • the gate of the third N-channel field effect transistor N3 receives the current output from the drain of the second P-channel P2, the third capacitor C3 and the fourth capacitor C4 are charged, and the third N The voltage across the gate and source of the channel field effect transistor N3 is clamped by the zener diode D0, so that the main switching circuit 203 is started under the action of the current.
  • the voltage across the gate and source of the third N-channel FET N3 is output, and the voltage across the gate and source is clamped by the Zener diode D0 to limit the voltage across the gate and source
  • the voltage output provides the required voltage for the start of the third N-channel field effect transistor N3, so that the main switch circuit 203 completes the start under the action of the current, thereby realizing the slow start of the analog switch. .
  • the third N-channel field effect transistor N3 is a main switching transistor of an analog switch opening circuit.
  • the voltage VA at the connection between the gate of the first N-channel field effect transistor N1 and the drain of the first N-channel field effect transistor N1 and the voltage of the main switch circuit The voltage VGS across the gate and source of the main switch tube is simulated, and the data is recorded to draw a graph.
  • the voltage between the gate and source of the main switch tube provided by an embodiment of the present invention is connected to the gate of the first N-channel field effect transistor and the drain of the first N-channel field effect transistor.
  • the voltage value of the voltage VA rapidly reaches an equilibrium with time.
  • the operating voltage VDD of the current generating circuit 102 is equal to the reference voltage VB, and the first N-channel field effect transistor N1, the second N-channel field effect transistor N2, the first P-channel field effect transistor P1 and the second P-channel field effect transistor P2 are turned on, so that the current generating circuit 102 reaches a stable state, at this time the current The current of the generating circuit reaching the steady state is output to the main switching circuit 103 through the drain of the second P-channel field effect transistor P2.
  • the gate-source voltage VGS of the main switching tube slowly rises with time, which means that the gate-source voltage VGS of the main switching tube is clamped by the Zener diode, limiting the gate
  • the voltage output across the pole and the source makes the gate-source voltage VGS of the main switch slowly rise with time, providing the required voltage for the start of the main switch to complete the slow start.
  • the analog switch opening circuit disclosed in the embodiment of the present invention includes a control circuit, a current generating circuit and a main switch circuit.
  • the control circuit decodes the input time setting signal into a second clock signal, and divides the second clock signal based on the input first clock signal to generate a third clock signal and a fourth clock signal having opposite phases.
  • the current generating circuit receives the third clock signal and the fourth clock signal. When the third clock signal is high level and the fourth clock signal is low level, the first capacitor is charged until the voltage of the first capacitor reaches the reference voltage After discharging, output current to the main switch circuit.
  • the main switch circuit When the main switch circuit receives current, after charging the third capacitor and the fourth capacitor, the voltage across the gate and source of the third N-channel field effect transistor is clamped by the Zener diode, so that the main switch The circuit completes startup under the action of the current. Therefore, through an analog switch opening circuit disclosed in an embodiment of the present invention, by inputting a time setting signal to a control circuit, the control circuit generates a third clock signal based on the input time setting signal and the first clock signal And the fourth clock signal, so that the main switch circuit suppresses the rise of the gate-source voltage of the main switch circuit based on the current generated by the current generation circuit, thereby completing the slow start of the analog switch, which can solve the audio equipment caused by the switch opening too fast The problem of POP sound is generated.
  • this embodiment since the time setting signal can be set in advance as required, this embodiment has an analog switch on time adjustable function.
  • an embodiment of the present invention also correspondingly discloses a method.
  • FIG. 5 it is a schematic flowchart of an analog switch opening method provided by an embodiment of the present invention.
  • the analog switch opening circuit includes: a control circuit, a current generating circuit and a main switch circuit.
  • the analog switch opening method includes:
  • step S501 the control circuit decodes the input time setting signal into a second clock signal.
  • control circuit includes a decoding module and a counter.
  • the decoding module decodes the input time setting signal into a second clock signal and transmits it to the counter.
  • Step S502 the control circuit divides the second clock signal based on the input first clock signal to generate a third clock signal and a fourth clock signal with opposite phases.
  • the counter divides the second clock signal based on the input first clock signal to generate a third clock signal and a fourth clock signal with opposite phases.
  • the third clock signal controls the first switch
  • the fourth clock signal controls the second switch
  • Step S503 the current generating circuit receives the third clock signal and the fourth clock signal in opposite phases, generates a current based on the control of the third clock signal and the fourth clock signal, and outputs the current to all Describe the main switch circuit.
  • the first switch is opened, the second switch is closed, and the first capacitor and the second capacitor Parallel increase the capacitance.
  • the first N-channel field effect tube, the second N-channel field effect tube, the first P-channel field effect tube and the second P-channel field effect tube are turned off, and no current is output.
  • step S504 the main switch circuit receives the current output by the current generation circuit, and completes startup under the action of the current.
  • the third N-channel field effect transistor is the main switching transistor of the analog switch opening circuit.
  • An analog switch opening method disclosed in an embodiment of the present invention decodes an input time setting signal into a second clock signal through a control circuit, and divides the second clock signal based on the input first clock signal to generate The third clock signal and the fourth clock signal having opposite phases. Receiving the third clock signal and the fourth clock signal in opposite phase through the current generation circuit, generating a current based on the control of the third clock signal and the fourth clock signal, and outputting the current to the Main switch circuit. The main switch circuit receives the current output by the current generation circuit, and completes startup under the action of the current.
  • an analog switch opening method disclosed in an embodiment of the present invention, by inputting a time setting signal to a control circuit, the control circuit generates a third clock signal and a third clock signal based on the input time setting signal and the first clock signal
  • the fourth clock signal enables the main switch circuit to suppress the rising speed of the gate-source voltage of the main switch circuit based on the current generated by the current generation circuit, thereby completing the slow start of the analog switch, which can solve the audio equipment caused by the switch being turned on too fast The problem of POP sound.
  • this embodiment since the time setting signal can be set in advance as required, this embodiment has an analog switch on time adjustable function.
  • the current generating circuit receives the third clock signal and the fourth clock signal having opposite phases.
  • the first switch is closed and the second switch is opened to charge the first capacitor until the The voltage of the first capacitor reaches the reference voltage, the first capacitor is discharged, and a current is output.
  • the first N-channel field effect transistor, the second N-channel field effect transistor, the first P-channel field effect transistor and the first The two P-channel field effect transistors are turned on, so that the analog switch opening circuit reaches a stable state, and the current is output to the gate of the third N-channel field effect transistor through the drain of the second P-channel field effect transistor.
  • the first N-channel field effect transistor, the second N-channel field effect transistor, the first P-channel field effect transistor and the second P-channel field effect transistor are turned on, then the The first N-channel field effect transistor is the same as the second N-channel field effect transistor, that is, the gate width and gate length of the field effect transistor are equal, then the first P-channel field effect transistor and the second P-channel field effect transistor The tube is the same.
  • the voltage at the connection between the gate of the first N-channel field effect transistor and the drain of the first N-channel field effect transistor is the voltage of the current generating circuit.
  • the third clock signal and the fourth clock signal having opposite phases are received by the current generating circuit.
  • the first switch is closed, the second switch is opened, and the first capacitor is charged until the first The voltage of a capacitor reaches the reference voltage, the first capacitor is discharged, and a current is output.
  • the first N-channel field effect transistor, the second N-channel field effect transistor, the first P-channel field effect transistor and the second P The channel field effect transistor is turned on, so that the analog switch opening circuit reaches a stable state, and the current is output to the gate of the third N channel field effect transistor through the drain of the second P channel field effect transistor.
  • the control circuit by inputting the time setting signal to the control circuit, the control circuit generates a third clock signal and a fourth clock signal based on the input time setting signal and the first clock signal, so that Based on the current generated by the current generation circuit, the main switch circuit suppresses the rise rate of the gate-source voltage of the main switch circuit, thereby completing the slow start of the analog switch, which can solve the problem of POP sound generated by audio equipment caused by the switch being turned on too quickly. Since the time setting signal can be set in advance as required, this embodiment has the function of adjusting the opening time of the analog switch.
  • the voltage across the gate and source of the third N-channel field effect transistor is clamped by the Zener diode to limit the voltage output across the gate and source, and the startup is completed.
  • the analog switch opening method disclosed in the above steps limits the voltage output across the gate and the source. It can solve the problem of POP sound generated by the audio equipment caused by the switch being turned on too fast, and has the function of adjusting the opening time of the analog switch.
  • An analog switch opening method disclosed in an embodiment of the present invention decodes an input time setting signal into a second clock signal through a control circuit, and divides the second clock signal based on the input first clock signal to generate The third clock signal and the fourth clock signal having opposite phases.
  • the third and fourth clock signals with opposite phases are received through the current generation circuit.
  • the third clock signal is high and the fourth clock signal is low, the first capacitor is charged until the first The voltage of a capacitor discharges after reaching the reference voltage, and outputs the current to the main switching circuit.
  • the main switch circuit receives the current output from the current generating circuit, charges the third capacitor and the fourth capacitor, and the voltage across the gate and source of the third N-channel field effect transistor is clamped by the Zener diode, so that the The main switch circuit completes startup under the action of the current. Therefore, through an analog switch opening method disclosed in an embodiment of the present invention, by inputting a time setting signal to a control circuit, the control circuit generates a third clock signal and a third clock signal based on the input time setting signal and the first clock signal The fourth clock signal enables the main switch circuit to suppress the rise rate of the gate-source voltage of the main switch circuit based on the current generated by the current generation circuit, thereby completing the slow start.
  • this embodiment since the time setting signal can be set in advance as needed, this embodiment has an analog switch on time adjustable function.

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Abstract

一种模拟开关开启电路及方法，该模拟开关电路包括：控制电路(101)、电流产生电路(102)和主开关电路(103)。控制电路(101)将输入的时间设定信号解码成第二时钟信号，并基于输入的第一时钟信号将第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号。电流产生电路(102)接收第三时钟信号和第四时钟信号，基于所述第三时钟信号和第四时钟信号的控制产生电流，并输出电流至主开关电路(103)。主开关电路(103)接收电流，并在电流的作用下完成启动。因此，该方法能够解决开关开启过快而导致的音频类设备产生POP声的问题。

Description

一种模拟开关开启电路及方法
本申请要求于2018年12月17日提交中国专利局、申请号为201811544435.7、发明名称为“一种模拟开关开启电路及方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体集成电路技术领域，尤其涉及一种模拟开关开启电路及方法。
背景技术
随着半导体技术的不断发展和进步，由半导体所制成的模拟开关也被广泛的应用于各个领域，成为我们生活中必不可少的一部分。半导体集成电路中的模拟开关在信号传播通道有着广泛应用，模拟开关主要是完成信号链路中的信号切换功能，其功能类似于开关。其中，音频类设备的模拟开关在开启时，由于开启过快，会导致相关的音频类设备产生POP声。
当前，模拟开关常用电容及电阻、开关电容或电流施加于电容的方法产生开关电压的滤波来对电路启动产生一定的延时。在现有技术中，模拟开关的缓慢开启电路主要是利用电流施加于电容的方法产生延时，在模拟开关的缓慢开启电路启动时，模拟开关闭合，齐纳二极管在电流的作用下产生钳位电压，为场效应管提供模拟开关所需要的电压，完成启动。但是，对于音频类的设备而言，该模拟开关开启虽然可以达到微秒级别，但仍然过快，在开关开启的过程中，会导致设备产生POP声。
由此可知，现有技术中模拟开关的缓慢开启电路，无法避免由开关开启过快而导致的音频类设备产生POP声。
发明内容
有鉴于此，本发明实施例提供一种模拟开关开启电路及方法，以解决现有技术中无法避免由开关开启过快而导致的音频类设备产生POP声的问题。
进一步地，本发明实施例提供的模拟开关开启电路及方法，具备模拟开关开启时间可调功能。
为实现上述目的，本发明实施例提供如下技术方案：
本发明第一方面公开了一种模拟开关开启电路，所述模拟开关开启电路包括：控制电路、电流产生电路和主开关电路；
所述控制电路，用于将输入的时间设定信号解码成第二时钟信号，以及基于输入的第一时钟信号将所述第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号；
所述电流产生电路的输入端与所述控制电路的输出端相连，用于接收所述第三时钟信号和第四时钟信号，所述电流产生电路基于所述第三时钟信号和第四时钟信号的控制产生电流，并输出所述电流至所述主开关电路；
所述主开关电路的输入端与所述电流产生电路的输出端相连，用于接收所述电流产生电路输出的所述电流，并在所述电流的作用下完成启动。
优选地，所述控制电路，包括：解码模块和计数器；
所述解码模块，用于将输入的时间设定信号解码成第二时钟信号，并传送给计数器；
所述计数器的输入端与所述解码模块的输出端相连，用于基于输入的第一时钟信号将所述第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号。
优选地，所述电流产生电路，包括：第一开关、第二开关、第一电容、第二电容、第一N沟道场效应管、第二N沟道场效应管、第一P沟道场效应管和第二P沟道场效应管；
所述第一开关的控制端用于输入所述第三时钟信号，所述第一开关的第一端为参考电压输入端，所述第一开关的第二端与所述第一电容的一端相连，所述第一开关的第二端与所述第二开关的第一端相连，所述第一电容的另一端接地；
所述第二开关的控制端用于输入所述第四时钟信号，所述第二开关的第二端与所述第二电容的一端相连，所述第二开关的第二端与所述第一N沟道场效应管的漏极相连，所述第二电容的另一端与所述第一N沟道场效应管的源 极相连，且接地；
所述第一N沟道场效应管的漏极和栅极连接，所述第一N沟道场效应管的栅极与所述第二N沟道场效应管的栅极相连，所述第一N沟道场效应管的源极与所述第二N沟道场效应管的源极相连；
所述第二N沟道场效应管的漏极与所述第一P沟道场效应管的漏极相连，所述第一P沟道场效应管的漏极与栅极连接，所述第一P沟道场效应管的栅极和所述第二P沟道场效应管的栅极相连；
所述第一P沟道场效应管的源极与所述第二P沟道场效应管的源极相连，用于产生所述电流产生电路的工作电压；
所述第二P沟道场效应管的漏极和主开关电路相连，用于将电流产生电路达到稳定状态的电流输出至所述主开关电路；
当所述第三时钟信号为高电平，所述第四时钟信号为低电平时，所述第一开关闭合，所述第二开关断开，为所述第一电容充电，直至所述第一电容的电压到达所述参考电压，所述第一电容放电，输出电流，使电流产生电路的工作电压升高；
当所述电流产生电路的工作电压和所述参考电压相等时，所述第一N沟道场效应管、所述第二N沟道场效应管、所述第一P沟道场效应管和所述第二P沟道场效应管导通，使得所述电流产生电路达到稳定状态，将电流产生电路达到稳定时的电流通过第二P沟道场效应管的漏极输出至所述主开关电路。
优选地，所述第一N沟道场效应管和所述第二N沟道场效应管相同，所述第一P沟道场效应管和所述第二P沟道场效应管相同。
优选地，所述主开关电路，包括：第三N沟道场效应管、第三电容、第四电容和齐纳二极管；
所述第三N沟道场效应管的栅极与所述电流产生电路的输出端相连；
所述第三N沟道场效应管的栅极与所述第三电容的一端相连，所述第三电容的另一端与所述第三N沟道场效应管的漏极相连；
所述第三N沟道场效应管的栅极与所述第四电容的一端相连，所述第四电容的另一端与所述第三N沟道场效应管的源极相连；
所述第四电容与所述齐纳二极管并联；
当所述第三N沟道场效应管的栅极接收所述第二P沟道场效应的漏极输出的电流时，对所述第三电容和第四电容充电，所述第三N沟道场效应管的栅极和源极两端的电压被所述齐纳二极管钳位，使所述主开关电路在所述电流的作用下完成启动。
优选地，所述第三N沟道场效应管为模拟开关开启电路的主开关管。
优选地，所述主开关管的栅源电压随着时间的变化而缓慢上升。
本发明第二方面公开了一种模拟开关开启方法，适用于第一方面公开的模拟开关电路，所述模拟开关缓慢开启电路包括控制电路，电流产生电路和主开关电路，该方法包括：
所述控制电路将输入的时间设定信号解码成第二时钟信号；
所述控制电路基于输入的第一时钟信号将所述第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号；
所述电流产生电路接收所述相位相反的第三时钟信号和第四时钟信号；
所述电流产生电路基于所述第三时钟信号和所述第四时钟信号的控制产生电流，并输出所述电流至所述主开关电路；
所述主开关电路接收所述电流产生电路输出的所述电流，并在所述电流的作用下完成启动。
优选地，所述电流产生电路包括：第一开关、第二开关、第一电容、第二电容、第一N沟道场效应管、第二N沟道场效应管、第一P沟道场效应管和第二P沟道场效应管，所述电流产生电路基于所述第三时钟信号和所述第四时钟信号的控制产生电流，并输出所述电流至所述主开关电路，包括：
当所述第三时钟信号为高电平，所述第四时钟信号为低电平时，所述第一开关闭合，所述第二开关断开，为所述第一电容充电，直至所述第一电容的电压到达所述参考电压时，所述第一电容放电，使电流产生电路的工作电压升高；
当所述电流产生电路的工作电压和所述参考电压相等时，所述第一N沟道场效应管、所述第二N沟道场效应管、所述第一P沟道场效应管和所述第二P沟道场效应管导通，使得所述电流产生电路达到稳定状态，将所述电流产生电路达到稳定时的电流通过所述第二P沟道场效应管的漏极输出至所述主开关电路。
优选地，所述主开关电路，包括：第三N沟道场效应管、第三电容、第四电容和齐纳二极管，所述主开关电路接收所述电流产生电路输出的所述电流，并在所述电流的作用下完成启动，包括：
所述第三N沟道场效应管的栅极接收所述第二P沟道场效应管的漏极输出的电流，对所述第三电容和所述第四电容充电，使所述第三N沟道场效应管栅极和源极两端的电压被所述齐纳二极管钳位，使所述主开关电路在所述电流的作用下完成启动。
基于上述本发明实施例提供的模拟开关开启电路及方法，所述模拟开关开启电路包括：控制电路、电流产生电路和主开关电路。所述控制电路将输入的时间设定信号解码成第二时钟信号，以及基于输入的第一时钟信号将所述第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号。所述电流产生电路接收所述第三时钟信号和所述第四时钟信号，基于所述第三时钟信号和所述第四时钟信号的控制产生电流，并输出所述电流至所述主开关电路。所述主开关电路接收所述电流产生电路输出的所述电流，并在所述电流的作用下完成启动。因此，通过本发明实施例公开的一种模拟开关开启电路及方法，能够解决由开关开启过快而导致的音频类设备产生POP声的问题，且具备模拟开关开启时间可调功能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本发明实施例公开的一种模拟开关开启电路的结构示意图；
图2为本发明实施例公开的另一种模拟开关开启电路的结构示意图；
图3为本发明实施例公开的第三时钟信号和第四时钟信号的波形图；
图4为本发明实施例公开的主开关管栅极和源极两端的电压与第一N沟道场效应管的栅极和第一N沟道场效应管的漏极连接处的电压仿真曲线的示意图；
图5为本发明实施例公开的一种模拟开关开启方法的流程示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本申请中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
由背景技术可知，现有技术中，模拟开关的缓慢开启电路主要是利用电流施加于电容的方法产生延时，在模拟开关的缓慢开启电路启动时，该模拟开关闭合，使电路导通，电路中的齐纳二极管在电流的作用下产生钳位电压，为场效应管提供模拟开关所需要的电压，完成启动。但是，对于音频类的设备而言，该模拟开关开启虽然可以达到微秒级别，但仍然过快，在模拟开关开启的过程中，会导致设备产生POP声。因此，本发明实施例公开的一种模拟开关开启电路及方法，能够解决由开关开启过快而导致的音频类设备产生POP声的问题，且具备模拟开关开启时间可调功能。
如图1所示，为本发明实施例提供的一种模拟开关开启电路的结构示意图。
所述模拟开关开启电路包括：控制电路101、电流产生电路102和主开关电路103。
其中，所述控制电路101与所述电流产生电路102相连。所述控制电路101用于产生第三时钟信号和第四时钟信号，所述第三时钟信号和第四时钟信号经过所述电流产生电路102处理后，所述电流产生电路102输出所述主开关电路103所需的电流。所述电流经过主开关电路103处理后，能够完成缓慢启动模拟开关。
具体的，所述控制电路101，用于将输入控制电路101的时间设定信号解码成第二时钟信号，以及基于输入控制电路101的第一时钟信号将所述第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号。
需要说明的是，时间设定信号用于指示开启模拟开关电路所用的时间。
进一步的，时间设定信号是预先设置的，可随意调节模拟开关电路的开启所用时间，对此可根据实际情况设置，本发明实施例不加以限制。
第一时间信号用于指示当前的时钟对应的时间。
具体的，所述电流产生电路102的输入端与所述控制电路101的输出端相连。所述电流产生电路102，用于接收所述相位相反的第三时钟信号和第四时钟信号，所述电流产生电路102基于所述第三时钟信号和第四时钟信号的控制产生电流，并输出所述电流至所述主开关电路103。
具体的，所述主开关电路103的输入端与所述电流产生电路102的输出端相连。所述主开关电路103，用于接收所述电流产生电路102输出的所述电流，并在所述电流的作用下完成缓慢启动模拟开关。
在具体实现中，所述主开关电路103，用于接收所述电流产生电路102输出的所述电流，并基于所述电流抑制所述主开关电路103的电压的上升速度使得所述主开关电路103的电压随着时间的变化而缓慢上升。
本发明实施例公开的模拟开关开启电路，包括控制电路、电流产生电路和主开关电路。所述控制电路将输入的时间设定信号解码成第二时钟信号，以及基于输入的第一时钟信号将第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号。所述电流产生电路接收第三时钟信号和第四时钟信号，并基于所述第三时钟信号和第四时钟信号的控制产生电流，并输出所述电流至所述主开关电路。所述主开关电路接收电流，接收所述电流产生电路输出的所述电流，并在所述电流的作用下完成启动。因此，通过本发明实施例公开的一种模拟开关开启电路，通过将时间设定信号输入至控制电路，此时控制电路基于输入的时间设定信号和第一时钟信号，产生第三时钟信号和第四时钟信号，使电流产生电路基于接收到的第三时钟信号和第四时钟信号的控制产生电流，使主开关电路基于接收到的电流抑制电压上升的速度，从而完成缓慢启动模拟开关，解决由开关开启过快而导致的音频类设备产生POP声的问题，此外，由 于时间设定信号可以根据需要预先设置，因而本实施例具备模拟开关开启时间可调功能。
进一步的，如图2所示，为本发明实施例提供的另一种模拟开关开启电路的结构示意图，所述模拟开关开启电路包括：控制电路201、电流产生电路202和主开关电路203。
所述控制电路201包括：解码模块和计数器。
其中，所述解码模块，用于将输入的时间设定信号解码成第二时钟信号，并传送给计数器。
所述计数器的输入端与所述解码模块的输出端相连，用于基于输入的第一时钟信号将所述第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号。
需要说明的是，在一个可选方案中，所述解码模块是数字代码实现的状态机。
基于上述图2中示出的控制电路201，对所述相位相反的第三时钟信号和第四时钟信号的具体表现绘制波形图。如图3所示，为本发明实施例提供的第三时钟信号和第四时钟信号的波形图。
继续参阅图2，所述电流产生电路202包括：第一开关S1、第二开关S2、第一电容C1、第二电容C2、第一N沟道场效应管N1、第二N沟道场效应管N2、第一P沟道场效应管P1和第二P沟道场效应管P2。
其中，所述第一开关S1的控制端用于输入所述第三时钟信号，所述第一开关S1的第一端为参考电压VB输入端，所述第一开关S1的第二端与所述第一电容C1的一端相连，所述第一开关S1的第二端与所述第二开关S2的第一端相连，所述第一电容C1的另一端接地。
所述第二开关S2的控制端用于输入所述第四时钟信号，所述第二开关S2的第二端与所述第二电容C2的一端相连，所述第二开关S2的第二端与所述第一N沟道场效应管N1的漏极相连，所述第二电容C2的另一端与所述第一N沟道场效应管N1的源极相连，且接地。
所述第一N沟道场效应管N1的漏极和栅极连接，所述第一N沟道场效应管N1的栅极与所述第二N沟道场效应管N2的栅极相连，所述第一N沟道 场效应管N1的源极与所述第二N沟道场效应管N2的源极相连。
所述第二N沟道场效应管N2的漏极与所述第一P沟道场效应管P1的漏极相连，所述第一P沟道场效应管P1的漏极与栅极连接，所述第一P沟道场效应管P1的栅极和所述第二P沟道场效应管P2的栅极相连。
所述第一P沟道场效应管P1的源极与所述第二P沟道场效应管P2的源极相连，用于产生电流产生电路的工作电压VDD。
所述第二P沟道场效应管P2的漏极和主开关电路203相连，用于将电流产生电路202达到稳定状态的电流输出至所述主开关电路203。
当所述第三时钟信号为高电平，所述第四时钟信号为低电平时，所述第一开关S1闭合，所述第二开关S2断开，为所述第一电容C1充电，直至所述第一电容C1的电压到达所述参考电压VB，所述第一电容C1放电，输出电流，使得电流产生电路202的工作电压VDD升高。
当所述电路的工作电压VDD和所述参考电压VB相等时，所述第一N沟道场效应管N1、所述第二N沟道场效应管N2、所述第一P沟道场效应管P1和所述第二P沟道场效应管P2导通，使得所述电流产生电路202达到稳定状态，此时将所述电流产生电路202达到稳定状态时的电流通过第二P沟道场效应管P2的漏极输出至主开关电路203，具体地，输出至主开关电路203中第三N沟道场效应管N3的栅极。
需要说明的是，在所述第一开关S1闭合，所述第二开关S2断开的情形下，所述第一N沟道场效应管N1、所述第二N沟道场效应管N2、所述第一P沟道场效应管P1和所述第二P沟道场效应管P2导通。优选地，所述第一N沟道场效应管N1和所述第二N沟道场效应管N2相同，即所述场效应管的栅宽和栅长相等，所述第一P沟道场效应管P1和所述第二P沟道场效应管P2也相同。
需要说明的是，所述计数器的第一输出端与所述第一开关S1相连，所述计数器的第二输出端与所述第二开关S2相连。当所述第三时钟信号为高电平，第四时钟信号为低电平时，第一开关S1闭合，第二开关S2断开。
需要说明的是，当所述第三时钟信号为低电平，第四时钟信号为高电平时，所述第一开关S1断开，第二开关S2闭合，所述第一电容C1和所述第二电容C2 并联提高电容容量。所述第一N沟道场效应管N1、所述第二N沟道场效应管N2、所述第一P沟道场效应管P1和所述第二P沟道场效应管P2截止，无电流产生。
基于上述电流产生电路202的具体结构，下面则对所述电流产生电路202的输出的具体原理进行阐述说明。
所述电流的大小为:
Figure PCTCN2019125837-appb-000001
其中，I为输出的电流，f为第三时钟信号的输出频率，u n为电子的迁移率，Cox是单位面积的栅氧化层电容，W为第一N沟道场效应管N1的栅宽，L为第一N沟道场效应管N1的栅长，Vt为场效应管的导通阈值电压，VB为参考电压，VA为第一N沟道场效应管N1的栅极与第一N沟道场效应管N1的漏极连接的公共端的电压，fC1(VB-VA)是单位时间内第一电容C1从参考电压VB运送到第一N沟道场效应管的电荷。
将所述公式(1)进行计算得到第一N沟道场效应管N1的栅极与第一N沟道场效应管N1的漏极并联的电压VA：
Figure PCTCN2019125837-appb-000002
需要说明的是，将公式(2)带入公式(1)进行计算得到所述电流I的表达式：
Figure PCTCN2019125837-appb-000003
由公式(3)可知，所述电流I的大小与所述第三时钟信号的频率的大小相对应。其中，所述第三时钟信号的频率的越大，则所述电流I也越大。
继续参阅图2，所述主开关电路203包括：第三N沟道场效应管N3、第三电容C3、第四电容C4和齐纳二极管D0。
其中，所述第三N沟道场效应管N3的栅极与所述第二P沟道场效应管P2的漏极相连。
所述第三N沟道场效应管N3的栅极与所述第三电容C3的一端相连，所述第三电容C3的另一端与所述第三N沟道场效应管N3的漏极相连。
所述第三N沟道场效应管N3的栅极与所述第四电容C4的一端相连，所述第四电容C4的另一端与所述第三N沟道场效应管N3的源极相连。
所述第四电容C4与所述齐纳二极管D0并联。
当所述第三N沟道场效应管N3的栅极接收所述第二P沟道P2的漏极输出的电流时，对所述第三电容C3和第四电容C4充电，所述第三N沟道场效应管N3的栅极和源极两端的电压被所述齐纳二极管D0钳位，使所述主开关电路203时在所述电流的作用下完成启动。
针对上述主开关电路203的具体实现过程进行如下说明：
当所述第三N沟道场效应管N3的栅极接收所述第二P沟道场效应管P2的漏极输出的电流时，对所述第三电容C3和第四电容C4充电。
接着，输出第三N沟道场效应管N3栅极和源极两端的电压，所述栅极和源极两端的电压被所述齐纳二极管D0钳位，限制所述栅极和源极两端的电压输出，为第三N沟道场效应管N3的启动提供所需的电压，使所述主开关电路203在所述电流的作用下完成启动，从而实现模拟开关的缓慢启动。。
需要说明的是，所述第三N沟道场效应管N3为模拟开关开启电路的主开关管。
基于上述图2示出的模拟开关开启电路，对所述第一N沟道场效应管N1的栅极和第一N沟道场效应管N1的漏极连接处的电压VA与所述主开关电路的主开关管的栅极和源极两端的电压VGS进行仿真，并记录数据绘制曲线图。如图4所示，为本发明一个实施例提供的主开关管栅极和源极两端的电压与第一N沟道场效应管的栅极和第一N沟道场效应管的漏极连接处的电压仿真曲线的示意图。
如图4所示，所述电压VA的电压值随着时间的变化快速达到均衡，此时说明电流产生电路102的工作电压VDD和所述参考电压VB相等，所述第一N沟道场效应管N1、所述第二N沟道场效应管N2、所述第一P沟道场效应管P1和所述 第二P沟道场效应管P2导通，使得电流产生电路102达到稳定状态，此时将电流产生电路的达到稳定状态的电流通过第二P沟道场效应管P2的漏极输出主开关电路103。
继续参阅图4，所述主开关管的栅源电压VGS随着时间的变化而缓慢上升，此时说明所述主开关管的栅源电压VGS被所述齐纳二极管钳位，限制所述栅极和源极两端的电压输出，使得所述主开关管的栅源电压VGS随着时间的变化而缓慢上升，为主开关管的启动提供所需的电压，从而完成缓慢启动。
本发明实施例公开的模拟开关开启电路，包括控制电路、电流产生电路和主开关电路。所述控制电路将输入的时间设定信号解码成第二时钟信号，以及基于输入的第一时钟信号将第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号。所述电流产生电路接收第三时钟信号和第四时钟信号，当第三时钟信号为高电平，第四时钟信号为低电平时，对第一电容充电，直至第一电容的电压到达参考电压后放电，输出电流至所述主开关电路。当所述主开关电路接收电流时，对第三电容和第四电容充电后，所述第三N沟道场效应管栅极和源极两端的电压被齐纳二极管钳位，使所述主开关电路在所述电流的作用下完成启动。因此，通过本发明实施例公开的一种模拟开关开启电路，通过将时间设定信号，输入至控制电路，此时控制电路基于输入的时间设定信号和第一时钟信号，产生第三时钟信号和第四时钟信号，使主开关电路基于电流产生电路产生的电流抑制主开关电路的栅源电压的上升的速度，从而完成缓慢启动模拟开关，能够解决由开关开启过快而导致的音频类设备产生POP声的问题，此外，由于时间设定信号可以根据需要预先设置，因而本实施例具备模拟开关开启时间可调功能。
基于上述本发明实施例公开的模拟开关开启电路，本发明实施例还对应公开了一种方法，如图5所示，为本发明实施例提供的一种模拟开关开启方法的流程示意图，所述模拟开关开启电路包括：控制电路、电流产生电路和主开关电路，所述模拟开关开启方法包括：
步骤S501，所述控制电路将输入的时间设定信号解码成第二时钟信号。
需要说明的是，所述控制电路包括解码模块和计数器。
进一步，需要说明的是，所述解码模块将输入的时间设定信号解码成第二 时钟信号，并传送给计数器。
步骤S502，所述控制电路基于输入的第一时钟信号将所述第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号。
需要说明的是，所述计数器基于输入的第一时钟信号将所述第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号。
进一步，需要说明的是，所述第三时钟信号控制第一开关，第四时钟信号控制第二开关。
步骤S503，所述电流产生电路接收所述相位相反的第三时钟信号和第四时钟信号，基于所述第三时钟信号和所述第四时钟信号的控制产生电流，并输出所述电流至所述主开关电路。
需要说明的是，当所述第三时钟信号为低电平，第四时钟信号为高电平时，所述第一开关断开，第二开关闭合，所述第一电容和所述第二电容并联提高电容容量。所述第一N沟道场效应管、所述第二N沟道场效应管、所述第一P沟道场效应管和所述第二P沟道场效应管截止，无电流输出。
步骤S504，所述主开关电路接收所述电流产生电路输出的所述电流，并在所述电流的作用下完成启动。
需要说明的是，第三N沟道场效应管为模拟开关开启电路的主开关管。
上述本发明实施例公开的模拟开关开启电路中的各个模块和单元具体的原理和执行过程，与上述本发明实施例公开的模拟开关开启方法相同，可参见上述本发明实施例公开的模拟开关开启电路中相应的部分，这里不再进行赘述。
本发明实施例公开的一种模拟开关开启方法，通过控制电路将输入的时间设定信号解码成第二时钟信号，以及基于输入的第一时钟信号将所述第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号。再通过所述电流产生电路接收所述相位相反的第三时钟信号和第四时钟信号，基于所述第三时钟信号和所述第四时钟信号的控制产生电流，并输出所述电流至所述主开关电路。所述主开关电路接收所述电流产生电路输出的所述电流，并在所述电流的作用下完成启动。因此，通过本发明实施例公开的一种模拟开关开启方法，通过将时间设定信号输入至控制电路，此时控制电路基于输入的时间设定信号 和第一时钟信号，产生第三时钟信号和第四时钟信号，使主开关电路基于电流产生电路产生的电流抑制主开关电路的栅源电压的上升的速度，从而完成缓慢启动模拟开关，能够解决由开关开启过快而导致的音频类设备产生POP声的问题，此外，由于时间设定信号可以根据需要预先设置，因而本实施例具备模拟开关开启时间可调功能。
基于上述步骤S503的执行过程，下面进行详细说明：
首先，所述电流产生电路接收所述相位相反的第三时钟信号和第四时钟信号。
其次，当所述第三时钟信号为高电平，所述第四时钟信号为低电平时，所述第一开关闭合，所述第二开关断开，为所述第一电容充电，直至所述第一电容的电压到达所述参考电压，所述第一电容放电，输出电流。
最后，当所述电路的工作电压和所述参考电压相等时，所述第一N沟道场效应管、所述第二N沟道场效应管、所述第一P沟道场效应管和所述第二P沟道场效应管导通，使得模拟开关开启电路达到稳定状态，电流通过第二P沟道场效应管的漏极输出至第三N沟道场效应管的栅极。
需要说明的是，所述第一N沟道场效应管、所述第二N沟道场效应管、所述第一P沟道场效应管和所述第二P沟道场效应管导通，则所述第一N沟道场效应管和所述第二N沟道场效应管相同，即场效应管的栅宽和栅长相等，则所述第一P沟道场效应管和所述第二P沟道场效应管也相同。
进一步，需要说明的是，所述第一N沟道场效应管的栅极与所述第一N沟道场效应管的漏极连接处的电压为所述电流产生电路的电压。
基于上述步骤可知，通过所述电流产生电路接收所述相位相反的第三时钟信号和第四时钟信号。当所述第三时钟信号为高电平，所述第四时钟信号为低电平时，所述第一开关闭合，所述第二开关断开，为所述第一电容充电，直至所述第一电容的电压到达所述参考电压，所述第一电容放电，输出电流。当所述电路的工作电压和所述参考电压相等时，所述第一N沟道场效应管、所述第二N沟道场效应管、所述第一P沟道场效应管和所述第二P沟道场效应管导通，使得模拟开关开启电路达到稳定状态，电流通过第二P沟道场效应管的漏极输出至第三N沟道场效应管的栅极。通过上述步骤公开的模拟开关开启方法，通 过将时间设定信号输入至控制电路，此时控制电路基于输入的时间设定信号和第一时钟信号，产生第三时钟信号和第四时钟信号，使主开关电路基于电流产生电路产生的电流抑制主开关电路的栅源电压的上升的速度，从而完成缓慢启动模拟开关，能够解决由开关开启过快而导致的音频类设备产生POP声的问题，此外，由于时间设定信号可以根据需要预先设置，因而本实施例具备模拟开关开启时间可调功能。
基于上述步骤S504的执行过程，下面进行详细说明：
首先，当所述第三N沟道场效应管的栅极接收所述第二P沟道场效应管的漏极输出的电流时，对所述第三电容和第四电容充电。
然后，所述第三N沟道场效应管的栅极和源极两端的电压被所述齐纳二极管钳位，限制所述栅极和源极两端的电压输出，完成启动。
基于上述步骤可知，当所述第三N沟道场效应管的栅极接收所述第二P沟道场效应管的漏极输出的电流时，对所述第三电容和第四电容充电。所述第三N沟道场效应管栅极和源极两端的电压被所述齐纳二极管钳位，限制所述栅极和源极两端的电压输出，完成启动。因此，通过上述步骤公开的模拟开关开启方法，限制所述栅极和源极两端的电压输出。能够解决由开关开启过快而导致的音频类设备产生POP声的问题，且具备模拟开关开启时间可调功能。
本发明实施例公开的一种模拟开关开启方法，通过控制电路将输入的时间设定信号解码成第二时钟信号，以及基于输入的第一时钟信号将所述第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号。再通过所述电流产生电路接收所述相位相反的第三时钟信号和第四时钟信号，当第三时钟信号为高电平，第四时钟信号为低电平时，对第一电容充电，直至第一电容的电压到达参考电压后放电，输出所述电流至所述主开关电路。所述主开关电路接收所述电流产生电路输出的电流，对第三电容和第四电容充电，第三N沟道场效应管栅极和源极两端的电压被齐纳二极管钳位，使所述主开关电路在所述电流的作用下完成启动。因此，通过本发明实施例公开的一种模拟开关开启方法，通过将时间设定信号输入至控制电路，此时控制电路基于输入的时间设定信号和第一时钟信号，产生第三时钟信号和第四时钟信号，使主开关电路基于电流产生电路产生的电流抑制主开关电路的栅源电压的上升的速度，从而完成缓慢 启动能够解决由开关开启过快而导致的音频类设备产生POP声的问题，此外，由于时间设定信号可以根据需要预先设置，因而本实施例具备模拟开关开启时间可调功能。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统或系统实施例而言，由于其基本相似于方法实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。以上所描述的系统及系统实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性劳动的情况下，即可以理解并实施。
专业人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种模拟开关开启电路，其特征在于，所述模拟开关开启电路包括：控制电路、电流产生电路和主开关电路；
    所述控制电路，用于将输入的时间设定信号解码成第二时钟信号，以及基于输入的第一时钟信号将所述第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号；
    所述电流产生电路的输入端与所述控制电路的输出端相连，用于接收所述第三时钟信号和第四时钟信号，所述电流产生电路基于所述第三时钟信号和第四时钟信号的控制产生电流，并输出所述电流至所述主开关电路；
    所述主开关电路的输入端与所述电流产生电路的输出端相连，用于接收所述电流产生电路输出的所述电流，并在所述电流的作用下完成启动。
  2. 根据权利要求1所述的模拟开关开启电路，其特征在于，所述控制电路，包括：解码模块和计数器；
    所述解码模块，用于将输入的时间设定信号解码成第二时钟信号，并传送给计数器；
    所述计数器的输入端与所述解码模块的输出端相连，用于基于输入的第一时钟信号将所述第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号。
  3. 根据权利要求1所述的模拟开关开启电路，其特征在于，所述电流产生电路，包括：第一开关、第二开关、第一电容、第二电容、第一N沟道场效应管、第二N沟道场效应管、第一P沟道场效应管和第二P沟道场效应管；
    所述第一开关的控制端用于输入所述第三时钟信号，所述第一开关的第一端为参考电压输入端，所述第一开关的第二端与所述第一电容的一端相连，所述第一开关的第二端与所述第二开关的第一端相连，所述第一电容的另一端接地；
    所述第二开关的控制端用于输入所述第四时钟信号，所述第二开关的第二端与所述第二电容的一端相连，所述第二开关的第二端与所述第一N沟道场效应管的漏极相连，所述第二电容的另一端与所述第一N沟道场效应管的源极相连，且接地；
    所述第一N沟道场效应管的漏极和栅极连接，所述第一N沟道场效应管的栅极与所述第二N沟道场效应管的栅极相连，所述第一N沟道场效应管的源极与所述第二N沟道场效应管的源极相连；
    所述第二N沟道场效应管的漏极与所述第一P沟道场效应管的漏极相连，所述第一P沟道场效应管的漏极与栅极连接，所述第一P沟道场效应管的栅极和所述第二P沟道场效应管的栅极相连；
    所述第一P沟道场效应管的源极与所述第二P沟道场效应管的源极相连，用于产生所述电流产生电路的工作电压；
    所述第二P沟道场效应管的漏极和主开关电路相连，用于将电流产生电路达到稳定状态的电流输出至所述主开关电路；
    当所述第三时钟信号为高电平，所述第四时钟信号为低电平时，所述第一开关闭合，所述第二开关断开，为所述第一电容充电，直至所述第一电容的电压到达所述参考电压，所述第一电容放电，输出电流，使电流产生电路的工作电压升高；
    当所述电流产生电路的工作电压和所述参考电压相等时，所述第一N沟道场效应管、所述第二N沟道场效应管、所述第一P沟道场效应管和所述第二P沟道场效应管导通，使得所述电流产生电路达到稳定状态，将电流产生电路达到稳定时的电流通过第二P沟道场效应管的漏极输出至所述主开关电路。
  4. 根据权利要求3所述的模拟开关开启电路，其特征在于，所述第一N沟道场效应管和所述第二N沟道场效应管相同，所述第一P沟道场效应管和所述第二P沟道场效应管相同。
  5. 根据权利要求1所述的模拟开关开启电路，其特征在于，所述主开关电路，包括：第三N沟道场效应管、第三电容、第四电容和齐纳二极管；
    所述第三N沟道场效应管的栅极与所述电流产生电路的输出端相连；
    所述第三N沟道场效应管的栅极与所述第三电容的一端相连，所述第三电容的另一端与所述第三N沟道场效应管的漏极相连；
    所述第三N沟道场效应管的栅极与所述第四电容的一端相连，所述第四电容的另一端与所述第三N沟道场效应管的源极相连；
    所述第四电容与所述齐纳二极管并联；
    当所述第三N沟道场效应管的栅极接收所述第二P沟道场效应的漏极输出的电流时，对所述第三电容和第四电容充电，所述第三N沟道场效应管的栅极和源极两端的电压被所述齐纳二极管钳位，使所述主开关电路在所述电流的作用下完成启动。
  6. 根据权利要求5所述的模拟开关开启电路，其特征在于，所述第三N沟道场效应管为模拟开关开启电路的主开关管。
  7. 根据权利要求5所述的模拟开关开启电路，其特征在于，所述主开关管的栅源电压随着时间的变化而缓慢上升。
  8. 一种模拟开关开启方法，其特征在于，适用于模拟开关缓慢开启电路，所述模拟开关缓慢开启电路包括控制电路，电流产生电路和主开关电路，该方法包括：
    所述控制电路将输入的时间设定信号解码成第二时钟信号；
    所述控制电路基于输入的第一时钟信号将所述第二时钟信号进行分频，产生相位相反的第三时钟信号和第四时钟信号；
    所述电流产生电路接收所述相位相反的第三时钟信号和第四时钟信号；
    所述电流产生电路基于所述第三时钟信号和所述第四时钟信号的控制产生电流，并输出所述电流至所述主开关电路；
    所述主开关电路接收所述电流产生电路输出的所述电流，并在所述电流的作用下完成启动。
  9. 根据权利要求8所述的方法，其特征在于，所述电流产生电路包括：第一开关、第二开关、第一电容、第二电容、第一N沟道场效应管、第二N沟道场效应管、第一P沟道场效应管和第二P沟道场效应管，所述电流产生电路基于所述第三时钟信号和所述第四时钟信号的控制产生电流，并输出所述电流至所述主开关电路，包括：
    当所述第三时钟信号为高电平，所述第四时钟信号为低电平时，所述第一开关闭合，所述第二开关断开，为所述第一电容充电，直至所述第一电容的电压到达所述参考电压时，所述第一电容放电，使电流产生电路的工作电压升高；
    当所述电流产生电路的工作电压和所述参考电压相等时，所述第一N沟道场效应管、所述第二N沟道场效应管、所述第一P沟道场效应管和所述第 二P沟道场效应管导通，使得所述电流产生电路达到稳定状态，将所述电流产生电路达到稳定时的电流通过所述第二P沟道场效应管的漏极输出至所述主开关电路。
  10. 根据权利要求8所述的方法，其特征在于，所述主开关电路，包括：第三N沟道场效应管、第三电容、第四电容和齐纳二极管，所述主开关电路接收所述电流产生电路输出的所述电流，并在所述电流的作用下完成启动，包括：
    所述第三N沟道场效应管的栅极接收所述第二P沟道场效应管的漏极输出的电流，对所述第三电容和所述第四电容充电，使所述第三N沟道场效应管栅极和源极两端的电压被所述齐纳二极管钳位，使所述主开关电路在所述电流的作用下完成启动。
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